257 lines
17 KiB
Plaintext
257 lines
17 KiB
Plaintext
1 ;--------------------------------------------------------
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2 ; File Created by SDCC : free open source ISO C Compiler
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3 ; Version 4.5.0 #15242 (Linux)
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4 ;--------------------------------------------------------
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5 .module main
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6
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7 ;--------------------------------------------------------
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8 ; Public variables in this module
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9 ;--------------------------------------------------------
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10 .globl _main
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11 .globl _RTC_ITConfig
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12 .globl _RTC_WakeUpCmd
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13 .globl _RTC_SetWakeUpCounter
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14 .globl _RTC_WakeUpClockConfig
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15 .globl _GPIO_ResetBits
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16 .globl _GPIO_SetBits
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17 .globl _GPIO_Init
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18 .globl _CLK_PeripheralClockConfig
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19 .globl _CLK_RTCClockConfig
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20 .globl _CLK_SYSCLKSourceSwitchCmd
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21 .globl _CLK_SYSCLKDivConfig
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22 .globl _CLK_GetSYSCLKSource
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23 .globl _CLK_SYSCLKSourceConfig
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24 ;--------------------------------------------------------
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25 ; ram data
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26 ;--------------------------------------------------------
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27 .area DATA
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28 ;--------------------------------------------------------
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29 ; ram data
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30 ;--------------------------------------------------------
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31 .area INITIALIZED
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32 ;--------------------------------------------------------
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33 ; Stack segment in internal ram
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34 ;--------------------------------------------------------
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35 .area SSEG
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000000 36 __start__stack:
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000000 37 .ds 1
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38
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39 ;--------------------------------------------------------
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40 ; absolute external ram data
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41 ;--------------------------------------------------------
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42 .area DABS (ABS)
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43
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44 ; default segment ordering for linker
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45 .area HOME
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46 .area GSINIT
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47 .area GSFINAL
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48 .area CONST
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49 .area INITIALIZER
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50 .area CODE
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51
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52 ;--------------------------------------------------------
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53 ; interrupt vector
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54 ;--------------------------------------------------------
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55 .area HOME
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000000 56 __interrupt_vect:
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000000 82v00u00u00 57 int s_GSINIT ; reset
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000004 82v00u00u00 58 int _TRAP_IRQHandler ; trap
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000008 82 00 00 00 59 int 0x000000 ; int0
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00000C 82v00u00u00 60 int _FLASH_IRQHandler ; int1
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000010 82v00u00u00 61 int _DMA1_CHANNEL0_1_IRQHandler ; int2
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000014 82v00u00u00 62 int _DMA1_CHANNEL2_3_IRQHandler ; int3
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000018 82v00u00u00 63 int _RTC_CSSLSE_IRQHandler ; int4
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00001C 82v00u00u00 64 int _EXTIE_F_PVD_IRQHandler ; int5
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000020 82v00u00u00 65 int _EXTIB_G_IRQHandler ; int6
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000024 82v00u00u00 66 int _EXTID_H_IRQHandler ; int7
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000028 82v00u00u00 67 int _EXTI0_IRQHandler ; int8
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00002C 82v00u00u00 68 int _EXTI1_IRQHandler ; int9
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000030 82v00u00u00 69 int _EXTI2_IRQHandler ; int10
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000034 82v00u00u00 70 int _EXTI3_IRQHandler ; int11
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000038 82v00u00u00 71 int _EXTI4_IRQHandler ; int12
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00003C 82v00u00u00 72 int _EXTI5_IRQHandler ; int13
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000040 82v00u00u00 73 int _EXTI6_IRQHandler ; int14
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000044 82v00u00u00 74 int _EXTI7_IRQHandler ; int15
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000048 82v00u00u00 75 int _LCD_AES_IRQHandler ; int16
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00004C 82v00u00u00 76 int _SWITCH_CSS_BREAK_DAC_IRQHandler ; int17
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000050 82v00u00u00 77 int _ADC1_COMP_IRQHandler ; int18
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000054 82v00u00u00 78 int _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler ; int19
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000058 82v00u00u00 79 int _TIM2_CC_USART2_RX_IRQHandler ; int20
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00005C 82v00u00u00 80 int _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler ; int21
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000060 82v00u00u00 81 int _TIM3_CC_USART3_RX_IRQHandler ; int22
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000064 82v00u00u00 82 int _TIM1_UPD_OVF_TRG_COM_IRQHandler ; int23
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000068 82v00u00u00 83 int _TIM1_CC_IRQHandler ; int24
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00006C 82v00u00u00 84 int _TIM4_UPD_OVF_TRG_IRQHandler ; int25
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000070 82v00u00u00 85 int _SPI1_IRQHandler ; int26
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000074 82v00u00u00 86 int _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler ; int27
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000078 82v00u00u00 87 int _USART1_RX_TIM5_CC_IRQHandler ; int28
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00007C 82v00u00u00 88 int _I2C1_SPI2_IRQHandler ; int29
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89 ;--------------------------------------------------------
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90 ; global & static initialisations
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91 ;--------------------------------------------------------
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92 .area HOME
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93 .area GSINIT
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94 .area GSFINAL
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95 .area GSINIT
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000000 CDr00r00 [ 4] 96 call ___sdcc_external_startup
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000003 4D [ 1] 97 tnz a
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000004 27 03 [ 1] 98 jreq __sdcc_init_data
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000006 CCr00r80 [ 2] 99 jp __sdcc_program_startup
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000009 100 __sdcc_init_data:
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101 ; stm8_genXINIT() start
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000009 AEr00r00 [ 2] 102 ldw x, #l_DATA
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00000C 27 07 [ 1] 103 jreq 00002$
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00000E 104 00001$:
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00000E 72 4FuFFuFF [ 1] 105 clr (s_DATA - 1, x)
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000012 5A [ 2] 106 decw x
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000013 26 F9 [ 1] 107 jrne 00001$
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000015 108 00002$:
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000015 AEr00r00 [ 2] 109 ldw x, #l_INITIALIZER
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000018 27 09 [ 1] 110 jreq 00004$
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00001A 111 00003$:
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00001A D6uFFuFF [ 1] 112 ld a, (s_INITIALIZER - 1, x)
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00001D D7uFFuFF [ 1] 113 ld (s_INITIALIZED - 1, x), a
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000020 5A [ 2] 114 decw x
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000021 26 F7 [ 1] 115 jrne 00003$
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000023 116 00004$:
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117 ; stm8_genXINIT() end
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118 .area GSFINAL
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000000 CCr00r80 [ 2] 119 jp __sdcc_program_startup
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120 ;--------------------------------------------------------
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121 ; Home
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122 ;--------------------------------------------------------
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123 .area HOME
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124 .area HOME
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000080 125 __sdcc_program_startup:
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000080 CCr00r00 [ 2] 126 jp _main
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127 ; return from main will return to caller
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128 ;--------------------------------------------------------
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129 ; code
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130 ;--------------------------------------------------------
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131 .area CODE
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132 ; ../src/main.c: 28: void main(void)
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133 ; -----------------------------------------
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134 ; function main
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135 ; -----------------------------------------
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000000 136 _main:
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137 ; ../src/main.c: 30: GPIO_Init(GPIOB, GPIO_Pin_2, GPIO_Mode_Out_PP_Low_Fast);
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000000 4B E0 [ 1] 138 push #0xe0
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000002 A6 04 [ 1] 139 ld a, #0x04
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000004 AE 50 05 [ 2] 140 ldw x, #0x5005
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000007 CDr00r00 [ 4] 141 call _GPIO_Init
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142 ; ../src/main.c: 33: CLK_Config();
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00000A CDr00r6A [ 4] 143 call _CLK_Config
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144 ; ../src/main.c: 34: PWR_Config();
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00000D CDr00r59 [ 4] 145 call _PWR_Config
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146 ; ../src/main.c: 35: Led2_Init;
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000010 4B E0 [ 1] 147 push #0xe0
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000012 A6 04 [ 1] 148 ld a, #0x04
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000014 AE 50 05 [ 2] 149 ldw x, #0x5005
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000017 CDr00r00 [ 4] 150 call _GPIO_Init
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151 ; ../src/main.c: 36: Mono_Init;
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00001A 4B D0 [ 1] 152 push #0xd0
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00001C A6 01 [ 1] 153 ld a, #0x01
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00001E AE 50 05 [ 2] 154 ldw x, #0x5005
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000021 CDr00r00 [ 4] 155 call _GPIO_Init
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156 ; ../src/main.c: 37: blink2();
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000024 CDr00r83 [ 4] 157 call _blink2
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158 ; ../src/main.c: 41: CLK_RTCClockConfig(CLK_RTCCLKSource_LSE, CLK_RTCCLKDiv_1);
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000027 4B 00 [ 1] 159 push #0x00
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000029 A6 10 [ 1] 160 ld a, #0x10
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00002B CDr00r00 [ 4] 161 call _CLK_RTCClockConfig
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162 ; ../src/main.c: 42: CLK_PeripheralClockConfig(CLK_Peripheral_RTC, ENABLE);
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00002E 4B 01 [ 1] 163 push #0x01
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000030 A6 12 [ 1] 164 ld a, #0x12
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000032 CDr00r00 [ 4] 165 call _CLK_PeripheralClockConfig
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166 ; ../src/main.c: 45: RTC_WakeUpCmd(DISABLE);
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000035 4F [ 1] 167 clr a
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000036 CDr00r00 [ 4] 168 call _RTC_WakeUpCmd
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169 ; ../src/main.c: 46: RTC_WakeUpClockConfig(RTC_WakeUpClock_RTCCLK_Div2);
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000039 A6 03 [ 1] 170 ld a, #0x03
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00003B CDr00r00 [ 4] 171 call _RTC_WakeUpClockConfig
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172 ; ../src/main.c: 47: RTC_SetWakeUpCounter(250);
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00003E AE 00 FA [ 2] 173 ldw x, #0x00fa
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000041 CDr00r00 [ 4] 174 call _RTC_SetWakeUpCounter
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175 ; ../src/main.c: 48: RTC_WakeUpCmd(ENABLE);
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000044 A6 01 [ 1] 176 ld a, #0x01
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000046 CDr00r00 [ 4] 177 call _RTC_WakeUpCmd
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178 ; ../src/main.c: 50: RTC_ITConfig(RTC_IT_WUT, ENABLE);
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000049 A6 01 [ 1] 179 ld a, #0x01
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00004B AE 00 40 [ 2] 180 ldw x, #0x0040
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00004E CDr00r00 [ 4] 181 call _RTC_ITConfig
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182 ; ../src/main.c: 52: enableInterrupts();
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000051 9A [ 1] 183 rim
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184 ; ../src/main.c: 53: while (1){
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000052 185 00102$:
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186 ; ../src/main.c: 54: blink2();
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000052 CDr00r83 [ 4] 187 call _blink2
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188 ; ../src/main.c: 55: halt();
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000055 8E [10] 189 halt
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000056 20 FA [ 2] 190 jra 00102$
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191 ; ../src/main.c: 57: }
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000058 81 [ 4] 192 ret
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193 ; ../src/main.c: 59: static void PWR_Config(void){
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194 ; -----------------------------------------
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195 ; function PWR_Config
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196 ; -----------------------------------------
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000059 197 _PWR_Config:
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198 ; ../src/main.c: 60: PWR->CSR1 = PWR_CSR1_PVDIF;
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000059 35 20 50 B2 [ 1] 199 mov 0x50b2+0, #0x20
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200 ; ../src/main.c: 61: PWR->CSR2 = PWR_CSR2_RESET_VALUE;
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00005D 35 00 50 B3 [ 1] 201 mov 0x50b3+0, #0x00
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202 ; ../src/main.c: 62: PWR->CSR2 |= PWR_CSR2_ULP;
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000061 72 12 50 B3 [ 1] 203 bset 0x50b3, #1
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204 ; ../src/main.c: 63: PWR->CSR2 |= PWR_CSR2_FWU;
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000065 72 14 50 B3 [ 1] 205 bset 0x50b3, #2
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206 ; ../src/main.c: 64: }
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000069 81 [ 4] 207 ret
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208 ; ../src/main.c: 66: static void CLK_Config(void)
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209 ; -----------------------------------------
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210 ; function CLK_Config
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211 ; -----------------------------------------
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00006A 212 _CLK_Config:
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213 ; ../src/main.c: 68: CLK_SYSCLKSourceSwitchCmd(ENABLE);
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00006A A6 01 [ 1] 214 ld a, #0x01
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00006C CDr00r00 [ 4] 215 call _CLK_SYSCLKSourceSwitchCmd
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216 ; ../src/main.c: 69: CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_LSI);
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00006F A6 02 [ 1] 217 ld a, #0x02
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000071 CDr00r00 [ 4] 218 call _CLK_SYSCLKSourceConfig
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219 ; ../src/main.c: 70: CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_1);
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000074 4F [ 1] 220 clr a
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000075 CDr00r00 [ 4] 221 call _CLK_SYSCLKDivConfig
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222 ; ../src/main.c: 71: while (CLK_GetSYSCLKSource() != CLK_SYSCLKSource_LSI);
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000078 223 00101$:
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000078 CDr00r00 [ 4] 224 call _CLK_GetSYSCLKSource
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00007B A1 02 [ 1] 225 cp a, #0x02
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00007D 26 F9 [ 1] 226 jrne 00101$
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00007F 81 [ 4] 227 ret
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000080 20 F6 [ 2] 228 jra 00101$
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229 ; ../src/main.c: 72: }
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000082 81 [ 4] 230 ret
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231 ; ../src/main.c: 85: static void blink2() {
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232 ; -----------------------------------------
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233 ; function blink2
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234 ; -----------------------------------------
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000083 235 _blink2:
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236 ; ../src/main.c: 86: Mono_ON;
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000083 A6 01 [ 1] 237 ld a, #0x01
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000085 AE 50 05 [ 2] 238 ldw x, #0x5005
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000088 CDr00r00 [ 4] 239 call _GPIO_ResetBits
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240 ; ../src/main.c: 87: Led2_ON;
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00008B A6 04 [ 1] 241 ld a, #0x04
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00008D AE 50 05 [ 2] 242 ldw x, #0x5005
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000090 CDr00r00 [ 4] 243 call _GPIO_SetBits
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244 ; ../src/main.c: 88: Led2_OFF;
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000093 A6 04 [ 1] 245 ld a, #0x04
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000095 AE 50 05 [ 2] 246 ldw x, #0x5005
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000098 CDr00r00 [ 4] 247 call _GPIO_ResetBits
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248 ; ../src/main.c: 89: Mono_OFF;
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00009B A6 01 [ 1] 249 ld a, #0x01
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00009D AE 50 05 [ 2] 250 ldw x, #0x5005
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251 ; ../src/main.c: 90: }
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0000A0 CCr00r00 [ 2] 252 jp _GPIO_SetBits
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253 .area CODE
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254 .area CONST
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255 .area INITIALIZER
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256 .area CABS (ABS)
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