1 ;-------------------------------------------------------- 2 ; File Created by SDCC : free open source ISO C Compiler 3 ; Version 4.5.0 #15242 (Linux) 4 ;-------------------------------------------------------- 5 .module main 6 7 ;-------------------------------------------------------- 8 ; Public variables in this module 9 ;-------------------------------------------------------- 10 .globl _main 11 .globl _RTC_ITConfig 12 .globl _RTC_WakeUpCmd 13 .globl _RTC_SetWakeUpCounter 14 .globl _RTC_WakeUpClockConfig 15 .globl _GPIO_ResetBits 16 .globl _GPIO_SetBits 17 .globl _GPIO_Init 18 .globl _CLK_PeripheralClockConfig 19 .globl _CLK_RTCClockConfig 20 .globl _CLK_SYSCLKSourceSwitchCmd 21 .globl _CLK_SYSCLKDivConfig 22 .globl _CLK_GetSYSCLKSource 23 .globl _CLK_SYSCLKSourceConfig 24 ;-------------------------------------------------------- 25 ; ram data 26 ;-------------------------------------------------------- 27 .area DATA 28 ;-------------------------------------------------------- 29 ; ram data 30 ;-------------------------------------------------------- 31 .area INITIALIZED 32 ;-------------------------------------------------------- 33 ; Stack segment in internal ram 34 ;-------------------------------------------------------- 35 .area SSEG 000000 36 __start__stack: 000000 37 .ds 1 38 39 ;-------------------------------------------------------- 40 ; absolute external ram data 41 ;-------------------------------------------------------- 42 .area DABS (ABS) 43 44 ; default segment ordering for linker 45 .area HOME 46 .area GSINIT 47 .area GSFINAL 48 .area CONST 49 .area INITIALIZER 50 .area CODE 51 52 ;-------------------------------------------------------- 53 ; interrupt vector 54 ;-------------------------------------------------------- 55 .area HOME 000000 56 __interrupt_vect: 000000 82v00u00u00 57 int s_GSINIT ; reset 000004 82v00u00u00 58 int _TRAP_IRQHandler ; trap 000008 82 00 00 00 59 int 0x000000 ; int0 00000C 82v00u00u00 60 int _FLASH_IRQHandler ; int1 000010 82v00u00u00 61 int _DMA1_CHANNEL0_1_IRQHandler ; int2 000014 82v00u00u00 62 int _DMA1_CHANNEL2_3_IRQHandler ; int3 000018 82v00u00u00 63 int _RTC_CSSLSE_IRQHandler ; int4 00001C 82v00u00u00 64 int _EXTIE_F_PVD_IRQHandler ; int5 000020 82v00u00u00 65 int _EXTIB_G_IRQHandler ; int6 000024 82v00u00u00 66 int _EXTID_H_IRQHandler ; int7 000028 82v00u00u00 67 int _EXTI0_IRQHandler ; int8 00002C 82v00u00u00 68 int _EXTI1_IRQHandler ; int9 000030 82v00u00u00 69 int _EXTI2_IRQHandler ; int10 000034 82v00u00u00 70 int _EXTI3_IRQHandler ; int11 000038 82v00u00u00 71 int _EXTI4_IRQHandler ; int12 00003C 82v00u00u00 72 int _EXTI5_IRQHandler ; int13 000040 82v00u00u00 73 int _EXTI6_IRQHandler ; int14 000044 82v00u00u00 74 int _EXTI7_IRQHandler ; int15 000048 82v00u00u00 75 int _LCD_AES_IRQHandler ; int16 00004C 82v00u00u00 76 int _SWITCH_CSS_BREAK_DAC_IRQHandler ; int17 000050 82v00u00u00 77 int _ADC1_COMP_IRQHandler ; int18 000054 82v00u00u00 78 int _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler ; int19 000058 82v00u00u00 79 int _TIM2_CC_USART2_RX_IRQHandler ; int20 00005C 82v00u00u00 80 int _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler ; int21 000060 82v00u00u00 81 int _TIM3_CC_USART3_RX_IRQHandler ; int22 000064 82v00u00u00 82 int _TIM1_UPD_OVF_TRG_COM_IRQHandler ; int23 000068 82v00u00u00 83 int _TIM1_CC_IRQHandler ; int24 00006C 82v00u00u00 84 int _TIM4_UPD_OVF_TRG_IRQHandler ; int25 000070 82v00u00u00 85 int _SPI1_IRQHandler ; int26 000074 82v00u00u00 86 int _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler ; int27 000078 82v00u00u00 87 int _USART1_RX_TIM5_CC_IRQHandler ; int28 00007C 82v00u00u00 88 int _I2C1_SPI2_IRQHandler ; int29 89 ;-------------------------------------------------------- 90 ; global & static initialisations 91 ;-------------------------------------------------------- 92 .area HOME 93 .area GSINIT 94 .area GSFINAL 95 .area GSINIT 000000 CDr00r00 [ 4] 96 call ___sdcc_external_startup 000003 4D [ 1] 97 tnz a 000004 27 03 [ 1] 98 jreq __sdcc_init_data 000006 CCr00r80 [ 2] 99 jp __sdcc_program_startup 000009 100 __sdcc_init_data: 101 ; stm8_genXINIT() start 000009 AEr00r00 [ 2] 102 ldw x, #l_DATA 00000C 27 07 [ 1] 103 jreq 00002$ 00000E 104 00001$: 00000E 72 4FuFFuFF [ 1] 105 clr (s_DATA - 1, x) 000012 5A [ 2] 106 decw x 000013 26 F9 [ 1] 107 jrne 00001$ 000015 108 00002$: 000015 AEr00r00 [ 2] 109 ldw x, #l_INITIALIZER 000018 27 09 [ 1] 110 jreq 00004$ 00001A 111 00003$: 00001A D6uFFuFF [ 1] 112 ld a, (s_INITIALIZER - 1, x) 00001D D7uFFuFF [ 1] 113 ld (s_INITIALIZED - 1, x), a 000020 5A [ 2] 114 decw x 000021 26 F7 [ 1] 115 jrne 00003$ 000023 116 00004$: 117 ; stm8_genXINIT() end 118 .area GSFINAL 000000 CCr00r80 [ 2] 119 jp __sdcc_program_startup 120 ;-------------------------------------------------------- 121 ; Home 122 ;-------------------------------------------------------- 123 .area HOME 124 .area HOME 000080 125 __sdcc_program_startup: 000080 CCr00r00 [ 2] 126 jp _main 127 ; return from main will return to caller 128 ;-------------------------------------------------------- 129 ; code 130 ;-------------------------------------------------------- 131 .area CODE 132 ; ../src/main.c: 28: void main(void) 133 ; ----------------------------------------- 134 ; function main 135 ; ----------------------------------------- 000000 136 _main: 137 ; ../src/main.c: 30: GPIO_Init(GPIOB, GPIO_Pin_2, GPIO_Mode_Out_PP_Low_Fast); 000000 4B E0 [ 1] 138 push #0xe0 000002 A6 04 [ 1] 139 ld a, #0x04 000004 AE 50 05 [ 2] 140 ldw x, #0x5005 000007 CDr00r00 [ 4] 141 call _GPIO_Init 142 ; ../src/main.c: 33: CLK_Config(); 00000A CDr00r6A [ 4] 143 call _CLK_Config 144 ; ../src/main.c: 34: PWR_Config(); 00000D CDr00r59 [ 4] 145 call _PWR_Config 146 ; ../src/main.c: 35: Led2_Init; 000010 4B E0 [ 1] 147 push #0xe0 000012 A6 04 [ 1] 148 ld a, #0x04 000014 AE 50 05 [ 2] 149 ldw x, #0x5005 000017 CDr00r00 [ 4] 150 call _GPIO_Init 151 ; ../src/main.c: 36: Mono_Init; 00001A 4B D0 [ 1] 152 push #0xd0 00001C A6 01 [ 1] 153 ld a, #0x01 00001E AE 50 05 [ 2] 154 ldw x, #0x5005 000021 CDr00r00 [ 4] 155 call _GPIO_Init 156 ; ../src/main.c: 37: blink2(); 000024 CDr00r83 [ 4] 157 call _blink2 158 ; ../src/main.c: 41: CLK_RTCClockConfig(CLK_RTCCLKSource_LSE, CLK_RTCCLKDiv_1); 000027 4B 00 [ 1] 159 push #0x00 000029 A6 10 [ 1] 160 ld a, #0x10 00002B CDr00r00 [ 4] 161 call _CLK_RTCClockConfig 162 ; ../src/main.c: 42: CLK_PeripheralClockConfig(CLK_Peripheral_RTC, ENABLE); 00002E 4B 01 [ 1] 163 push #0x01 000030 A6 12 [ 1] 164 ld a, #0x12 000032 CDr00r00 [ 4] 165 call _CLK_PeripheralClockConfig 166 ; ../src/main.c: 45: RTC_WakeUpCmd(DISABLE); 000035 4F [ 1] 167 clr a 000036 CDr00r00 [ 4] 168 call _RTC_WakeUpCmd 169 ; ../src/main.c: 46: RTC_WakeUpClockConfig(RTC_WakeUpClock_RTCCLK_Div2); 000039 A6 03 [ 1] 170 ld a, #0x03 00003B CDr00r00 [ 4] 171 call _RTC_WakeUpClockConfig 172 ; ../src/main.c: 47: RTC_SetWakeUpCounter(250); 00003E AE 00 FA [ 2] 173 ldw x, #0x00fa 000041 CDr00r00 [ 4] 174 call _RTC_SetWakeUpCounter 175 ; ../src/main.c: 48: RTC_WakeUpCmd(ENABLE); 000044 A6 01 [ 1] 176 ld a, #0x01 000046 CDr00r00 [ 4] 177 call _RTC_WakeUpCmd 178 ; ../src/main.c: 50: RTC_ITConfig(RTC_IT_WUT, ENABLE); 000049 A6 01 [ 1] 179 ld a, #0x01 00004B AE 00 40 [ 2] 180 ldw x, #0x0040 00004E CDr00r00 [ 4] 181 call _RTC_ITConfig 182 ; ../src/main.c: 52: enableInterrupts(); 000051 9A [ 1] 183 rim 184 ; ../src/main.c: 53: while (1){ 000052 185 00102$: 186 ; ../src/main.c: 54: blink2(); 000052 CDr00r83 [ 4] 187 call _blink2 188 ; ../src/main.c: 55: halt(); 000055 8E [10] 189 halt 000056 20 FA [ 2] 190 jra 00102$ 191 ; ../src/main.c: 57: } 000058 81 [ 4] 192 ret 193 ; ../src/main.c: 59: static void PWR_Config(void){ 194 ; ----------------------------------------- 195 ; function PWR_Config 196 ; ----------------------------------------- 000059 197 _PWR_Config: 198 ; ../src/main.c: 60: PWR->CSR1 = PWR_CSR1_PVDIF; 000059 35 20 50 B2 [ 1] 199 mov 0x50b2+0, #0x20 200 ; ../src/main.c: 61: PWR->CSR2 = PWR_CSR2_RESET_VALUE; 00005D 35 00 50 B3 [ 1] 201 mov 0x50b3+0, #0x00 202 ; ../src/main.c: 62: PWR->CSR2 |= PWR_CSR2_ULP; 000061 72 12 50 B3 [ 1] 203 bset 0x50b3, #1 204 ; ../src/main.c: 63: PWR->CSR2 |= PWR_CSR2_FWU; 000065 72 14 50 B3 [ 1] 205 bset 0x50b3, #2 206 ; ../src/main.c: 64: } 000069 81 [ 4] 207 ret 208 ; ../src/main.c: 66: static void CLK_Config(void) 209 ; ----------------------------------------- 210 ; function CLK_Config 211 ; ----------------------------------------- 00006A 212 _CLK_Config: 213 ; ../src/main.c: 68: CLK_SYSCLKSourceSwitchCmd(ENABLE); 00006A A6 01 [ 1] 214 ld a, #0x01 00006C CDr00r00 [ 4] 215 call _CLK_SYSCLKSourceSwitchCmd 216 ; ../src/main.c: 69: CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_LSI); 00006F A6 02 [ 1] 217 ld a, #0x02 000071 CDr00r00 [ 4] 218 call _CLK_SYSCLKSourceConfig 219 ; ../src/main.c: 70: CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_1); 000074 4F [ 1] 220 clr a 000075 CDr00r00 [ 4] 221 call _CLK_SYSCLKDivConfig 222 ; ../src/main.c: 71: while (CLK_GetSYSCLKSource() != CLK_SYSCLKSource_LSI); 000078 223 00101$: 000078 CDr00r00 [ 4] 224 call _CLK_GetSYSCLKSource 00007B A1 02 [ 1] 225 cp a, #0x02 00007D 26 F9 [ 1] 226 jrne 00101$ 00007F 81 [ 4] 227 ret 000080 20 F6 [ 2] 228 jra 00101$ 229 ; ../src/main.c: 72: } 000082 81 [ 4] 230 ret 231 ; ../src/main.c: 85: static void blink2() { 232 ; ----------------------------------------- 233 ; function blink2 234 ; ----------------------------------------- 000083 235 _blink2: 236 ; ../src/main.c: 86: Mono_ON; 000083 A6 01 [ 1] 237 ld a, #0x01 000085 AE 50 05 [ 2] 238 ldw x, #0x5005 000088 CDr00r00 [ 4] 239 call _GPIO_ResetBits 240 ; ../src/main.c: 87: Led2_ON; 00008B A6 04 [ 1] 241 ld a, #0x04 00008D AE 50 05 [ 2] 242 ldw x, #0x5005 000090 CDr00r00 [ 4] 243 call _GPIO_SetBits 244 ; ../src/main.c: 88: Led2_OFF; 000093 A6 04 [ 1] 245 ld a, #0x04 000095 AE 50 05 [ 2] 246 ldw x, #0x5005 000098 CDr00r00 [ 4] 247 call _GPIO_ResetBits 248 ; ../src/main.c: 89: Mono_OFF; 00009B A6 01 [ 1] 249 ld a, #0x01 00009D AE 50 05 [ 2] 250 ldw x, #0x5005 251 ; ../src/main.c: 90: } 0000A0 CCr00r00 [ 2] 252 jp _GPIO_SetBits 253 .area CODE 254 .area CONST 255 .area INITIALIZER 256 .area CABS (ABS)