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add spl, first tries programming

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This commit is contained in:
seppl
2025-06-28 16:14:14 +02:00
parent 2155e2b176
commit 012355c2e8
104 changed files with 58111 additions and 3 deletions
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18
electronics/rosaled.kicad_sch
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@@ -2179,6 +2179,7 @@
)
(alternate "" input line)
(alternate "OSC_OUT" output line)
(alternate "" input line)
(alternate "[SPI_MOSI]" bidirectional line)
(alternate "[USART_RX]" input line)
)
@@ -2369,6 +2370,7 @@
)
)
(alternate "" input line)
(alternate "" input line)
)
(pin power_in line
(at 0 -21.59 90)
@@ -2388,6 +2390,7 @@
)
)
(alternate "" input line)
(alternate "" input line)
)
(pin bidirectional line
(at 17.78 11.43 180)
@@ -2408,6 +2411,8 @@
)
(alternate "" input line)
(alternate "I2C_SDA" bidirectional line)
(alternate "" input line)
(alternate "" input line)
)
(pin bidirectional line
(at 17.78 8.89 180)
@@ -2428,6 +2433,7 @@
)
(alternate "" input line)
(alternate "I2C_SCL" bidirectional line)
(alternate "" input line)
)
(pin bidirectional line
(at 17.78 6.35 180)
@@ -2452,6 +2458,8 @@
(alternate "COMP1_INP" input line)
(alternate "COMP2_INM" input line)
(alternate "I2C1_SMB" bidirectional line)
(alternate "" input line)
(alternate "" input line)
(alternate "USART_CK" output line)
)
(pin bidirectional line
@@ -2519,6 +2527,7 @@
(alternate "ADC1_IN22" input line)
(alternate "COMP1_INP" input line)
(alternate "COMP2_INP" input line)
(alternate "" input line)
(alternate "TIM3_CH2" bidirectional line)
(alternate "[ADC1_TRIG]" input line)
)
@@ -6312,6 +6321,7 @@
)
(pin "1"
(uuid "8916c4e7-9253-474d-be2b-d978fa4d559c")
(alternate "OSC32_IN")
)
(pin "10"
(uuid "45fa452a-64bf-4166-a177-0b9c0b29cfd4")
@@ -6339,21 +6349,23 @@
)
(pin "18"
(uuid "fcfdc83f-b9bc-4d93-a6d9-5b09713ae9a7")
(alternate "OSC32_IN")
(alternate "PC0")
)
(pin "19"
(uuid "4f90a02c-d04c-4396-9cc5-9373393fbafb")
(alternate "OSC32_OUT")
(alternate "PC1")
)
(pin "2"
(uuid "b3830cd6-6f6a-4a83-930b-47bcc649dbd0")
(alternate "OSC32_OUT")
)
(pin "20"
(uuid "41fec565-2eac-4722-b138-f04a0dd20b41")
(alternate "SWIM")
(alternate "PC4")
)
(pin "3"
(uuid "50cab925-848a-4400-9717-69e4ed163194")
(alternate "SWIM")
)
(pin "4"
(uuid "8abd8544-d06b-4baf-8b59-070ea786c743")

18
firmware/.vscode/c_cpp_properties.json vendored Normal file
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@@ -0,0 +1,18 @@
{
"configurations": [
{
"name": "Linux",
"includePath": [
"${workspaceFolder}/**",
"/usr/lib/stm8l151x/**",
"${workspaceFolder}/src"
],
"defines": [],
"compilerPath": "/usr/bin/gcc",
"cStandard": "c17",
"cppStandard": "gnu++17",
"intelliSenseMode": "linux-gcc-x64"
}
],
"version": 4
}

35
firmware/.vscode/launch.json vendored Normal file
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@@ -0,0 +1,35 @@
{
// Use IntelliSense to learn about possible attributes.
// Hover to view descriptions of existing attributes.
// For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
"version": "0.2.0",
"configurations": [
{
"name": "STM8-gdb",
"type": "cppdbg",
"request": "launch",
"program": "${workspaceRoot}/build/main.elf",
"args": [],
"stopAtEntry": true,
"cwd": "${workspaceRoot}",
"environment": [],
"externalConsole": false,
"MIMode": "gdb",
"miDebuggerPath": "stm8-gdb",
"setupCommands": [
{
"description": "connect to target",
"text": "-target-select extended-remote localhost:3333",
"ignoreFailures": true
},
],
"logging": {
"moduleLoad": true,
"trace": true,
"engineLogging": true,
"programOutput": true,
"exceptions": true
},
},
]
}

10
firmware/.vscode/settings.json vendored Normal file
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@@ -0,0 +1,10 @@
{
"files.associations": {
"stm8l15x.h": "c",
"stm8l15x_it.h": "c",
"stm8l15x_conf.h": "c",
"stm8l15x_rtc.h": "c",
"stdio.h": "c",
"stm8l15x_usart.h": "c"
}
}

66
firmware/SDCC/Makefile Normal file
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@@ -0,0 +1,66 @@
#######
# makefile for STM8*_StdPeriph_Lib and SDCC compiler
#
# note: paths in this Makefile assume unmodified SPL folder structure
#
# usage:
# 1. if SDCC not in PATH set path -> CC_ROOT
# 2. set correct STM8 device -> DEVICE
# 3. set project paths -> PRJ_ROOT, PRJ_SRC_DIR, PRJ_INC_DIR
# 4. set SPL paths -> SPL_ROOT
# 5. add required SPL modules -> SPL_SOURCE
# 6. add required STM8_EVAL modules -> EVAL_SOURCE, EVAL_COMM_SOURCE, EVAL_STM8L1526_SOURCE, EVAL_STM8L1528_SOURCE
#
#######
# STM8 device (for supported devices see stm8l15x.h)
DEVICE=STM8L15X_LD
# set compiler path & parameters
CC_ROOT =
CC = sdcc
CFLAGS = -out-fmt-ihx -mstm8 -lstm8 --opt-code-size --stack-auto
# set output folder and target name
OUTPUT_DIR = ../$(DEVICE)
TARGET = $(OUTPUT_DIR)/$(DEVICE).hex
# set project folder and files (all *.c)
PRJ_ROOT = ..
PRJ_SRC_DIR = $(PRJ_ROOT)/src
PRJ_INC_DIR = $(PRJ_ROOT)/inc
PRJ_SOURCE = $(notdir $(wildcard $(PRJ_SRC_DIR)/*.c))
PRJ_OBJECTS := $(addprefix $(OUTPUT_DIR)/, $(PRJ_SOURCE:.c=.rel))
# set SPL paths
SPL_ROOT = $(PRJ_INC_DIR)/stm8l151x
SPL_SRC_DIR = $(SPL_ROOT)/src
SPL_INC_DIR = $(SPL_ROOT)/inc
SPL_SOURCE = stm8l15x_usart.c stm8l15x_clk.c stm8l15x_gpio.c stm8l15x_rtc.c #$(notdir $(wildcard $(SPL_SRC_DIR)/*.c))
SPL_OBJECTS := $(addprefix $(OUTPUT_DIR)/, $(SPL_SOURCE:.c=.rel))
# collect all include folders
INCLUDE = -I$(PRJ_INC_DIR) -I$(SPL_INC_DIR)
# collect all source directories
VPATH=$(PRJ_SRC_DIR):$(SPL_SRC_DIR)
.PHONY: clean
all: $(OUTPUT_DIR) $(TARGET)
$(OUTPUT_DIR):
mkdir -p $(OUTPUT_DIR)
$(OUTPUT_DIR)/%.rel: %.c
$(CC) $(CFLAGS) $(INCLUDE) -D$(DEVICE) -c $?
$(OUTPUT_DIR)/%.rel: %.c
$(CC) $(CFLAGS) $(INCLUDE) -D$(DEVICE) -c $? -o $@
$(TARGET): $(PRJ_OBJECTS) $(SPL_OBJECTS) $(EVAL_OBJECTS) $(EVAL_COMM_OBJECTS) $(EVAL_STM8L1526_OBJECTS) $(EVAL_STM8L1528_OBJECTS)
$(CC) $(CFLAGS) -o $(TARGET) $^
clean:
rm -fr $(OUTPUT_DIR)

20
firmware/SDCC/_UX_clean.sh Executable file
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@@ -0,0 +1,20 @@
#!/bin/bash
# change to current working directory
cd `dirname $0`
# just for output
echo off
clear
# target device (for supported devices see stm8l15x.h)
DEVICE=STM8L15X_MD
# set make tool (if not in PATH, set complete path)
MAKE=make
# use Makefiles to delete outputs
$MAKE -f Makefile DEVICE=$DEVICE clean
echo on

48
firmware/SDCC/_UX_compile_run.sh Executable file
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@@ -0,0 +1,48 @@
#!/bin/bash
# change to current working directory
# echo $(dirname $0)
cd `dirname $0`
# just for output
clear
# target device (for supported devices see stm8l15x.h)
DEVICE=STM8L15X_LD
# set make tool (if not in PATH, set complete path)
MAKE=make
# set serial upload tool and serial port (stm8gal from https://github.com/gicking/stm8gal)
# BSL_LOADER=~/Öffentlich/GitHub/stm8gal/stm8gal/stm8gal
# BSL_PORT=/dev/ttyUSB0
# set SWIM upload tool and device name (stm8flash from https://github.com/vdudouyt/stm8flash)
SWIM_LOADER=stm8flash
SWIM_TOOL=stlinkv2
SWIM_DEVICE=stm8l151?2
# target hexfile
TARGET=../$DEVICE/$DEVICE.hex
# make project
echo "make application"
$MAKE -f Makefile DEVICE=$DEVICE
if [ $? -ne 0 ]; then
echo " "
read -p "press key to close window..."
echo on
exit
fi
echo "done with application"
echo " "
# upload using STM8 serial bootloader (stm8gal from https://github.com/gicking/stm8gal)
#$BSL_LOADER -p $BSL_PORT -w $TARGET -v
# upload using SWIM debug interface (stm8flash from https://github.com/vdudouyt/stm8flash)
$SWIM_LOADER -c $SWIM_TOOL -w "$TARGET" -p $SWIM_DEVICE
# echo " "
# read -p "press key to close window..."
# echo " "

15
firmware/SDCC/_WIN_clean.bat Normal file
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@@ -0,0 +1,15 @@
REM just for output
echo off
cls
REM target device (for supported devices see stm8l15x.h)
set DEVICE=STM8L15X_MD
REM set make tool (if not in PATH, set complete path)
set MAKE=mingw32-make
REM use makefile to delete sdcc output
%MAKE% -f Makefile DEVICE=%DEVICE% clean
echo on

49
firmware/SDCC/_WIN_compile_run.bat Normal file
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@@ -0,0 +1,49 @@
REM just for output
echo off
cls
REM target device (for supported devices see stm8l15x.h)
set DEVICE=STM8L15X_MD
REM set make tool (if not in PATH, set complete path)
set MAKE=mingw32-make
REM set serial upload tool and serial port (stm8gal from https://github.com/gicking/stm8gal)
set BSL_LOADER="C:\Programme\stm8gal\stm8gal.exe"
set BSL_PORT=7
REM set SWIM upload tool and device name (stm8flash from https://github.com/vdudouyt/stm8flash)
REM set SWIM_LOADER=C:\Programme\stm8flash\stm8flash.exe"
REM set SWIM_TOOL=stlinkv2
REM set SWIM_DEVICE=stm8l152?6
REM set SWIM upload tool and device name (STVP-STM8 on http://www.st.com)
set SWIM_LOADER="C:\Programme\STMicroelectronics\st_toolset\stvp\STVP_CmdLine.exe"
set SWIM_DEVICE=STM8L15xC6
REM name of target hexfile
set TARGET=.\%DEVICE%\%DEVICE%.hex
REM compile and link
echo make application
%MAKE% -f Makefile DEVICE=%DEVICE%
IF ERRORLEVEL 1 GOTO END
echo done with application
echo.
REM GOTO END
REM upload using STM8 serial bootloader (stm8gal from https://github.com/gicking/stm8gal)
REM %BSL_LOADER% -p %BSL_PORT% -w %TARGET% -v
REM upload using SWIM debug interface (stm8flash from https://github.com/vdudouyt/stm8flash)
REM %SWIM_LOADER% -c %SWIM_TOOL% -w %TARGET% -p %SWIM_DEVICE%
REM upload using SWIM debug interface (STVP-STM8 on http://www.st.com)
%SWIM_LOADER% -BoardName=ST-LINK -Port=USB -ProgMode=SWIM -Device=%DEVICE_STVP% -readData -readOption -no_progData -no_progOption -no_loop -no_log -FileProg=%TARGET%
REM clean up
:END
PAUSE
echo on

26
firmware/SDCC/_WIN_upload.bat Normal file
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@@ -0,0 +1,26 @@
REM just for output
echo off
cls
REM set serial upload tool and serial port (stm8gal from https://github.com/gicking/stm8gal)
set LOADER="C:\Programme\stm8gal\stm8gal.exe"
set PORT=7
REM name of target hexfile
set TARGET=Debug\stm8l15x.s19
REM ask user to put STM8 to bootloader mode
echo.
echo.
echo reset STM8 and press return
echo.
PAUSE
REM upload using STM8 serial bootloader (stm8gal from https://github.com/gicking/stm8gal)
%LOADER% -p COM%PORT% -w %TARGET% -v
REM clean up
:END
PAUSE
echo on

155
firmware/STM8L15X_LD/STM8L15X_LD.hex Normal file
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@@ -0,0 +1,155 @@
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:208F9B00A4FBC751495F7204514C08A3FFFF27035C20F37204514C024FC5A60135FF515954
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:2091FB009F43C7514D9E43A47FC7514C8188C651496B019F14016B01C6514D545454548973
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:00000001FF

16
firmware/STM8L15X_LD/STM8L15X_LD.lk Normal file
View File

@@ -0,0 +1,16 @@
-muwx
-i ../STM8L15X_LD/STM8L15X_LD.hex
-b HOME = 0x8000
-b DATA = 0x0001
-k /opt/sdcc/bin/../share/sdcc/lib/stm8
-k /usr/local/share/sdcc/lib/stm8
-l stm8
-l stm8
../STM8L15X_LD/main.rel
../STM8L15X_LD/stm8l15x_it.rel
../STM8L15X_LD/stm8l15x_usart.rel
../STM8L15X_LD/stm8l15x_clk.rel
../STM8L15X_LD/stm8l15x_gpio.rel
../STM8L15X_LD/stm8l15x_rtc.rel
-e

274
firmware/STM8L15X_LD/STM8L15X_LD.map Normal file
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@@ -0,0 +1,274 @@
ASxxxx Linker V03.00/V05.40 + sdld, page 1.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
. .ABS. 00000000 00000000 = 0. bytes (ABS,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00000000 .__.ABS. _startup
00000000 l_CABS
00000000 l_DABS
00000000 l_DATA
00000000 l_INITIALIZED
00000000 l_INITIALIZER
00000000 l__CODE
00000000 s_CABS
00000000 s_DABS
00000000 s__CODE
00000001 l_SSEG
00000001 s_DATA
00000001 s_INITIALIZED
00000001 s_SSEG
00000003 l_GSFINAL
0000000B l_CONST
00000023 l_GSINIT
00000083 l_HOME
00001205 l_CODE
00008000 s_HOME
00008083 s_GSINIT
000080A6 s_GSFINAL
000080A9 s_CONST
000080B4 s_CODE
000080B4 s_INITIALIZER
ASxxxx Linker V03.00/V05.40 + sdld, page 2.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
SSEG 00000001 00000001 = 1. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 3.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
HOME 00008000 00000083 = 131. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 4.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
GSINIT 00008083 00000023 = 35. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 5.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
GSFINAL 000080A6 00000003 = 3. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
ASxxxx Linker V03.00/V05.40 + sdld, page 6.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
CONST 000080A9 0000000B = 11. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
000080AF _SYSDivFactor stm8l15x_clk
ASxxxx Linker V03.00/V05.40 + sdld, page 7.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
CODE 000080B4 00001205 = 4613. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
000080B4 _main main
0000818F _TRAP_IRQHandler stm8l15x_it
00008190 _FLASH_IRQHandler stm8l15x_it
00008191 _DMA1_CHANNEL0_1_IRQHandler stm8l15x_it
00008192 _DMA1_CHANNEL2_3_IRQHandler stm8l15x_it
00008193 _RTC_CSSLSE_IRQHandler stm8l15x_it
00008194 _EXTIE_F_PVD_IRQHandler stm8l15x_it
00008195 _EXTIB_G_IRQHandler stm8l15x_it
00008196 _EXTID_H_IRQHandler stm8l15x_it
00008197 _EXTI0_IRQHandler stm8l15x_it
00008198 _EXTI1_IRQHandler stm8l15x_it
00008199 _EXTI2_IRQHandler stm8l15x_it
0000819A _EXTI3_IRQHandler stm8l15x_it
0000819B _EXTI4_IRQHandler stm8l15x_it
0000819C _EXTI5_IRQHandler stm8l15x_it
0000819D _EXTI6_IRQHandler stm8l15x_it
0000819E _EXTI7_IRQHandler stm8l15x_it
0000819F _LCD_AES_IRQHandler stm8l15x_it
000081A0 _SWITCH_CSS_BREAK_DAC_IRQHandler stm8l15x_it
000081A1 _ADC1_COMP_IRQHandler stm8l15x_it
000081A2 _TIM2_UPD_OVF_TRG_BRK_USART2_TX_ stm8l15x_it
000081A3 _TIM2_CC_USART2_RX_IRQHandler stm8l15x_it
000081A4 _TIM3_UPD_OVF_TRG_BRK_USART3_TX_ stm8l15x_it
000081A5 _TIM3_CC_USART3_RX_IRQHandler stm8l15x_it
000081A6 _TIM1_UPD_OVF_TRG_COM_IRQHandler stm8l15x_it
000081A7 _TIM1_CC_IRQHandler stm8l15x_it
000081A8 _TIM4_UPD_OVF_TRG_IRQHandler stm8l15x_it
000081A9 _SPI1_IRQHandler stm8l15x_it
000081AA _USART1_TX_TIM5_UPD_OVF_TRG_BRK_ stm8l15x_it
000081AB _USART1_RX_TIM5_CC_IRQHandler stm8l15x_it
000081AC _I2C1_SPI2_IRQHandler stm8l15x_it
000081AD _USART_DeInit stm8l15x_usart
000081C4 _USART_Init stm8l15x_usart
00008241 _USART_ClockInit stm8l15x_usart
0000827B _USART_Cmd stm8l15x_usart
00008290 _USART_SetPrescaler stm8l15x_usart
00008295 _USART_SendBreak stm8l15x_usart
0000829D _USART_ReceiveData8 stm8l15x_usart
000082A0 _USART_ReceiveData9 stm8l15x_usart
000082BB _USART_SendData8 stm8l15x_usart
000082BE _USART_SendData9 stm8l15x_usart
000082E3 _USART_ReceiverWakeUpCmd stm8l15x_usart
000082F8 _USART_SetAddress stm8l15x_usart
00008307 _USART_WakeUpConfig stm8l15x_usart
00008316 _USART_HalfDuplexCmd stm8l15x_usart
0000832B _USART_SmartCardCmd stm8l15x_usart
00008340 _USART_SmartCardNACKCmd stm8l15x_usart
00008355 _USART_SetGuardTime stm8l15x_usart
0000835A _USART_IrDAConfig stm8l15x_usart
0000836F _USART_IrDACmd stm8l15x_usart
ASxxxx Linker V03.00/V05.40 + sdld, page 8.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
CODE 000080B4 00001205 = 4613. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00008384 _USART_DMACmd stm8l15x_usart
0000839E _USART_ITConfig stm8l15x_usart
0000842D _USART_GetFlagStatus stm8l15x_usart
00008455 _USART_ClearFlag stm8l15x_usart
00008461 _USART_GetITStatus stm8l15x_usart
000084F9 _USART_ClearITPendingBit stm8l15x_usart
00008502 _CLK_DeInit stm8l15x_clk
00008543 _CLK_HSICmd stm8l15x_clk
0000855B _CLK_AdjustHSICalibrationValue stm8l15x_clk
00008567 _CLK_LSICmd stm8l15x_clk
0000857F _CLK_HSEConfig stm8l15x_clk
00008594 _CLK_LSEConfig stm8l15x_clk
000085A9 _CLK_ClockSecuritySystemEnable stm8l15x_clk
000085AE _CLK_ClockSecuritySytemDeglitchC stm8l15x_clk
000085C6 _CLK_CCOConfig stm8l15x_clk
000085CE _CLK_SYSCLKSourceConfig stm8l15x_clk
000085D2 _CLK_GetSYSCLKSource stm8l15x_clk
000085D6 _CLK_GetClockFreq stm8l15x_clk
00008629 _CLK_SYSCLKDivConfig stm8l15x_clk
0000862D _CLK_SYSCLKSourceSwitchCmd stm8l15x_clk
00008645 _CLK_RTCClockConfig stm8l15x_clk
0000864D _CLK_BEEPClockConfig stm8l15x_clk
00008651 _CLK_PeripheralClockConfig stm8l15x_clk
000086B9 _CLK_LSEClockSecuritySystemEnabl stm8l15x_clk
000086BE _CLK_RTCCLKSwitchOnLSEFailureEna stm8l15x_clk
000086C3 _CLK_HaltConfig stm8l15x_clk
000086E1 _CLK_MainRegulatorCmd stm8l15x_clk
000086F9 _CLK_ITConfig stm8l15x_clk
0000875E _CLK_GetFlagStatus stm8l15x_clk
000087CC _CLK_ClearFlag stm8l15x_clk
000087D1 _CLK_GetITStatus stm8l15x_clk
0000880B _CLK_ClearITPendingBit stm8l15x_clk
0000881B _GPIO_DeInit stm8l15x_gpio
00008828 _GPIO_Init stm8l15x_gpio
000088A3 _GPIO_ExternalPullUpConfig stm8l15x_gpio
000088BD _GPIO_Write stm8l15x_gpio
000088BF _GPIO_WriteBit stm8l15x_gpio
000088D6 _GPIO_SetBits stm8l15x_gpio
000088DF _GPIO_ResetBits stm8l15x_gpio
000088EB _GPIO_ToggleBits stm8l15x_gpio
000088F4 _GPIO_ReadInputData stm8l15x_gpio
000088F7 _GPIO_ReadOutputData stm8l15x_gpio
000088F9 _GPIO_ReadInputDataBit stm8l15x_gpio
00008906 _GPIO_ReadOutputDataBit stm8l15x_gpio
00008912 _RTC_DeInit stm8l15x_rtc
000089DD _RTC_Init stm8l15x_rtc
00008A26 _RTC_StructInit stm8l15x_rtc
00008A36 _RTC_WriteProtectionCmd stm8l15x_rtc
00008A47 _RTC_EnterInitMode stm8l15x_rtc
00008A68 _RTC_ExitInitMode stm8l15x_rtc
00008A6D _RTC_WaitForSynchro stm8l15x_rtc
ASxxxx Linker V03.00/V05.40 + sdld, page 9.
Hexadecimal [32-Bits]
Area Addr Size Decimal Bytes (Attributes)
-------------------------------- ---- ---- ------- ----- ------------
CODE 000080B4 00001205 = 4613. bytes (REL,CON)
Value Global Global Defined In Module
----- -------------------------------- ------------------------
00008A99 _RTC_RatioCmd stm8l15x_rtc
00008ABD _RTC_BypassShadowCmd stm8l15x_rtc
00008AE1 _RTC_SetTime stm8l15x_rtc
00008B6D _RTC_TimeStructInit stm8l15x_rtc
00008B7A _RTC_GetTime stm8l15x_rtc
00008BCC _RTC_GetSubSecond stm8l15x_rtc
00008BDD _RTC_SetDate stm8l15x_rtc
00008C84 _RTC_DateStructInit stm8l15x_rtc
00008C98 _RTC_GetDate stm8l15x_rtc
00008CF1 _RTC_SetAlarm stm8l15x_rtc
00008DE9 _RTC_AlarmStructInit stm8l15x_rtc
00008E03 _RTC_GetAlarm stm8l15x_rtc
00008EB5 _RTC_AlarmCmd stm8l15x_rtc
00008EFD _RTC_AlarmSubSecondConfig stm8l15x_rtc
00008F38 _RTC_WakeUpClockConfig stm8l15x_rtc
00008F5D _RTC_SetWakeUpCounter stm8l15x_rtc
00008F72 _RTC_GetWakeUpCounter stm8l15x_rtc
00008F80 _RTC_WakeUpCmd stm8l15x_rtc
00008FBE _RTC_DayLightSavingConfig stm8l15x_rtc
00008FE5 _RTC_GetStoreOperation stm8l15x_rtc
00008FEB _RTC_OutputConfig stm8l15x_rtc
00009012 _RTC_SynchroShiftConfig stm8l15x_rtc
0000904D _RTC_SmoothCalibConfig stm8l15x_rtc
0000908F _RTC_CalibOutputConfig stm8l15x_rtc
000090B3 _RTC_CalibOutputCmd stm8l15x_rtc
000090D7 _RTC_TamperLevelConfig stm8l15x_rtc
00009101 _RTC_TamperFilterConfig stm8l15x_rtc
00009122 _RTC_TamperSamplingFreqConfig stm8l15x_rtc
00009143 _RTC_TamperPinsPrechargeDuration stm8l15x_rtc
00009164 _RTC_TamperCmd stm8l15x_rtc
0000918E _RTC_ITConfig stm8l15x_rtc
000091D6 _RTC_GetFlagStatus stm8l15x_rtc
000091FB _RTC_ClearFlag stm8l15x_rtc
00009208 _RTC_GetITStatus stm8l15x_rtc
0000922C _RTC_ClearITPendingBit stm8l15x_rtc
0000925C __divulong _divulong
000092B7 ___sdcc_external_startup _startup
ASxxxx Linker V03.00/V05.40 + sdld, page 10.
Files Linked [ module(s) ]
../STM8L15X_LD/main.rel [ main ]
../STM8L15X_LD/stm8l15x_it.rel [ stm8l15x_it ]
../STM8L15X_LD/stm8l15x_usart.rel [ stm8l15x_usart ]
../STM8L15X_LD/stm8l15x_clk.rel [ stm8l15x_clk ]
../STM8L15X_LD/stm8l15x_gpio.rel [ stm8l15x_gpio ]
../STM8L15X_LD/stm8l15x_rtc.rel [ stm8l15x_rtc ]
Libraries Linked [ object file ]
/opt/sdcc/bin/../share/sdcc/lib/stm8/stm8.lib
[ _divulong.rel ]
/opt/sdcc/bin/../share/sdcc/lib/stm8/stm8.lib
[ _startup.rel ]
ASxxxx Linker V03.00/V05.40 + sdld, page 11.
User Base Address Definitions
HOME = 0x8000
DATA = 0x0001

324
firmware/STM8L15X_LD/main.asm Normal file
View File

@@ -0,0 +1,324 @@
;--------------------------------------------------------
; File Created by SDCC : free open source ISO C Compiler
; Version 4.5.0 #15242 (Linux)
;--------------------------------------------------------
.module main
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _main
.globl _USART_Cmd
.globl _USART_Init
.globl _GPIO_ResetBits
.globl _GPIO_SetBits
.globl _GPIO_Init
.globl _CLK_PeripheralClockConfig
.globl _CLK_SYSCLKSourceSwitchCmd
.globl _CLK_SYSCLKDivConfig
.globl _CLK_GetSYSCLKSource
.globl _CLK_SYSCLKSourceConfig
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area DATA
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area INITIALIZED
;--------------------------------------------------------
; Stack segment in internal ram
;--------------------------------------------------------
.area SSEG
__start__stack:
.ds 1
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area DABS (ABS)
; default segment ordering for linker
.area HOME
.area GSINIT
.area GSFINAL
.area CONST
.area INITIALIZER
.area CODE
;--------------------------------------------------------
; interrupt vector
;--------------------------------------------------------
.area HOME
__interrupt_vect:
int s_GSINIT ; reset
int _TRAP_IRQHandler ; trap
int 0x000000 ; int0
int _FLASH_IRQHandler ; int1
int _DMA1_CHANNEL0_1_IRQHandler ; int2
int _DMA1_CHANNEL2_3_IRQHandler ; int3
int _RTC_CSSLSE_IRQHandler ; int4
int _EXTIE_F_PVD_IRQHandler ; int5
int _EXTIB_G_IRQHandler ; int6
int _EXTID_H_IRQHandler ; int7
int _EXTI0_IRQHandler ; int8
int _EXTI1_IRQHandler ; int9
int _EXTI2_IRQHandler ; int10
int _EXTI3_IRQHandler ; int11
int _EXTI4_IRQHandler ; int12
int _EXTI5_IRQHandler ; int13
int _EXTI6_IRQHandler ; int14
int _EXTI7_IRQHandler ; int15
int _LCD_AES_IRQHandler ; int16
int _SWITCH_CSS_BREAK_DAC_IRQHandler ; int17
int _ADC1_COMP_IRQHandler ; int18
int _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler ; int19
int _TIM2_CC_USART2_RX_IRQHandler ; int20
int _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler ; int21
int _TIM3_CC_USART3_RX_IRQHandler ; int22
int _TIM1_UPD_OVF_TRG_COM_IRQHandler ; int23
int _TIM1_CC_IRQHandler ; int24
int _TIM4_UPD_OVF_TRG_IRQHandler ; int25
int _SPI1_IRQHandler ; int26
int _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler ; int27
int _USART1_RX_TIM5_CC_IRQHandler ; int28
int _I2C1_SPI2_IRQHandler ; int29
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area HOME
.area GSINIT
.area GSFINAL
.area GSINIT
call ___sdcc_external_startup
tnz a
jreq __sdcc_init_data
jp __sdcc_program_startup
__sdcc_init_data:
; stm8_genXINIT() start
ldw x, #l_DATA
jreq 00002$
00001$:
clr (s_DATA - 1, x)
decw x
jrne 00001$
00002$:
ldw x, #l_INITIALIZER
jreq 00004$
00003$:
ld a, (s_INITIALIZER - 1, x)
ld (s_INITIALIZED - 1, x), a
decw x
jrne 00003$
00004$:
; stm8_genXINIT() end
.area GSFINAL
jp __sdcc_program_startup
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area HOME
.area HOME
__sdcc_program_startup:
jp _main
; return from main will return to caller
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area CODE
; ../src/main.c: 24: void main(void)
; -----------------------------------------
; function main
; -----------------------------------------
_main:
; ../src/main.c: 27: Led_Init;
push #0xc0
ld a, #0x10
ldw x, #0x500a
call _GPIO_Init
; ../src/main.c: 28: blink(1);
clrw x
incw x
call _blink
; ../src/main.c: 29: USART_Config();
call _USART_Config
; ../src/main.c: 30: println("Hello");
ldw x, #(___str_0+0)
call _println
; ../src/main.c: 31: while (1);
00102$:
jra 00102$
; ../src/main.c: 32: }
ret
; ../src/main.c: 34: static void CLK_Config(void)
; -----------------------------------------
; function CLK_Config
; -----------------------------------------
_CLK_Config:
; ../src/main.c: 37: CLK_SYSCLKSourceSwitchCmd(ENABLE);
ld a, #0x01
call _CLK_SYSCLKSourceSwitchCmd
; ../src/main.c: 38: CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_LSE);
ld a, #0x08
call _CLK_SYSCLKSourceConfig
; ../src/main.c: 40: CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_1);
clr a
call _CLK_SYSCLKDivConfig
; ../src/main.c: 41: while (CLK_GetSYSCLKSource() != CLK_SYSCLKSource_LSE);
00101$:
call _CLK_GetSYSCLKSource
cp a, #0x08
jrne 00101$
ret
jra 00101$
; ../src/main.c: 42: }
ret
; ../src/main.c: 44: static void blink(uint16_t repeats) {
; -----------------------------------------
; function blink
; -----------------------------------------
_blink:
sub sp, #4
ldw (0x01, sp), x
; ../src/main.c: 45: for (uint16_t i = 0; i <= repeats; i++) {
clrw x
ldw (0x03, sp), x
00111$:
ldw x, (0x03, sp)
cpw x, (0x01, sp)
jrugt 00113$
; ../src/main.c: 46: Led_ON;
ld a, #0x10
ldw x, #0x500a
call _GPIO_SetBits
; ../src/main.c: 47: for (uint16_t j = 0; j <= 4000; j++) {nop();}
clrw x
00105$:
ldw y, x
cpw y, #0x0fa0
jrugt 00101$
nop
incw x
jra 00105$
00101$:
; ../src/main.c: 48: Led_OFF;
ld a, #0x10
ldw x, #0x500a
call _GPIO_ResetBits
; ../src/main.c: 49: for (uint16_t j = 0; j <= 4000; j++) {nop();}
clrw x
00108$:
ldw y, x
cpw y, #0x0fa0
jrugt 00112$
nop
incw x
jra 00108$
00112$:
; ../src/main.c: 45: for (uint16_t i = 0; i <= repeats; i++) {
ldw x, (0x03, sp)
incw x
ldw (0x03, sp), x
jra 00111$
00113$:
; ../src/main.c: 51: }
addw sp, #4
ret
; ../src/main.c: 53: static void putchar(uint8_t Data) {
; -----------------------------------------
; function putchar
; -----------------------------------------
_putchar:
; ../src/main.c: 54: while (!(USART1->SR & USART_FLAG_TXE));
00101$:
ldw x, #0x5230
push a
ld a, (x)
ld xh, a
pop a
tnzw x
jrpl 00101$
; ../src/main.c: 55: USART1->DR = Data;
ld 0x5231, a
; ../src/main.c: 56: }
ret
; ../src/main.c: 58: static void print(const char* s){
; -----------------------------------------
; function print
; -----------------------------------------
_print:
; ../src/main.c: 59: while (*s) {
00101$:
ld a, (x)
jrne 00121$
ret
00121$:
; ../src/main.c: 60: putchar(*s++);
incw x
pushw x
call _putchar
popw x
jra 00101$
; ../src/main.c: 62: }
ret
; ../src/main.c: 64: static void println(const char* s){
; -----------------------------------------
; function println
; -----------------------------------------
_println:
; ../src/main.c: 65: print(s);
call _print
; ../src/main.c: 66: putchar('\n');
ld a, #0x0a
; ../src/main.c: 67: }
jp _putchar
; ../src/main.c: 69: static void USART_Config(void)
; -----------------------------------------
; function USART_Config
; -----------------------------------------
_USART_Config:
; ../src/main.c: 72: SYSCFG->RMPCR1 &= ~(0b11 << 4);
ld a, 0x509e
and a, #0xcf
ld 0x509e, a
; ../src/main.c: 73: SYSCFG->RMPCR1 |= (0b01 << 4);
bset 0x509e, #4
; ../src/main.c: 75: GPIO_Init(GPIOA, GPIO_Pin_2, GPIO_Mode_Out_PP_High_Fast);
push #0xf0
ld a, #0x04
ldw x, #0x5000
call _GPIO_Init
; ../src/main.c: 76: GPIO_Init(GPIOA, GPIO_Pin_3, GPIO_Mode_In_FL_No_IT);
push #0x00
ld a, #0x08
ldw x, #0x5000
call _GPIO_Init
; ../src/main.c: 78: CLK_PeripheralClockConfig(CLK_Peripheral_USART1, ENABLE);
push #0x01
ld a, #0x05
call _CLK_PeripheralClockConfig
; ../src/main.c: 80: USART_Init(USART1, (uint32_t)9600,
push #0x08
push #0x00
push #0x00
push #0x00
push #0x80
push #0x25
clrw x
pushw x
ldw x, #0x5230
call _USART_Init
; ../src/main.c: 83: USART_Cmd(USART1, ENABLE);
ld a, #0x01
ldw x, #0x5230
; ../src/main.c: 84: }
jp _USART_Cmd
.area CODE
.area CONST
.area CONST
___str_0:
.ascii "Hello"
.db 0x00
.area CODE
.area INITIALIZER
.area CABS (ABS)

324
firmware/STM8L15X_LD/main.lst Normal file
View File

@@ -0,0 +1,324 @@
1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ISO C Compiler
3 ; Version 4.5.0 #15242 (Linux)
4 ;--------------------------------------------------------
5 .module main
6
7 ;--------------------------------------------------------
8 ; Public variables in this module
9 ;--------------------------------------------------------
10 .globl _main
11 .globl _USART_Cmd
12 .globl _USART_Init
13 .globl _GPIO_ResetBits
14 .globl _GPIO_SetBits
15 .globl _GPIO_Init
16 .globl _CLK_PeripheralClockConfig
17 .globl _CLK_SYSCLKSourceSwitchCmd
18 .globl _CLK_SYSCLKDivConfig
19 .globl _CLK_GetSYSCLKSource
20 .globl _CLK_SYSCLKSourceConfig
21 ;--------------------------------------------------------
22 ; ram data
23 ;--------------------------------------------------------
24 .area DATA
25 ;--------------------------------------------------------
26 ; ram data
27 ;--------------------------------------------------------
28 .area INITIALIZED
29 ;--------------------------------------------------------
30 ; Stack segment in internal ram
31 ;--------------------------------------------------------
32 .area SSEG
000000 33 __start__stack:
000000 34 .ds 1
35
36 ;--------------------------------------------------------
37 ; absolute external ram data
38 ;--------------------------------------------------------
39 .area DABS (ABS)
40
41 ; default segment ordering for linker
42 .area HOME
43 .area GSINIT
44 .area GSFINAL
45 .area CONST
46 .area INITIALIZER
47 .area CODE
48
49 ;--------------------------------------------------------
50 ; interrupt vector
51 ;--------------------------------------------------------
52 .area HOME
000000 53 __interrupt_vect:
000000 82v00u00u00 54 int s_GSINIT ; reset
000004 82v00u00u00 55 int _TRAP_IRQHandler ; trap
000008 82 00 00 00 56 int 0x000000 ; int0
00000C 82v00u00u00 57 int _FLASH_IRQHandler ; int1
000010 82v00u00u00 58 int _DMA1_CHANNEL0_1_IRQHandler ; int2
000014 82v00u00u00 59 int _DMA1_CHANNEL2_3_IRQHandler ; int3
000018 82v00u00u00 60 int _RTC_CSSLSE_IRQHandler ; int4
00001C 82v00u00u00 61 int _EXTIE_F_PVD_IRQHandler ; int5
000020 82v00u00u00 62 int _EXTIB_G_IRQHandler ; int6
000024 82v00u00u00 63 int _EXTID_H_IRQHandler ; int7
000028 82v00u00u00 64 int _EXTI0_IRQHandler ; int8
00002C 82v00u00u00 65 int _EXTI1_IRQHandler ; int9
000030 82v00u00u00 66 int _EXTI2_IRQHandler ; int10
000034 82v00u00u00 67 int _EXTI3_IRQHandler ; int11
000038 82v00u00u00 68 int _EXTI4_IRQHandler ; int12
00003C 82v00u00u00 69 int _EXTI5_IRQHandler ; int13
000040 82v00u00u00 70 int _EXTI6_IRQHandler ; int14
000044 82v00u00u00 71 int _EXTI7_IRQHandler ; int15
000048 82v00u00u00 72 int _LCD_AES_IRQHandler ; int16
00004C 82v00u00u00 73 int _SWITCH_CSS_BREAK_DAC_IRQHandler ; int17
000050 82v00u00u00 74 int _ADC1_COMP_IRQHandler ; int18
000054 82v00u00u00 75 int _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler ; int19
000058 82v00u00u00 76 int _TIM2_CC_USART2_RX_IRQHandler ; int20
00005C 82v00u00u00 77 int _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler ; int21
000060 82v00u00u00 78 int _TIM3_CC_USART3_RX_IRQHandler ; int22
000064 82v00u00u00 79 int _TIM1_UPD_OVF_TRG_COM_IRQHandler ; int23
000068 82v00u00u00 80 int _TIM1_CC_IRQHandler ; int24
00006C 82v00u00u00 81 int _TIM4_UPD_OVF_TRG_IRQHandler ; int25
000070 82v00u00u00 82 int _SPI1_IRQHandler ; int26
000074 82v00u00u00 83 int _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler ; int27
000078 82v00u00u00 84 int _USART1_RX_TIM5_CC_IRQHandler ; int28
00007C 82v00u00u00 85 int _I2C1_SPI2_IRQHandler ; int29
86 ;--------------------------------------------------------
87 ; global & static initialisations
88 ;--------------------------------------------------------
89 .area HOME
90 .area GSINIT
91 .area GSFINAL
92 .area GSINIT
000000 CDr00r00 [ 4] 93 call ___sdcc_external_startup
000003 4D [ 1] 94 tnz a
000004 27 03 [ 1] 95 jreq __sdcc_init_data
000006 CCr00r80 [ 2] 96 jp __sdcc_program_startup
000009 97 __sdcc_init_data:
98 ; stm8_genXINIT() start
000009 AEr00r00 [ 2] 99 ldw x, #l_DATA
00000C 27 07 [ 1] 100 jreq 00002$
00000E 101 00001$:
00000E 72 4FuFFuFF [ 1] 102 clr (s_DATA - 1, x)
000012 5A [ 2] 103 decw x
000013 26 F9 [ 1] 104 jrne 00001$
000015 105 00002$:
000015 AEr00r00 [ 2] 106 ldw x, #l_INITIALIZER
000018 27 09 [ 1] 107 jreq 00004$
00001A 108 00003$:
00001A D6uFFuFF [ 1] 109 ld a, (s_INITIALIZER - 1, x)
00001D D7uFFuFF [ 1] 110 ld (s_INITIALIZED - 1, x), a
000020 5A [ 2] 111 decw x
000021 26 F7 [ 1] 112 jrne 00003$
000023 113 00004$:
114 ; stm8_genXINIT() end
115 .area GSFINAL
000000 CCr00r80 [ 2] 116 jp __sdcc_program_startup
117 ;--------------------------------------------------------
118 ; Home
119 ;--------------------------------------------------------
120 .area HOME
121 .area HOME
000080 122 __sdcc_program_startup:
000080 CCr00r00 [ 2] 123 jp _main
124 ; return from main will return to caller
125 ;--------------------------------------------------------
126 ; code
127 ;--------------------------------------------------------
128 .area CODE
129 ; ../src/main.c: 24: void main(void)
130 ; -----------------------------------------
131 ; function main
132 ; -----------------------------------------
000000 133 _main:
134 ; ../src/main.c: 27: Led_Init;
000000 4B C0 [ 1] 135 push #0xc0
000002 A6 10 [ 1] 136 ld a, #0x10
000004 AE 50 0A [ 2] 137 ldw x, #0x500a
000007 CDr00r00 [ 4] 138 call _GPIO_Init
139 ; ../src/main.c: 28: blink(1);
00000A 5F [ 1] 140 clrw x
00000B 5C [ 1] 141 incw x
00000C CDr00r34 [ 4] 142 call _blink
143 ; ../src/main.c: 29: USART_Config();
00000F CDr00r98 [ 4] 144 call _USART_Config
145 ; ../src/main.c: 30: println("Hello");
000012 AEr00r00 [ 2] 146 ldw x, #(___str_0+0)
000015 CDr00r90 [ 4] 147 call _println
148 ; ../src/main.c: 31: while (1);
000018 149 00102$:
000018 20 FE [ 2] 150 jra 00102$
151 ; ../src/main.c: 32: }
00001A 81 [ 4] 152 ret
153 ; ../src/main.c: 34: static void CLK_Config(void)
154 ; -----------------------------------------
155 ; function CLK_Config
156 ; -----------------------------------------
00001B 157 _CLK_Config:
158 ; ../src/main.c: 37: CLK_SYSCLKSourceSwitchCmd(ENABLE);
00001B A6 01 [ 1] 159 ld a, #0x01
00001D CDr00r00 [ 4] 160 call _CLK_SYSCLKSourceSwitchCmd
161 ; ../src/main.c: 38: CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_LSE);
000020 A6 08 [ 1] 162 ld a, #0x08
000022 CDr00r00 [ 4] 163 call _CLK_SYSCLKSourceConfig
164 ; ../src/main.c: 40: CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_1);
000025 4F [ 1] 165 clr a
000026 CDr00r00 [ 4] 166 call _CLK_SYSCLKDivConfig
167 ; ../src/main.c: 41: while (CLK_GetSYSCLKSource() != CLK_SYSCLKSource_LSE);
000029 168 00101$:
000029 CDr00r00 [ 4] 169 call _CLK_GetSYSCLKSource
00002C A1 08 [ 1] 170 cp a, #0x08
00002E 26 F9 [ 1] 171 jrne 00101$
000030 81 [ 4] 172 ret
000031 20 F6 [ 2] 173 jra 00101$
174 ; ../src/main.c: 42: }
000033 81 [ 4] 175 ret
176 ; ../src/main.c: 44: static void blink(uint16_t repeats) {
177 ; -----------------------------------------
178 ; function blink
179 ; -----------------------------------------
000034 180 _blink:
000034 52 04 [ 2] 181 sub sp, #4
000036 1F 01 [ 2] 182 ldw (0x01, sp), x
183 ; ../src/main.c: 45: for (uint16_t i = 0; i <= repeats; i++) {
000038 5F [ 1] 184 clrw x
000039 1F 03 [ 2] 185 ldw (0x03, sp), x
00003B 186 00111$:
00003B 1E 03 [ 2] 187 ldw x, (0x03, sp)
00003D 13 01 [ 2] 188 cpw x, (0x01, sp)
00003F 22 31 [ 1] 189 jrugt 00113$
190 ; ../src/main.c: 46: Led_ON;
000041 A6 10 [ 1] 191 ld a, #0x10
000043 AE 50 0A [ 2] 192 ldw x, #0x500a
000046 CDr00r00 [ 4] 193 call _GPIO_SetBits
194 ; ../src/main.c: 47: for (uint16_t j = 0; j <= 4000; j++) {nop();}
000049 5F [ 1] 195 clrw x
00004A 196 00105$:
00004A 90 93 [ 1] 197 ldw y, x
00004C 90 A3 0F A0 [ 2] 198 cpw y, #0x0fa0
000050 22 04 [ 1] 199 jrugt 00101$
000052 9D [ 1] 200 nop
000053 5C [ 1] 201 incw x
000054 20 F4 [ 2] 202 jra 00105$
000056 203 00101$:
204 ; ../src/main.c: 48: Led_OFF;
000056 A6 10 [ 1] 205 ld a, #0x10
000058 AE 50 0A [ 2] 206 ldw x, #0x500a
00005B CDr00r00 [ 4] 207 call _GPIO_ResetBits
208 ; ../src/main.c: 49: for (uint16_t j = 0; j <= 4000; j++) {nop();}
00005E 5F [ 1] 209 clrw x
00005F 210 00108$:
00005F 90 93 [ 1] 211 ldw y, x
000061 90 A3 0F A0 [ 2] 212 cpw y, #0x0fa0
000065 22 04 [ 1] 213 jrugt 00112$
000067 9D [ 1] 214 nop
000068 5C [ 1] 215 incw x
000069 20 F4 [ 2] 216 jra 00108$
00006B 217 00112$:
218 ; ../src/main.c: 45: for (uint16_t i = 0; i <= repeats; i++) {
00006B 1E 03 [ 2] 219 ldw x, (0x03, sp)
00006D 5C [ 1] 220 incw x
00006E 1F 03 [ 2] 221 ldw (0x03, sp), x
000070 20 C9 [ 2] 222 jra 00111$
000072 223 00113$:
224 ; ../src/main.c: 51: }
000072 5B 04 [ 2] 225 addw sp, #4
000074 81 [ 4] 226 ret
227 ; ../src/main.c: 53: static void putchar(uint8_t Data) {
228 ; -----------------------------------------
229 ; function putchar
230 ; -----------------------------------------
000075 231 _putchar:
232 ; ../src/main.c: 54: while (!(USART1->SR & USART_FLAG_TXE));
000075 233 00101$:
000075 AE 52 30 [ 2] 234 ldw x, #0x5230
000078 88 [ 1] 235 push a
000079 F6 [ 1] 236 ld a, (x)
00007A 95 [ 1] 237 ld xh, a
00007B 84 [ 1] 238 pop a
00007C 5D [ 2] 239 tnzw x
00007D 2A F6 [ 1] 240 jrpl 00101$
241 ; ../src/main.c: 55: USART1->DR = Data;
00007F C7 52 31 [ 1] 242 ld 0x5231, a
243 ; ../src/main.c: 56: }
000082 81 [ 4] 244 ret
245 ; ../src/main.c: 58: static void print(const char* s){
246 ; -----------------------------------------
247 ; function print
248 ; -----------------------------------------
000083 249 _print:
250 ; ../src/main.c: 59: while (*s) {
000083 251 00101$:
000083 F6 [ 1] 252 ld a, (x)
000084 26 01 [ 1] 253 jrne 00121$
000086 81 [ 4] 254 ret
000087 255 00121$:
256 ; ../src/main.c: 60: putchar(*s++);
000087 5C [ 1] 257 incw x
000088 89 [ 2] 258 pushw x
000089 CDr00r75 [ 4] 259 call _putchar
00008C 85 [ 2] 260 popw x
00008D 20 F4 [ 2] 261 jra 00101$
262 ; ../src/main.c: 62: }
00008F 81 [ 4] 263 ret
264 ; ../src/main.c: 64: static void println(const char* s){
265 ; -----------------------------------------
266 ; function println
267 ; -----------------------------------------
000090 268 _println:
269 ; ../src/main.c: 65: print(s);
000090 CDr00r83 [ 4] 270 call _print
271 ; ../src/main.c: 66: putchar('\n');
000093 A6 0A [ 1] 272 ld a, #0x0a
273 ; ../src/main.c: 67: }
000095 CCr00r75 [ 2] 274 jp _putchar
275 ; ../src/main.c: 69: static void USART_Config(void)
276 ; -----------------------------------------
277 ; function USART_Config
278 ; -----------------------------------------
000098 279 _USART_Config:
280 ; ../src/main.c: 72: SYSCFG->RMPCR1 &= ~(0b11 << 4);
000098 C6 50 9E [ 1] 281 ld a, 0x509e
00009B A4 CF [ 1] 282 and a, #0xcf
00009D C7 50 9E [ 1] 283 ld 0x509e, a
284 ; ../src/main.c: 73: SYSCFG->RMPCR1 |= (0b01 << 4);
0000A0 72 18 50 9E [ 1] 285 bset 0x509e, #4
286 ; ../src/main.c: 75: GPIO_Init(GPIOA, GPIO_Pin_2, GPIO_Mode_Out_PP_High_Fast);
0000A4 4B F0 [ 1] 287 push #0xf0
0000A6 A6 04 [ 1] 288 ld a, #0x04
0000A8 AE 50 00 [ 2] 289 ldw x, #0x5000
0000AB CDr00r00 [ 4] 290 call _GPIO_Init
291 ; ../src/main.c: 76: GPIO_Init(GPIOA, GPIO_Pin_3, GPIO_Mode_In_FL_No_IT);
0000AE 4B 00 [ 1] 292 push #0x00
0000B0 A6 08 [ 1] 293 ld a, #0x08
0000B2 AE 50 00 [ 2] 294 ldw x, #0x5000
0000B5 CDr00r00 [ 4] 295 call _GPIO_Init
296 ; ../src/main.c: 78: CLK_PeripheralClockConfig(CLK_Peripheral_USART1, ENABLE);
0000B8 4B 01 [ 1] 297 push #0x01
0000BA A6 05 [ 1] 298 ld a, #0x05
0000BC CDr00r00 [ 4] 299 call _CLK_PeripheralClockConfig
300 ; ../src/main.c: 80: USART_Init(USART1, (uint32_t)9600,
0000BF 4B 08 [ 1] 301 push #0x08
0000C1 4B 00 [ 1] 302 push #0x00
0000C3 4B 00 [ 1] 303 push #0x00
0000C5 4B 00 [ 1] 304 push #0x00
0000C7 4B 80 [ 1] 305 push #0x80
0000C9 4B 25 [ 1] 306 push #0x25
0000CB 5F [ 1] 307 clrw x
0000CC 89 [ 2] 308 pushw x
0000CD AE 52 30 [ 2] 309 ldw x, #0x5230
0000D0 CDr00r00 [ 4] 310 call _USART_Init
311 ; ../src/main.c: 83: USART_Cmd(USART1, ENABLE);
0000D3 A6 01 [ 1] 312 ld a, #0x01
0000D5 AE 52 30 [ 2] 313 ldw x, #0x5230
314 ; ../src/main.c: 84: }
0000D8 CCr00r00 [ 2] 315 jp _USART_Cmd
316 .area CODE
317 .area CONST
318 .area CONST
000000 319 ___str_0:
000000 48 65 6C 6C 6F 320 .ascii "Hello"
000005 00 321 .db 0x00
322 .area CODE
323 .area INITIALIZER
324 .area CABS (ABS)

220
firmware/STM8L15X_LD/main.rel Normal file
View File

@@ -0,0 +1,220 @@
XH3
H C areas 31 global symbols
M main
S _GPIO_Init Ref000000
S _CLK_GetSYSCLKSource Ref000000
S _GPIO_ResetBits Ref000000
S _DMA1_CHANNEL0_1_IRQHandler Ref000000
S _SPI1_IRQHandler Ref000000
S _DMA1_CHANNEL2_3_IRQHandler Ref000000
S s_INITIALIZED Ref000000
S _EXTIB_G_IRQHandler Ref000000
S _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler Ref000000
S _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler Ref000000
S _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler Ref000000
S _EXTID_H_IRQHandler Ref000000
S l_INITIALIZER Ref000000
S _TIM2_CC_USART2_RX_IRQHandler Ref000000
S _EXTI0_IRQHandler Ref000000
S _EXTI1_IRQHandler Ref000000
S _I2C1_SPI2_IRQHandler Ref000000
S _USART1_RX_TIM5_CC_IRQHandler Ref000000
S _TIM3_CC_USART3_RX_IRQHandler Ref000000
S _EXTI2_IRQHandler Ref000000
S _EXTI3_IRQHandler Ref000000
S _EXTIE_F_PVD_IRQHandler Ref000000
S s_INITIALIZER Ref000000
S _EXTI4_IRQHandler Ref000000
S _FLASH_IRQHandler Ref000000
S _EXTI5_IRQHandler Ref000000
S _EXTI6_IRQHandler Ref000000
S _EXTI7_IRQHandler Ref000000
S .__.ABS. Def000000
S _TIM1_UPD_OVF_TRG_COM_IRQHandler Ref000000
S _TRAP_IRQHandler Ref000000
S s_GSINIT Ref000000
S _USART_Init Ref000000
S _USART_Cmd Ref000000
S _TIM4_UPD_OVF_TRG_IRQHandler Ref000000
S l_DATA Ref000000
S _CLK_PeripheralClockConfig Ref000000
S _TIM1_CC_IRQHandler Ref000000
S _CLK_SYSCLKSourceSwitchCmd Ref000000
S _CLK_SYSCLKDivConfig Ref000000
S _GPIO_SetBits Ref000000
S s_DATA Ref000000
S _SWITCH_CSS_BREAK_DAC_IRQHandler Ref000000
S ___sdcc_external_startup Ref000000
S _ADC1_COMP_IRQHandler Ref000000
S _LCD_AES_IRQHandler Ref000000
S _CLK_SYSCLKSourceConfig Ref000000
S _RTC_CSSLSE_IRQHandler Ref000000
A _CODE size 0 flags 0 addr 0
A DATA size 0 flags 0 addr 0
A INITIALIZED size 0 flags 0 addr 0
A SSEG size 1 flags 0 addr 0
A DABS size 0 flags 8 addr 0
A HOME size 83 flags 0 addr 0
A GSINIT size 23 flags 0 addr 0
A GSFINAL size 3 flags 0 addr 0
A CONST size 6 flags 0 addr 0
A INITIALIZER size 0 flags 0 addr 0
A CODE size DB flags 0 addr 0
S _main Def000000
A CABS size 0 flags 8 addr 0
T 00 00 00
R 00 00 00 03
T 00 00 00
R 00 00 00 03
T 00 00 00
R 00 00 00 05
T 00 00 00 82 00 00 00 82 00 00 00 82 00 00 00 82
R 00 00 00 05 92 04 00 1F 92 08 00 1E
T 00 00 0D 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 18 92 07 00 03
T 00 00 15 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 05 92 07 00 2F
T 00 00 1D 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 15 92 07 00 07
T 00 00 25 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 0B 92 07 00 0E
T 00 00 2D 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 0F 92 07 00 13
T 00 00 35 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 14 92 07 00 17
T 00 00 3D 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 19 92 07 00 1A
T 00 00 45 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 1B 92 07 00 2D
T 00 00 4D 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 2A 92 07 00 2C
T 00 00 55 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 08 92 07 00 0D
T 00 00 5D 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 0A 92 07 00 12
T 00 00 65 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 1D 92 07 00 25
T 00 00 6D 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 22 92 07 00 04
T 00 00 75 00 00 00 82 00 00 00 82
R 00 00 00 05 92 03 00 09 92 07 00 11
T 00 00 7D 00 00 00
R 00 00 00 05 92 03 00 10
T 00 00 00 CD 00 00 4D 27 03 CC 00 80
R 00 00 00 06 02 04 00 2B 00 0A 00 05
T 00 00 09
R 00 00 00 06
T 00 00 09 AE 00 00 27 07
R 00 00 00 06 02 04 00 23
T 00 00 0E
R 00 00 00 06
T 00 00 0E 72 4F FF FF 5A 26 F9
R 00 00 00 06 12 05 00 29
T 00 00 15
R 00 00 00 06
T 00 00 15 AE 00 00 27 09
R 00 00 00 06 02 04 00 0C
T 00 00 1A
R 00 00 00 06
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R 00 00 00 06 12 04 00 16 12 07 00 06
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R 00 00 00 06
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R 00 00 00 07 00 04 00 05
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R 00 00 00 05
T 00 00 80 CC 00 00
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T 00 00 00 4B C0 A6 10 AE 50 0A CD 00 00 5F 5C CD
R 00 00 00 0A 02 0B 00 00
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R 00 00 00 0A 00 03 00 0A 00 06 00 0A
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R 00 00 00 0A 00 03 00 08 00 06 00 0A
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R 00 00 00 0A
T 00 00 18 20 FE 81
R 00 00 00 0A
T 00 00 1B
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R 00 00 00 0A 02 06 00 26 02 0B 00 2E
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R 00 00 00 0A 02 03 00 27
T 00 00 29
R 00 00 00 0A
T 00 00 29 CD 00 00 A1 08 26 F9 81 20 F6 81
R 00 00 00 0A 02 04 00 01
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R 00 00 00 0A
T 00 00 34 52 04 1F 01 5F 1F 03
R 00 00 00 0A
T 00 00 3B
R 00 00 00 0A
T 00 00 3B 1E 03 13 01 22 31 A6 10 AE 50 0A CD
R 00 00 00 0A
T 00 00 47 00 00 5F
R 00 00 00 0A 02 03 00 28
T 00 00 4A
R 00 00 00 0A
T 00 00 4A 90 93 90 A3 0F A0 22 04 9D 5C 20 F4
R 00 00 00 0A
T 00 00 56
R 00 00 00 0A
T 00 00 56 A6 10 AE 50 0A CD 00 00 5F
R 00 00 00 0A 02 09 00 02
T 00 00 5F
R 00 00 00 0A
T 00 00 5F 90 93 90 A3 0F A0 22 04 9D 5C 20 F4
R 00 00 00 0A
T 00 00 6B
R 00 00 00 0A
T 00 00 6B 1E 03 5C 1F 03 20 C9
R 00 00 00 0A
T 00 00 72
R 00 00 00 0A
T 00 00 72 5B 04 81
R 00 00 00 0A
T 00 00 75
R 00 00 00 0A
T 00 00 75
R 00 00 00 0A
T 00 00 75 AE 52 30 88 F6 95 84 5D 2A F6 C7 52 31
R 00 00 00 0A
T 00 00 82 81
R 00 00 00 0A
T 00 00 83
R 00 00 00 0A
T 00 00 83
R 00 00 00 0A
T 00 00 83 F6 26 01 81
R 00 00 00 0A
T 00 00 87
R 00 00 00 0A
T 00 00 87 5C 89 CD 00 75 85 20 F4 81
R 00 00 00 0A 00 06 00 0A
T 00 00 90
R 00 00 00 0A
T 00 00 90 CD 00 83 A6 0A CC 00 75
R 00 00 00 0A 00 04 00 0A 00 09 00 0A
T 00 00 98
R 00 00 00 0A
T 00 00 98 C6 50 9E A4 CF C7 50 9E 72 18 50 9E 4B
R 00 00 00 0A
T 00 00 A5 F0 A6 04 AE 50 00 CD 00 00 4B 00 A6 08
R 00 00 00 0A 02 0A 00 00
T 00 00 B2 AE 50 00 CD 00 00 4B 01 A6 05 CD 00 00
R 00 00 00 0A 02 07 00 00 02 0E 00 24
T 00 00 BF 4B 08 4B 00 4B 00 4B 00 4B 80 4B 25 5F
R 00 00 00 0A
T 00 00 CC 89 AE 52 30 CD 00 00 A6 01 AE 52 30 CC
R 00 00 00 0A 02 08 00 20
T 00 00 D9 00 00
R 00 00 00 0A 02 03 00 21
T 00 00 00
R 00 00 00 08
T 00 00 00 48 65 6C 6C 6F 00
R 00 00 00 08

324
firmware/STM8L15X_LD/main.rst Normal file
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1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ISO C Compiler
3 ; Version 4.5.0 #15242 (Linux)
4 ;--------------------------------------------------------
5 .module main
6
7 ;--------------------------------------------------------
8 ; Public variables in this module
9 ;--------------------------------------------------------
10 .globl _main
11 .globl _USART_Cmd
12 .globl _USART_Init
13 .globl _GPIO_ResetBits
14 .globl _GPIO_SetBits
15 .globl _GPIO_Init
16 .globl _CLK_PeripheralClockConfig
17 .globl _CLK_SYSCLKSourceSwitchCmd
18 .globl _CLK_SYSCLKDivConfig
19 .globl _CLK_GetSYSCLKSource
20 .globl _CLK_SYSCLKSourceConfig
21 ;--------------------------------------------------------
22 ; ram data
23 ;--------------------------------------------------------
24 .area DATA
25 ;--------------------------------------------------------
26 ; ram data
27 ;--------------------------------------------------------
28 .area INITIALIZED
29 ;--------------------------------------------------------
30 ; Stack segment in internal ram
31 ;--------------------------------------------------------
32 .area SSEG
000001 33 __start__stack:
000001 34 .ds 1
35
36 ;--------------------------------------------------------
37 ; absolute external ram data
38 ;--------------------------------------------------------
39 .area DABS (ABS)
40
41 ; default segment ordering for linker
42 .area HOME
43 .area GSINIT
44 .area GSFINAL
45 .area CONST
46 .area INITIALIZER
47 .area CODE
48
49 ;--------------------------------------------------------
50 ; interrupt vector
51 ;--------------------------------------------------------
52 .area HOME
008000 53 __interrupt_vect:
008000 82 00 80 83 54 int s_GSINIT ; reset
008004 82 00 81 8F 55 int _TRAP_IRQHandler ; trap
008008 82 00 00 00 56 int 0x000000 ; int0
00800C 82 00 81 90 57 int _FLASH_IRQHandler ; int1
008010 82 00 81 91 58 int _DMA1_CHANNEL0_1_IRQHandler ; int2
008014 82 00 81 92 59 int _DMA1_CHANNEL2_3_IRQHandler ; int3
008018 82 00 81 93 60 int _RTC_CSSLSE_IRQHandler ; int4
00801C 82 00 81 94 61 int _EXTIE_F_PVD_IRQHandler ; int5
008020 82 00 81 95 62 int _EXTIB_G_IRQHandler ; int6
008024 82 00 81 96 63 int _EXTID_H_IRQHandler ; int7
008028 82 00 81 97 64 int _EXTI0_IRQHandler ; int8
00802C 82 00 81 98 65 int _EXTI1_IRQHandler ; int9
008030 82 00 81 99 66 int _EXTI2_IRQHandler ; int10
008034 82 00 81 9A 67 int _EXTI3_IRQHandler ; int11
008038 82 00 81 9B 68 int _EXTI4_IRQHandler ; int12
00803C 82 00 81 9C 69 int _EXTI5_IRQHandler ; int13
008040 82 00 81 9D 70 int _EXTI6_IRQHandler ; int14
008044 82 00 81 9E 71 int _EXTI7_IRQHandler ; int15
008048 82 00 81 9F 72 int _LCD_AES_IRQHandler ; int16
00804C 82 00 81 A0 73 int _SWITCH_CSS_BREAK_DAC_IRQHandler ; int17
008050 82 00 81 A1 74 int _ADC1_COMP_IRQHandler ; int18
008054 82 00 81 A2 75 int _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler ; int19
008058 82 00 81 A3 76 int _TIM2_CC_USART2_RX_IRQHandler ; int20
00805C 82 00 81 A4 77 int _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler ; int21
008060 82 00 81 A5 78 int _TIM3_CC_USART3_RX_IRQHandler ; int22
008064 82 00 81 A6 79 int _TIM1_UPD_OVF_TRG_COM_IRQHandler ; int23
008068 82 00 81 A7 80 int _TIM1_CC_IRQHandler ; int24
00806C 82 00 81 A8 81 int _TIM4_UPD_OVF_TRG_IRQHandler ; int25
008070 82 00 81 A9 82 int _SPI1_IRQHandler ; int26
008074 82 00 81 AA 83 int _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler ; int27
008078 82 00 81 AB 84 int _USART1_RX_TIM5_CC_IRQHandler ; int28
00807C 82 00 81 AC 85 int _I2C1_SPI2_IRQHandler ; int29
86 ;--------------------------------------------------------
87 ; global & static initialisations
88 ;--------------------------------------------------------
89 .area HOME
90 .area GSINIT
91 .area GSFINAL
92 .area GSINIT
008083 CD 92 B7 [ 4] 93 call ___sdcc_external_startup
008086 4D [ 1] 94 tnz a
008087 27 03 [ 1] 95 jreq __sdcc_init_data
008089 CC 80 80 [ 2] 96 jp __sdcc_program_startup
00808C 97 __sdcc_init_data:
98 ; stm8_genXINIT() start
00808C AE 00 00 [ 2] 99 ldw x, #l_DATA
00808F 27 07 [ 1] 100 jreq 00002$
008091 101 00001$:
008091 72 4F 00 00 [ 1] 102 clr (s_DATA - 1, x)
008095 5A [ 2] 103 decw x
008096 26 F9 [ 1] 104 jrne 00001$
008098 105 00002$:
008098 AE 00 00 [ 2] 106 ldw x, #l_INITIALIZER
00809B 27 09 [ 1] 107 jreq 00004$
00809D 108 00003$:
00809D D6 80 B3 [ 1] 109 ld a, (s_INITIALIZER - 1, x)
0080A0 D7 00 00 [ 1] 110 ld (s_INITIALIZED - 1, x), a
0080A3 5A [ 2] 111 decw x
0080A4 26 F7 [ 1] 112 jrne 00003$
0080A6 113 00004$:
114 ; stm8_genXINIT() end
115 .area GSFINAL
0080A6 CC 80 80 [ 2] 116 jp __sdcc_program_startup
117 ;--------------------------------------------------------
118 ; Home
119 ;--------------------------------------------------------
120 .area HOME
121 .area HOME
008080 122 __sdcc_program_startup:
008080 CC 80 B4 [ 2] 123 jp _main
124 ; return from main will return to caller
125 ;--------------------------------------------------------
126 ; code
127 ;--------------------------------------------------------
128 .area CODE
129 ; ../src/main.c: 24: void main(void)
130 ; -----------------------------------------
131 ; function main
132 ; -----------------------------------------
0080B4 133 _main:
134 ; ../src/main.c: 27: Led_Init;
0080B4 4B C0 [ 1] 135 push #0xc0
0080B6 A6 10 [ 1] 136 ld a, #0x10
0080B8 AE 50 0A [ 2] 137 ldw x, #0x500a
0080BB CD 88 28 [ 4] 138 call _GPIO_Init
139 ; ../src/main.c: 28: blink(1);
0080BE 5F [ 1] 140 clrw x
0080BF 5C [ 1] 141 incw x
0080C0 CD 80 E8 [ 4] 142 call _blink
143 ; ../src/main.c: 29: USART_Config();
0080C3 CD 81 4C [ 4] 144 call _USART_Config
145 ; ../src/main.c: 30: println("Hello");
0080C6 AE 80 A9 [ 2] 146 ldw x, #(___str_0+0)
0080C9 CD 81 44 [ 4] 147 call _println
148 ; ../src/main.c: 31: while (1);
0080CC 149 00102$:
0080CC 20 FE [ 2] 150 jra 00102$
151 ; ../src/main.c: 32: }
0080CE 81 [ 4] 152 ret
153 ; ../src/main.c: 34: static void CLK_Config(void)
154 ; -----------------------------------------
155 ; function CLK_Config
156 ; -----------------------------------------
0080CF 157 _CLK_Config:
158 ; ../src/main.c: 37: CLK_SYSCLKSourceSwitchCmd(ENABLE);
0080CF A6 01 [ 1] 159 ld a, #0x01
0080D1 CD 86 2D [ 4] 160 call _CLK_SYSCLKSourceSwitchCmd
161 ; ../src/main.c: 38: CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_LSE);
0080D4 A6 08 [ 1] 162 ld a, #0x08
0080D6 CD 85 CE [ 4] 163 call _CLK_SYSCLKSourceConfig
164 ; ../src/main.c: 40: CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_1);
0080D9 4F [ 1] 165 clr a
0080DA CD 86 29 [ 4] 166 call _CLK_SYSCLKDivConfig
167 ; ../src/main.c: 41: while (CLK_GetSYSCLKSource() != CLK_SYSCLKSource_LSE);
0080DD 168 00101$:
0080DD CD 85 D2 [ 4] 169 call _CLK_GetSYSCLKSource
0080E0 A1 08 [ 1] 170 cp a, #0x08
0080E2 26 F9 [ 1] 171 jrne 00101$
0080E4 81 [ 4] 172 ret
0080E5 20 F6 [ 2] 173 jra 00101$
174 ; ../src/main.c: 42: }
0080E7 81 [ 4] 175 ret
176 ; ../src/main.c: 44: static void blink(uint16_t repeats) {
177 ; -----------------------------------------
178 ; function blink
179 ; -----------------------------------------
0080E8 180 _blink:
0080E8 52 04 [ 2] 181 sub sp, #4
0080EA 1F 01 [ 2] 182 ldw (0x01, sp), x
183 ; ../src/main.c: 45: for (uint16_t i = 0; i <= repeats; i++) {
0080EC 5F [ 1] 184 clrw x
0080ED 1F 03 [ 2] 185 ldw (0x03, sp), x
0080EF 186 00111$:
0080EF 1E 03 [ 2] 187 ldw x, (0x03, sp)
0080F1 13 01 [ 2] 188 cpw x, (0x01, sp)
0080F3 22 31 [ 1] 189 jrugt 00113$
190 ; ../src/main.c: 46: Led_ON;
0080F5 A6 10 [ 1] 191 ld a, #0x10
0080F7 AE 50 0A [ 2] 192 ldw x, #0x500a
0080FA CD 88 D6 [ 4] 193 call _GPIO_SetBits
194 ; ../src/main.c: 47: for (uint16_t j = 0; j <= 4000; j++) {nop();}
0080FD 5F [ 1] 195 clrw x
0080FE 196 00105$:
0080FE 90 93 [ 1] 197 ldw y, x
008100 90 A3 0F A0 [ 2] 198 cpw y, #0x0fa0
008104 22 04 [ 1] 199 jrugt 00101$
008106 9D [ 1] 200 nop
008107 5C [ 1] 201 incw x
008108 20 F4 [ 2] 202 jra 00105$
00810A 203 00101$:
204 ; ../src/main.c: 48: Led_OFF;
00810A A6 10 [ 1] 205 ld a, #0x10
00810C AE 50 0A [ 2] 206 ldw x, #0x500a
00810F CD 88 DF [ 4] 207 call _GPIO_ResetBits
208 ; ../src/main.c: 49: for (uint16_t j = 0; j <= 4000; j++) {nop();}
008112 5F [ 1] 209 clrw x
008113 210 00108$:
008113 90 93 [ 1] 211 ldw y, x
008115 90 A3 0F A0 [ 2] 212 cpw y, #0x0fa0
008119 22 04 [ 1] 213 jrugt 00112$
00811B 9D [ 1] 214 nop
00811C 5C [ 1] 215 incw x
00811D 20 F4 [ 2] 216 jra 00108$
00811F 217 00112$:
218 ; ../src/main.c: 45: for (uint16_t i = 0; i <= repeats; i++) {
00811F 1E 03 [ 2] 219 ldw x, (0x03, sp)
008121 5C [ 1] 220 incw x
008122 1F 03 [ 2] 221 ldw (0x03, sp), x
008124 20 C9 [ 2] 222 jra 00111$
008126 223 00113$:
224 ; ../src/main.c: 51: }
008126 5B 04 [ 2] 225 addw sp, #4
008128 81 [ 4] 226 ret
227 ; ../src/main.c: 53: static void putchar(uint8_t Data) {
228 ; -----------------------------------------
229 ; function putchar
230 ; -----------------------------------------
008129 231 _putchar:
232 ; ../src/main.c: 54: while (!(USART1->SR & USART_FLAG_TXE));
008129 233 00101$:
008129 AE 52 30 [ 2] 234 ldw x, #0x5230
00812C 88 [ 1] 235 push a
00812D F6 [ 1] 236 ld a, (x)
00812E 95 [ 1] 237 ld xh, a
00812F 84 [ 1] 238 pop a
008130 5D [ 2] 239 tnzw x
008131 2A F6 [ 1] 240 jrpl 00101$
241 ; ../src/main.c: 55: USART1->DR = Data;
008133 C7 52 31 [ 1] 242 ld 0x5231, a
243 ; ../src/main.c: 56: }
008136 81 [ 4] 244 ret
245 ; ../src/main.c: 58: static void print(const char* s){
246 ; -----------------------------------------
247 ; function print
248 ; -----------------------------------------
008137 249 _print:
250 ; ../src/main.c: 59: while (*s) {
008137 251 00101$:
008137 F6 [ 1] 252 ld a, (x)
008138 26 01 [ 1] 253 jrne 00121$
00813A 81 [ 4] 254 ret
00813B 255 00121$:
256 ; ../src/main.c: 60: putchar(*s++);
00813B 5C [ 1] 257 incw x
00813C 89 [ 2] 258 pushw x
00813D CD 81 29 [ 4] 259 call _putchar
008140 85 [ 2] 260 popw x
008141 20 F4 [ 2] 261 jra 00101$
262 ; ../src/main.c: 62: }
008143 81 [ 4] 263 ret
264 ; ../src/main.c: 64: static void println(const char* s){
265 ; -----------------------------------------
266 ; function println
267 ; -----------------------------------------
008144 268 _println:
269 ; ../src/main.c: 65: print(s);
008144 CD 81 37 [ 4] 270 call _print
271 ; ../src/main.c: 66: putchar('\n');
008147 A6 0A [ 1] 272 ld a, #0x0a
273 ; ../src/main.c: 67: }
008149 CC 81 29 [ 2] 274 jp _putchar
275 ; ../src/main.c: 69: static void USART_Config(void)
276 ; -----------------------------------------
277 ; function USART_Config
278 ; -----------------------------------------
00814C 279 _USART_Config:
280 ; ../src/main.c: 72: SYSCFG->RMPCR1 &= ~(0b11 << 4);
00814C C6 50 9E [ 1] 281 ld a, 0x509e
00814F A4 CF [ 1] 282 and a, #0xcf
008151 C7 50 9E [ 1] 283 ld 0x509e, a
284 ; ../src/main.c: 73: SYSCFG->RMPCR1 |= (0b01 << 4);
008154 72 18 50 9E [ 1] 285 bset 0x509e, #4
286 ; ../src/main.c: 75: GPIO_Init(GPIOA, GPIO_Pin_2, GPIO_Mode_Out_PP_High_Fast);
008158 4B F0 [ 1] 287 push #0xf0
00815A A6 04 [ 1] 288 ld a, #0x04
00815C AE 50 00 [ 2] 289 ldw x, #0x5000
00815F CD 88 28 [ 4] 290 call _GPIO_Init
291 ; ../src/main.c: 76: GPIO_Init(GPIOA, GPIO_Pin_3, GPIO_Mode_In_FL_No_IT);
008162 4B 00 [ 1] 292 push #0x00
008164 A6 08 [ 1] 293 ld a, #0x08
008166 AE 50 00 [ 2] 294 ldw x, #0x5000
008169 CD 88 28 [ 4] 295 call _GPIO_Init
296 ; ../src/main.c: 78: CLK_PeripheralClockConfig(CLK_Peripheral_USART1, ENABLE);
00816C 4B 01 [ 1] 297 push #0x01
00816E A6 05 [ 1] 298 ld a, #0x05
008170 CD 86 51 [ 4] 299 call _CLK_PeripheralClockConfig
300 ; ../src/main.c: 80: USART_Init(USART1, (uint32_t)9600,
008173 4B 08 [ 1] 301 push #0x08
008175 4B 00 [ 1] 302 push #0x00
008177 4B 00 [ 1] 303 push #0x00
008179 4B 00 [ 1] 304 push #0x00
00817B 4B 80 [ 1] 305 push #0x80
00817D 4B 25 [ 1] 306 push #0x25
00817F 5F [ 1] 307 clrw x
008180 89 [ 2] 308 pushw x
008181 AE 52 30 [ 2] 309 ldw x, #0x5230
008184 CD 81 C4 [ 4] 310 call _USART_Init
311 ; ../src/main.c: 83: USART_Cmd(USART1, ENABLE);
008187 A6 01 [ 1] 312 ld a, #0x01
008189 AE 52 30 [ 2] 313 ldw x, #0x5230
314 ; ../src/main.c: 84: }
00818C CC 82 7B [ 2] 315 jp _USART_Cmd
316 .area CODE
317 .area CONST
318 .area CONST
0080A9 319 ___str_0:
0080A9 48 65 6C 6C 6F 320 .ascii "Hello"
0080AE 00 321 .db 0x00
322 .area CODE
323 .area INITIALIZER
324 .area CABS (ABS)

92
firmware/STM8L15X_LD/main.sym Normal file
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ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 1
Hexadecimal [24-Bits]
Symbol Table
.__.$$$. = 002710 L
.__.ABS. = 000000 G
.__.CPU. = 000000 L
.__.H$L. = 000001 L
_ADC1_COMP_IRQHandler ****** GX
A _CLK_Config 00001B R
_CLK_GetSYSCLKSource ****** GX
_CLK_PeripheralClockConfig ****** GX
_CLK_SYSCLKDivConfig ****** GX
_CLK_SYSCLKSourceConfig ****** GX
_CLK_SYSCLKSourceSwitchCmd ****** GX
_DMA1_CHANNEL0_1_IRQHandler ****** GX
_DMA1_CHANNEL2_3_IRQHandler ****** GX
_EXTI0_IRQHandler ****** GX
_EXTI1_IRQHandler ****** GX
_EXTI2_IRQHandler ****** GX
_EXTI3_IRQHandler ****** GX
_EXTI4_IRQHandler ****** GX
_EXTI5_IRQHandler ****** GX
_EXTI6_IRQHandler ****** GX
_EXTI7_IRQHandler ****** GX
_EXTIB_G_IRQHandler ****** GX
_EXTID_H_IRQHandler ****** GX
_EXTIE_F_PVD_IRQHandler ****** GX
_FLASH_IRQHandler ****** GX
_GPIO_Init ****** GX
_GPIO_ResetBits ****** GX
_GPIO_SetBits ****** GX
_I2C1_SPI2_IRQHandler ****** GX
_LCD_AES_IRQHandler ****** GX
_RTC_CSSLSE_IRQHandler ****** GX
_SPI1_IRQHandler ****** GX
_SWITCH_CSS_BREAK_DAC_IRQHandler ****** GX
_TIM1_CC_IRQHandler ****** GX
_TIM1_UPD_OVF_TRG_COM_IRQHandler ****** GX
_TIM2_CC_USART2_RX_IRQHandler ****** GX
_TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler ****** GX
_TIM3_CC_USART3_RX_IRQHandler ****** GX
_TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler ****** GX
_TIM4_UPD_OVF_TRG_IRQHandler ****** GX
_TRAP_IRQHandler ****** GX
_USART1_RX_TIM5_CC_IRQHandler ****** GX
_USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler ****** GX
_USART_Cmd ****** GX
A _USART_Config 000098 R
_USART_Init ****** GX
___sdcc_external_startup ****** GX
8 ___str_0 000000 R
5 __interrupt_vect 000000 R
6 __sdcc_init_data 000009 R
5 __sdcc_program_startup 000080 R
3 __start__stack 000000 R
A _blink 000034 R
A _main 000000 GR
A _print 000083 R
ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 2
Hexadecimal [24-Bits]
Symbol Table
A _println 000090 R
A _putchar 000075 R
l_DATA ****** GX
l_INITIALIZER ****** GX
s_DATA ****** GX
s_GSINIT ****** GX
s_INITIALIZED ****** GX
s_INITIALIZER ****** GX
ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 3
Hexadecimal [24-Bits]
Area Table
0 _CODE size 0 flags 0
1 DATA size 0 flags 0
2 INITIALIZED size 0 flags 0
3 SSEG size 1 flags 0
4 DABS size 0 flags 8
5 HOME size 83 flags 0
6 GSINIT size 23 flags 0
7 GSFINAL size 3 flags 0
8 CONST size 6 flags 0
9 INITIALIZER size 0 flags 0
A CODE size DB flags 0
B CABS size 0 flags 8

823
firmware/STM8L15X_LD/stm8l15x_clk.asm Normal file
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;--------------------------------------------------------
; File Created by SDCC : free open source ISO C Compiler
; Version 4.5.0 #15242 (Linux)
;--------------------------------------------------------
.module stm8l15x_clk
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _SYSDivFactor
.globl _CLK_DeInit
.globl _CLK_HSICmd
.globl _CLK_AdjustHSICalibrationValue
.globl _CLK_LSICmd
.globl _CLK_HSEConfig
.globl _CLK_LSEConfig
.globl _CLK_ClockSecuritySystemEnable
.globl _CLK_ClockSecuritySytemDeglitchCmd
.globl _CLK_CCOConfig
.globl _CLK_SYSCLKSourceConfig
.globl _CLK_GetSYSCLKSource
.globl _CLK_GetClockFreq
.globl _CLK_SYSCLKDivConfig
.globl _CLK_SYSCLKSourceSwitchCmd
.globl _CLK_RTCClockConfig
.globl _CLK_BEEPClockConfig
.globl _CLK_PeripheralClockConfig
.globl _CLK_LSEClockSecuritySystemEnable
.globl _CLK_RTCCLKSwitchOnLSEFailureEnable
.globl _CLK_HaltConfig
.globl _CLK_MainRegulatorCmd
.globl _CLK_ITConfig
.globl _CLK_GetFlagStatus
.globl _CLK_ClearFlag
.globl _CLK_GetITStatus
.globl _CLK_ClearITPendingBit
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area DATA
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area INITIALIZED
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area DABS (ABS)
; default segment ordering for linker
.area HOME
.area GSINIT
.area GSFINAL
.area CONST
.area INITIALIZER
.area CODE
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area HOME
.area GSINIT
.area GSFINAL
.area GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area HOME
.area HOME
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area CODE
; ../inc/stm8l151x/src/stm8l15x_clk.c: 120: void CLK_DeInit(void)
; -----------------------------------------
; function CLK_DeInit
; -----------------------------------------
_CLK_DeInit:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 122: CLK->ICKCR = CLK_ICKCR_RESET_VALUE;
mov 0x50c2+0, #0x11
; ../inc/stm8l151x/src/stm8l15x_clk.c: 123: CLK->ECKCR = CLK_ECKCR_RESET_VALUE;
mov 0x50c6+0, #0x00
; ../inc/stm8l151x/src/stm8l15x_clk.c: 124: CLK->CRTCR = CLK_CRTCR_RESET_VALUE;
mov 0x50c1+0, #0x00
; ../inc/stm8l151x/src/stm8l15x_clk.c: 125: CLK->CBEEPR = CLK_CBEEPR_RESET_VALUE;
mov 0x50cb+0, #0x00
; ../inc/stm8l151x/src/stm8l15x_clk.c: 126: CLK->SWR = CLK_SWR_RESET_VALUE;
mov 0x50c8+0, #0x01
; ../inc/stm8l151x/src/stm8l15x_clk.c: 127: CLK->SWCR = CLK_SWCR_RESET_VALUE;
mov 0x50c9+0, #0x00
; ../inc/stm8l151x/src/stm8l15x_clk.c: 128: CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
mov 0x50c0+0, #0x03
; ../inc/stm8l151x/src/stm8l15x_clk.c: 129: CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
mov 0x50c3+0, #0x00
; ../inc/stm8l151x/src/stm8l15x_clk.c: 130: CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
mov 0x50c4+0, #0x80
; ../inc/stm8l151x/src/stm8l15x_clk.c: 131: CLK->PCKENR3 = CLK_PCKENR3_RESET_VALUE;
mov 0x50d0+0, #0x00
; ../inc/stm8l151x/src/stm8l15x_clk.c: 132: CLK->CSSR = CLK_CSSR_RESET_VALUE;
mov 0x50ca+0, #0x00
; ../inc/stm8l151x/src/stm8l15x_clk.c: 133: CLK->CCOR = CLK_CCOR_RESET_VALUE;
mov 0x50c5+0, #0x00
; ../inc/stm8l151x/src/stm8l15x_clk.c: 134: CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
mov 0x50cd+0, #0x00
; ../inc/stm8l151x/src/stm8l15x_clk.c: 135: CLK->HSICALR = CLK_HSICALR_RESET_VALUE;
mov 0x50cc+0, #0x00
; ../inc/stm8l151x/src/stm8l15x_clk.c: 136: CLK->HSIUNLCKR = CLK_HSIUNLCKR_RESET_VALUE;
mov 0x50ce+0, #0x00
; ../inc/stm8l151x/src/stm8l15x_clk.c: 137: CLK->REGCSR = CLK_REGCSR_RESET_VALUE;
mov 0x50cf+0, #0xb9
; ../inc/stm8l151x/src/stm8l15x_clk.c: 138: }
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 160: void CLK_HSICmd(FunctionalState NewState)
; -----------------------------------------
; function CLK_HSICmd
; -----------------------------------------
_CLK_HSICmd:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 168: CLK->ICKCR |= CLK_ICKCR_HSION;
ld a, 0x50c2
; ../inc/stm8l151x/src/stm8l15x_clk.c: 165: if (NewState != DISABLE)
tnz (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 168: CLK->ICKCR |= CLK_ICKCR_HSION;
or a, #0x01
ld 0x50c2, a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 173: CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_HSION);
and a, #0xfe
ld 0x50c2, a
00104$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 175: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 188: void CLK_AdjustHSICalibrationValue(uint8_t CLK_HSICalibrationValue)
; -----------------------------------------
; function CLK_AdjustHSICalibrationValue
; -----------------------------------------
_CLK_AdjustHSICalibrationValue:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 191: CLK->HSIUNLCKR = 0xAC;
mov 0x50ce+0, #0xac
; ../inc/stm8l151x/src/stm8l15x_clk.c: 192: CLK->HSIUNLCKR = 0x35;
mov 0x50ce+0, #0x35
; ../inc/stm8l151x/src/stm8l15x_clk.c: 195: CLK->HSITRIMR = (uint8_t)CLK_HSICalibrationValue;
ld 0x50cd, a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 196: }
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 212: void CLK_LSICmd(FunctionalState NewState)
; -----------------------------------------
; function CLK_LSICmd
; -----------------------------------------
_CLK_LSICmd:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 221: CLK->ICKCR |= CLK_ICKCR_LSION;
ld a, 0x50c2
; ../inc/stm8l151x/src/stm8l15x_clk.c: 218: if (NewState != DISABLE)
tnz (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 221: CLK->ICKCR |= CLK_ICKCR_LSION;
or a, #0x04
ld 0x50c2, a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 226: CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_LSION);
and a, #0xfb
ld 0x50c2, a
00104$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 228: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 249: void CLK_HSEConfig(CLK_HSE_TypeDef CLK_HSE)
; -----------------------------------------
; function CLK_HSEConfig
; -----------------------------------------
_CLK_HSEConfig:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 256: CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEON;
bres 0x50c6, #0
; ../inc/stm8l151x/src/stm8l15x_clk.c: 259: CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEBYP;
bres 0x50c6, #4
; ../inc/stm8l151x/src/stm8l15x_clk.c: 262: CLK->ECKCR |= (uint8_t)CLK_HSE;
ld a, 0x50c6
or a, (0x01, sp)
ld 0x50c6, a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 263: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 280: void CLK_LSEConfig(CLK_LSE_TypeDef CLK_LSE)
; -----------------------------------------
; function CLK_LSEConfig
; -----------------------------------------
_CLK_LSEConfig:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 287: CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEON;
bres 0x50c6, #2
; ../inc/stm8l151x/src/stm8l15x_clk.c: 290: CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEBYP;
bres 0x50c6, #5
; ../inc/stm8l151x/src/stm8l15x_clk.c: 293: CLK->ECKCR |= (uint8_t)CLK_LSE;
ld a, 0x50c6
or a, (0x01, sp)
ld 0x50c6, a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 295: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 306: void CLK_ClockSecuritySystemEnable(void)
; -----------------------------------------
; function CLK_ClockSecuritySystemEnable
; -----------------------------------------
_CLK_ClockSecuritySystemEnable:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 309: CLK->CSSR |= CLK_CSSR_CSSEN;
bset 0x50ca, #0
; ../inc/stm8l151x/src/stm8l15x_clk.c: 310: }
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 317: void CLK_ClockSecuritySytemDeglitchCmd(FunctionalState NewState)
; -----------------------------------------
; function CLK_ClockSecuritySytemDeglitchCmd
; -----------------------------------------
_CLK_ClockSecuritySytemDeglitchCmd:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 325: CLK->CSSR |= CLK_CSSR_CSSDGON;
ld a, 0x50ca
; ../inc/stm8l151x/src/stm8l15x_clk.c: 322: if (NewState != DISABLE)
tnz (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 325: CLK->CSSR |= CLK_CSSR_CSSDGON;
or a, #0x10
ld 0x50ca, a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 330: CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDGON);
and a, #0xef
ld 0x50ca, a
00104$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 332: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 356: void CLK_CCOConfig(CLK_CCOSource_TypeDef CLK_CCOSource, CLK_CCODiv_TypeDef CLK_CCODiv)
; -----------------------------------------
; function CLK_CCOConfig
; -----------------------------------------
_CLK_CCOConfig:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 363: CLK->CCOR = (uint8_t)((uint8_t)CLK_CCOSource | (uint8_t)CLK_CCODiv);
or a, (0x03, sp)
ld 0x50c5, a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 364: }
popw x
pop a
jp (x)
; ../inc/stm8l151x/src/stm8l15x_clk.c: 416: void CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_TypeDef CLK_SYSCLKSource)
; -----------------------------------------
; function CLK_SYSCLKSourceConfig
; -----------------------------------------
_CLK_SYSCLKSourceConfig:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 422: CLK->SWR = (uint8_t)CLK_SYSCLKSource;
ld 0x50c8, a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 423: }
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 435: CLK_SYSCLKSource_TypeDef CLK_GetSYSCLKSource(void)
; -----------------------------------------
; function CLK_GetSYSCLKSource
; -----------------------------------------
_CLK_GetSYSCLKSource:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 437: return ((CLK_SYSCLKSource_TypeDef)(CLK->SCSR));
ld a, 0x50c7
; ../inc/stm8l151x/src/stm8l15x_clk.c: 438: }
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 478: uint32_t CLK_GetClockFreq(void)
; -----------------------------------------
; function CLK_GetClockFreq
; -----------------------------------------
_CLK_GetClockFreq:
sub sp, #8
; ../inc/stm8l151x/src/stm8l15x_clk.c: 481: uint32_t sourcefrequency = 0;
clrw x
ldw (0x03, sp), x
ldw (0x01, sp), x
; ../inc/stm8l151x/src/stm8l15x_clk.c: 486: clocksource = (CLK_SYSCLKSource_TypeDef)CLK->SCSR;
ld a, 0x50c7
; ../inc/stm8l151x/src/stm8l15x_clk.c: 488: if ( clocksource == CLK_SYSCLKSource_HSI)
cp a, #0x01
jrne 00108$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 490: sourcefrequency = HSI_VALUE;
ldw x, #0x2400
ldw (0x03, sp), x
ldw x, #0x00f4
ldw (0x01, sp), x
jra 00109$
00108$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 492: else if ( clocksource == CLK_SYSCLKSource_LSI)
cp a, #0x02
jrne 00105$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 494: sourcefrequency = LSI_VALUE;
ldw x, #0x9470
ldw (0x03, sp), x
clrw x
ldw (0x01, sp), x
jra 00109$
00105$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 496: else if ( clocksource == CLK_SYSCLKSource_HSE)
cp a, #0x04
jrne 00109$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 498: sourcefrequency = HSE_VALUE;
ldw x, #0x2400
ldw (0x03, sp), x
ldw x, #0x00f4
ldw (0x01, sp), x
; ../inc/stm8l151x/src/stm8l15x_clk.c: 502: clockfrequency = LSE_VALUE;
00109$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 506: tmp = (uint8_t)(CLK->CKDIVR & CLK_CKDIVR_CKM);
ld a, 0x50c0
and a, #0x07
; ../inc/stm8l151x/src/stm8l15x_clk.c: 507: presc = SYSDivFactor[tmp];
clrw x
ld xl, a
ld a, (_SYSDivFactor+0, x)
; ../inc/stm8l151x/src/stm8l15x_clk.c: 510: clockfrequency = sourcefrequency / presc;
clrw x
clr (0x05, sp)
push a
pushw x
clr a
push a
ldw x, (0x07, sp)
pushw x
ldw x, (0x07, sp)
pushw x
; ../inc/stm8l151x/src/stm8l15x_clk.c: 512: return((uint32_t)clockfrequency);
call __divulong
; ../inc/stm8l151x/src/stm8l15x_clk.c: 513: }
addw sp, #16
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 528: void CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_TypeDef CLK_SYSCLKDiv)
; -----------------------------------------
; function CLK_SYSCLKDivConfig
; -----------------------------------------
_CLK_SYSCLKDivConfig:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 533: CLK->CKDIVR = (uint8_t)(CLK_SYSCLKDiv);
ld 0x50c0, a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 534: }
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 541: void CLK_SYSCLKSourceSwitchCmd(FunctionalState NewState)
; -----------------------------------------
; function CLK_SYSCLKSourceSwitchCmd
; -----------------------------------------
_CLK_SYSCLKSourceSwitchCmd:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 549: CLK->SWCR |= CLK_SWCR_SWEN;
ld a, 0x50c9
; ../inc/stm8l151x/src/stm8l15x_clk.c: 546: if (NewState != DISABLE)
tnz (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 549: CLK->SWCR |= CLK_SWCR_SWEN;
or a, #0x02
ld 0x50c9, a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 554: CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWEN);
and a, #0xfd
ld 0x50c9, a
00104$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 556: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 616: void CLK_RTCClockConfig(CLK_RTCCLKSource_TypeDef CLK_RTCCLKSource, CLK_RTCCLKDiv_TypeDef CLK_RTCCLKDiv)
; -----------------------------------------
; function CLK_RTCClockConfig
; -----------------------------------------
_CLK_RTCClockConfig:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 623: CLK->CRTCR = (uint8_t)((uint8_t)CLK_RTCCLKSource | (uint8_t)CLK_RTCCLKDiv);
or a, (0x03, sp)
ld 0x50c1, a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 624: }
popw x
pop a
jp (x)
; ../inc/stm8l151x/src/stm8l15x_clk.c: 635: void CLK_BEEPClockConfig(CLK_BEEPCLKSource_TypeDef CLK_BEEPCLKSource)
; -----------------------------------------
; function CLK_BEEPClockConfig
; -----------------------------------------
_CLK_BEEPClockConfig:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 641: CLK->CBEEPR = (uint8_t)(CLK_BEEPCLKSource);
ld 0x50cb, a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 643: }
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 677: void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
; -----------------------------------------
; function CLK_PeripheralClockConfig
; -----------------------------------------
_CLK_PeripheralClockConfig:
pushw x
; ../inc/stm8l151x/src/stm8l15x_clk.c: 686: reg = (uint8_t)((uint8_t)CLK_Peripheral & (uint8_t)0xF0);
push a
and a, #0xf0
ld xl, a
pop a
ldw y, x
; ../inc/stm8l151x/src/stm8l15x_clk.c: 693: CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
and a, #0x0f
push a
ld a, #0x01
ld (0x02, sp), a
pop a
tnz a
jreq 00154$
00153$:
sll (0x01, sp)
dec a
jrne 00153$
00154$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 698: CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
ld a, (0x01, sp)
cpl a
ld (0x02, sp), a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 688: if ( reg == 0x00)
ld a, xl
tnz a
jrne 00114$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 693: CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
ld a, 0x50c3
; ../inc/stm8l151x/src/stm8l15x_clk.c: 690: if (NewState != DISABLE)
tnz (0x05, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 693: CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
or a, (0x01, sp)
ld 0x50c3, a
jra 00116$
00102$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 698: CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
and a, (0x02, sp)
ld 0x50c3, a
jra 00116$
00114$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 701: else if (reg == 0x10)
ld a, yl
cp a, #0x10
jrne 00111$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 706: CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
ld a, 0x50c4
; ../inc/stm8l151x/src/stm8l15x_clk.c: 703: if (NewState != DISABLE)
tnz (0x05, sp)
jreq 00105$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 706: CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
or a, (0x01, sp)
ld 0x50c4, a
jra 00116$
00105$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 711: CLK->PCKENR2 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
and a, (0x02, sp)
ld 0x50c4, a
jra 00116$
00111$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 719: CLK->PCKENR3 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
ld a, 0x50d0
; ../inc/stm8l151x/src/stm8l15x_clk.c: 716: if (NewState != DISABLE)
tnz (0x05, sp)
jreq 00108$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 719: CLK->PCKENR3 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
or a, (0x01, sp)
ld 0x50d0, a
jra 00116$
00108$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 724: CLK->PCKENR3 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
and a, (0x02, sp)
ld 0x50d0, a
00116$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 727: }
popw x
popw x
pop a
jp (x)
; ../inc/stm8l151x/src/stm8l15x_clk.c: 765: void CLK_LSEClockSecuritySystemEnable(void)
; -----------------------------------------
; function CLK_LSEClockSecuritySystemEnable
; -----------------------------------------
_CLK_LSEClockSecuritySystemEnable:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 768: CSSLSE->CSR |= CSSLSE_CSR_CSSEN;
bset 0x5190, #0
; ../inc/stm8l151x/src/stm8l15x_clk.c: 769: }
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 777: void CLK_RTCCLKSwitchOnLSEFailureEnable(void)
; -----------------------------------------
; function CLK_RTCCLKSwitchOnLSEFailureEnable
; -----------------------------------------
_CLK_RTCCLKSwitchOnLSEFailureEnable:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 780: CSSLSE->CSR |= CSSLSE_CSR_SWITCHEN;
bset 0x5190, #1
; ../inc/stm8l151x/src/stm8l15x_clk.c: 781: }
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 807: void CLK_HaltConfig(CLK_Halt_TypeDef CLK_Halt, FunctionalState NewState)
; -----------------------------------------
; function CLK_HaltConfig
; -----------------------------------------
_CLK_HaltConfig:
push a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 815: CLK->ICKCR |= (uint8_t)(CLK_Halt);
ldw x, #0x50c2
push a
ld a, (x)
ld (0x02, sp), a
pop a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 813: if (NewState != DISABLE)
tnz (0x04, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 815: CLK->ICKCR |= (uint8_t)(CLK_Halt);
or a, (0x01, sp)
ld 0x50c2, a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 819: CLK->ICKCR &= (uint8_t)(~CLK_Halt);
cpl a
and a, (0x01, sp)
ld 0x50c2, a
00104$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 821: }
pop a
popw x
pop a
jp (x)
; ../inc/stm8l151x/src/stm8l15x_clk.c: 831: void CLK_MainRegulatorCmd(FunctionalState NewState)
; -----------------------------------------
; function CLK_MainRegulatorCmd
; -----------------------------------------
_CLK_MainRegulatorCmd:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 839: CLK->REGCSR &= (uint8_t)(~CLK_REGCSR_REGOFF);
ld a, 0x50cf
; ../inc/stm8l151x/src/stm8l15x_clk.c: 836: if (NewState != DISABLE)
tnz (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 839: CLK->REGCSR &= (uint8_t)(~CLK_REGCSR_REGOFF);
and a, #0xfd
ld 0x50cf, a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 844: CLK->REGCSR |= CLK_REGCSR_REGOFF;
or a, #0x02
ld 0x50cf, a
00104$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 846: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 875: void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
; -----------------------------------------
; function CLK_ITConfig
; -----------------------------------------
_CLK_ITConfig:
push a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 884: if (CLK_IT == CLK_IT_SWIF)
cp a, #0x1c
jrne 00154$
push a
ld a, #0x01
ld (0x02, sp), a
pop a
.byte 0xc5
00154$:
clr (0x01, sp)
00155$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 889: else if (CLK_IT == CLK_IT_LSECSSF)
sub a, #0x2c
jrne 00157$
inc a
.byte 0x21
00157$:
clr a
00158$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 882: if (NewState != DISABLE)
tnz (0x04, sp)
jreq 00114$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 884: if (CLK_IT == CLK_IT_SWIF)
tnz (0x01, sp)
jreq 00105$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 887: CLK->SWCR |= CLK_SWCR_SWIEN;
ld a, 0x50c9
or a, #0x04
ld 0x50c9, a
jra 00116$
00105$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 889: else if (CLK_IT == CLK_IT_LSECSSF)
tnz a
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 892: CSSLSE->CSR |= CSSLSE_CSR_CSSIE;
ld a, 0x5190
or a, #0x04
ld 0x5190, a
jra 00116$
00102$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 897: CLK->CSSR |= CLK_CSSR_CSSDIE;
ld a, 0x50ca
or a, #0x04
ld 0x50ca, a
jra 00116$
00114$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 902: if (CLK_IT == CLK_IT_SWIF)
tnz (0x01, sp)
jreq 00111$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 905: CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);
ld a, 0x50c9
and a, #0xfb
ld 0x50c9, a
jra 00116$
00111$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 907: else if (CLK_IT == CLK_IT_LSECSSF)
tnz a
jreq 00108$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 910: CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSIE);
ld a, 0x5190
and a, #0xfb
ld 0x5190, a
jra 00116$
00108$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 915: CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDIE);
ld a, 0x50ca
and a, #0xfb
ld 0x50ca, a
00116$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 918: }
pop a
popw x
pop a
jp (x)
; ../inc/stm8l151x/src/stm8l15x_clk.c: 945: FlagStatus CLK_GetFlagStatus(CLK_FLAG_TypeDef CLK_FLAG)
; -----------------------------------------
; function CLK_GetFlagStatus
; -----------------------------------------
_CLK_GetFlagStatus:
push a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 955: reg = (uint8_t)((uint8_t)CLK_FLAG & (uint8_t)0xF0);
ld xl, a
and a, #0xf0
; ../inc/stm8l151x/src/stm8l15x_clk.c: 958: pos = (uint8_t)((uint8_t)CLK_FLAG & (uint8_t)0x0F);
push a
ld a, xl
and a, #0x0f
ld xl, a
pop a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 960: if (reg == 0x00) /* The flag to check is in CRTC Rregister */
tnz a
jrne 00123$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 962: reg = CLK->CRTCR;
ld a, 0x50c1
jra 00124$
00123$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 964: else if (reg == 0x10) /* The flag to check is in ICKCR register */
cp a, #0x10
jrne 00120$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 966: reg = CLK->ICKCR;
ld a, 0x50c2
jra 00124$
00120$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 968: else if (reg == 0x20) /* The flag to check is in CCOR register */
cp a, #0x20
jrne 00117$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 970: reg = CLK->CCOR;
ld a, 0x50c5
jra 00124$
00117$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 972: else if (reg == 0x30) /* The flag to check is in ECKCR register */
cp a, #0x30
jrne 00114$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 974: reg = CLK->ECKCR;
ld a, 0x50c6
jra 00124$
00114$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 976: else if (reg == 0x40) /* The flag to check is in SWCR register */
cp a, #0x40
jrne 00111$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 978: reg = CLK->SWCR;
ld a, 0x50c9
jra 00124$
00111$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 980: else if (reg == 0x50) /* The flag to check is in CSSR register */
cp a, #0x50
jrne 00108$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 982: reg = CLK->CSSR;
ld a, 0x50ca
jra 00124$
00108$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 984: else if (reg == 0x70) /* The flag to check is in REGCSR register */
cp a, #0x70
jrne 00105$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 986: reg = CLK->REGCSR;
ld a, 0x50cf
jra 00124$
00105$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 988: else if (reg == 0x80) /* The flag to check is in CSSLSE_CSRregister */
cp a, #0x80
jrne 00102$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 990: reg = CSSLSE->CSR;
ld a, 0x5190
jra 00124$
00102$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 994: reg = CLK->CBEEPR;
ld a, 0x50cb
00124$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 998: if ((reg & (uint8_t)((uint8_t)1 << (uint8_t)pos)) != (uint8_t)RESET)
push a
ld a, #0x01
ld (0x02, sp), a
ld a, xl
tnz a
jreq 00216$
00215$:
sll (0x02, sp)
dec a
jrne 00215$
00216$:
pop a
and a, (0x01, sp)
jreq 00126$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1000: bitstatus = SET;
ld a, #0x01
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1004: bitstatus = RESET;
.byte 0x21
00126$:
clr a
00127$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1008: return((FlagStatus)bitstatus);
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1009: }
addw sp, #1
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1016: void CLK_ClearFlag(void)
; -----------------------------------------
; function CLK_ClearFlag
; -----------------------------------------
_CLK_ClearFlag:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1020: CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSF);
bres 0x5190, #3
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1021: }
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1032: ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
; -----------------------------------------
; function CLK_GetITStatus
; -----------------------------------------
_CLK_GetITStatus:
push a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1040: if (CLK_IT == CLK_IT_SWIF)
ld (0x01, sp), a
cp a, #0x1c
jrne 00114$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1043: if ((CLK->SWCR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
ld a, 0x50c9
and a, (0x01, sp)
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1045: bitstatus = SET;
sub a, #0x0c
jrne 00102$
inc a
jra 00115$
00102$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1049: bitstatus = RESET;
clr a
jra 00115$
00114$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1052: else if (CLK_IT == CLK_IT_LSECSSF)
ld a, (0x01, sp)
cp a, #0x2c
jrne 00111$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1055: if ((CSSLSE->CSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
ld a, 0x5190
and a, (0x01, sp)
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1057: bitstatus = SET;
sub a, #0x0c
jrne 00105$
inc a
jra 00115$
00105$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1061: bitstatus = RESET;
clr a
jra 00115$
00111$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1067: if ((CLK->CSSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
ld a, 0x50ca
and a, (0x01, sp)
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1069: bitstatus = SET;
sub a, #0x0c
jrne 00108$
inc a
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1073: bitstatus = RESET;
.byte 0x21
00108$:
clr a
00115$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1078: return bitstatus;
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1079: }
addw sp, #1
ret
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1089: void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
; -----------------------------------------
; function CLK_ClearITPendingBit
; -----------------------------------------
_CLK_ClearITPendingBit:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1095: if ((uint8_t)((uint8_t)CLK_IT & (uint8_t)0xF0) == (uint8_t)0x20)
and a, #0xf0
cp a, #0x20
jrne 00102$
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1098: CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSF);
bres 0x5190, #3
ret
00102$:
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1103: CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIF);
bres 0x50c9, #3
; ../inc/stm8l151x/src/stm8l15x_clk.c: 1105: }
ret
.area CODE
.area CONST
.area CONST
_SYSDivFactor:
.db #0x01 ; 1
.db #0x02 ; 2
.db #0x04 ; 4
.db #0x08 ; 8
.db #0x10 ; 16
.area CODE
.area INITIALIZER
.area CABS (ABS)

823
firmware/STM8L15X_LD/stm8l15x_clk.lst Normal file
View File

@@ -0,0 +1,823 @@
1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ISO C Compiler
3 ; Version 4.5.0 #15242 (Linux)
4 ;--------------------------------------------------------
5 .module stm8l15x_clk
6
7 ;--------------------------------------------------------
8 ; Public variables in this module
9 ;--------------------------------------------------------
10 .globl _SYSDivFactor
11 .globl _CLK_DeInit
12 .globl _CLK_HSICmd
13 .globl _CLK_AdjustHSICalibrationValue
14 .globl _CLK_LSICmd
15 .globl _CLK_HSEConfig
16 .globl _CLK_LSEConfig
17 .globl _CLK_ClockSecuritySystemEnable
18 .globl _CLK_ClockSecuritySytemDeglitchCmd
19 .globl _CLK_CCOConfig
20 .globl _CLK_SYSCLKSourceConfig
21 .globl _CLK_GetSYSCLKSource
22 .globl _CLK_GetClockFreq
23 .globl _CLK_SYSCLKDivConfig
24 .globl _CLK_SYSCLKSourceSwitchCmd
25 .globl _CLK_RTCClockConfig
26 .globl _CLK_BEEPClockConfig
27 .globl _CLK_PeripheralClockConfig
28 .globl _CLK_LSEClockSecuritySystemEnable
29 .globl _CLK_RTCCLKSwitchOnLSEFailureEnable
30 .globl _CLK_HaltConfig
31 .globl _CLK_MainRegulatorCmd
32 .globl _CLK_ITConfig
33 .globl _CLK_GetFlagStatus
34 .globl _CLK_ClearFlag
35 .globl _CLK_GetITStatus
36 .globl _CLK_ClearITPendingBit
37 ;--------------------------------------------------------
38 ; ram data
39 ;--------------------------------------------------------
40 .area DATA
41 ;--------------------------------------------------------
42 ; ram data
43 ;--------------------------------------------------------
44 .area INITIALIZED
45 ;--------------------------------------------------------
46 ; absolute external ram data
47 ;--------------------------------------------------------
48 .area DABS (ABS)
49
50 ; default segment ordering for linker
51 .area HOME
52 .area GSINIT
53 .area GSFINAL
54 .area CONST
55 .area INITIALIZER
56 .area CODE
57
58 ;--------------------------------------------------------
59 ; global & static initialisations
60 ;--------------------------------------------------------
61 .area HOME
62 .area GSINIT
63 .area GSFINAL
64 .area GSINIT
65 ;--------------------------------------------------------
66 ; Home
67 ;--------------------------------------------------------
68 .area HOME
69 .area HOME
70 ;--------------------------------------------------------
71 ; code
72 ;--------------------------------------------------------
73 .area CODE
74 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 120: void CLK_DeInit(void)
75 ; -----------------------------------------
76 ; function CLK_DeInit
77 ; -----------------------------------------
000000 78 _CLK_DeInit:
79 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 122: CLK->ICKCR = CLK_ICKCR_RESET_VALUE;
000000 35 11 50 C2 [ 1] 80 mov 0x50c2+0, #0x11
81 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 123: CLK->ECKCR = CLK_ECKCR_RESET_VALUE;
000004 35 00 50 C6 [ 1] 82 mov 0x50c6+0, #0x00
83 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 124: CLK->CRTCR = CLK_CRTCR_RESET_VALUE;
000008 35 00 50 C1 [ 1] 84 mov 0x50c1+0, #0x00
85 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 125: CLK->CBEEPR = CLK_CBEEPR_RESET_VALUE;
00000C 35 00 50 CB [ 1] 86 mov 0x50cb+0, #0x00
87 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 126: CLK->SWR = CLK_SWR_RESET_VALUE;
000010 35 01 50 C8 [ 1] 88 mov 0x50c8+0, #0x01
89 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 127: CLK->SWCR = CLK_SWCR_RESET_VALUE;
000014 35 00 50 C9 [ 1] 90 mov 0x50c9+0, #0x00
91 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 128: CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
000018 35 03 50 C0 [ 1] 92 mov 0x50c0+0, #0x03
93 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 129: CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
00001C 35 00 50 C3 [ 1] 94 mov 0x50c3+0, #0x00
95 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 130: CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
000020 35 80 50 C4 [ 1] 96 mov 0x50c4+0, #0x80
97 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 131: CLK->PCKENR3 = CLK_PCKENR3_RESET_VALUE;
000024 35 00 50 D0 [ 1] 98 mov 0x50d0+0, #0x00
99 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 132: CLK->CSSR = CLK_CSSR_RESET_VALUE;
000028 35 00 50 CA [ 1] 100 mov 0x50ca+0, #0x00
101 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 133: CLK->CCOR = CLK_CCOR_RESET_VALUE;
00002C 35 00 50 C5 [ 1] 102 mov 0x50c5+0, #0x00
103 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 134: CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
000030 35 00 50 CD [ 1] 104 mov 0x50cd+0, #0x00
105 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 135: CLK->HSICALR = CLK_HSICALR_RESET_VALUE;
000034 35 00 50 CC [ 1] 106 mov 0x50cc+0, #0x00
107 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 136: CLK->HSIUNLCKR = CLK_HSIUNLCKR_RESET_VALUE;
000038 35 00 50 CE [ 1] 108 mov 0x50ce+0, #0x00
109 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 137: CLK->REGCSR = CLK_REGCSR_RESET_VALUE;
00003C 35 B9 50 CF [ 1] 110 mov 0x50cf+0, #0xb9
111 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 138: }
000040 81 [ 4] 112 ret
113 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 160: void CLK_HSICmd(FunctionalState NewState)
114 ; -----------------------------------------
115 ; function CLK_HSICmd
116 ; -----------------------------------------
000041 117 _CLK_HSICmd:
000041 88 [ 1] 118 push a
000042 6B 01 [ 1] 119 ld (0x01, sp), a
120 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 168: CLK->ICKCR |= CLK_ICKCR_HSION;
000044 C6 50 C2 [ 1] 121 ld a, 0x50c2
122 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 165: if (NewState != DISABLE)
000047 0D 01 [ 1] 123 tnz (0x01, sp)
000049 27 07 [ 1] 124 jreq 00102$
125 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 168: CLK->ICKCR |= CLK_ICKCR_HSION;
00004B AA 01 [ 1] 126 or a, #0x01
00004D C7 50 C2 [ 1] 127 ld 0x50c2, a
000050 20 05 [ 2] 128 jra 00104$
000052 129 00102$:
130 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 173: CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_HSION);
000052 A4 FE [ 1] 131 and a, #0xfe
000054 C7 50 C2 [ 1] 132 ld 0x50c2, a
000057 133 00104$:
134 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 175: }
000057 84 [ 1] 135 pop a
000058 81 [ 4] 136 ret
137 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 188: void CLK_AdjustHSICalibrationValue(uint8_t CLK_HSICalibrationValue)
138 ; -----------------------------------------
139 ; function CLK_AdjustHSICalibrationValue
140 ; -----------------------------------------
000059 141 _CLK_AdjustHSICalibrationValue:
142 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 191: CLK->HSIUNLCKR = 0xAC;
000059 35 AC 50 CE [ 1] 143 mov 0x50ce+0, #0xac
144 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 192: CLK->HSIUNLCKR = 0x35;
00005D 35 35 50 CE [ 1] 145 mov 0x50ce+0, #0x35
146 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 195: CLK->HSITRIMR = (uint8_t)CLK_HSICalibrationValue;
000061 C7 50 CD [ 1] 147 ld 0x50cd, a
148 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 196: }
000064 81 [ 4] 149 ret
150 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 212: void CLK_LSICmd(FunctionalState NewState)
151 ; -----------------------------------------
152 ; function CLK_LSICmd
153 ; -----------------------------------------
000065 154 _CLK_LSICmd:
000065 88 [ 1] 155 push a
000066 6B 01 [ 1] 156 ld (0x01, sp), a
157 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 221: CLK->ICKCR |= CLK_ICKCR_LSION;
000068 C6 50 C2 [ 1] 158 ld a, 0x50c2
159 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 218: if (NewState != DISABLE)
00006B 0D 01 [ 1] 160 tnz (0x01, sp)
00006D 27 07 [ 1] 161 jreq 00102$
162 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 221: CLK->ICKCR |= CLK_ICKCR_LSION;
00006F AA 04 [ 1] 163 or a, #0x04
000071 C7 50 C2 [ 1] 164 ld 0x50c2, a
000074 20 05 [ 2] 165 jra 00104$
000076 166 00102$:
167 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 226: CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_LSION);
000076 A4 FB [ 1] 168 and a, #0xfb
000078 C7 50 C2 [ 1] 169 ld 0x50c2, a
00007B 170 00104$:
171 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 228: }
00007B 84 [ 1] 172 pop a
00007C 81 [ 4] 173 ret
174 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 249: void CLK_HSEConfig(CLK_HSE_TypeDef CLK_HSE)
175 ; -----------------------------------------
176 ; function CLK_HSEConfig
177 ; -----------------------------------------
00007D 178 _CLK_HSEConfig:
00007D 88 [ 1] 179 push a
00007E 6B 01 [ 1] 180 ld (0x01, sp), a
181 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 256: CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEON;
000080 72 11 50 C6 [ 1] 182 bres 0x50c6, #0
183 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 259: CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEBYP;
000084 72 19 50 C6 [ 1] 184 bres 0x50c6, #4
185 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 262: CLK->ECKCR |= (uint8_t)CLK_HSE;
000088 C6 50 C6 [ 1] 186 ld a, 0x50c6
00008B 1A 01 [ 1] 187 or a, (0x01, sp)
00008D C7 50 C6 [ 1] 188 ld 0x50c6, a
189 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 263: }
000090 84 [ 1] 190 pop a
000091 81 [ 4] 191 ret
192 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 280: void CLK_LSEConfig(CLK_LSE_TypeDef CLK_LSE)
193 ; -----------------------------------------
194 ; function CLK_LSEConfig
195 ; -----------------------------------------
000092 196 _CLK_LSEConfig:
000092 88 [ 1] 197 push a
000093 6B 01 [ 1] 198 ld (0x01, sp), a
199 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 287: CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEON;
000095 72 15 50 C6 [ 1] 200 bres 0x50c6, #2
201 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 290: CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEBYP;
000099 72 1B 50 C6 [ 1] 202 bres 0x50c6, #5
203 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 293: CLK->ECKCR |= (uint8_t)CLK_LSE;
00009D C6 50 C6 [ 1] 204 ld a, 0x50c6
0000A0 1A 01 [ 1] 205 or a, (0x01, sp)
0000A2 C7 50 C6 [ 1] 206 ld 0x50c6, a
207 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 295: }
0000A5 84 [ 1] 208 pop a
0000A6 81 [ 4] 209 ret
210 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 306: void CLK_ClockSecuritySystemEnable(void)
211 ; -----------------------------------------
212 ; function CLK_ClockSecuritySystemEnable
213 ; -----------------------------------------
0000A7 214 _CLK_ClockSecuritySystemEnable:
215 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 309: CLK->CSSR |= CLK_CSSR_CSSEN;
0000A7 72 10 50 CA [ 1] 216 bset 0x50ca, #0
217 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 310: }
0000AB 81 [ 4] 218 ret
219 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 317: void CLK_ClockSecuritySytemDeglitchCmd(FunctionalState NewState)
220 ; -----------------------------------------
221 ; function CLK_ClockSecuritySytemDeglitchCmd
222 ; -----------------------------------------
0000AC 223 _CLK_ClockSecuritySytemDeglitchCmd:
0000AC 88 [ 1] 224 push a
0000AD 6B 01 [ 1] 225 ld (0x01, sp), a
226 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 325: CLK->CSSR |= CLK_CSSR_CSSDGON;
0000AF C6 50 CA [ 1] 227 ld a, 0x50ca
228 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 322: if (NewState != DISABLE)
0000B2 0D 01 [ 1] 229 tnz (0x01, sp)
0000B4 27 07 [ 1] 230 jreq 00102$
231 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 325: CLK->CSSR |= CLK_CSSR_CSSDGON;
0000B6 AA 10 [ 1] 232 or a, #0x10
0000B8 C7 50 CA [ 1] 233 ld 0x50ca, a
0000BB 20 05 [ 2] 234 jra 00104$
0000BD 235 00102$:
236 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 330: CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDGON);
0000BD A4 EF [ 1] 237 and a, #0xef
0000BF C7 50 CA [ 1] 238 ld 0x50ca, a
0000C2 239 00104$:
240 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 332: }
0000C2 84 [ 1] 241 pop a
0000C3 81 [ 4] 242 ret
243 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 356: void CLK_CCOConfig(CLK_CCOSource_TypeDef CLK_CCOSource, CLK_CCODiv_TypeDef CLK_CCODiv)
244 ; -----------------------------------------
245 ; function CLK_CCOConfig
246 ; -----------------------------------------
0000C4 247 _CLK_CCOConfig:
248 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 363: CLK->CCOR = (uint8_t)((uint8_t)CLK_CCOSource | (uint8_t)CLK_CCODiv);
0000C4 1A 03 [ 1] 249 or a, (0x03, sp)
0000C6 C7 50 C5 [ 1] 250 ld 0x50c5, a
251 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 364: }
0000C9 85 [ 2] 252 popw x
0000CA 84 [ 1] 253 pop a
0000CB FC [ 2] 254 jp (x)
255 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 416: void CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_TypeDef CLK_SYSCLKSource)
256 ; -----------------------------------------
257 ; function CLK_SYSCLKSourceConfig
258 ; -----------------------------------------
0000CC 259 _CLK_SYSCLKSourceConfig:
260 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 422: CLK->SWR = (uint8_t)CLK_SYSCLKSource;
0000CC C7 50 C8 [ 1] 261 ld 0x50c8, a
262 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 423: }
0000CF 81 [ 4] 263 ret
264 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 435: CLK_SYSCLKSource_TypeDef CLK_GetSYSCLKSource(void)
265 ; -----------------------------------------
266 ; function CLK_GetSYSCLKSource
267 ; -----------------------------------------
0000D0 268 _CLK_GetSYSCLKSource:
269 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 437: return ((CLK_SYSCLKSource_TypeDef)(CLK->SCSR));
0000D0 C6 50 C7 [ 1] 270 ld a, 0x50c7
271 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 438: }
0000D3 81 [ 4] 272 ret
273 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 478: uint32_t CLK_GetClockFreq(void)
274 ; -----------------------------------------
275 ; function CLK_GetClockFreq
276 ; -----------------------------------------
0000D4 277 _CLK_GetClockFreq:
0000D4 52 08 [ 2] 278 sub sp, #8
279 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 481: uint32_t sourcefrequency = 0;
0000D6 5F [ 1] 280 clrw x
0000D7 1F 03 [ 2] 281 ldw (0x03, sp), x
0000D9 1F 01 [ 2] 282 ldw (0x01, sp), x
283 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 486: clocksource = (CLK_SYSCLKSource_TypeDef)CLK->SCSR;
0000DB C6 50 C7 [ 1] 284 ld a, 0x50c7
285 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 488: if ( clocksource == CLK_SYSCLKSource_HSI)
0000DE A1 01 [ 1] 286 cp a, #0x01
0000E0 26 0C [ 1] 287 jrne 00108$
288 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 490: sourcefrequency = HSI_VALUE;
0000E2 AE 24 00 [ 2] 289 ldw x, #0x2400
0000E5 1F 03 [ 2] 290 ldw (0x03, sp), x
0000E7 AE 00 F4 [ 2] 291 ldw x, #0x00f4
0000EA 1F 01 [ 2] 292 ldw (0x01, sp), x
0000EC 20 1C [ 2] 293 jra 00109$
0000EE 294 00108$:
295 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 492: else if ( clocksource == CLK_SYSCLKSource_LSI)
0000EE A1 02 [ 1] 296 cp a, #0x02
0000F0 26 0A [ 1] 297 jrne 00105$
298 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 494: sourcefrequency = LSI_VALUE;
0000F2 AE 94 70 [ 2] 299 ldw x, #0x9470
0000F5 1F 03 [ 2] 300 ldw (0x03, sp), x
0000F7 5F [ 1] 301 clrw x
0000F8 1F 01 [ 2] 302 ldw (0x01, sp), x
0000FA 20 0E [ 2] 303 jra 00109$
0000FC 304 00105$:
305 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 496: else if ( clocksource == CLK_SYSCLKSource_HSE)
0000FC A1 04 [ 1] 306 cp a, #0x04
0000FE 26 0A [ 1] 307 jrne 00109$
308 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 498: sourcefrequency = HSE_VALUE;
000100 AE 24 00 [ 2] 309 ldw x, #0x2400
000103 1F 03 [ 2] 310 ldw (0x03, sp), x
000105 AE 00 F4 [ 2] 311 ldw x, #0x00f4
000108 1F 01 [ 2] 312 ldw (0x01, sp), x
313 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 502: clockfrequency = LSE_VALUE;
00010A 314 00109$:
315 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 506: tmp = (uint8_t)(CLK->CKDIVR & CLK_CKDIVR_CKM);
00010A C6 50 C0 [ 1] 316 ld a, 0x50c0
00010D A4 07 [ 1] 317 and a, #0x07
318 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 507: presc = SYSDivFactor[tmp];
00010F 5F [ 1] 319 clrw x
000110 97 [ 1] 320 ld xl, a
000111 D6u00u00 [ 1] 321 ld a, (_SYSDivFactor+0, x)
322 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 510: clockfrequency = sourcefrequency / presc;
000114 5F [ 1] 323 clrw x
000115 0F 05 [ 1] 324 clr (0x05, sp)
000117 88 [ 1] 325 push a
000118 89 [ 2] 326 pushw x
000119 4F [ 1] 327 clr a
00011A 88 [ 1] 328 push a
00011B 1E 07 [ 2] 329 ldw x, (0x07, sp)
00011D 89 [ 2] 330 pushw x
00011E 1E 07 [ 2] 331 ldw x, (0x07, sp)
000120 89 [ 2] 332 pushw x
333 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 512: return((uint32_t)clockfrequency);
000121 CDr00r00 [ 4] 334 call __divulong
335 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 513: }
000124 5B 10 [ 2] 336 addw sp, #16
000126 81 [ 4] 337 ret
338 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 528: void CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_TypeDef CLK_SYSCLKDiv)
339 ; -----------------------------------------
340 ; function CLK_SYSCLKDivConfig
341 ; -----------------------------------------
000127 342 _CLK_SYSCLKDivConfig:
343 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 533: CLK->CKDIVR = (uint8_t)(CLK_SYSCLKDiv);
000127 C7 50 C0 [ 1] 344 ld 0x50c0, a
345 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 534: }
00012A 81 [ 4] 346 ret
347 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 541: void CLK_SYSCLKSourceSwitchCmd(FunctionalState NewState)
348 ; -----------------------------------------
349 ; function CLK_SYSCLKSourceSwitchCmd
350 ; -----------------------------------------
00012B 351 _CLK_SYSCLKSourceSwitchCmd:
00012B 88 [ 1] 352 push a
00012C 6B 01 [ 1] 353 ld (0x01, sp), a
354 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 549: CLK->SWCR |= CLK_SWCR_SWEN;
00012E C6 50 C9 [ 1] 355 ld a, 0x50c9
356 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 546: if (NewState != DISABLE)
000131 0D 01 [ 1] 357 tnz (0x01, sp)
000133 27 07 [ 1] 358 jreq 00102$
359 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 549: CLK->SWCR |= CLK_SWCR_SWEN;
000135 AA 02 [ 1] 360 or a, #0x02
000137 C7 50 C9 [ 1] 361 ld 0x50c9, a
00013A 20 05 [ 2] 362 jra 00104$
00013C 363 00102$:
364 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 554: CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWEN);
00013C A4 FD [ 1] 365 and a, #0xfd
00013E C7 50 C9 [ 1] 366 ld 0x50c9, a
000141 367 00104$:
368 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 556: }
000141 84 [ 1] 369 pop a
000142 81 [ 4] 370 ret
371 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 616: void CLK_RTCClockConfig(CLK_RTCCLKSource_TypeDef CLK_RTCCLKSource, CLK_RTCCLKDiv_TypeDef CLK_RTCCLKDiv)
372 ; -----------------------------------------
373 ; function CLK_RTCClockConfig
374 ; -----------------------------------------
000143 375 _CLK_RTCClockConfig:
376 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 623: CLK->CRTCR = (uint8_t)((uint8_t)CLK_RTCCLKSource | (uint8_t)CLK_RTCCLKDiv);
000143 1A 03 [ 1] 377 or a, (0x03, sp)
000145 C7 50 C1 [ 1] 378 ld 0x50c1, a
379 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 624: }
000148 85 [ 2] 380 popw x
000149 84 [ 1] 381 pop a
00014A FC [ 2] 382 jp (x)
383 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 635: void CLK_BEEPClockConfig(CLK_BEEPCLKSource_TypeDef CLK_BEEPCLKSource)
384 ; -----------------------------------------
385 ; function CLK_BEEPClockConfig
386 ; -----------------------------------------
00014B 387 _CLK_BEEPClockConfig:
388 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 641: CLK->CBEEPR = (uint8_t)(CLK_BEEPCLKSource);
00014B C7 50 CB [ 1] 389 ld 0x50cb, a
390 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 643: }
00014E 81 [ 4] 391 ret
392 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 677: void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
393 ; -----------------------------------------
394 ; function CLK_PeripheralClockConfig
395 ; -----------------------------------------
00014F 396 _CLK_PeripheralClockConfig:
00014F 89 [ 2] 397 pushw x
398 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 686: reg = (uint8_t)((uint8_t)CLK_Peripheral & (uint8_t)0xF0);
000150 88 [ 1] 399 push a
000151 A4 F0 [ 1] 400 and a, #0xf0
000153 97 [ 1] 401 ld xl, a
000154 84 [ 1] 402 pop a
000155 90 93 [ 1] 403 ldw y, x
404 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 693: CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
000157 A4 0F [ 1] 405 and a, #0x0f
000159 88 [ 1] 406 push a
00015A A6 01 [ 1] 407 ld a, #0x01
00015C 6B 02 [ 1] 408 ld (0x02, sp), a
00015E 84 [ 1] 409 pop a
00015F 4D [ 1] 410 tnz a
000160 27 05 [ 1] 411 jreq 00154$
000162 412 00153$:
000162 08 01 [ 1] 413 sll (0x01, sp)
000164 4A [ 1] 414 dec a
000165 26 FB [ 1] 415 jrne 00153$
000167 416 00154$:
417 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 698: CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
000167 7B 01 [ 1] 418 ld a, (0x01, sp)
000169 43 [ 1] 419 cpl a
00016A 6B 02 [ 1] 420 ld (0x02, sp), a
421 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 688: if ( reg == 0x00)
00016C 9F [ 1] 422 ld a, xl
00016D 4D [ 1] 423 tnz a
00016E 26 15 [ 1] 424 jrne 00114$
425 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 693: CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
000170 C6 50 C3 [ 1] 426 ld a, 0x50c3
427 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 690: if (NewState != DISABLE)
000173 0D 05 [ 1] 428 tnz (0x05, sp)
000175 27 07 [ 1] 429 jreq 00102$
430 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 693: CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
000177 1A 01 [ 1] 431 or a, (0x01, sp)
000179 C7 50 C3 [ 1] 432 ld 0x50c3, a
00017C 20 35 [ 2] 433 jra 00116$
00017E 434 00102$:
435 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 698: CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
00017E 14 02 [ 1] 436 and a, (0x02, sp)
000180 C7 50 C3 [ 1] 437 ld 0x50c3, a
000183 20 2E [ 2] 438 jra 00116$
000185 439 00114$:
440 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 701: else if (reg == 0x10)
000185 90 9F [ 1] 441 ld a, yl
000187 A1 10 [ 1] 442 cp a, #0x10
000189 26 15 [ 1] 443 jrne 00111$
444 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 706: CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
00018B C6 50 C4 [ 1] 445 ld a, 0x50c4
446 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 703: if (NewState != DISABLE)
00018E 0D 05 [ 1] 447 tnz (0x05, sp)
000190 27 07 [ 1] 448 jreq 00105$
449 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 706: CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
000192 1A 01 [ 1] 450 or a, (0x01, sp)
000194 C7 50 C4 [ 1] 451 ld 0x50c4, a
000197 20 1A [ 2] 452 jra 00116$
000199 453 00105$:
454 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 711: CLK->PCKENR2 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
000199 14 02 [ 1] 455 and a, (0x02, sp)
00019B C7 50 C4 [ 1] 456 ld 0x50c4, a
00019E 20 13 [ 2] 457 jra 00116$
0001A0 458 00111$:
459 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 719: CLK->PCKENR3 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
0001A0 C6 50 D0 [ 1] 460 ld a, 0x50d0
461 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 716: if (NewState != DISABLE)
0001A3 0D 05 [ 1] 462 tnz (0x05, sp)
0001A5 27 07 [ 1] 463 jreq 00108$
464 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 719: CLK->PCKENR3 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
0001A7 1A 01 [ 1] 465 or a, (0x01, sp)
0001A9 C7 50 D0 [ 1] 466 ld 0x50d0, a
0001AC 20 05 [ 2] 467 jra 00116$
0001AE 468 00108$:
469 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 724: CLK->PCKENR3 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
0001AE 14 02 [ 1] 470 and a, (0x02, sp)
0001B0 C7 50 D0 [ 1] 471 ld 0x50d0, a
0001B3 472 00116$:
473 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 727: }
0001B3 85 [ 2] 474 popw x
0001B4 85 [ 2] 475 popw x
0001B5 84 [ 1] 476 pop a
0001B6 FC [ 2] 477 jp (x)
478 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 765: void CLK_LSEClockSecuritySystemEnable(void)
479 ; -----------------------------------------
480 ; function CLK_LSEClockSecuritySystemEnable
481 ; -----------------------------------------
0001B7 482 _CLK_LSEClockSecuritySystemEnable:
483 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 768: CSSLSE->CSR |= CSSLSE_CSR_CSSEN;
0001B7 72 10 51 90 [ 1] 484 bset 0x5190, #0
485 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 769: }
0001BB 81 [ 4] 486 ret
487 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 777: void CLK_RTCCLKSwitchOnLSEFailureEnable(void)
488 ; -----------------------------------------
489 ; function CLK_RTCCLKSwitchOnLSEFailureEnable
490 ; -----------------------------------------
0001BC 491 _CLK_RTCCLKSwitchOnLSEFailureEnable:
492 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 780: CSSLSE->CSR |= CSSLSE_CSR_SWITCHEN;
0001BC 72 12 51 90 [ 1] 493 bset 0x5190, #1
494 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 781: }
0001C0 81 [ 4] 495 ret
496 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 807: void CLK_HaltConfig(CLK_Halt_TypeDef CLK_Halt, FunctionalState NewState)
497 ; -----------------------------------------
498 ; function CLK_HaltConfig
499 ; -----------------------------------------
0001C1 500 _CLK_HaltConfig:
0001C1 88 [ 1] 501 push a
502 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 815: CLK->ICKCR |= (uint8_t)(CLK_Halt);
0001C2 AE 50 C2 [ 2] 503 ldw x, #0x50c2
0001C5 88 [ 1] 504 push a
0001C6 F6 [ 1] 505 ld a, (x)
0001C7 6B 02 [ 1] 506 ld (0x02, sp), a
0001C9 84 [ 1] 507 pop a
508 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 813: if (NewState != DISABLE)
0001CA 0D 04 [ 1] 509 tnz (0x04, sp)
0001CC 27 07 [ 1] 510 jreq 00102$
511 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 815: CLK->ICKCR |= (uint8_t)(CLK_Halt);
0001CE 1A 01 [ 1] 512 or a, (0x01, sp)
0001D0 C7 50 C2 [ 1] 513 ld 0x50c2, a
0001D3 20 06 [ 2] 514 jra 00104$
0001D5 515 00102$:
516 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 819: CLK->ICKCR &= (uint8_t)(~CLK_Halt);
0001D5 43 [ 1] 517 cpl a
0001D6 14 01 [ 1] 518 and a, (0x01, sp)
0001D8 C7 50 C2 [ 1] 519 ld 0x50c2, a
0001DB 520 00104$:
521 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 821: }
0001DB 84 [ 1] 522 pop a
0001DC 85 [ 2] 523 popw x
0001DD 84 [ 1] 524 pop a
0001DE FC [ 2] 525 jp (x)
526 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 831: void CLK_MainRegulatorCmd(FunctionalState NewState)
527 ; -----------------------------------------
528 ; function CLK_MainRegulatorCmd
529 ; -----------------------------------------
0001DF 530 _CLK_MainRegulatorCmd:
0001DF 88 [ 1] 531 push a
0001E0 6B 01 [ 1] 532 ld (0x01, sp), a
533 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 839: CLK->REGCSR &= (uint8_t)(~CLK_REGCSR_REGOFF);
0001E2 C6 50 CF [ 1] 534 ld a, 0x50cf
535 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 836: if (NewState != DISABLE)
0001E5 0D 01 [ 1] 536 tnz (0x01, sp)
0001E7 27 07 [ 1] 537 jreq 00102$
538 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 839: CLK->REGCSR &= (uint8_t)(~CLK_REGCSR_REGOFF);
0001E9 A4 FD [ 1] 539 and a, #0xfd
0001EB C7 50 CF [ 1] 540 ld 0x50cf, a
0001EE 20 05 [ 2] 541 jra 00104$
0001F0 542 00102$:
543 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 844: CLK->REGCSR |= CLK_REGCSR_REGOFF;
0001F0 AA 02 [ 1] 544 or a, #0x02
0001F2 C7 50 CF [ 1] 545 ld 0x50cf, a
0001F5 546 00104$:
547 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 846: }
0001F5 84 [ 1] 548 pop a
0001F6 81 [ 4] 549 ret
550 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 875: void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
551 ; -----------------------------------------
552 ; function CLK_ITConfig
553 ; -----------------------------------------
0001F7 554 _CLK_ITConfig:
0001F7 88 [ 1] 555 push a
556 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 884: if (CLK_IT == CLK_IT_SWIF)
0001F8 A1 1C [ 1] 557 cp a, #0x1c
0001FA 26 07 [ 1] 558 jrne 00154$
0001FC 88 [ 1] 559 push a
0001FD A6 01 [ 1] 560 ld a, #0x01
0001FF 6B 02 [ 1] 561 ld (0x02, sp), a
000201 84 [ 1] 562 pop a
000202 C5 563 .byte 0xc5
000203 564 00154$:
000203 0F 01 [ 1] 565 clr (0x01, sp)
000205 566 00155$:
567 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 889: else if (CLK_IT == CLK_IT_LSECSSF)
000205 A0 2C [ 1] 568 sub a, #0x2c
000207 26 02 [ 1] 569 jrne 00157$
000209 4C [ 1] 570 inc a
00020A 21 571 .byte 0x21
00020B 572 00157$:
00020B 4F [ 1] 573 clr a
00020C 574 00158$:
575 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 882: if (NewState != DISABLE)
00020C 0D 04 [ 1] 576 tnz (0x04, sp)
00020E 27 25 [ 1] 577 jreq 00114$
578 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 884: if (CLK_IT == CLK_IT_SWIF)
000210 0D 01 [ 1] 579 tnz (0x01, sp)
000212 27 0A [ 1] 580 jreq 00105$
581 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 887: CLK->SWCR |= CLK_SWCR_SWIEN;
000214 C6 50 C9 [ 1] 582 ld a, 0x50c9
000217 AA 04 [ 1] 583 or a, #0x04
000219 C7 50 C9 [ 1] 584 ld 0x50c9, a
00021C 20 3A [ 2] 585 jra 00116$
00021E 586 00105$:
587 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 889: else if (CLK_IT == CLK_IT_LSECSSF)
00021E 4D [ 1] 588 tnz a
00021F 27 0A [ 1] 589 jreq 00102$
590 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 892: CSSLSE->CSR |= CSSLSE_CSR_CSSIE;
000221 C6 51 90 [ 1] 591 ld a, 0x5190
000224 AA 04 [ 1] 592 or a, #0x04
000226 C7 51 90 [ 1] 593 ld 0x5190, a
000229 20 2D [ 2] 594 jra 00116$
00022B 595 00102$:
596 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 897: CLK->CSSR |= CLK_CSSR_CSSDIE;
00022B C6 50 CA [ 1] 597 ld a, 0x50ca
00022E AA 04 [ 1] 598 or a, #0x04
000230 C7 50 CA [ 1] 599 ld 0x50ca, a
000233 20 23 [ 2] 600 jra 00116$
000235 601 00114$:
602 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 902: if (CLK_IT == CLK_IT_SWIF)
000235 0D 01 [ 1] 603 tnz (0x01, sp)
000237 27 0A [ 1] 604 jreq 00111$
605 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 905: CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);
000239 C6 50 C9 [ 1] 606 ld a, 0x50c9
00023C A4 FB [ 1] 607 and a, #0xfb
00023E C7 50 C9 [ 1] 608 ld 0x50c9, a
000241 20 15 [ 2] 609 jra 00116$
000243 610 00111$:
611 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 907: else if (CLK_IT == CLK_IT_LSECSSF)
000243 4D [ 1] 612 tnz a
000244 27 0A [ 1] 613 jreq 00108$
614 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 910: CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSIE);
000246 C6 51 90 [ 1] 615 ld a, 0x5190
000249 A4 FB [ 1] 616 and a, #0xfb
00024B C7 51 90 [ 1] 617 ld 0x5190, a
00024E 20 08 [ 2] 618 jra 00116$
000250 619 00108$:
620 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 915: CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDIE);
000250 C6 50 CA [ 1] 621 ld a, 0x50ca
000253 A4 FB [ 1] 622 and a, #0xfb
000255 C7 50 CA [ 1] 623 ld 0x50ca, a
000258 624 00116$:
625 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 918: }
000258 84 [ 1] 626 pop a
000259 85 [ 2] 627 popw x
00025A 84 [ 1] 628 pop a
00025B FC [ 2] 629 jp (x)
630 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 945: FlagStatus CLK_GetFlagStatus(CLK_FLAG_TypeDef CLK_FLAG)
631 ; -----------------------------------------
632 ; function CLK_GetFlagStatus
633 ; -----------------------------------------
00025C 634 _CLK_GetFlagStatus:
00025C 88 [ 1] 635 push a
636 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 955: reg = (uint8_t)((uint8_t)CLK_FLAG & (uint8_t)0xF0);
00025D 97 [ 1] 637 ld xl, a
00025E A4 F0 [ 1] 638 and a, #0xf0
639 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 958: pos = (uint8_t)((uint8_t)CLK_FLAG & (uint8_t)0x0F);
000260 88 [ 1] 640 push a
000261 9F [ 1] 641 ld a, xl
000262 A4 0F [ 1] 642 and a, #0x0f
000264 97 [ 1] 643 ld xl, a
000265 84 [ 1] 644 pop a
645 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 960: if (reg == 0x00) /* The flag to check is in CRTC Rregister */
000266 4D [ 1] 646 tnz a
000267 26 05 [ 1] 647 jrne 00123$
648 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 962: reg = CLK->CRTCR;
000269 C6 50 C1 [ 1] 649 ld a, 0x50c1
00026C 20 42 [ 2] 650 jra 00124$
00026E 651 00123$:
652 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 964: else if (reg == 0x10) /* The flag to check is in ICKCR register */
00026E A1 10 [ 1] 653 cp a, #0x10
000270 26 05 [ 1] 654 jrne 00120$
655 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 966: reg = CLK->ICKCR;
000272 C6 50 C2 [ 1] 656 ld a, 0x50c2
000275 20 39 [ 2] 657 jra 00124$
000277 658 00120$:
659 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 968: else if (reg == 0x20) /* The flag to check is in CCOR register */
000277 A1 20 [ 1] 660 cp a, #0x20
000279 26 05 [ 1] 661 jrne 00117$
662 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 970: reg = CLK->CCOR;
00027B C6 50 C5 [ 1] 663 ld a, 0x50c5
00027E 20 30 [ 2] 664 jra 00124$
000280 665 00117$:
666 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 972: else if (reg == 0x30) /* The flag to check is in ECKCR register */
000280 A1 30 [ 1] 667 cp a, #0x30
000282 26 05 [ 1] 668 jrne 00114$
669 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 974: reg = CLK->ECKCR;
000284 C6 50 C6 [ 1] 670 ld a, 0x50c6
000287 20 27 [ 2] 671 jra 00124$
000289 672 00114$:
673 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 976: else if (reg == 0x40) /* The flag to check is in SWCR register */
000289 A1 40 [ 1] 674 cp a, #0x40
00028B 26 05 [ 1] 675 jrne 00111$
676 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 978: reg = CLK->SWCR;
00028D C6 50 C9 [ 1] 677 ld a, 0x50c9
000290 20 1E [ 2] 678 jra 00124$
000292 679 00111$:
680 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 980: else if (reg == 0x50) /* The flag to check is in CSSR register */
000292 A1 50 [ 1] 681 cp a, #0x50
000294 26 05 [ 1] 682 jrne 00108$
683 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 982: reg = CLK->CSSR;
000296 C6 50 CA [ 1] 684 ld a, 0x50ca
000299 20 15 [ 2] 685 jra 00124$
00029B 686 00108$:
687 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 984: else if (reg == 0x70) /* The flag to check is in REGCSR register */
00029B A1 70 [ 1] 688 cp a, #0x70
00029D 26 05 [ 1] 689 jrne 00105$
690 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 986: reg = CLK->REGCSR;
00029F C6 50 CF [ 1] 691 ld a, 0x50cf
0002A2 20 0C [ 2] 692 jra 00124$
0002A4 693 00105$:
694 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 988: else if (reg == 0x80) /* The flag to check is in CSSLSE_CSRregister */
0002A4 A1 80 [ 1] 695 cp a, #0x80
0002A6 26 05 [ 1] 696 jrne 00102$
697 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 990: reg = CSSLSE->CSR;
0002A8 C6 51 90 [ 1] 698 ld a, 0x5190
0002AB 20 03 [ 2] 699 jra 00124$
0002AD 700 00102$:
701 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 994: reg = CLK->CBEEPR;
0002AD C6 50 CB [ 1] 702 ld a, 0x50cb
0002B0 703 00124$:
704 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 998: if ((reg & (uint8_t)((uint8_t)1 << (uint8_t)pos)) != (uint8_t)RESET)
0002B0 88 [ 1] 705 push a
0002B1 A6 01 [ 1] 706 ld a, #0x01
0002B3 6B 02 [ 1] 707 ld (0x02, sp), a
0002B5 9F [ 1] 708 ld a, xl
0002B6 4D [ 1] 709 tnz a
0002B7 27 05 [ 1] 710 jreq 00216$
0002B9 711 00215$:
0002B9 08 02 [ 1] 712 sll (0x02, sp)
0002BB 4A [ 1] 713 dec a
0002BC 26 FB [ 1] 714 jrne 00215$
0002BE 715 00216$:
0002BE 84 [ 1] 716 pop a
0002BF 14 01 [ 1] 717 and a, (0x01, sp)
0002C1 27 03 [ 1] 718 jreq 00126$
719 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1000: bitstatus = SET;
0002C3 A6 01 [ 1] 720 ld a, #0x01
721 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1004: bitstatus = RESET;
0002C5 21 722 .byte 0x21
0002C6 723 00126$:
0002C6 4F [ 1] 724 clr a
0002C7 725 00127$:
726 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1008: return((FlagStatus)bitstatus);
727 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1009: }
0002C7 5B 01 [ 2] 728 addw sp, #1
0002C9 81 [ 4] 729 ret
730 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1016: void CLK_ClearFlag(void)
731 ; -----------------------------------------
732 ; function CLK_ClearFlag
733 ; -----------------------------------------
0002CA 734 _CLK_ClearFlag:
735 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1020: CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSF);
0002CA 72 17 51 90 [ 1] 736 bres 0x5190, #3
737 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1021: }
0002CE 81 [ 4] 738 ret
739 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1032: ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
740 ; -----------------------------------------
741 ; function CLK_GetITStatus
742 ; -----------------------------------------
0002CF 743 _CLK_GetITStatus:
0002CF 88 [ 1] 744 push a
745 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1040: if (CLK_IT == CLK_IT_SWIF)
0002D0 6B 01 [ 1] 746 ld (0x01, sp), a
0002D2 A1 1C [ 1] 747 cp a, #0x1c
0002D4 26 0F [ 1] 748 jrne 00114$
749 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1043: if ((CLK->SWCR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
0002D6 C6 50 C9 [ 1] 750 ld a, 0x50c9
0002D9 14 01 [ 1] 751 and a, (0x01, sp)
752 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1045: bitstatus = SET;
0002DB A0 0C [ 1] 753 sub a, #0x0c
0002DD 26 03 [ 1] 754 jrne 00102$
0002DF 4C [ 1] 755 inc a
0002E0 20 24 [ 2] 756 jra 00115$
0002E2 757 00102$:
758 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1049: bitstatus = RESET;
0002E2 4F [ 1] 759 clr a
0002E3 20 21 [ 2] 760 jra 00115$
0002E5 761 00114$:
762 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1052: else if (CLK_IT == CLK_IT_LSECSSF)
0002E5 7B 01 [ 1] 763 ld a, (0x01, sp)
0002E7 A1 2C [ 1] 764 cp a, #0x2c
0002E9 26 0F [ 1] 765 jrne 00111$
766 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1055: if ((CSSLSE->CSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
0002EB C6 51 90 [ 1] 767 ld a, 0x5190
0002EE 14 01 [ 1] 768 and a, (0x01, sp)
769 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1057: bitstatus = SET;
0002F0 A0 0C [ 1] 770 sub a, #0x0c
0002F2 26 03 [ 1] 771 jrne 00105$
0002F4 4C [ 1] 772 inc a
0002F5 20 0F [ 2] 773 jra 00115$
0002F7 774 00105$:
775 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1061: bitstatus = RESET;
0002F7 4F [ 1] 776 clr a
0002F8 20 0C [ 2] 777 jra 00115$
0002FA 778 00111$:
779 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1067: if ((CLK->CSSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
0002FA C6 50 CA [ 1] 780 ld a, 0x50ca
0002FD 14 01 [ 1] 781 and a, (0x01, sp)
782 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1069: bitstatus = SET;
0002FF A0 0C [ 1] 783 sub a, #0x0c
000301 26 02 [ 1] 784 jrne 00108$
000303 4C [ 1] 785 inc a
786 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1073: bitstatus = RESET;
000304 21 787 .byte 0x21
000305 788 00108$:
000305 4F [ 1] 789 clr a
000306 790 00115$:
791 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1078: return bitstatus;
792 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1079: }
000306 5B 01 [ 2] 793 addw sp, #1
000308 81 [ 4] 794 ret
795 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1089: void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
796 ; -----------------------------------------
797 ; function CLK_ClearITPendingBit
798 ; -----------------------------------------
000309 799 _CLK_ClearITPendingBit:
800 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1095: if ((uint8_t)((uint8_t)CLK_IT & (uint8_t)0xF0) == (uint8_t)0x20)
000309 A4 F0 [ 1] 801 and a, #0xf0
00030B A1 20 [ 1] 802 cp a, #0x20
00030D 26 05 [ 1] 803 jrne 00102$
804 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1098: CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSF);
00030F 72 17 51 90 [ 1] 805 bres 0x5190, #3
000313 81 [ 4] 806 ret
000314 807 00102$:
808 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1103: CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIF);
000314 72 17 50 C9 [ 1] 809 bres 0x50c9, #3
810 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1105: }
000318 81 [ 4] 811 ret
812 .area CODE
813 .area CONST
814 .area CONST
000000 815 _SYSDivFactor:
000000 01 816 .db #0x01 ; 1
000001 02 817 .db #0x02 ; 2
000002 04 818 .db #0x04 ; 4
000003 08 819 .db #0x08 ; 8
000004 10 820 .db #0x10 ; 16
821 .area CODE
822 .area INITIALIZER
823 .area CABS (ABS)

417
firmware/STM8L15X_LD/stm8l15x_clk.rel Normal file
View File

@@ -0,0 +1,417 @@
XH3
H B areas 1D global symbols
M stm8l15x_clk
S .__.ABS. Def000000
S __divulong Ref000000
A _CODE size 0 flags 0 addr 0
A DATA size 0 flags 0 addr 0
A INITIALIZED size 0 flags 0 addr 0
A DABS size 0 flags 8 addr 0
A HOME size 0 flags 0 addr 0
A GSINIT size 0 flags 0 addr 0
A GSFINAL size 0 flags 0 addr 0
A CONST size 5 flags 0 addr 0
S _SYSDivFactor Def000000
A INITIALIZER size 0 flags 0 addr 0
A CODE size 319 flags 0 addr 0
S _CLK_ClearITPendingBit Def000309
S _CLK_GetSYSCLKSource Def0000D0
S _CLK_RTCClockConfig Def000143
S _CLK_CCOConfig Def0000C4
S _CLK_ITConfig Def0001F7
S _CLK_LSEClockSecuritySystemEnable Def0001B7
S _CLK_AdjustHSICalibrationValue Def000059
S _CLK_HSEConfig Def00007D
S _CLK_HSICmd Def000041
S _CLK_LSEConfig Def000092
S _CLK_LSICmd Def000065
S _CLK_DeInit Def000000
S _CLK_GetITStatus Def0002CF
S _CLK_MainRegulatorCmd Def0001DF
S _CLK_PeripheralClockConfig Def00014F
S _CLK_ClockSecuritySytemDeglitchCmd Def0000AC
S _CLK_SYSCLKSourceSwitchCmd Def00012B
S _CLK_ClockSecuritySystemEnable Def0000A7
S _CLK_SYSCLKDivConfig Def000127
S _CLK_GetClockFreq Def0000D4
S _CLK_GetFlagStatus Def00025C
S _CLK_BEEPClockConfig Def00014B
S _CLK_HaltConfig Def0001C1
S _CLK_SYSCLKSourceConfig Def0000CC
S _CLK_ClearFlag Def0002CA
S _CLK_RTCCLKSwitchOnLSEFailureEnable Def0001BC
A CABS size 0 flags 8 addr 0
T 00 00 00
R 00 00 00 09
T 00 00 00 35 11 50 C2 35 00 50 C6 35 00 50 C1 35
R 00 00 00 09
T 00 00 0D 00 50 CB 35 01 50 C8 35 00 50 C9 35 03
R 00 00 00 09
T 00 00 1A 50 C0 35 00 50 C3 35 80 50 C4 35 00
R 00 00 00 09
T 00 00 26 50 D0 35 00 50 CA 35 00 50 C5 35 00
R 00 00 00 09
T 00 00 32 50 CD 35 00 50 CC 35 00 50 CE 35 B9
R 00 00 00 09
T 00 00 3E 50 CF 81
R 00 00 00 09
T 00 00 41
R 00 00 00 09
T 00 00 41 88 6B 01 C6 50 C2 0D 01 27 07 AA 01 C7
R 00 00 00 09
T 00 00 4E 50 C2 20 05
R 00 00 00 09
T 00 00 52
R 00 00 00 09
T 00 00 52 A4 FE C7 50 C2
R 00 00 00 09
T 00 00 57
R 00 00 00 09
T 00 00 57 84 81
R 00 00 00 09
T 00 00 59
R 00 00 00 09
T 00 00 59 35 AC 50 CE 35 35 50 CE C7 50 CD 81
R 00 00 00 09
T 00 00 65
R 00 00 00 09
T 00 00 65 88 6B 01 C6 50 C2 0D 01 27 07 AA 04 C7
R 00 00 00 09
T 00 00 72 50 C2 20 05
R 00 00 00 09
T 00 00 76
R 00 00 00 09
T 00 00 76 A4 FB C7 50 C2
R 00 00 00 09
T 00 00 7B
R 00 00 00 09
T 00 00 7B 84 81
R 00 00 00 09
T 00 00 7D
R 00 00 00 09
T 00 00 7D 88 6B 01 72 11 50 C6 72 19 50 C6 C6
R 00 00 00 09
T 00 00 89 50 C6 1A 01 C7 50 C6 84 81
R 00 00 00 09
T 00 00 92
R 00 00 00 09
T 00 00 92 88 6B 01 72 15 50 C6 72 1B 50 C6 C6
R 00 00 00 09
T 00 00 9E 50 C6 1A 01 C7 50 C6 84 81
R 00 00 00 09
T 00 00 A7
R 00 00 00 09
T 00 00 A7 72 10 50 CA 81
R 00 00 00 09
T 00 00 AC
R 00 00 00 09
T 00 00 AC 88 6B 01 C6 50 CA 0D 01 27 07 AA 10 C7
R 00 00 00 09
T 00 00 B9 50 CA 20 05
R 00 00 00 09
T 00 00 BD
R 00 00 00 09
T 00 00 BD A4 EF C7 50 CA
R 00 00 00 09
T 00 00 C2
R 00 00 00 09
T 00 00 C2 84 81
R 00 00 00 09
T 00 00 C4
R 00 00 00 09
T 00 00 C4 1A 03 C7 50 C5 85 84 FC
R 00 00 00 09
T 00 00 CC
R 00 00 00 09
T 00 00 CC C7 50 C8 81
R 00 00 00 09
T 00 00 D0
R 00 00 00 09
T 00 00 D0 C6 50 C7 81
R 00 00 00 09
T 00 00 D4
R 00 00 00 09
T 00 00 D4 52 08 5F 1F 03 1F 01 C6 50 C7 A1 01 26
R 00 00 00 09
T 00 00 E1 0C AE 24 00 1F 03 AE 00 F4 1F 01 20 1C
R 00 00 00 09
T 00 00 EE
R 00 00 00 09
T 00 00 EE A1 02 26 0A AE 94 70 1F 03 5F 1F 01 20
R 00 00 00 09
T 00 00 FB 0E
R 00 00 00 09
T 00 00 FC
R 00 00 00 09
T 00 00 FC A1 04 26 0A AE 24 00 1F 03 AE 00 F4 1F
R 00 00 00 09
T 00 01 09 01
R 00 00 00 09
T 00 01 0A
R 00 00 00 09
T 00 01 0A C6 50 C0 A4 07 5F 97 D6 00 00 5F 0F 05
R 00 00 00 09 10 0B 00 07
T 00 01 17 88 89 4F 88 1E 07 89 1E 07 89 CD 00 00
R 00 00 00 09 02 0E 00 01
T 00 01 24 5B 10 81
R 00 00 00 09
T 00 01 27
R 00 00 00 09
T 00 01 27 C7 50 C0 81
R 00 00 00 09
T 00 01 2B
R 00 00 00 09
T 00 01 2B 88 6B 01 C6 50 C9 0D 01 27 07 AA 02 C7
R 00 00 00 09
T 00 01 38 50 C9 20 05
R 00 00 00 09
T 00 01 3C
R 00 00 00 09
T 00 01 3C A4 FD C7 50 C9
R 00 00 00 09
T 00 01 41
R 00 00 00 09
T 00 01 41 84 81
R 00 00 00 09
T 00 01 43
R 00 00 00 09
T 00 01 43 1A 03 C7 50 C1 85 84 FC
R 00 00 00 09
T 00 01 4B
R 00 00 00 09
T 00 01 4B C7 50 CB 81
R 00 00 00 09
T 00 01 4F
R 00 00 00 09
T 00 01 4F 89 88 A4 F0 97 84 90 93 A4 0F 88 A6 01
R 00 00 00 09
T 00 01 5C 6B 02 84 4D 27 05
R 00 00 00 09
T 00 01 62
R 00 00 00 09
T 00 01 62 08 01 4A 26 FB
R 00 00 00 09
T 00 01 67
R 00 00 00 09
T 00 01 67 7B 01 43 6B 02 9F 4D 26 15 C6 50 C3 0D
R 00 00 00 09
T 00 01 74 05 27 07 1A 01 C7 50 C3 20 35
R 00 00 00 09
T 00 01 7E
R 00 00 00 09
T 00 01 7E 14 02 C7 50 C3 20 2E
R 00 00 00 09
T 00 01 85
R 00 00 00 09
T 00 01 85 90 9F A1 10 26 15 C6 50 C4 0D 05 27 07
R 00 00 00 09
T 00 01 92 1A 01 C7 50 C4 20 1A
R 00 00 00 09
T 00 01 99
R 00 00 00 09
T 00 01 99 14 02 C7 50 C4 20 13
R 00 00 00 09
T 00 01 A0
R 00 00 00 09
T 00 01 A0 C6 50 D0 0D 05 27 07 1A 01 C7 50 D0 20
R 00 00 00 09
T 00 01 AD 05
R 00 00 00 09
T 00 01 AE
R 00 00 00 09
T 00 01 AE 14 02 C7 50 D0
R 00 00 00 09
T 00 01 B3
R 00 00 00 09
T 00 01 B3 85 85 84 FC
R 00 00 00 09
T 00 01 B7
R 00 00 00 09
T 00 01 B7 72 10 51 90 81
R 00 00 00 09
T 00 01 BC
R 00 00 00 09
T 00 01 BC 72 12 51 90 81
R 00 00 00 09
T 00 01 C1
R 00 00 00 09
T 00 01 C1 88 AE 50 C2 88 F6 6B 02 84 0D 04 27 07
R 00 00 00 09
T 00 01 CE 1A 01 C7 50 C2 20 06
R 00 00 00 09
T 00 01 D5
R 00 00 00 09
T 00 01 D5 43 14 01 C7 50 C2
R 00 00 00 09
T 00 01 DB
R 00 00 00 09
T 00 01 DB 84 85 84 FC
R 00 00 00 09
T 00 01 DF
R 00 00 00 09
T 00 01 DF 88 6B 01 C6 50 CF 0D 01 27 07 A4 FD C7
R 00 00 00 09
T 00 01 EC 50 CF 20 05
R 00 00 00 09
T 00 01 F0
R 00 00 00 09
T 00 01 F0 AA 02 C7 50 CF
R 00 00 00 09
T 00 01 F5
R 00 00 00 09
T 00 01 F5 84 81
R 00 00 00 09
T 00 01 F7
R 00 00 00 09
T 00 01 F7 88 A1 1C 26 07 88 A6 01 6B 02 84 C5
R 00 00 00 09
T 00 02 03
R 00 00 00 09
T 00 02 03 0F 01
R 00 00 00 09
T 00 02 05
R 00 00 00 09
T 00 02 05 A0 2C 26 02 4C 21
R 00 00 00 09
T 00 02 0B
R 00 00 00 09
T 00 02 0B 4F
R 00 00 00 09
T 00 02 0C
R 00 00 00 09
T 00 02 0C 0D 04 27 25 0D 01 27 0A C6 50 C9 AA 04
R 00 00 00 09
T 00 02 19 C7 50 C9 20 3A
R 00 00 00 09
T 00 02 1E
R 00 00 00 09
T 00 02 1E 4D 27 0A C6 51 90 AA 04 C7 51 90 20 2D
R 00 00 00 09
T 00 02 2B
R 00 00 00 09
T 00 02 2B C6 50 CA AA 04 C7 50 CA 20 23
R 00 00 00 09
T 00 02 35
R 00 00 00 09
T 00 02 35 0D 01 27 0A C6 50 C9 A4 FB C7 50 C9 20
R 00 00 00 09
T 00 02 42 15
R 00 00 00 09
T 00 02 43
R 00 00 00 09
T 00 02 43 4D 27 0A C6 51 90 A4 FB C7 51 90 20 08
R 00 00 00 09
T 00 02 50
R 00 00 00 09
T 00 02 50 C6 50 CA A4 FB C7 50 CA
R 00 00 00 09
T 00 02 58
R 00 00 00 09
T 00 02 58 84 85 84 FC
R 00 00 00 09
T 00 02 5C
R 00 00 00 09
T 00 02 5C 88 97 A4 F0 88 9F A4 0F 97 84 4D 26 05
R 00 00 00 09
T 00 02 69 C6 50 C1 20 42
R 00 00 00 09
T 00 02 6E
R 00 00 00 09
T 00 02 6E A1 10 26 05 C6 50 C2 20 39
R 00 00 00 09
T 00 02 77
R 00 00 00 09
T 00 02 77 A1 20 26 05 C6 50 C5 20 30
R 00 00 00 09
T 00 02 80
R 00 00 00 09
T 00 02 80 A1 30 26 05 C6 50 C6 20 27
R 00 00 00 09
T 00 02 89
R 00 00 00 09
T 00 02 89 A1 40 26 05 C6 50 C9 20 1E
R 00 00 00 09
T 00 02 92
R 00 00 00 09
T 00 02 92 A1 50 26 05 C6 50 CA 20 15
R 00 00 00 09
T 00 02 9B
R 00 00 00 09
T 00 02 9B A1 70 26 05 C6 50 CF 20 0C
R 00 00 00 09
T 00 02 A4
R 00 00 00 09
T 00 02 A4 A1 80 26 05 C6 51 90 20 03
R 00 00 00 09
T 00 02 AD
R 00 00 00 09
T 00 02 AD C6 50 CB
R 00 00 00 09
T 00 02 B0
R 00 00 00 09
T 00 02 B0 88 A6 01 6B 02 9F 4D 27 05
R 00 00 00 09
T 00 02 B9
R 00 00 00 09
T 00 02 B9 08 02 4A 26 FB
R 00 00 00 09
T 00 02 BE
R 00 00 00 09
T 00 02 BE 84 14 01 27 03 A6 01 21
R 00 00 00 09
T 00 02 C6
R 00 00 00 09
T 00 02 C6 4F
R 00 00 00 09
T 00 02 C7
R 00 00 00 09
T 00 02 C7 5B 01 81
R 00 00 00 09
T 00 02 CA
R 00 00 00 09
T 00 02 CA 72 17 51 90 81
R 00 00 00 09
T 00 02 CF
R 00 00 00 09
T 00 02 CF 88 6B 01 A1 1C 26 0F C6 50 C9 14 01 A0
R 00 00 00 09
T 00 02 DC 0C 26 03 4C 20 24
R 00 00 00 09
T 00 02 E2
R 00 00 00 09
T 00 02 E2 4F 20 21
R 00 00 00 09
T 00 02 E5
R 00 00 00 09
T 00 02 E5 7B 01 A1 2C 26 0F C6 51 90 14 01 A0 0C
R 00 00 00 09
T 00 02 F2 26 03 4C 20 0F
R 00 00 00 09
T 00 02 F7
R 00 00 00 09
T 00 02 F7 4F 20 0C
R 00 00 00 09
T 00 02 FA
R 00 00 00 09
T 00 02 FA C6 50 CA 14 01 A0 0C 26 02 4C 21
R 00 00 00 09
T 00 03 05
R 00 00 00 09
T 00 03 05 4F
R 00 00 00 09
T 00 03 06
R 00 00 00 09
T 00 03 06 5B 01 81
R 00 00 00 09
T 00 03 09
R 00 00 00 09
T 00 03 09 A4 F0 A1 20 26 05 72 17 51 90 81
R 00 00 00 09
T 00 03 14
R 00 00 00 09
T 00 03 14 72 17 50 C9 81
R 00 00 00 09
T 00 00 00
R 00 00 00 07
T 00 00 00 01 02 04 08 10
R 00 00 00 07

823
firmware/STM8L15X_LD/stm8l15x_clk.rst Normal file
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@@ -0,0 +1,823 @@
1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ISO C Compiler
3 ; Version 4.5.0 #15242 (Linux)
4 ;--------------------------------------------------------
5 .module stm8l15x_clk
6
7 ;--------------------------------------------------------
8 ; Public variables in this module
9 ;--------------------------------------------------------
10 .globl _SYSDivFactor
11 .globl _CLK_DeInit
12 .globl _CLK_HSICmd
13 .globl _CLK_AdjustHSICalibrationValue
14 .globl _CLK_LSICmd
15 .globl _CLK_HSEConfig
16 .globl _CLK_LSEConfig
17 .globl _CLK_ClockSecuritySystemEnable
18 .globl _CLK_ClockSecuritySytemDeglitchCmd
19 .globl _CLK_CCOConfig
20 .globl _CLK_SYSCLKSourceConfig
21 .globl _CLK_GetSYSCLKSource
22 .globl _CLK_GetClockFreq
23 .globl _CLK_SYSCLKDivConfig
24 .globl _CLK_SYSCLKSourceSwitchCmd
25 .globl _CLK_RTCClockConfig
26 .globl _CLK_BEEPClockConfig
27 .globl _CLK_PeripheralClockConfig
28 .globl _CLK_LSEClockSecuritySystemEnable
29 .globl _CLK_RTCCLKSwitchOnLSEFailureEnable
30 .globl _CLK_HaltConfig
31 .globl _CLK_MainRegulatorCmd
32 .globl _CLK_ITConfig
33 .globl _CLK_GetFlagStatus
34 .globl _CLK_ClearFlag
35 .globl _CLK_GetITStatus
36 .globl _CLK_ClearITPendingBit
37 ;--------------------------------------------------------
38 ; ram data
39 ;--------------------------------------------------------
40 .area DATA
41 ;--------------------------------------------------------
42 ; ram data
43 ;--------------------------------------------------------
44 .area INITIALIZED
45 ;--------------------------------------------------------
46 ; absolute external ram data
47 ;--------------------------------------------------------
48 .area DABS (ABS)
49
50 ; default segment ordering for linker
51 .area HOME
52 .area GSINIT
53 .area GSFINAL
54 .area CONST
55 .area INITIALIZER
56 .area CODE
57
58 ;--------------------------------------------------------
59 ; global & static initialisations
60 ;--------------------------------------------------------
61 .area HOME
62 .area GSINIT
63 .area GSFINAL
64 .area GSINIT
65 ;--------------------------------------------------------
66 ; Home
67 ;--------------------------------------------------------
68 .area HOME
69 .area HOME
70 ;--------------------------------------------------------
71 ; code
72 ;--------------------------------------------------------
73 .area CODE
74 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 120: void CLK_DeInit(void)
75 ; -----------------------------------------
76 ; function CLK_DeInit
77 ; -----------------------------------------
008502 78 _CLK_DeInit:
79 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 122: CLK->ICKCR = CLK_ICKCR_RESET_VALUE;
008502 35 11 50 C2 [ 1] 80 mov 0x50c2+0, #0x11
81 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 123: CLK->ECKCR = CLK_ECKCR_RESET_VALUE;
008506 35 00 50 C6 [ 1] 82 mov 0x50c6+0, #0x00
83 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 124: CLK->CRTCR = CLK_CRTCR_RESET_VALUE;
00850A 35 00 50 C1 [ 1] 84 mov 0x50c1+0, #0x00
85 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 125: CLK->CBEEPR = CLK_CBEEPR_RESET_VALUE;
00850E 35 00 50 CB [ 1] 86 mov 0x50cb+0, #0x00
87 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 126: CLK->SWR = CLK_SWR_RESET_VALUE;
008512 35 01 50 C8 [ 1] 88 mov 0x50c8+0, #0x01
89 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 127: CLK->SWCR = CLK_SWCR_RESET_VALUE;
008516 35 00 50 C9 [ 1] 90 mov 0x50c9+0, #0x00
91 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 128: CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
00851A 35 03 50 C0 [ 1] 92 mov 0x50c0+0, #0x03
93 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 129: CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
00851E 35 00 50 C3 [ 1] 94 mov 0x50c3+0, #0x00
95 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 130: CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
008522 35 80 50 C4 [ 1] 96 mov 0x50c4+0, #0x80
97 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 131: CLK->PCKENR3 = CLK_PCKENR3_RESET_VALUE;
008526 35 00 50 D0 [ 1] 98 mov 0x50d0+0, #0x00
99 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 132: CLK->CSSR = CLK_CSSR_RESET_VALUE;
00852A 35 00 50 CA [ 1] 100 mov 0x50ca+0, #0x00
101 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 133: CLK->CCOR = CLK_CCOR_RESET_VALUE;
00852E 35 00 50 C5 [ 1] 102 mov 0x50c5+0, #0x00
103 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 134: CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
008532 35 00 50 CD [ 1] 104 mov 0x50cd+0, #0x00
105 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 135: CLK->HSICALR = CLK_HSICALR_RESET_VALUE;
008536 35 00 50 CC [ 1] 106 mov 0x50cc+0, #0x00
107 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 136: CLK->HSIUNLCKR = CLK_HSIUNLCKR_RESET_VALUE;
00853A 35 00 50 CE [ 1] 108 mov 0x50ce+0, #0x00
109 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 137: CLK->REGCSR = CLK_REGCSR_RESET_VALUE;
00853E 35 B9 50 CF [ 1] 110 mov 0x50cf+0, #0xb9
111 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 138: }
008542 81 [ 4] 112 ret
113 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 160: void CLK_HSICmd(FunctionalState NewState)
114 ; -----------------------------------------
115 ; function CLK_HSICmd
116 ; -----------------------------------------
008543 117 _CLK_HSICmd:
008543 88 [ 1] 118 push a
008544 6B 01 [ 1] 119 ld (0x01, sp), a
120 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 168: CLK->ICKCR |= CLK_ICKCR_HSION;
008546 C6 50 C2 [ 1] 121 ld a, 0x50c2
122 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 165: if (NewState != DISABLE)
008549 0D 01 [ 1] 123 tnz (0x01, sp)
00854B 27 07 [ 1] 124 jreq 00102$
125 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 168: CLK->ICKCR |= CLK_ICKCR_HSION;
00854D AA 01 [ 1] 126 or a, #0x01
00854F C7 50 C2 [ 1] 127 ld 0x50c2, a
008552 20 05 [ 2] 128 jra 00104$
008554 129 00102$:
130 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 173: CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_HSION);
008554 A4 FE [ 1] 131 and a, #0xfe
008556 C7 50 C2 [ 1] 132 ld 0x50c2, a
008559 133 00104$:
134 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 175: }
008559 84 [ 1] 135 pop a
00855A 81 [ 4] 136 ret
137 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 188: void CLK_AdjustHSICalibrationValue(uint8_t CLK_HSICalibrationValue)
138 ; -----------------------------------------
139 ; function CLK_AdjustHSICalibrationValue
140 ; -----------------------------------------
00855B 141 _CLK_AdjustHSICalibrationValue:
142 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 191: CLK->HSIUNLCKR = 0xAC;
00855B 35 AC 50 CE [ 1] 143 mov 0x50ce+0, #0xac
144 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 192: CLK->HSIUNLCKR = 0x35;
00855F 35 35 50 CE [ 1] 145 mov 0x50ce+0, #0x35
146 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 195: CLK->HSITRIMR = (uint8_t)CLK_HSICalibrationValue;
008563 C7 50 CD [ 1] 147 ld 0x50cd, a
148 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 196: }
008566 81 [ 4] 149 ret
150 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 212: void CLK_LSICmd(FunctionalState NewState)
151 ; -----------------------------------------
152 ; function CLK_LSICmd
153 ; -----------------------------------------
008567 154 _CLK_LSICmd:
008567 88 [ 1] 155 push a
008568 6B 01 [ 1] 156 ld (0x01, sp), a
157 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 221: CLK->ICKCR |= CLK_ICKCR_LSION;
00856A C6 50 C2 [ 1] 158 ld a, 0x50c2
159 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 218: if (NewState != DISABLE)
00856D 0D 01 [ 1] 160 tnz (0x01, sp)
00856F 27 07 [ 1] 161 jreq 00102$
162 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 221: CLK->ICKCR |= CLK_ICKCR_LSION;
008571 AA 04 [ 1] 163 or a, #0x04
008573 C7 50 C2 [ 1] 164 ld 0x50c2, a
008576 20 05 [ 2] 165 jra 00104$
008578 166 00102$:
167 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 226: CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_LSION);
008578 A4 FB [ 1] 168 and a, #0xfb
00857A C7 50 C2 [ 1] 169 ld 0x50c2, a
00857D 170 00104$:
171 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 228: }
00857D 84 [ 1] 172 pop a
00857E 81 [ 4] 173 ret
174 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 249: void CLK_HSEConfig(CLK_HSE_TypeDef CLK_HSE)
175 ; -----------------------------------------
176 ; function CLK_HSEConfig
177 ; -----------------------------------------
00857F 178 _CLK_HSEConfig:
00857F 88 [ 1] 179 push a
008580 6B 01 [ 1] 180 ld (0x01, sp), a
181 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 256: CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEON;
008582 72 11 50 C6 [ 1] 182 bres 0x50c6, #0
183 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 259: CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEBYP;
008586 72 19 50 C6 [ 1] 184 bres 0x50c6, #4
185 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 262: CLK->ECKCR |= (uint8_t)CLK_HSE;
00858A C6 50 C6 [ 1] 186 ld a, 0x50c6
00858D 1A 01 [ 1] 187 or a, (0x01, sp)
00858F C7 50 C6 [ 1] 188 ld 0x50c6, a
189 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 263: }
008592 84 [ 1] 190 pop a
008593 81 [ 4] 191 ret
192 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 280: void CLK_LSEConfig(CLK_LSE_TypeDef CLK_LSE)
193 ; -----------------------------------------
194 ; function CLK_LSEConfig
195 ; -----------------------------------------
008594 196 _CLK_LSEConfig:
008594 88 [ 1] 197 push a
008595 6B 01 [ 1] 198 ld (0x01, sp), a
199 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 287: CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEON;
008597 72 15 50 C6 [ 1] 200 bres 0x50c6, #2
201 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 290: CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEBYP;
00859B 72 1B 50 C6 [ 1] 202 bres 0x50c6, #5
203 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 293: CLK->ECKCR |= (uint8_t)CLK_LSE;
00859F C6 50 C6 [ 1] 204 ld a, 0x50c6
0085A2 1A 01 [ 1] 205 or a, (0x01, sp)
0085A4 C7 50 C6 [ 1] 206 ld 0x50c6, a
207 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 295: }
0085A7 84 [ 1] 208 pop a
0085A8 81 [ 4] 209 ret
210 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 306: void CLK_ClockSecuritySystemEnable(void)
211 ; -----------------------------------------
212 ; function CLK_ClockSecuritySystemEnable
213 ; -----------------------------------------
0085A9 214 _CLK_ClockSecuritySystemEnable:
215 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 309: CLK->CSSR |= CLK_CSSR_CSSEN;
0085A9 72 10 50 CA [ 1] 216 bset 0x50ca, #0
217 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 310: }
0085AD 81 [ 4] 218 ret
219 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 317: void CLK_ClockSecuritySytemDeglitchCmd(FunctionalState NewState)
220 ; -----------------------------------------
221 ; function CLK_ClockSecuritySytemDeglitchCmd
222 ; -----------------------------------------
0085AE 223 _CLK_ClockSecuritySytemDeglitchCmd:
0085AE 88 [ 1] 224 push a
0085AF 6B 01 [ 1] 225 ld (0x01, sp), a
226 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 325: CLK->CSSR |= CLK_CSSR_CSSDGON;
0085B1 C6 50 CA [ 1] 227 ld a, 0x50ca
228 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 322: if (NewState != DISABLE)
0085B4 0D 01 [ 1] 229 tnz (0x01, sp)
0085B6 27 07 [ 1] 230 jreq 00102$
231 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 325: CLK->CSSR |= CLK_CSSR_CSSDGON;
0085B8 AA 10 [ 1] 232 or a, #0x10
0085BA C7 50 CA [ 1] 233 ld 0x50ca, a
0085BD 20 05 [ 2] 234 jra 00104$
0085BF 235 00102$:
236 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 330: CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDGON);
0085BF A4 EF [ 1] 237 and a, #0xef
0085C1 C7 50 CA [ 1] 238 ld 0x50ca, a
0085C4 239 00104$:
240 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 332: }
0085C4 84 [ 1] 241 pop a
0085C5 81 [ 4] 242 ret
243 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 356: void CLK_CCOConfig(CLK_CCOSource_TypeDef CLK_CCOSource, CLK_CCODiv_TypeDef CLK_CCODiv)
244 ; -----------------------------------------
245 ; function CLK_CCOConfig
246 ; -----------------------------------------
0085C6 247 _CLK_CCOConfig:
248 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 363: CLK->CCOR = (uint8_t)((uint8_t)CLK_CCOSource | (uint8_t)CLK_CCODiv);
0085C6 1A 03 [ 1] 249 or a, (0x03, sp)
0085C8 C7 50 C5 [ 1] 250 ld 0x50c5, a
251 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 364: }
0085CB 85 [ 2] 252 popw x
0085CC 84 [ 1] 253 pop a
0085CD FC [ 2] 254 jp (x)
255 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 416: void CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_TypeDef CLK_SYSCLKSource)
256 ; -----------------------------------------
257 ; function CLK_SYSCLKSourceConfig
258 ; -----------------------------------------
0085CE 259 _CLK_SYSCLKSourceConfig:
260 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 422: CLK->SWR = (uint8_t)CLK_SYSCLKSource;
0085CE C7 50 C8 [ 1] 261 ld 0x50c8, a
262 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 423: }
0085D1 81 [ 4] 263 ret
264 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 435: CLK_SYSCLKSource_TypeDef CLK_GetSYSCLKSource(void)
265 ; -----------------------------------------
266 ; function CLK_GetSYSCLKSource
267 ; -----------------------------------------
0085D2 268 _CLK_GetSYSCLKSource:
269 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 437: return ((CLK_SYSCLKSource_TypeDef)(CLK->SCSR));
0085D2 C6 50 C7 [ 1] 270 ld a, 0x50c7
271 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 438: }
0085D5 81 [ 4] 272 ret
273 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 478: uint32_t CLK_GetClockFreq(void)
274 ; -----------------------------------------
275 ; function CLK_GetClockFreq
276 ; -----------------------------------------
0085D6 277 _CLK_GetClockFreq:
0085D6 52 08 [ 2] 278 sub sp, #8
279 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 481: uint32_t sourcefrequency = 0;
0085D8 5F [ 1] 280 clrw x
0085D9 1F 03 [ 2] 281 ldw (0x03, sp), x
0085DB 1F 01 [ 2] 282 ldw (0x01, sp), x
283 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 486: clocksource = (CLK_SYSCLKSource_TypeDef)CLK->SCSR;
0085DD C6 50 C7 [ 1] 284 ld a, 0x50c7
285 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 488: if ( clocksource == CLK_SYSCLKSource_HSI)
0085E0 A1 01 [ 1] 286 cp a, #0x01
0085E2 26 0C [ 1] 287 jrne 00108$
288 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 490: sourcefrequency = HSI_VALUE;
0085E4 AE 24 00 [ 2] 289 ldw x, #0x2400
0085E7 1F 03 [ 2] 290 ldw (0x03, sp), x
0085E9 AE 00 F4 [ 2] 291 ldw x, #0x00f4
0085EC 1F 01 [ 2] 292 ldw (0x01, sp), x
0085EE 20 1C [ 2] 293 jra 00109$
0085F0 294 00108$:
295 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 492: else if ( clocksource == CLK_SYSCLKSource_LSI)
0085F0 A1 02 [ 1] 296 cp a, #0x02
0085F2 26 0A [ 1] 297 jrne 00105$
298 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 494: sourcefrequency = LSI_VALUE;
0085F4 AE 94 70 [ 2] 299 ldw x, #0x9470
0085F7 1F 03 [ 2] 300 ldw (0x03, sp), x
0085F9 5F [ 1] 301 clrw x
0085FA 1F 01 [ 2] 302 ldw (0x01, sp), x
0085FC 20 0E [ 2] 303 jra 00109$
0085FE 304 00105$:
305 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 496: else if ( clocksource == CLK_SYSCLKSource_HSE)
0085FE A1 04 [ 1] 306 cp a, #0x04
008600 26 0A [ 1] 307 jrne 00109$
308 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 498: sourcefrequency = HSE_VALUE;
008602 AE 24 00 [ 2] 309 ldw x, #0x2400
008605 1F 03 [ 2] 310 ldw (0x03, sp), x
008607 AE 00 F4 [ 2] 311 ldw x, #0x00f4
00860A 1F 01 [ 2] 312 ldw (0x01, sp), x
313 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 502: clockfrequency = LSE_VALUE;
00860C 314 00109$:
315 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 506: tmp = (uint8_t)(CLK->CKDIVR & CLK_CKDIVR_CKM);
00860C C6 50 C0 [ 1] 316 ld a, 0x50c0
00860F A4 07 [ 1] 317 and a, #0x07
318 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 507: presc = SYSDivFactor[tmp];
008611 5F [ 1] 319 clrw x
008612 97 [ 1] 320 ld xl, a
008613 D6 80 AF [ 1] 321 ld a, (_SYSDivFactor+0, x)
322 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 510: clockfrequency = sourcefrequency / presc;
008616 5F [ 1] 323 clrw x
008617 0F 05 [ 1] 324 clr (0x05, sp)
008619 88 [ 1] 325 push a
00861A 89 [ 2] 326 pushw x
00861B 4F [ 1] 327 clr a
00861C 88 [ 1] 328 push a
00861D 1E 07 [ 2] 329 ldw x, (0x07, sp)
00861F 89 [ 2] 330 pushw x
008620 1E 07 [ 2] 331 ldw x, (0x07, sp)
008622 89 [ 2] 332 pushw x
333 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 512: return((uint32_t)clockfrequency);
008623 CD 92 5C [ 4] 334 call __divulong
335 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 513: }
008626 5B 10 [ 2] 336 addw sp, #16
008628 81 [ 4] 337 ret
338 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 528: void CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_TypeDef CLK_SYSCLKDiv)
339 ; -----------------------------------------
340 ; function CLK_SYSCLKDivConfig
341 ; -----------------------------------------
008629 342 _CLK_SYSCLKDivConfig:
343 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 533: CLK->CKDIVR = (uint8_t)(CLK_SYSCLKDiv);
008629 C7 50 C0 [ 1] 344 ld 0x50c0, a
345 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 534: }
00862C 81 [ 4] 346 ret
347 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 541: void CLK_SYSCLKSourceSwitchCmd(FunctionalState NewState)
348 ; -----------------------------------------
349 ; function CLK_SYSCLKSourceSwitchCmd
350 ; -----------------------------------------
00862D 351 _CLK_SYSCLKSourceSwitchCmd:
00862D 88 [ 1] 352 push a
00862E 6B 01 [ 1] 353 ld (0x01, sp), a
354 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 549: CLK->SWCR |= CLK_SWCR_SWEN;
008630 C6 50 C9 [ 1] 355 ld a, 0x50c9
356 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 546: if (NewState != DISABLE)
008633 0D 01 [ 1] 357 tnz (0x01, sp)
008635 27 07 [ 1] 358 jreq 00102$
359 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 549: CLK->SWCR |= CLK_SWCR_SWEN;
008637 AA 02 [ 1] 360 or a, #0x02
008639 C7 50 C9 [ 1] 361 ld 0x50c9, a
00863C 20 05 [ 2] 362 jra 00104$
00863E 363 00102$:
364 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 554: CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWEN);
00863E A4 FD [ 1] 365 and a, #0xfd
008640 C7 50 C9 [ 1] 366 ld 0x50c9, a
008643 367 00104$:
368 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 556: }
008643 84 [ 1] 369 pop a
008644 81 [ 4] 370 ret
371 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 616: void CLK_RTCClockConfig(CLK_RTCCLKSource_TypeDef CLK_RTCCLKSource, CLK_RTCCLKDiv_TypeDef CLK_RTCCLKDiv)
372 ; -----------------------------------------
373 ; function CLK_RTCClockConfig
374 ; -----------------------------------------
008645 375 _CLK_RTCClockConfig:
376 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 623: CLK->CRTCR = (uint8_t)((uint8_t)CLK_RTCCLKSource | (uint8_t)CLK_RTCCLKDiv);
008645 1A 03 [ 1] 377 or a, (0x03, sp)
008647 C7 50 C1 [ 1] 378 ld 0x50c1, a
379 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 624: }
00864A 85 [ 2] 380 popw x
00864B 84 [ 1] 381 pop a
00864C FC [ 2] 382 jp (x)
383 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 635: void CLK_BEEPClockConfig(CLK_BEEPCLKSource_TypeDef CLK_BEEPCLKSource)
384 ; -----------------------------------------
385 ; function CLK_BEEPClockConfig
386 ; -----------------------------------------
00864D 387 _CLK_BEEPClockConfig:
388 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 641: CLK->CBEEPR = (uint8_t)(CLK_BEEPCLKSource);
00864D C7 50 CB [ 1] 389 ld 0x50cb, a
390 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 643: }
008650 81 [ 4] 391 ret
392 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 677: void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
393 ; -----------------------------------------
394 ; function CLK_PeripheralClockConfig
395 ; -----------------------------------------
008651 396 _CLK_PeripheralClockConfig:
008651 89 [ 2] 397 pushw x
398 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 686: reg = (uint8_t)((uint8_t)CLK_Peripheral & (uint8_t)0xF0);
008652 88 [ 1] 399 push a
008653 A4 F0 [ 1] 400 and a, #0xf0
008655 97 [ 1] 401 ld xl, a
008656 84 [ 1] 402 pop a
008657 90 93 [ 1] 403 ldw y, x
404 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 693: CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
008659 A4 0F [ 1] 405 and a, #0x0f
00865B 88 [ 1] 406 push a
00865C A6 01 [ 1] 407 ld a, #0x01
00865E 6B 02 [ 1] 408 ld (0x02, sp), a
008660 84 [ 1] 409 pop a
008661 4D [ 1] 410 tnz a
008662 27 05 [ 1] 411 jreq 00154$
008664 412 00153$:
008664 08 01 [ 1] 413 sll (0x01, sp)
008666 4A [ 1] 414 dec a
008667 26 FB [ 1] 415 jrne 00153$
008669 416 00154$:
417 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 698: CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
008669 7B 01 [ 1] 418 ld a, (0x01, sp)
00866B 43 [ 1] 419 cpl a
00866C 6B 02 [ 1] 420 ld (0x02, sp), a
421 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 688: if ( reg == 0x00)
00866E 9F [ 1] 422 ld a, xl
00866F 4D [ 1] 423 tnz a
008670 26 15 [ 1] 424 jrne 00114$
425 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 693: CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
008672 C6 50 C3 [ 1] 426 ld a, 0x50c3
427 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 690: if (NewState != DISABLE)
008675 0D 05 [ 1] 428 tnz (0x05, sp)
008677 27 07 [ 1] 429 jreq 00102$
430 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 693: CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
008679 1A 01 [ 1] 431 or a, (0x01, sp)
00867B C7 50 C3 [ 1] 432 ld 0x50c3, a
00867E 20 35 [ 2] 433 jra 00116$
008680 434 00102$:
435 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 698: CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
008680 14 02 [ 1] 436 and a, (0x02, sp)
008682 C7 50 C3 [ 1] 437 ld 0x50c3, a
008685 20 2E [ 2] 438 jra 00116$
008687 439 00114$:
440 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 701: else if (reg == 0x10)
008687 90 9F [ 1] 441 ld a, yl
008689 A1 10 [ 1] 442 cp a, #0x10
00868B 26 15 [ 1] 443 jrne 00111$
444 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 706: CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
00868D C6 50 C4 [ 1] 445 ld a, 0x50c4
446 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 703: if (NewState != DISABLE)
008690 0D 05 [ 1] 447 tnz (0x05, sp)
008692 27 07 [ 1] 448 jreq 00105$
449 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 706: CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
008694 1A 01 [ 1] 450 or a, (0x01, sp)
008696 C7 50 C4 [ 1] 451 ld 0x50c4, a
008699 20 1A [ 2] 452 jra 00116$
00869B 453 00105$:
454 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 711: CLK->PCKENR2 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
00869B 14 02 [ 1] 455 and a, (0x02, sp)
00869D C7 50 C4 [ 1] 456 ld 0x50c4, a
0086A0 20 13 [ 2] 457 jra 00116$
0086A2 458 00111$:
459 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 719: CLK->PCKENR3 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
0086A2 C6 50 D0 [ 1] 460 ld a, 0x50d0
461 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 716: if (NewState != DISABLE)
0086A5 0D 05 [ 1] 462 tnz (0x05, sp)
0086A7 27 07 [ 1] 463 jreq 00108$
464 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 719: CLK->PCKENR3 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
0086A9 1A 01 [ 1] 465 or a, (0x01, sp)
0086AB C7 50 D0 [ 1] 466 ld 0x50d0, a
0086AE 20 05 [ 2] 467 jra 00116$
0086B0 468 00108$:
469 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 724: CLK->PCKENR3 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
0086B0 14 02 [ 1] 470 and a, (0x02, sp)
0086B2 C7 50 D0 [ 1] 471 ld 0x50d0, a
0086B5 472 00116$:
473 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 727: }
0086B5 85 [ 2] 474 popw x
0086B6 85 [ 2] 475 popw x
0086B7 84 [ 1] 476 pop a
0086B8 FC [ 2] 477 jp (x)
478 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 765: void CLK_LSEClockSecuritySystemEnable(void)
479 ; -----------------------------------------
480 ; function CLK_LSEClockSecuritySystemEnable
481 ; -----------------------------------------
0086B9 482 _CLK_LSEClockSecuritySystemEnable:
483 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 768: CSSLSE->CSR |= CSSLSE_CSR_CSSEN;
0086B9 72 10 51 90 [ 1] 484 bset 0x5190, #0
485 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 769: }
0086BD 81 [ 4] 486 ret
487 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 777: void CLK_RTCCLKSwitchOnLSEFailureEnable(void)
488 ; -----------------------------------------
489 ; function CLK_RTCCLKSwitchOnLSEFailureEnable
490 ; -----------------------------------------
0086BE 491 _CLK_RTCCLKSwitchOnLSEFailureEnable:
492 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 780: CSSLSE->CSR |= CSSLSE_CSR_SWITCHEN;
0086BE 72 12 51 90 [ 1] 493 bset 0x5190, #1
494 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 781: }
0086C2 81 [ 4] 495 ret
496 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 807: void CLK_HaltConfig(CLK_Halt_TypeDef CLK_Halt, FunctionalState NewState)
497 ; -----------------------------------------
498 ; function CLK_HaltConfig
499 ; -----------------------------------------
0086C3 500 _CLK_HaltConfig:
0086C3 88 [ 1] 501 push a
502 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 815: CLK->ICKCR |= (uint8_t)(CLK_Halt);
0086C4 AE 50 C2 [ 2] 503 ldw x, #0x50c2
0086C7 88 [ 1] 504 push a
0086C8 F6 [ 1] 505 ld a, (x)
0086C9 6B 02 [ 1] 506 ld (0x02, sp), a
0086CB 84 [ 1] 507 pop a
508 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 813: if (NewState != DISABLE)
0086CC 0D 04 [ 1] 509 tnz (0x04, sp)
0086CE 27 07 [ 1] 510 jreq 00102$
511 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 815: CLK->ICKCR |= (uint8_t)(CLK_Halt);
0086D0 1A 01 [ 1] 512 or a, (0x01, sp)
0086D2 C7 50 C2 [ 1] 513 ld 0x50c2, a
0086D5 20 06 [ 2] 514 jra 00104$
0086D7 515 00102$:
516 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 819: CLK->ICKCR &= (uint8_t)(~CLK_Halt);
0086D7 43 [ 1] 517 cpl a
0086D8 14 01 [ 1] 518 and a, (0x01, sp)
0086DA C7 50 C2 [ 1] 519 ld 0x50c2, a
0086DD 520 00104$:
521 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 821: }
0086DD 84 [ 1] 522 pop a
0086DE 85 [ 2] 523 popw x
0086DF 84 [ 1] 524 pop a
0086E0 FC [ 2] 525 jp (x)
526 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 831: void CLK_MainRegulatorCmd(FunctionalState NewState)
527 ; -----------------------------------------
528 ; function CLK_MainRegulatorCmd
529 ; -----------------------------------------
0086E1 530 _CLK_MainRegulatorCmd:
0086E1 88 [ 1] 531 push a
0086E2 6B 01 [ 1] 532 ld (0x01, sp), a
533 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 839: CLK->REGCSR &= (uint8_t)(~CLK_REGCSR_REGOFF);
0086E4 C6 50 CF [ 1] 534 ld a, 0x50cf
535 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 836: if (NewState != DISABLE)
0086E7 0D 01 [ 1] 536 tnz (0x01, sp)
0086E9 27 07 [ 1] 537 jreq 00102$
538 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 839: CLK->REGCSR &= (uint8_t)(~CLK_REGCSR_REGOFF);
0086EB A4 FD [ 1] 539 and a, #0xfd
0086ED C7 50 CF [ 1] 540 ld 0x50cf, a
0086F0 20 05 [ 2] 541 jra 00104$
0086F2 542 00102$:
543 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 844: CLK->REGCSR |= CLK_REGCSR_REGOFF;
0086F2 AA 02 [ 1] 544 or a, #0x02
0086F4 C7 50 CF [ 1] 545 ld 0x50cf, a
0086F7 546 00104$:
547 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 846: }
0086F7 84 [ 1] 548 pop a
0086F8 81 [ 4] 549 ret
550 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 875: void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
551 ; -----------------------------------------
552 ; function CLK_ITConfig
553 ; -----------------------------------------
0086F9 554 _CLK_ITConfig:
0086F9 88 [ 1] 555 push a
556 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 884: if (CLK_IT == CLK_IT_SWIF)
0086FA A1 1C [ 1] 557 cp a, #0x1c
0086FC 26 07 [ 1] 558 jrne 00154$
0086FE 88 [ 1] 559 push a
0086FF A6 01 [ 1] 560 ld a, #0x01
008701 6B 02 [ 1] 561 ld (0x02, sp), a
008703 84 [ 1] 562 pop a
008704 C5 563 .byte 0xc5
008705 564 00154$:
008705 0F 01 [ 1] 565 clr (0x01, sp)
008707 566 00155$:
567 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 889: else if (CLK_IT == CLK_IT_LSECSSF)
008707 A0 2C [ 1] 568 sub a, #0x2c
008709 26 02 [ 1] 569 jrne 00157$
00870B 4C [ 1] 570 inc a
00870C 21 571 .byte 0x21
00870D 572 00157$:
00870D 4F [ 1] 573 clr a
00870E 574 00158$:
575 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 882: if (NewState != DISABLE)
00870E 0D 04 [ 1] 576 tnz (0x04, sp)
008710 27 25 [ 1] 577 jreq 00114$
578 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 884: if (CLK_IT == CLK_IT_SWIF)
008712 0D 01 [ 1] 579 tnz (0x01, sp)
008714 27 0A [ 1] 580 jreq 00105$
581 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 887: CLK->SWCR |= CLK_SWCR_SWIEN;
008716 C6 50 C9 [ 1] 582 ld a, 0x50c9
008719 AA 04 [ 1] 583 or a, #0x04
00871B C7 50 C9 [ 1] 584 ld 0x50c9, a
00871E 20 3A [ 2] 585 jra 00116$
008720 586 00105$:
587 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 889: else if (CLK_IT == CLK_IT_LSECSSF)
008720 4D [ 1] 588 tnz a
008721 27 0A [ 1] 589 jreq 00102$
590 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 892: CSSLSE->CSR |= CSSLSE_CSR_CSSIE;
008723 C6 51 90 [ 1] 591 ld a, 0x5190
008726 AA 04 [ 1] 592 or a, #0x04
008728 C7 51 90 [ 1] 593 ld 0x5190, a
00872B 20 2D [ 2] 594 jra 00116$
00872D 595 00102$:
596 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 897: CLK->CSSR |= CLK_CSSR_CSSDIE;
00872D C6 50 CA [ 1] 597 ld a, 0x50ca
008730 AA 04 [ 1] 598 or a, #0x04
008732 C7 50 CA [ 1] 599 ld 0x50ca, a
008735 20 23 [ 2] 600 jra 00116$
008737 601 00114$:
602 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 902: if (CLK_IT == CLK_IT_SWIF)
008737 0D 01 [ 1] 603 tnz (0x01, sp)
008739 27 0A [ 1] 604 jreq 00111$
605 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 905: CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);
00873B C6 50 C9 [ 1] 606 ld a, 0x50c9
00873E A4 FB [ 1] 607 and a, #0xfb
008740 C7 50 C9 [ 1] 608 ld 0x50c9, a
008743 20 15 [ 2] 609 jra 00116$
008745 610 00111$:
611 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 907: else if (CLK_IT == CLK_IT_LSECSSF)
008745 4D [ 1] 612 tnz a
008746 27 0A [ 1] 613 jreq 00108$
614 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 910: CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSIE);
008748 C6 51 90 [ 1] 615 ld a, 0x5190
00874B A4 FB [ 1] 616 and a, #0xfb
00874D C7 51 90 [ 1] 617 ld 0x5190, a
008750 20 08 [ 2] 618 jra 00116$
008752 619 00108$:
620 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 915: CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDIE);
008752 C6 50 CA [ 1] 621 ld a, 0x50ca
008755 A4 FB [ 1] 622 and a, #0xfb
008757 C7 50 CA [ 1] 623 ld 0x50ca, a
00875A 624 00116$:
625 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 918: }
00875A 84 [ 1] 626 pop a
00875B 85 [ 2] 627 popw x
00875C 84 [ 1] 628 pop a
00875D FC [ 2] 629 jp (x)
630 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 945: FlagStatus CLK_GetFlagStatus(CLK_FLAG_TypeDef CLK_FLAG)
631 ; -----------------------------------------
632 ; function CLK_GetFlagStatus
633 ; -----------------------------------------
00875E 634 _CLK_GetFlagStatus:
00875E 88 [ 1] 635 push a
636 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 955: reg = (uint8_t)((uint8_t)CLK_FLAG & (uint8_t)0xF0);
00875F 97 [ 1] 637 ld xl, a
008760 A4 F0 [ 1] 638 and a, #0xf0
639 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 958: pos = (uint8_t)((uint8_t)CLK_FLAG & (uint8_t)0x0F);
008762 88 [ 1] 640 push a
008763 9F [ 1] 641 ld a, xl
008764 A4 0F [ 1] 642 and a, #0x0f
008766 97 [ 1] 643 ld xl, a
008767 84 [ 1] 644 pop a
645 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 960: if (reg == 0x00) /* The flag to check is in CRTC Rregister */
008768 4D [ 1] 646 tnz a
008769 26 05 [ 1] 647 jrne 00123$
648 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 962: reg = CLK->CRTCR;
00876B C6 50 C1 [ 1] 649 ld a, 0x50c1
00876E 20 42 [ 2] 650 jra 00124$
008770 651 00123$:
652 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 964: else if (reg == 0x10) /* The flag to check is in ICKCR register */
008770 A1 10 [ 1] 653 cp a, #0x10
008772 26 05 [ 1] 654 jrne 00120$
655 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 966: reg = CLK->ICKCR;
008774 C6 50 C2 [ 1] 656 ld a, 0x50c2
008777 20 39 [ 2] 657 jra 00124$
008779 658 00120$:
659 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 968: else if (reg == 0x20) /* The flag to check is in CCOR register */
008779 A1 20 [ 1] 660 cp a, #0x20
00877B 26 05 [ 1] 661 jrne 00117$
662 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 970: reg = CLK->CCOR;
00877D C6 50 C5 [ 1] 663 ld a, 0x50c5
008780 20 30 [ 2] 664 jra 00124$
008782 665 00117$:
666 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 972: else if (reg == 0x30) /* The flag to check is in ECKCR register */
008782 A1 30 [ 1] 667 cp a, #0x30
008784 26 05 [ 1] 668 jrne 00114$
669 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 974: reg = CLK->ECKCR;
008786 C6 50 C6 [ 1] 670 ld a, 0x50c6
008789 20 27 [ 2] 671 jra 00124$
00878B 672 00114$:
673 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 976: else if (reg == 0x40) /* The flag to check is in SWCR register */
00878B A1 40 [ 1] 674 cp a, #0x40
00878D 26 05 [ 1] 675 jrne 00111$
676 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 978: reg = CLK->SWCR;
00878F C6 50 C9 [ 1] 677 ld a, 0x50c9
008792 20 1E [ 2] 678 jra 00124$
008794 679 00111$:
680 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 980: else if (reg == 0x50) /* The flag to check is in CSSR register */
008794 A1 50 [ 1] 681 cp a, #0x50
008796 26 05 [ 1] 682 jrne 00108$
683 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 982: reg = CLK->CSSR;
008798 C6 50 CA [ 1] 684 ld a, 0x50ca
00879B 20 15 [ 2] 685 jra 00124$
00879D 686 00108$:
687 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 984: else if (reg == 0x70) /* The flag to check is in REGCSR register */
00879D A1 70 [ 1] 688 cp a, #0x70
00879F 26 05 [ 1] 689 jrne 00105$
690 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 986: reg = CLK->REGCSR;
0087A1 C6 50 CF [ 1] 691 ld a, 0x50cf
0087A4 20 0C [ 2] 692 jra 00124$
0087A6 693 00105$:
694 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 988: else if (reg == 0x80) /* The flag to check is in CSSLSE_CSRregister */
0087A6 A1 80 [ 1] 695 cp a, #0x80
0087A8 26 05 [ 1] 696 jrne 00102$
697 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 990: reg = CSSLSE->CSR;
0087AA C6 51 90 [ 1] 698 ld a, 0x5190
0087AD 20 03 [ 2] 699 jra 00124$
0087AF 700 00102$:
701 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 994: reg = CLK->CBEEPR;
0087AF C6 50 CB [ 1] 702 ld a, 0x50cb
0087B2 703 00124$:
704 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 998: if ((reg & (uint8_t)((uint8_t)1 << (uint8_t)pos)) != (uint8_t)RESET)
0087B2 88 [ 1] 705 push a
0087B3 A6 01 [ 1] 706 ld a, #0x01
0087B5 6B 02 [ 1] 707 ld (0x02, sp), a
0087B7 9F [ 1] 708 ld a, xl
0087B8 4D [ 1] 709 tnz a
0087B9 27 05 [ 1] 710 jreq 00216$
0087BB 711 00215$:
0087BB 08 02 [ 1] 712 sll (0x02, sp)
0087BD 4A [ 1] 713 dec a
0087BE 26 FB [ 1] 714 jrne 00215$
0087C0 715 00216$:
0087C0 84 [ 1] 716 pop a
0087C1 14 01 [ 1] 717 and a, (0x01, sp)
0087C3 27 03 [ 1] 718 jreq 00126$
719 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1000: bitstatus = SET;
0087C5 A6 01 [ 1] 720 ld a, #0x01
721 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1004: bitstatus = RESET;
0087C7 21 722 .byte 0x21
0087C8 723 00126$:
0087C8 4F [ 1] 724 clr a
0087C9 725 00127$:
726 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1008: return((FlagStatus)bitstatus);
727 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1009: }
0087C9 5B 01 [ 2] 728 addw sp, #1
0087CB 81 [ 4] 729 ret
730 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1016: void CLK_ClearFlag(void)
731 ; -----------------------------------------
732 ; function CLK_ClearFlag
733 ; -----------------------------------------
0087CC 734 _CLK_ClearFlag:
735 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1020: CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSF);
0087CC 72 17 51 90 [ 1] 736 bres 0x5190, #3
737 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1021: }
0087D0 81 [ 4] 738 ret
739 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1032: ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
740 ; -----------------------------------------
741 ; function CLK_GetITStatus
742 ; -----------------------------------------
0087D1 743 _CLK_GetITStatus:
0087D1 88 [ 1] 744 push a
745 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1040: if (CLK_IT == CLK_IT_SWIF)
0087D2 6B 01 [ 1] 746 ld (0x01, sp), a
0087D4 A1 1C [ 1] 747 cp a, #0x1c
0087D6 26 0F [ 1] 748 jrne 00114$
749 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1043: if ((CLK->SWCR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
0087D8 C6 50 C9 [ 1] 750 ld a, 0x50c9
0087DB 14 01 [ 1] 751 and a, (0x01, sp)
752 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1045: bitstatus = SET;
0087DD A0 0C [ 1] 753 sub a, #0x0c
0087DF 26 03 [ 1] 754 jrne 00102$
0087E1 4C [ 1] 755 inc a
0087E2 20 24 [ 2] 756 jra 00115$
0087E4 757 00102$:
758 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1049: bitstatus = RESET;
0087E4 4F [ 1] 759 clr a
0087E5 20 21 [ 2] 760 jra 00115$
0087E7 761 00114$:
762 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1052: else if (CLK_IT == CLK_IT_LSECSSF)
0087E7 7B 01 [ 1] 763 ld a, (0x01, sp)
0087E9 A1 2C [ 1] 764 cp a, #0x2c
0087EB 26 0F [ 1] 765 jrne 00111$
766 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1055: if ((CSSLSE->CSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
0087ED C6 51 90 [ 1] 767 ld a, 0x5190
0087F0 14 01 [ 1] 768 and a, (0x01, sp)
769 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1057: bitstatus = SET;
0087F2 A0 0C [ 1] 770 sub a, #0x0c
0087F4 26 03 [ 1] 771 jrne 00105$
0087F6 4C [ 1] 772 inc a
0087F7 20 0F [ 2] 773 jra 00115$
0087F9 774 00105$:
775 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1061: bitstatus = RESET;
0087F9 4F [ 1] 776 clr a
0087FA 20 0C [ 2] 777 jra 00115$
0087FC 778 00111$:
779 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1067: if ((CLK->CSSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
0087FC C6 50 CA [ 1] 780 ld a, 0x50ca
0087FF 14 01 [ 1] 781 and a, (0x01, sp)
782 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1069: bitstatus = SET;
008801 A0 0C [ 1] 783 sub a, #0x0c
008803 26 02 [ 1] 784 jrne 00108$
008805 4C [ 1] 785 inc a
786 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1073: bitstatus = RESET;
008806 21 787 .byte 0x21
008807 788 00108$:
008807 4F [ 1] 789 clr a
008808 790 00115$:
791 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1078: return bitstatus;
792 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1079: }
008808 5B 01 [ 2] 793 addw sp, #1
00880A 81 [ 4] 794 ret
795 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1089: void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
796 ; -----------------------------------------
797 ; function CLK_ClearITPendingBit
798 ; -----------------------------------------
00880B 799 _CLK_ClearITPendingBit:
800 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1095: if ((uint8_t)((uint8_t)CLK_IT & (uint8_t)0xF0) == (uint8_t)0x20)
00880B A4 F0 [ 1] 801 and a, #0xf0
00880D A1 20 [ 1] 802 cp a, #0x20
00880F 26 05 [ 1] 803 jrne 00102$
804 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1098: CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSF);
008811 72 17 51 90 [ 1] 805 bres 0x5190, #3
008815 81 [ 4] 806 ret
008816 807 00102$:
808 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1103: CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIF);
008816 72 17 50 C9 [ 1] 809 bres 0x50c9, #3
810 ; ../inc/stm8l151x/src/stm8l15x_clk.c: 1105: }
00881A 81 [ 4] 811 ret
812 .area CODE
813 .area CONST
814 .area CONST
0080AF 815 _SYSDivFactor:
0080AF 01 816 .db #0x01 ; 1
0080B0 02 817 .db #0x02 ; 2
0080B1 04 818 .db #0x04 ; 4
0080B2 08 819 .db #0x08 ; 8
0080B3 10 820 .db #0x10 ; 16
821 .area CODE
822 .area INITIALIZER
823 .area CABS (ABS)

56
firmware/STM8L15X_LD/stm8l15x_clk.sym Normal file
View File

@@ -0,0 +1,56 @@
ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 1
Hexadecimal [24-Bits]
Symbol Table
.__.$$$. = 002710 L
.__.ABS. = 000000 G
.__.CPU. = 000000 L
.__.H$L. = 000001 L
9 _CLK_AdjustHSICalibrationValue 000059 GR
9 _CLK_BEEPClockConfig 00014B GR
9 _CLK_CCOConfig 0000C4 GR
9 _CLK_ClearFlag 0002CA GR
9 _CLK_ClearITPendingBit 000309 GR
9 _CLK_ClockSecuritySystemEnable 0000A7 GR
9 _CLK_ClockSecuritySytemDeglitchCmd 0000AC GR
9 _CLK_DeInit 000000 GR
9 _CLK_GetClockFreq 0000D4 GR
9 _CLK_GetFlagStatus 00025C GR
9 _CLK_GetITStatus 0002CF GR
9 _CLK_GetSYSCLKSource 0000D0 GR
9 _CLK_HSEConfig 00007D GR
9 _CLK_HSICmd 000041 GR
9 _CLK_HaltConfig 0001C1 GR
9 _CLK_ITConfig 0001F7 GR
9 _CLK_LSEClockSecuritySystemEnable 0001B7 GR
9 _CLK_LSEConfig 000092 GR
9 _CLK_LSICmd 000065 GR
9 _CLK_MainRegulatorCmd 0001DF GR
9 _CLK_PeripheralClockConfig 00014F GR
9 _CLK_RTCCLKSwitchOnLSEFailureEnable 0001BC GR
9 _CLK_RTCClockConfig 000143 GR
9 _CLK_SYSCLKDivConfig 000127 GR
9 _CLK_SYSCLKSourceConfig 0000CC GR
9 _CLK_SYSCLKSourceSwitchCmd 00012B GR
7 _SYSDivFactor 000000 GR
__divulong ****** GX
ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 2
Hexadecimal [24-Bits]
Area Table
0 _CODE size 0 flags 0
1 DATA size 0 flags 0
2 INITIALIZED size 0 flags 0
3 DABS size 0 flags 8
4 HOME size 0 flags 0
5 GSINIT size 0 flags 0
6 GSFINAL size 0 flags 0
7 CONST size 5 flags 0
8 INITIALIZER size 0 flags 0
9 CODE size 319 flags 0
A CABS size 0 flags 8

349
firmware/STM8L15X_LD/stm8l15x_gpio.asm Normal file
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@@ -0,0 +1,349 @@
;--------------------------------------------------------
; File Created by SDCC : free open source ISO C Compiler
; Version 4.5.0 #15242 (Linux)
;--------------------------------------------------------
.module stm8l15x_gpio
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _GPIO_DeInit
.globl _GPIO_Init
.globl _GPIO_ExternalPullUpConfig
.globl _GPIO_Write
.globl _GPIO_WriteBit
.globl _GPIO_SetBits
.globl _GPIO_ResetBits
.globl _GPIO_ToggleBits
.globl _GPIO_ReadInputData
.globl _GPIO_ReadOutputData
.globl _GPIO_ReadInputDataBit
.globl _GPIO_ReadOutputDataBit
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area DATA
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area INITIALIZED
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area DABS (ABS)
; default segment ordering for linker
.area HOME
.area GSINIT
.area GSFINAL
.area CONST
.area INITIALIZER
.area CODE
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area HOME
.area GSINIT
.area GSFINAL
.area GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area HOME
.area HOME
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area CODE
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 96: void GPIO_DeInit(GPIO_TypeDef* GPIOx)
; -----------------------------------------
; function GPIO_DeInit
; -----------------------------------------
_GPIO_DeInit:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 98: GPIOx->CR2 = GPIO_CR2_RESET_VALUE; /* Reset Control Register 2 */
ldw y, x
clr (0x0004, x)
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 99: GPIOx->ODR = GPIO_ODR_RESET_VALUE; /* Reset Output Data Register */
clr (y)
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 100: GPIOx->DDR = GPIO_DDR_RESET_VALUE; /* Reset Data Direction Register */
ldw x, y
clr (0x02, x)
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 101: GPIOx->CR1 = GPIO_CR1_RESET_VALUE; /* Reset Control Register 1 */
ldw x, y
clr (0x0003, x)
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 102: }
ret
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 133: void GPIO_Init(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
; -----------------------------------------
; function GPIO_Init
; -----------------------------------------
_GPIO_Init:
sub sp, #8
ldw (0x07, sp), x
ld (0x06, sp), a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 143: GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
ldw x, (0x07, sp)
addw x, #0x0004
ldw (0x01, sp), x
ld a, (x)
push a
ld a, (0x07, sp)
cpl a
ld (0x04, sp), a
pop a
and a, (0x03, sp)
ldw x, (0x01, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 159: GPIOx->DDR |= GPIO_Pin;
ldw x, (0x07, sp)
incw x
incw x
ldw (0x04, sp), x
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 149: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x80) != (uint8_t)0x00) /* Output mode */
tnz (0x0b, sp)
jrpl 00105$
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 153: GPIOx->ODR |= GPIO_Pin;
ldw x, (0x07, sp)
ld a, (x)
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 151: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x10) != (uint8_t)0x00) /* High level */
push a
ld a, (0x0c, sp)
bcp a, #0x10
pop a
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 153: GPIOx->ODR |= GPIO_Pin;
or a, (0x06, sp)
ld (x), a
jra 00103$
00102$:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 156: GPIOx->ODR &= (uint8_t)(~(GPIO_Pin));
and a, (0x03, sp)
ld (x), a
00103$:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 159: GPIOx->DDR |= GPIO_Pin;
ldw x, (0x04, sp)
ld a, (x)
or a, (0x06, sp)
ldw x, (0x04, sp)
ld (x), a
jra 00106$
00105$:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 163: GPIOx->DDR &= (uint8_t)(~(GPIO_Pin));
ldw x, (0x04, sp)
ld a, (x)
and a, (0x03, sp)
ldw x, (0x04, sp)
ld (x), a
00106$:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 172: GPIOx->CR1 |= GPIO_Pin;
ldw x, (0x07, sp)
addw x, #0x0003
ld a, (x)
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 170: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x40) != (uint8_t)0x00) /* Pull-Up or Push-Pull */
push a
ld a, (0x0c, sp)
bcp a, #0x40
pop a
jreq 00108$
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 172: GPIOx->CR1 |= GPIO_Pin;
or a, (0x06, sp)
ld (x), a
jra 00109$
00108$:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 175: GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
and a, (0x03, sp)
ld (x), a
00109$:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 143: GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
ldw x, (0x01, sp)
ld a, (x)
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 182: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x20) != (uint8_t)0x00) /* Interrupt or Slow slope */
push a
ld a, (0x0c, sp)
bcp a, #0x20
pop a
jreq 00111$
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 184: GPIOx->CR2 |= GPIO_Pin;
or a, (0x06, sp)
ldw x, (0x01, sp)
ld (x), a
jra 00113$
00111$:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 187: GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
and a, (0x03, sp)
ldw x, (0x01, sp)
ld (x), a
00113$:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 190: }
addw sp, #8
popw x
pop a
jp (x)
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 209: void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, FunctionalState NewState)
; -----------------------------------------
; function GPIO_ExternalPullUpConfig
; -----------------------------------------
_GPIO_ExternalPullUpConfig:
push a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 217: GPIOx->CR1 |= GPIO_Pin;
addw x, #0x0003
push a
ld a, (x)
ld (0x02, sp), a
pop a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 215: if (NewState != DISABLE) /* External Pull-Up Set*/
tnz (0x04, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 217: GPIOx->CR1 |= GPIO_Pin;
or a, (0x01, sp)
ld (x), a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 220: GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
cpl a
and a, (0x01, sp)
ld (x), a
00104$:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 222: }
pop a
popw x
pop a
jp (x)
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 248: void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t GPIO_PortVal)
; -----------------------------------------
; function GPIO_Write
; -----------------------------------------
_GPIO_Write:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 250: GPIOx->ODR = GPIO_PortVal;
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 251: }
ret
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 270: void GPIO_WriteBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction GPIO_BitVal)
; -----------------------------------------
; function GPIO_WriteBit
; -----------------------------------------
_GPIO_WriteBit:
push a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 278: GPIOx->ODR |= GPIO_Pin;
push a
ld a, (x)
ld (0x02, sp), a
pop a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 276: if (GPIO_BitVal != RESET)
tnz (0x04, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 278: GPIOx->ODR |= GPIO_Pin;
or a, (0x01, sp)
ld (x), a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 283: GPIOx->ODR &= (uint8_t)(~GPIO_Pin);
cpl a
and a, (0x01, sp)
ld (x), a
00104$:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 285: }
pop a
popw x
pop a
jp (x)
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 303: void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
; -----------------------------------------
; function GPIO_SetBits
; -----------------------------------------
_GPIO_SetBits:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 305: GPIOx->ODR |= GPIO_Pin;
ld a, (x)
or a, (0x01, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 306: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 324: void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
; -----------------------------------------
; function GPIO_ResetBits
; -----------------------------------------
_GPIO_ResetBits:
push a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 326: GPIOx->ODR &= (uint8_t)(~GPIO_Pin);
push a
ld a, (x)
ld (0x02, sp), a
pop a
cpl a
and a, (0x01, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 327: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 336: void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
; -----------------------------------------
; function GPIO_ToggleBits
; -----------------------------------------
_GPIO_ToggleBits:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 338: GPIOx->ODR ^= GPIO_Pin;
ld a, (x)
xor a, (0x01, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 339: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 347: uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
; -----------------------------------------
; function GPIO_ReadInputData
; -----------------------------------------
_GPIO_ReadInputData:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 349: return ((uint8_t)GPIOx->IDR);
ld a, (0x1, x)
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 350: }
ret
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 358: uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
; -----------------------------------------
; function GPIO_ReadOutputData
; -----------------------------------------
_GPIO_ReadOutputData:
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 360: return ((uint8_t)GPIOx->ODR);
ld a, (x)
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 361: }
ret
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 378: BitStatus GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
; -----------------------------------------
; function GPIO_ReadInputDataBit
; -----------------------------------------
_GPIO_ReadInputDataBit:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 380: return ((BitStatus)(GPIOx->IDR & (uint8_t)GPIO_Pin));
ld a, (0x1, x)
and a, (0x01, sp)
neg a
clr a
rlc a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 381: }
addw sp, #1
ret
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 389: BitStatus GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
; -----------------------------------------
; function GPIO_ReadOutputDataBit
; -----------------------------------------
_GPIO_ReadOutputDataBit:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 391: return ((BitStatus)(GPIOx->ODR & (uint8_t)GPIO_Pin));
ld a, (x)
and a, (0x01, sp)
neg a
clr a
rlc a
; ../inc/stm8l151x/src/stm8l15x_gpio.c: 392: }
addw sp, #1
ret
.area CODE
.area CONST
.area INITIALIZER
.area CABS (ABS)

349
firmware/STM8L15X_LD/stm8l15x_gpio.lst Normal file
View File

@@ -0,0 +1,349 @@
1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ISO C Compiler
3 ; Version 4.5.0 #15242 (Linux)
4 ;--------------------------------------------------------
5 .module stm8l15x_gpio
6
7 ;--------------------------------------------------------
8 ; Public variables in this module
9 ;--------------------------------------------------------
10 .globl _GPIO_DeInit
11 .globl _GPIO_Init
12 .globl _GPIO_ExternalPullUpConfig
13 .globl _GPIO_Write
14 .globl _GPIO_WriteBit
15 .globl _GPIO_SetBits
16 .globl _GPIO_ResetBits
17 .globl _GPIO_ToggleBits
18 .globl _GPIO_ReadInputData
19 .globl _GPIO_ReadOutputData
20 .globl _GPIO_ReadInputDataBit
21 .globl _GPIO_ReadOutputDataBit
22 ;--------------------------------------------------------
23 ; ram data
24 ;--------------------------------------------------------
25 .area DATA
26 ;--------------------------------------------------------
27 ; ram data
28 ;--------------------------------------------------------
29 .area INITIALIZED
30 ;--------------------------------------------------------
31 ; absolute external ram data
32 ;--------------------------------------------------------
33 .area DABS (ABS)
34
35 ; default segment ordering for linker
36 .area HOME
37 .area GSINIT
38 .area GSFINAL
39 .area CONST
40 .area INITIALIZER
41 .area CODE
42
43 ;--------------------------------------------------------
44 ; global & static initialisations
45 ;--------------------------------------------------------
46 .area HOME
47 .area GSINIT
48 .area GSFINAL
49 .area GSINIT
50 ;--------------------------------------------------------
51 ; Home
52 ;--------------------------------------------------------
53 .area HOME
54 .area HOME
55 ;--------------------------------------------------------
56 ; code
57 ;--------------------------------------------------------
58 .area CODE
59 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 96: void GPIO_DeInit(GPIO_TypeDef* GPIOx)
60 ; -----------------------------------------
61 ; function GPIO_DeInit
62 ; -----------------------------------------
000000 63 _GPIO_DeInit:
64 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 98: GPIOx->CR2 = GPIO_CR2_RESET_VALUE; /* Reset Control Register 2 */
000000 90 93 [ 1] 65 ldw y, x
000002 6F 04 [ 1] 66 clr (0x0004, x)
67 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 99: GPIOx->ODR = GPIO_ODR_RESET_VALUE; /* Reset Output Data Register */
000004 90 7F [ 1] 68 clr (y)
69 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 100: GPIOx->DDR = GPIO_DDR_RESET_VALUE; /* Reset Data Direction Register */
000006 93 [ 1] 70 ldw x, y
000007 6F 02 [ 1] 71 clr (0x02, x)
72 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 101: GPIOx->CR1 = GPIO_CR1_RESET_VALUE; /* Reset Control Register 1 */
000009 93 [ 1] 73 ldw x, y
00000A 6F 03 [ 1] 74 clr (0x0003, x)
75 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 102: }
00000C 81 [ 4] 76 ret
77 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 133: void GPIO_Init(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
78 ; -----------------------------------------
79 ; function GPIO_Init
80 ; -----------------------------------------
00000D 81 _GPIO_Init:
00000D 52 08 [ 2] 82 sub sp, #8
00000F 1F 07 [ 2] 83 ldw (0x07, sp), x
000011 6B 06 [ 1] 84 ld (0x06, sp), a
85 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 143: GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
000013 1E 07 [ 2] 86 ldw x, (0x07, sp)
000015 1C 00 04 [ 2] 87 addw x, #0x0004
000018 1F 01 [ 2] 88 ldw (0x01, sp), x
00001A F6 [ 1] 89 ld a, (x)
00001B 88 [ 1] 90 push a
00001C 7B 07 [ 1] 91 ld a, (0x07, sp)
00001E 43 [ 1] 92 cpl a
00001F 6B 04 [ 1] 93 ld (0x04, sp), a
000021 84 [ 1] 94 pop a
000022 14 03 [ 1] 95 and a, (0x03, sp)
000024 1E 01 [ 2] 96 ldw x, (0x01, sp)
000026 F7 [ 1] 97 ld (x), a
98 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 159: GPIOx->DDR |= GPIO_Pin;
000027 1E 07 [ 2] 99 ldw x, (0x07, sp)
000029 5C [ 1] 100 incw x
00002A 5C [ 1] 101 incw x
00002B 1F 04 [ 2] 102 ldw (0x04, sp), x
103 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 149: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x80) != (uint8_t)0x00) /* Output mode */
00002D 0D 0B [ 1] 104 tnz (0x0b, sp)
00002F 2A 1D [ 1] 105 jrpl 00105$
106 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 153: GPIOx->ODR |= GPIO_Pin;
000031 1E 07 [ 2] 107 ldw x, (0x07, sp)
000033 F6 [ 1] 108 ld a, (x)
109 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 151: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x10) != (uint8_t)0x00) /* High level */
000034 88 [ 1] 110 push a
000035 7B 0C [ 1] 111 ld a, (0x0c, sp)
000037 A5 10 [ 1] 112 bcp a, #0x10
000039 84 [ 1] 113 pop a
00003A 27 05 [ 1] 114 jreq 00102$
115 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 153: GPIOx->ODR |= GPIO_Pin;
00003C 1A 06 [ 1] 116 or a, (0x06, sp)
00003E F7 [ 1] 117 ld (x), a
00003F 20 03 [ 2] 118 jra 00103$
000041 119 00102$:
120 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 156: GPIOx->ODR &= (uint8_t)(~(GPIO_Pin));
000041 14 03 [ 1] 121 and a, (0x03, sp)
000043 F7 [ 1] 122 ld (x), a
000044 123 00103$:
124 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 159: GPIOx->DDR |= GPIO_Pin;
000044 1E 04 [ 2] 125 ldw x, (0x04, sp)
000046 F6 [ 1] 126 ld a, (x)
000047 1A 06 [ 1] 127 or a, (0x06, sp)
000049 1E 04 [ 2] 128 ldw x, (0x04, sp)
00004B F7 [ 1] 129 ld (x), a
00004C 20 08 [ 2] 130 jra 00106$
00004E 131 00105$:
132 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 163: GPIOx->DDR &= (uint8_t)(~(GPIO_Pin));
00004E 1E 04 [ 2] 133 ldw x, (0x04, sp)
000050 F6 [ 1] 134 ld a, (x)
000051 14 03 [ 1] 135 and a, (0x03, sp)
000053 1E 04 [ 2] 136 ldw x, (0x04, sp)
000055 F7 [ 1] 137 ld (x), a
000056 138 00106$:
139 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 172: GPIOx->CR1 |= GPIO_Pin;
000056 1E 07 [ 2] 140 ldw x, (0x07, sp)
000058 1C 00 03 [ 2] 141 addw x, #0x0003
00005B F6 [ 1] 142 ld a, (x)
143 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 170: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x40) != (uint8_t)0x00) /* Pull-Up or Push-Pull */
00005C 88 [ 1] 144 push a
00005D 7B 0C [ 1] 145 ld a, (0x0c, sp)
00005F A5 40 [ 1] 146 bcp a, #0x40
000061 84 [ 1] 147 pop a
000062 27 05 [ 1] 148 jreq 00108$
149 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 172: GPIOx->CR1 |= GPIO_Pin;
000064 1A 06 [ 1] 150 or a, (0x06, sp)
000066 F7 [ 1] 151 ld (x), a
000067 20 03 [ 2] 152 jra 00109$
000069 153 00108$:
154 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 175: GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
000069 14 03 [ 1] 155 and a, (0x03, sp)
00006B F7 [ 1] 156 ld (x), a
00006C 157 00109$:
158 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 143: GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
00006C 1E 01 [ 2] 159 ldw x, (0x01, sp)
00006E F6 [ 1] 160 ld a, (x)
161 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 182: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x20) != (uint8_t)0x00) /* Interrupt or Slow slope */
00006F 88 [ 1] 162 push a
000070 7B 0C [ 1] 163 ld a, (0x0c, sp)
000072 A5 20 [ 1] 164 bcp a, #0x20
000074 84 [ 1] 165 pop a
000075 27 07 [ 1] 166 jreq 00111$
167 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 184: GPIOx->CR2 |= GPIO_Pin;
000077 1A 06 [ 1] 168 or a, (0x06, sp)
000079 1E 01 [ 2] 169 ldw x, (0x01, sp)
00007B F7 [ 1] 170 ld (x), a
00007C 20 05 [ 2] 171 jra 00113$
00007E 172 00111$:
173 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 187: GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
00007E 14 03 [ 1] 174 and a, (0x03, sp)
000080 1E 01 [ 2] 175 ldw x, (0x01, sp)
000082 F7 [ 1] 176 ld (x), a
000083 177 00113$:
178 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 190: }
000083 5B 08 [ 2] 179 addw sp, #8
000085 85 [ 2] 180 popw x
000086 84 [ 1] 181 pop a
000087 FC [ 2] 182 jp (x)
183 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 209: void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, FunctionalState NewState)
184 ; -----------------------------------------
185 ; function GPIO_ExternalPullUpConfig
186 ; -----------------------------------------
000088 187 _GPIO_ExternalPullUpConfig:
000088 88 [ 1] 188 push a
189 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 217: GPIOx->CR1 |= GPIO_Pin;
000089 1C 00 03 [ 2] 190 addw x, #0x0003
00008C 88 [ 1] 191 push a
00008D F6 [ 1] 192 ld a, (x)
00008E 6B 02 [ 1] 193 ld (0x02, sp), a
000090 84 [ 1] 194 pop a
195 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 215: if (NewState != DISABLE) /* External Pull-Up Set*/
000091 0D 04 [ 1] 196 tnz (0x04, sp)
000093 27 05 [ 1] 197 jreq 00102$
198 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 217: GPIOx->CR1 |= GPIO_Pin;
000095 1A 01 [ 1] 199 or a, (0x01, sp)
000097 F7 [ 1] 200 ld (x), a
000098 20 04 [ 2] 201 jra 00104$
00009A 202 00102$:
203 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 220: GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
00009A 43 [ 1] 204 cpl a
00009B 14 01 [ 1] 205 and a, (0x01, sp)
00009D F7 [ 1] 206 ld (x), a
00009E 207 00104$:
208 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 222: }
00009E 84 [ 1] 209 pop a
00009F 85 [ 2] 210 popw x
0000A0 84 [ 1] 211 pop a
0000A1 FC [ 2] 212 jp (x)
213 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 248: void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t GPIO_PortVal)
214 ; -----------------------------------------
215 ; function GPIO_Write
216 ; -----------------------------------------
0000A2 217 _GPIO_Write:
218 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 250: GPIOx->ODR = GPIO_PortVal;
0000A2 F7 [ 1] 219 ld (x), a
220 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 251: }
0000A3 81 [ 4] 221 ret
222 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 270: void GPIO_WriteBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction GPIO_BitVal)
223 ; -----------------------------------------
224 ; function GPIO_WriteBit
225 ; -----------------------------------------
0000A4 226 _GPIO_WriteBit:
0000A4 88 [ 1] 227 push a
228 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 278: GPIOx->ODR |= GPIO_Pin;
0000A5 88 [ 1] 229 push a
0000A6 F6 [ 1] 230 ld a, (x)
0000A7 6B 02 [ 1] 231 ld (0x02, sp), a
0000A9 84 [ 1] 232 pop a
233 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 276: if (GPIO_BitVal != RESET)
0000AA 0D 04 [ 1] 234 tnz (0x04, sp)
0000AC 27 05 [ 1] 235 jreq 00102$
236 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 278: GPIOx->ODR |= GPIO_Pin;
0000AE 1A 01 [ 1] 237 or a, (0x01, sp)
0000B0 F7 [ 1] 238 ld (x), a
0000B1 20 04 [ 2] 239 jra 00104$
0000B3 240 00102$:
241 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 283: GPIOx->ODR &= (uint8_t)(~GPIO_Pin);
0000B3 43 [ 1] 242 cpl a
0000B4 14 01 [ 1] 243 and a, (0x01, sp)
0000B6 F7 [ 1] 244 ld (x), a
0000B7 245 00104$:
246 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 285: }
0000B7 84 [ 1] 247 pop a
0000B8 85 [ 2] 248 popw x
0000B9 84 [ 1] 249 pop a
0000BA FC [ 2] 250 jp (x)
251 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 303: void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
252 ; -----------------------------------------
253 ; function GPIO_SetBits
254 ; -----------------------------------------
0000BB 255 _GPIO_SetBits:
0000BB 88 [ 1] 256 push a
0000BC 6B 01 [ 1] 257 ld (0x01, sp), a
258 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 305: GPIOx->ODR |= GPIO_Pin;
0000BE F6 [ 1] 259 ld a, (x)
0000BF 1A 01 [ 1] 260 or a, (0x01, sp)
0000C1 F7 [ 1] 261 ld (x), a
262 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 306: }
0000C2 84 [ 1] 263 pop a
0000C3 81 [ 4] 264 ret
265 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 324: void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
266 ; -----------------------------------------
267 ; function GPIO_ResetBits
268 ; -----------------------------------------
0000C4 269 _GPIO_ResetBits:
0000C4 88 [ 1] 270 push a
271 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 326: GPIOx->ODR &= (uint8_t)(~GPIO_Pin);
0000C5 88 [ 1] 272 push a
0000C6 F6 [ 1] 273 ld a, (x)
0000C7 6B 02 [ 1] 274 ld (0x02, sp), a
0000C9 84 [ 1] 275 pop a
0000CA 43 [ 1] 276 cpl a
0000CB 14 01 [ 1] 277 and a, (0x01, sp)
0000CD F7 [ 1] 278 ld (x), a
279 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 327: }
0000CE 84 [ 1] 280 pop a
0000CF 81 [ 4] 281 ret
282 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 336: void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
283 ; -----------------------------------------
284 ; function GPIO_ToggleBits
285 ; -----------------------------------------
0000D0 286 _GPIO_ToggleBits:
0000D0 88 [ 1] 287 push a
0000D1 6B 01 [ 1] 288 ld (0x01, sp), a
289 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 338: GPIOx->ODR ^= GPIO_Pin;
0000D3 F6 [ 1] 290 ld a, (x)
0000D4 18 01 [ 1] 291 xor a, (0x01, sp)
0000D6 F7 [ 1] 292 ld (x), a
293 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 339: }
0000D7 84 [ 1] 294 pop a
0000D8 81 [ 4] 295 ret
296 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 347: uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
297 ; -----------------------------------------
298 ; function GPIO_ReadInputData
299 ; -----------------------------------------
0000D9 300 _GPIO_ReadInputData:
301 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 349: return ((uint8_t)GPIOx->IDR);
0000D9 E6 01 [ 1] 302 ld a, (0x1, x)
303 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 350: }
0000DB 81 [ 4] 304 ret
305 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 358: uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
306 ; -----------------------------------------
307 ; function GPIO_ReadOutputData
308 ; -----------------------------------------
0000DC 309 _GPIO_ReadOutputData:
310 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 360: return ((uint8_t)GPIOx->ODR);
0000DC F6 [ 1] 311 ld a, (x)
312 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 361: }
0000DD 81 [ 4] 313 ret
314 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 378: BitStatus GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
315 ; -----------------------------------------
316 ; function GPIO_ReadInputDataBit
317 ; -----------------------------------------
0000DE 318 _GPIO_ReadInputDataBit:
0000DE 88 [ 1] 319 push a
0000DF 6B 01 [ 1] 320 ld (0x01, sp), a
321 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 380: return ((BitStatus)(GPIOx->IDR & (uint8_t)GPIO_Pin));
0000E1 E6 01 [ 1] 322 ld a, (0x1, x)
0000E3 14 01 [ 1] 323 and a, (0x01, sp)
0000E5 40 [ 1] 324 neg a
0000E6 4F [ 1] 325 clr a
0000E7 49 [ 1] 326 rlc a
327 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 381: }
0000E8 5B 01 [ 2] 328 addw sp, #1
0000EA 81 [ 4] 329 ret
330 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 389: BitStatus GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
331 ; -----------------------------------------
332 ; function GPIO_ReadOutputDataBit
333 ; -----------------------------------------
0000EB 334 _GPIO_ReadOutputDataBit:
0000EB 88 [ 1] 335 push a
0000EC 6B 01 [ 1] 336 ld (0x01, sp), a
337 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 391: return ((BitStatus)(GPIOx->ODR & (uint8_t)GPIO_Pin));
0000EE F6 [ 1] 338 ld a, (x)
0000EF 14 01 [ 1] 339 and a, (0x01, sp)
0000F1 40 [ 1] 340 neg a
0000F2 4F [ 1] 341 clr a
0000F3 49 [ 1] 342 rlc a
343 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 392: }
0000F4 5B 01 [ 2] 344 addw sp, #1
0000F6 81 [ 4] 345 ret
346 .area CODE
347 .area CONST
348 .area INITIALIZER
349 .area CABS (ABS)

137
firmware/STM8L15X_LD/stm8l15x_gpio.rel Normal file
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XH3
H B areas D global symbols
M stm8l15x_gpio
S .__.ABS. Def000000
A _CODE size 0 flags 0 addr 0
A DATA size 0 flags 0 addr 0
A INITIALIZED size 0 flags 0 addr 0
A DABS size 0 flags 8 addr 0
A HOME size 0 flags 0 addr 0
A GSINIT size 0 flags 0 addr 0
A GSFINAL size 0 flags 0 addr 0
A CONST size 0 flags 0 addr 0
A INITIALIZER size 0 flags 0 addr 0
A CODE size F7 flags 0 addr 0
S _GPIO_Init Def00000D
S _GPIO_ResetBits Def0000C4
S _GPIO_ReadInputDataBit Def0000DE
S _GPIO_ReadOutputDataBit Def0000EB
S _GPIO_WriteBit Def0000A4
S _GPIO_ToggleBits Def0000D0
S _GPIO_ExternalPullUpConfig Def000088
S _GPIO_DeInit Def000000
S _GPIO_SetBits Def0000BB
S _GPIO_ReadInputData Def0000D9
S _GPIO_ReadOutputData Def0000DC
S _GPIO_Write Def0000A2
A CABS size 0 flags 8 addr 0
T 00 00 00
R 00 00 00 09
T 00 00 00 90 93 6F 04 90 7F 93 6F 02 93 6F 03 81
R 00 00 00 09
T 00 00 0D
R 00 00 00 09
T 00 00 0D 52 08 1F 07 6B 06 1E 07 1C 00 04 1F 01
R 00 00 00 09
T 00 00 1A F6 88 7B 07 43 6B 04 84 14 03 1E 01 F7
R 00 00 00 09
T 00 00 27 1E 07 5C 5C 1F 04 0D 0B 2A 1D 1E 07 F6
R 00 00 00 09
T 00 00 34 88 7B 0C A5 10 84 27 05 1A 06 F7 20 03
R 00 00 00 09
T 00 00 41
R 00 00 00 09
T 00 00 41 14 03 F7
R 00 00 00 09
T 00 00 44
R 00 00 00 09
T 00 00 44 1E 04 F6 1A 06 1E 04 F7 20 08
R 00 00 00 09
T 00 00 4E
R 00 00 00 09
T 00 00 4E 1E 04 F6 14 03 1E 04 F7
R 00 00 00 09
T 00 00 56
R 00 00 00 09
T 00 00 56 1E 07 1C 00 03 F6 88 7B 0C A5 40 84 27
R 00 00 00 09
T 00 00 63 05 1A 06 F7 20 03
R 00 00 00 09
T 00 00 69
R 00 00 00 09
T 00 00 69 14 03 F7
R 00 00 00 09
T 00 00 6C
R 00 00 00 09
T 00 00 6C 1E 01 F6 88 7B 0C A5 20 84 27 07 1A 06
R 00 00 00 09
T 00 00 79 1E 01 F7 20 05
R 00 00 00 09
T 00 00 7E
R 00 00 00 09
T 00 00 7E 14 03 1E 01 F7
R 00 00 00 09
T 00 00 83
R 00 00 00 09
T 00 00 83 5B 08 85 84 FC
R 00 00 00 09
T 00 00 88
R 00 00 00 09
T 00 00 88 88 1C 00 03 88 F6 6B 02 84 0D 04 27 05
R 00 00 00 09
T 00 00 95 1A 01 F7 20 04
R 00 00 00 09
T 00 00 9A
R 00 00 00 09
T 00 00 9A 43 14 01 F7
R 00 00 00 09
T 00 00 9E
R 00 00 00 09
T 00 00 9E 84 85 84 FC
R 00 00 00 09
T 00 00 A2
R 00 00 00 09
T 00 00 A2 F7 81
R 00 00 00 09
T 00 00 A4
R 00 00 00 09
T 00 00 A4 88 88 F6 6B 02 84 0D 04 27 05 1A 01 F7
R 00 00 00 09
T 00 00 B1 20 04
R 00 00 00 09
T 00 00 B3
R 00 00 00 09
T 00 00 B3 43 14 01 F7
R 00 00 00 09
T 00 00 B7
R 00 00 00 09
T 00 00 B7 84 85 84 FC
R 00 00 00 09
T 00 00 BB
R 00 00 00 09
T 00 00 BB 88 6B 01 F6 1A 01 F7 84 81
R 00 00 00 09
T 00 00 C4
R 00 00 00 09
T 00 00 C4 88 88 F6 6B 02 84 43 14 01 F7 84 81
R 00 00 00 09
T 00 00 D0
R 00 00 00 09
T 00 00 D0 88 6B 01 F6 18 01 F7 84 81
R 00 00 00 09
T 00 00 D9
R 00 00 00 09
T 00 00 D9 E6 01 81
R 00 00 00 09
T 00 00 DC
R 00 00 00 09
T 00 00 DC F6 81
R 00 00 00 09
T 00 00 DE
R 00 00 00 09
T 00 00 DE 88 6B 01 E6 01 14 01 40 4F 49 5B 01 81
R 00 00 00 09
T 00 00 EB
R 00 00 00 09
T 00 00 EB 88 6B 01 F6 14 01 40 4F 49 5B 01 81
R 00 00 00 09

349
firmware/STM8L15X_LD/stm8l15x_gpio.rst Normal file
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@@ -0,0 +1,349 @@
1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ISO C Compiler
3 ; Version 4.5.0 #15242 (Linux)
4 ;--------------------------------------------------------
5 .module stm8l15x_gpio
6
7 ;--------------------------------------------------------
8 ; Public variables in this module
9 ;--------------------------------------------------------
10 .globl _GPIO_DeInit
11 .globl _GPIO_Init
12 .globl _GPIO_ExternalPullUpConfig
13 .globl _GPIO_Write
14 .globl _GPIO_WriteBit
15 .globl _GPIO_SetBits
16 .globl _GPIO_ResetBits
17 .globl _GPIO_ToggleBits
18 .globl _GPIO_ReadInputData
19 .globl _GPIO_ReadOutputData
20 .globl _GPIO_ReadInputDataBit
21 .globl _GPIO_ReadOutputDataBit
22 ;--------------------------------------------------------
23 ; ram data
24 ;--------------------------------------------------------
25 .area DATA
26 ;--------------------------------------------------------
27 ; ram data
28 ;--------------------------------------------------------
29 .area INITIALIZED
30 ;--------------------------------------------------------
31 ; absolute external ram data
32 ;--------------------------------------------------------
33 .area DABS (ABS)
34
35 ; default segment ordering for linker
36 .area HOME
37 .area GSINIT
38 .area GSFINAL
39 .area CONST
40 .area INITIALIZER
41 .area CODE
42
43 ;--------------------------------------------------------
44 ; global & static initialisations
45 ;--------------------------------------------------------
46 .area HOME
47 .area GSINIT
48 .area GSFINAL
49 .area GSINIT
50 ;--------------------------------------------------------
51 ; Home
52 ;--------------------------------------------------------
53 .area HOME
54 .area HOME
55 ;--------------------------------------------------------
56 ; code
57 ;--------------------------------------------------------
58 .area CODE
59 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 96: void GPIO_DeInit(GPIO_TypeDef* GPIOx)
60 ; -----------------------------------------
61 ; function GPIO_DeInit
62 ; -----------------------------------------
00881B 63 _GPIO_DeInit:
64 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 98: GPIOx->CR2 = GPIO_CR2_RESET_VALUE; /* Reset Control Register 2 */
00881B 90 93 [ 1] 65 ldw y, x
00881D 6F 04 [ 1] 66 clr (0x0004, x)
67 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 99: GPIOx->ODR = GPIO_ODR_RESET_VALUE; /* Reset Output Data Register */
00881F 90 7F [ 1] 68 clr (y)
69 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 100: GPIOx->DDR = GPIO_DDR_RESET_VALUE; /* Reset Data Direction Register */
008821 93 [ 1] 70 ldw x, y
008822 6F 02 [ 1] 71 clr (0x02, x)
72 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 101: GPIOx->CR1 = GPIO_CR1_RESET_VALUE; /* Reset Control Register 1 */
008824 93 [ 1] 73 ldw x, y
008825 6F 03 [ 1] 74 clr (0x0003, x)
75 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 102: }
008827 81 [ 4] 76 ret
77 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 133: void GPIO_Init(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
78 ; -----------------------------------------
79 ; function GPIO_Init
80 ; -----------------------------------------
008828 81 _GPIO_Init:
008828 52 08 [ 2] 82 sub sp, #8
00882A 1F 07 [ 2] 83 ldw (0x07, sp), x
00882C 6B 06 [ 1] 84 ld (0x06, sp), a
85 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 143: GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
00882E 1E 07 [ 2] 86 ldw x, (0x07, sp)
008830 1C 00 04 [ 2] 87 addw x, #0x0004
008833 1F 01 [ 2] 88 ldw (0x01, sp), x
008835 F6 [ 1] 89 ld a, (x)
008836 88 [ 1] 90 push a
008837 7B 07 [ 1] 91 ld a, (0x07, sp)
008839 43 [ 1] 92 cpl a
00883A 6B 04 [ 1] 93 ld (0x04, sp), a
00883C 84 [ 1] 94 pop a
00883D 14 03 [ 1] 95 and a, (0x03, sp)
00883F 1E 01 [ 2] 96 ldw x, (0x01, sp)
008841 F7 [ 1] 97 ld (x), a
98 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 159: GPIOx->DDR |= GPIO_Pin;
008842 1E 07 [ 2] 99 ldw x, (0x07, sp)
008844 5C [ 1] 100 incw x
008845 5C [ 1] 101 incw x
008846 1F 04 [ 2] 102 ldw (0x04, sp), x
103 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 149: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x80) != (uint8_t)0x00) /* Output mode */
008848 0D 0B [ 1] 104 tnz (0x0b, sp)
00884A 2A 1D [ 1] 105 jrpl 00105$
106 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 153: GPIOx->ODR |= GPIO_Pin;
00884C 1E 07 [ 2] 107 ldw x, (0x07, sp)
00884E F6 [ 1] 108 ld a, (x)
109 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 151: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x10) != (uint8_t)0x00) /* High level */
00884F 88 [ 1] 110 push a
008850 7B 0C [ 1] 111 ld a, (0x0c, sp)
008852 A5 10 [ 1] 112 bcp a, #0x10
008854 84 [ 1] 113 pop a
008855 27 05 [ 1] 114 jreq 00102$
115 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 153: GPIOx->ODR |= GPIO_Pin;
008857 1A 06 [ 1] 116 or a, (0x06, sp)
008859 F7 [ 1] 117 ld (x), a
00885A 20 03 [ 2] 118 jra 00103$
00885C 119 00102$:
120 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 156: GPIOx->ODR &= (uint8_t)(~(GPIO_Pin));
00885C 14 03 [ 1] 121 and a, (0x03, sp)
00885E F7 [ 1] 122 ld (x), a
00885F 123 00103$:
124 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 159: GPIOx->DDR |= GPIO_Pin;
00885F 1E 04 [ 2] 125 ldw x, (0x04, sp)
008861 F6 [ 1] 126 ld a, (x)
008862 1A 06 [ 1] 127 or a, (0x06, sp)
008864 1E 04 [ 2] 128 ldw x, (0x04, sp)
008866 F7 [ 1] 129 ld (x), a
008867 20 08 [ 2] 130 jra 00106$
008869 131 00105$:
132 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 163: GPIOx->DDR &= (uint8_t)(~(GPIO_Pin));
008869 1E 04 [ 2] 133 ldw x, (0x04, sp)
00886B F6 [ 1] 134 ld a, (x)
00886C 14 03 [ 1] 135 and a, (0x03, sp)
00886E 1E 04 [ 2] 136 ldw x, (0x04, sp)
008870 F7 [ 1] 137 ld (x), a
008871 138 00106$:
139 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 172: GPIOx->CR1 |= GPIO_Pin;
008871 1E 07 [ 2] 140 ldw x, (0x07, sp)
008873 1C 00 03 [ 2] 141 addw x, #0x0003
008876 F6 [ 1] 142 ld a, (x)
143 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 170: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x40) != (uint8_t)0x00) /* Pull-Up or Push-Pull */
008877 88 [ 1] 144 push a
008878 7B 0C [ 1] 145 ld a, (0x0c, sp)
00887A A5 40 [ 1] 146 bcp a, #0x40
00887C 84 [ 1] 147 pop a
00887D 27 05 [ 1] 148 jreq 00108$
149 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 172: GPIOx->CR1 |= GPIO_Pin;
00887F 1A 06 [ 1] 150 or a, (0x06, sp)
008881 F7 [ 1] 151 ld (x), a
008882 20 03 [ 2] 152 jra 00109$
008884 153 00108$:
154 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 175: GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
008884 14 03 [ 1] 155 and a, (0x03, sp)
008886 F7 [ 1] 156 ld (x), a
008887 157 00109$:
158 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 143: GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
008887 1E 01 [ 2] 159 ldw x, (0x01, sp)
008889 F6 [ 1] 160 ld a, (x)
161 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 182: if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x20) != (uint8_t)0x00) /* Interrupt or Slow slope */
00888A 88 [ 1] 162 push a
00888B 7B 0C [ 1] 163 ld a, (0x0c, sp)
00888D A5 20 [ 1] 164 bcp a, #0x20
00888F 84 [ 1] 165 pop a
008890 27 07 [ 1] 166 jreq 00111$
167 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 184: GPIOx->CR2 |= GPIO_Pin;
008892 1A 06 [ 1] 168 or a, (0x06, sp)
008894 1E 01 [ 2] 169 ldw x, (0x01, sp)
008896 F7 [ 1] 170 ld (x), a
008897 20 05 [ 2] 171 jra 00113$
008899 172 00111$:
173 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 187: GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
008899 14 03 [ 1] 174 and a, (0x03, sp)
00889B 1E 01 [ 2] 175 ldw x, (0x01, sp)
00889D F7 [ 1] 176 ld (x), a
00889E 177 00113$:
178 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 190: }
00889E 5B 08 [ 2] 179 addw sp, #8
0088A0 85 [ 2] 180 popw x
0088A1 84 [ 1] 181 pop a
0088A2 FC [ 2] 182 jp (x)
183 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 209: void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, FunctionalState NewState)
184 ; -----------------------------------------
185 ; function GPIO_ExternalPullUpConfig
186 ; -----------------------------------------
0088A3 187 _GPIO_ExternalPullUpConfig:
0088A3 88 [ 1] 188 push a
189 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 217: GPIOx->CR1 |= GPIO_Pin;
0088A4 1C 00 03 [ 2] 190 addw x, #0x0003
0088A7 88 [ 1] 191 push a
0088A8 F6 [ 1] 192 ld a, (x)
0088A9 6B 02 [ 1] 193 ld (0x02, sp), a
0088AB 84 [ 1] 194 pop a
195 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 215: if (NewState != DISABLE) /* External Pull-Up Set*/
0088AC 0D 04 [ 1] 196 tnz (0x04, sp)
0088AE 27 05 [ 1] 197 jreq 00102$
198 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 217: GPIOx->CR1 |= GPIO_Pin;
0088B0 1A 01 [ 1] 199 or a, (0x01, sp)
0088B2 F7 [ 1] 200 ld (x), a
0088B3 20 04 [ 2] 201 jra 00104$
0088B5 202 00102$:
203 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 220: GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
0088B5 43 [ 1] 204 cpl a
0088B6 14 01 [ 1] 205 and a, (0x01, sp)
0088B8 F7 [ 1] 206 ld (x), a
0088B9 207 00104$:
208 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 222: }
0088B9 84 [ 1] 209 pop a
0088BA 85 [ 2] 210 popw x
0088BB 84 [ 1] 211 pop a
0088BC FC [ 2] 212 jp (x)
213 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 248: void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t GPIO_PortVal)
214 ; -----------------------------------------
215 ; function GPIO_Write
216 ; -----------------------------------------
0088BD 217 _GPIO_Write:
218 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 250: GPIOx->ODR = GPIO_PortVal;
0088BD F7 [ 1] 219 ld (x), a
220 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 251: }
0088BE 81 [ 4] 221 ret
222 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 270: void GPIO_WriteBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction GPIO_BitVal)
223 ; -----------------------------------------
224 ; function GPIO_WriteBit
225 ; -----------------------------------------
0088BF 226 _GPIO_WriteBit:
0088BF 88 [ 1] 227 push a
228 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 278: GPIOx->ODR |= GPIO_Pin;
0088C0 88 [ 1] 229 push a
0088C1 F6 [ 1] 230 ld a, (x)
0088C2 6B 02 [ 1] 231 ld (0x02, sp), a
0088C4 84 [ 1] 232 pop a
233 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 276: if (GPIO_BitVal != RESET)
0088C5 0D 04 [ 1] 234 tnz (0x04, sp)
0088C7 27 05 [ 1] 235 jreq 00102$
236 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 278: GPIOx->ODR |= GPIO_Pin;
0088C9 1A 01 [ 1] 237 or a, (0x01, sp)
0088CB F7 [ 1] 238 ld (x), a
0088CC 20 04 [ 2] 239 jra 00104$
0088CE 240 00102$:
241 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 283: GPIOx->ODR &= (uint8_t)(~GPIO_Pin);
0088CE 43 [ 1] 242 cpl a
0088CF 14 01 [ 1] 243 and a, (0x01, sp)
0088D1 F7 [ 1] 244 ld (x), a
0088D2 245 00104$:
246 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 285: }
0088D2 84 [ 1] 247 pop a
0088D3 85 [ 2] 248 popw x
0088D4 84 [ 1] 249 pop a
0088D5 FC [ 2] 250 jp (x)
251 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 303: void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
252 ; -----------------------------------------
253 ; function GPIO_SetBits
254 ; -----------------------------------------
0088D6 255 _GPIO_SetBits:
0088D6 88 [ 1] 256 push a
0088D7 6B 01 [ 1] 257 ld (0x01, sp), a
258 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 305: GPIOx->ODR |= GPIO_Pin;
0088D9 F6 [ 1] 259 ld a, (x)
0088DA 1A 01 [ 1] 260 or a, (0x01, sp)
0088DC F7 [ 1] 261 ld (x), a
262 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 306: }
0088DD 84 [ 1] 263 pop a
0088DE 81 [ 4] 264 ret
265 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 324: void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
266 ; -----------------------------------------
267 ; function GPIO_ResetBits
268 ; -----------------------------------------
0088DF 269 _GPIO_ResetBits:
0088DF 88 [ 1] 270 push a
271 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 326: GPIOx->ODR &= (uint8_t)(~GPIO_Pin);
0088E0 88 [ 1] 272 push a
0088E1 F6 [ 1] 273 ld a, (x)
0088E2 6B 02 [ 1] 274 ld (0x02, sp), a
0088E4 84 [ 1] 275 pop a
0088E5 43 [ 1] 276 cpl a
0088E6 14 01 [ 1] 277 and a, (0x01, sp)
0088E8 F7 [ 1] 278 ld (x), a
279 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 327: }
0088E9 84 [ 1] 280 pop a
0088EA 81 [ 4] 281 ret
282 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 336: void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
283 ; -----------------------------------------
284 ; function GPIO_ToggleBits
285 ; -----------------------------------------
0088EB 286 _GPIO_ToggleBits:
0088EB 88 [ 1] 287 push a
0088EC 6B 01 [ 1] 288 ld (0x01, sp), a
289 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 338: GPIOx->ODR ^= GPIO_Pin;
0088EE F6 [ 1] 290 ld a, (x)
0088EF 18 01 [ 1] 291 xor a, (0x01, sp)
0088F1 F7 [ 1] 292 ld (x), a
293 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 339: }
0088F2 84 [ 1] 294 pop a
0088F3 81 [ 4] 295 ret
296 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 347: uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
297 ; -----------------------------------------
298 ; function GPIO_ReadInputData
299 ; -----------------------------------------
0088F4 300 _GPIO_ReadInputData:
301 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 349: return ((uint8_t)GPIOx->IDR);
0088F4 E6 01 [ 1] 302 ld a, (0x1, x)
303 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 350: }
0088F6 81 [ 4] 304 ret
305 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 358: uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
306 ; -----------------------------------------
307 ; function GPIO_ReadOutputData
308 ; -----------------------------------------
0088F7 309 _GPIO_ReadOutputData:
310 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 360: return ((uint8_t)GPIOx->ODR);
0088F7 F6 [ 1] 311 ld a, (x)
312 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 361: }
0088F8 81 [ 4] 313 ret
314 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 378: BitStatus GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
315 ; -----------------------------------------
316 ; function GPIO_ReadInputDataBit
317 ; -----------------------------------------
0088F9 318 _GPIO_ReadInputDataBit:
0088F9 88 [ 1] 319 push a
0088FA 6B 01 [ 1] 320 ld (0x01, sp), a
321 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 380: return ((BitStatus)(GPIOx->IDR & (uint8_t)GPIO_Pin));
0088FC E6 01 [ 1] 322 ld a, (0x1, x)
0088FE 14 01 [ 1] 323 and a, (0x01, sp)
008900 40 [ 1] 324 neg a
008901 4F [ 1] 325 clr a
008902 49 [ 1] 326 rlc a
327 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 381: }
008903 5B 01 [ 2] 328 addw sp, #1
008905 81 [ 4] 329 ret
330 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 389: BitStatus GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
331 ; -----------------------------------------
332 ; function GPIO_ReadOutputDataBit
333 ; -----------------------------------------
008906 334 _GPIO_ReadOutputDataBit:
008906 88 [ 1] 335 push a
008907 6B 01 [ 1] 336 ld (0x01, sp), a
337 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 391: return ((BitStatus)(GPIOx->ODR & (uint8_t)GPIO_Pin));
008909 F6 [ 1] 338 ld a, (x)
00890A 14 01 [ 1] 339 and a, (0x01, sp)
00890C 40 [ 1] 340 neg a
00890D 4F [ 1] 341 clr a
00890E 49 [ 1] 342 rlc a
343 ; ../inc/stm8l151x/src/stm8l15x_gpio.c: 392: }
00890F 5B 01 [ 2] 344 addw sp, #1
008911 81 [ 4] 345 ret
346 .area CODE
347 .area CONST
348 .area INITIALIZER
349 .area CABS (ABS)

40
firmware/STM8L15X_LD/stm8l15x_gpio.sym Normal file
View File

@@ -0,0 +1,40 @@
ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 1
Hexadecimal [24-Bits]
Symbol Table
.__.$$$. = 002710 L
.__.ABS. = 000000 G
.__.CPU. = 000000 L
.__.H$L. = 000001 L
9 _GPIO_DeInit 000000 GR
9 _GPIO_ExternalPullUpConfig 000088 GR
9 _GPIO_Init 00000D GR
9 _GPIO_ReadInputData 0000D9 GR
9 _GPIO_ReadInputDataBit 0000DE GR
9 _GPIO_ReadOutputData 0000DC GR
9 _GPIO_ReadOutputDataBit 0000EB GR
9 _GPIO_ResetBits 0000C4 GR
9 _GPIO_SetBits 0000BB GR
9 _GPIO_ToggleBits 0000D0 GR
9 _GPIO_Write 0000A2 GR
9 _GPIO_WriteBit 0000A4 GR
ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 2
Hexadecimal [24-Bits]
Area Table
0 _CODE size 0 flags 0
1 DATA size 0 flags 0
2 INITIALIZED size 0 flags 0
3 DABS size 0 flags 8
4 HOME size 0 flags 0
5 GSINIT size 0 flags 0
6 GSFINAL size 0 flags 0
7 CONST size 0 flags 0
8 INITIALIZER size 0 flags 0
9 CODE size F7 flags 0
A CABS size 0 flags 8

290
firmware/STM8L15X_LD/stm8l15x_it.asm Normal file
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@@ -0,0 +1,290 @@
;--------------------------------------------------------
; File Created by SDCC : free open source ISO C Compiler
; Version 4.5.0 #15242 (Linux)
;--------------------------------------------------------
.module stm8l15x_it
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _TRAP_IRQHandler
.globl _FLASH_IRQHandler
.globl _DMA1_CHANNEL0_1_IRQHandler
.globl _DMA1_CHANNEL2_3_IRQHandler
.globl _RTC_CSSLSE_IRQHandler
.globl _EXTIE_F_PVD_IRQHandler
.globl _EXTIB_G_IRQHandler
.globl _EXTID_H_IRQHandler
.globl _EXTI0_IRQHandler
.globl _EXTI1_IRQHandler
.globl _EXTI2_IRQHandler
.globl _EXTI3_IRQHandler
.globl _EXTI4_IRQHandler
.globl _EXTI5_IRQHandler
.globl _EXTI6_IRQHandler
.globl _EXTI7_IRQHandler
.globl _LCD_AES_IRQHandler
.globl _SWITCH_CSS_BREAK_DAC_IRQHandler
.globl _ADC1_COMP_IRQHandler
.globl _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler
.globl _TIM2_CC_USART2_RX_IRQHandler
.globl _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler
.globl _TIM3_CC_USART3_RX_IRQHandler
.globl _TIM1_UPD_OVF_TRG_COM_IRQHandler
.globl _TIM1_CC_IRQHandler
.globl _TIM4_UPD_OVF_TRG_IRQHandler
.globl _SPI1_IRQHandler
.globl _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler
.globl _USART1_RX_TIM5_CC_IRQHandler
.globl _I2C1_SPI2_IRQHandler
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area DATA
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area INITIALIZED
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area DABS (ABS)
; default segment ordering for linker
.area HOME
.area GSINIT
.area GSFINAL
.area CONST
.area INITIALIZER
.area CODE
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area HOME
.area GSINIT
.area GSFINAL
.area GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area HOME
.area HOME
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area CODE
; ../src/stm8l15x_it.c: 67: INTERRUPT_HANDLER_TRAP(TRAP_IRQHandler)
; -----------------------------------------
; function TRAP_IRQHandler
; -----------------------------------------
_TRAP_IRQHandler:
; ../src/stm8l15x_it.c: 72: }
iret
; ../src/stm8l15x_it.c: 78: INTERRUPT_HANDLER(FLASH_IRQHandler,1)
; -----------------------------------------
; function FLASH_IRQHandler
; -----------------------------------------
_FLASH_IRQHandler:
; ../src/stm8l15x_it.c: 83: }
iret
; ../src/stm8l15x_it.c: 89: INTERRUPT_HANDLER(DMA1_CHANNEL0_1_IRQHandler,2)
; -----------------------------------------
; function DMA1_CHANNEL0_1_IRQHandler
; -----------------------------------------
_DMA1_CHANNEL0_1_IRQHandler:
; ../src/stm8l15x_it.c: 94: }
iret
; ../src/stm8l15x_it.c: 100: INTERRUPT_HANDLER(DMA1_CHANNEL2_3_IRQHandler,3)
; -----------------------------------------
; function DMA1_CHANNEL2_3_IRQHandler
; -----------------------------------------
_DMA1_CHANNEL2_3_IRQHandler:
; ../src/stm8l15x_it.c: 105: }
iret
; ../src/stm8l15x_it.c: 111: INTERRUPT_HANDLER(RTC_CSSLSE_IRQHandler,4)
; -----------------------------------------
; function RTC_CSSLSE_IRQHandler
; -----------------------------------------
_RTC_CSSLSE_IRQHandler:
; ../src/stm8l15x_it.c: 116: }
iret
; ../src/stm8l15x_it.c: 122: INTERRUPT_HANDLER(EXTIE_F_PVD_IRQHandler,5)
; -----------------------------------------
; function EXTIE_F_PVD_IRQHandler
; -----------------------------------------
_EXTIE_F_PVD_IRQHandler:
; ../src/stm8l15x_it.c: 127: }
iret
; ../src/stm8l15x_it.c: 134: INTERRUPT_HANDLER(EXTIB_G_IRQHandler,6)
; -----------------------------------------
; function EXTIB_G_IRQHandler
; -----------------------------------------
_EXTIB_G_IRQHandler:
; ../src/stm8l15x_it.c: 139: }
iret
; ../src/stm8l15x_it.c: 146: INTERRUPT_HANDLER(EXTID_H_IRQHandler,7)
; -----------------------------------------
; function EXTID_H_IRQHandler
; -----------------------------------------
_EXTID_H_IRQHandler:
; ../src/stm8l15x_it.c: 151: }
iret
; ../src/stm8l15x_it.c: 158: INTERRUPT_HANDLER(EXTI0_IRQHandler,8)
; -----------------------------------------
; function EXTI0_IRQHandler
; -----------------------------------------
_EXTI0_IRQHandler:
; ../src/stm8l15x_it.c: 163: }
iret
; ../src/stm8l15x_it.c: 170: INTERRUPT_HANDLER(EXTI1_IRQHandler,9)
; -----------------------------------------
; function EXTI1_IRQHandler
; -----------------------------------------
_EXTI1_IRQHandler:
; ../src/stm8l15x_it.c: 175: }
iret
; ../src/stm8l15x_it.c: 182: INTERRUPT_HANDLER(EXTI2_IRQHandler,10)
; -----------------------------------------
; function EXTI2_IRQHandler
; -----------------------------------------
_EXTI2_IRQHandler:
; ../src/stm8l15x_it.c: 187: }
iret
; ../src/stm8l15x_it.c: 194: INTERRUPT_HANDLER(EXTI3_IRQHandler,11)
; -----------------------------------------
; function EXTI3_IRQHandler
; -----------------------------------------
_EXTI3_IRQHandler:
; ../src/stm8l15x_it.c: 199: }
iret
; ../src/stm8l15x_it.c: 206: INTERRUPT_HANDLER(EXTI4_IRQHandler,12)
; -----------------------------------------
; function EXTI4_IRQHandler
; -----------------------------------------
_EXTI4_IRQHandler:
; ../src/stm8l15x_it.c: 211: }
iret
; ../src/stm8l15x_it.c: 218: INTERRUPT_HANDLER(EXTI5_IRQHandler,13)
; -----------------------------------------
; function EXTI5_IRQHandler
; -----------------------------------------
_EXTI5_IRQHandler:
; ../src/stm8l15x_it.c: 223: }
iret
; ../src/stm8l15x_it.c: 230: INTERRUPT_HANDLER(EXTI6_IRQHandler,14)
; -----------------------------------------
; function EXTI6_IRQHandler
; -----------------------------------------
_EXTI6_IRQHandler:
; ../src/stm8l15x_it.c: 235: }
iret
; ../src/stm8l15x_it.c: 242: INTERRUPT_HANDLER(EXTI7_IRQHandler,15)
; -----------------------------------------
; function EXTI7_IRQHandler
; -----------------------------------------
_EXTI7_IRQHandler:
; ../src/stm8l15x_it.c: 247: }
iret
; ../src/stm8l15x_it.c: 253: INTERRUPT_HANDLER(LCD_AES_IRQHandler,16)
; -----------------------------------------
; function LCD_AES_IRQHandler
; -----------------------------------------
_LCD_AES_IRQHandler:
; ../src/stm8l15x_it.c: 258: }
iret
; ../src/stm8l15x_it.c: 264: INTERRUPT_HANDLER(SWITCH_CSS_BREAK_DAC_IRQHandler,17)
; -----------------------------------------
; function SWITCH_CSS_BREAK_DAC_IRQHandler
; -----------------------------------------
_SWITCH_CSS_BREAK_DAC_IRQHandler:
; ../src/stm8l15x_it.c: 269: }
iret
; ../src/stm8l15x_it.c: 276: INTERRUPT_HANDLER(ADC1_COMP_IRQHandler,18)
; -----------------------------------------
; function ADC1_COMP_IRQHandler
; -----------------------------------------
_ADC1_COMP_IRQHandler:
; ../src/stm8l15x_it.c: 281: }
iret
; ../src/stm8l15x_it.c: 288: INTERRUPT_HANDLER(TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler,19)
; -----------------------------------------
; function TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler
; -----------------------------------------
_TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler:
; ../src/stm8l15x_it.c: 293: }
iret
; ../src/stm8l15x_it.c: 300: INTERRUPT_HANDLER(TIM2_CC_USART2_RX_IRQHandler,20)
; -----------------------------------------
; function TIM2_CC_USART2_RX_IRQHandler
; -----------------------------------------
_TIM2_CC_USART2_RX_IRQHandler:
; ../src/stm8l15x_it.c: 305: }
iret
; ../src/stm8l15x_it.c: 313: INTERRUPT_HANDLER(TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler,21)
; -----------------------------------------
; function TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler
; -----------------------------------------
_TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler:
; ../src/stm8l15x_it.c: 318: }
iret
; ../src/stm8l15x_it.c: 324: INTERRUPT_HANDLER(TIM3_CC_USART3_RX_IRQHandler,22)
; -----------------------------------------
; function TIM3_CC_USART3_RX_IRQHandler
; -----------------------------------------
_TIM3_CC_USART3_RX_IRQHandler:
; ../src/stm8l15x_it.c: 329: }
iret
; ../src/stm8l15x_it.c: 335: INTERRUPT_HANDLER(TIM1_UPD_OVF_TRG_COM_IRQHandler,23)
; -----------------------------------------
; function TIM1_UPD_OVF_TRG_COM_IRQHandler
; -----------------------------------------
_TIM1_UPD_OVF_TRG_COM_IRQHandler:
; ../src/stm8l15x_it.c: 340: }
iret
; ../src/stm8l15x_it.c: 346: INTERRUPT_HANDLER(TIM1_CC_IRQHandler,24)
; -----------------------------------------
; function TIM1_CC_IRQHandler
; -----------------------------------------
_TIM1_CC_IRQHandler:
; ../src/stm8l15x_it.c: 351: }
iret
; ../src/stm8l15x_it.c: 358: INTERRUPT_HANDLER(TIM4_UPD_OVF_TRG_IRQHandler,25)
; -----------------------------------------
; function TIM4_UPD_OVF_TRG_IRQHandler
; -----------------------------------------
_TIM4_UPD_OVF_TRG_IRQHandler:
; ../src/stm8l15x_it.c: 363: }
iret
; ../src/stm8l15x_it.c: 369: INTERRUPT_HANDLER(SPI1_IRQHandler,26)
; -----------------------------------------
; function SPI1_IRQHandler
; -----------------------------------------
_SPI1_IRQHandler:
; ../src/stm8l15x_it.c: 374: }
iret
; ../src/stm8l15x_it.c: 381: INTERRUPT_HANDLER(USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler,27)
; -----------------------------------------
; function USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler
; -----------------------------------------
_USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler:
; ../src/stm8l15x_it.c: 386: }
iret
; ../src/stm8l15x_it.c: 393: INTERRUPT_HANDLER(USART1_RX_TIM5_CC_IRQHandler,28)
; -----------------------------------------
; function USART1_RX_TIM5_CC_IRQHandler
; -----------------------------------------
_USART1_RX_TIM5_CC_IRQHandler:
; ../src/stm8l15x_it.c: 398: }
iret
; ../src/stm8l15x_it.c: 405: INTERRUPT_HANDLER(I2C1_SPI2_IRQHandler,29)
; -----------------------------------------
; function I2C1_SPI2_IRQHandler
; -----------------------------------------
_I2C1_SPI2_IRQHandler:
; ../src/stm8l15x_it.c: 410: }
iret
.area CODE
.area CONST
.area INITIALIZER
.area CABS (ABS)

290
firmware/STM8L15X_LD/stm8l15x_it.lst Normal file
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@@ -0,0 +1,290 @@
1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ISO C Compiler
3 ; Version 4.5.0 #15242 (Linux)
4 ;--------------------------------------------------------
5 .module stm8l15x_it
6
7 ;--------------------------------------------------------
8 ; Public variables in this module
9 ;--------------------------------------------------------
10 .globl _TRAP_IRQHandler
11 .globl _FLASH_IRQHandler
12 .globl _DMA1_CHANNEL0_1_IRQHandler
13 .globl _DMA1_CHANNEL2_3_IRQHandler
14 .globl _RTC_CSSLSE_IRQHandler
15 .globl _EXTIE_F_PVD_IRQHandler
16 .globl _EXTIB_G_IRQHandler
17 .globl _EXTID_H_IRQHandler
18 .globl _EXTI0_IRQHandler
19 .globl _EXTI1_IRQHandler
20 .globl _EXTI2_IRQHandler
21 .globl _EXTI3_IRQHandler
22 .globl _EXTI4_IRQHandler
23 .globl _EXTI5_IRQHandler
24 .globl _EXTI6_IRQHandler
25 .globl _EXTI7_IRQHandler
26 .globl _LCD_AES_IRQHandler
27 .globl _SWITCH_CSS_BREAK_DAC_IRQHandler
28 .globl _ADC1_COMP_IRQHandler
29 .globl _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler
30 .globl _TIM2_CC_USART2_RX_IRQHandler
31 .globl _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler
32 .globl _TIM3_CC_USART3_RX_IRQHandler
33 .globl _TIM1_UPD_OVF_TRG_COM_IRQHandler
34 .globl _TIM1_CC_IRQHandler
35 .globl _TIM4_UPD_OVF_TRG_IRQHandler
36 .globl _SPI1_IRQHandler
37 .globl _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler
38 .globl _USART1_RX_TIM5_CC_IRQHandler
39 .globl _I2C1_SPI2_IRQHandler
40 ;--------------------------------------------------------
41 ; ram data
42 ;--------------------------------------------------------
43 .area DATA
44 ;--------------------------------------------------------
45 ; ram data
46 ;--------------------------------------------------------
47 .area INITIALIZED
48 ;--------------------------------------------------------
49 ; absolute external ram data
50 ;--------------------------------------------------------
51 .area DABS (ABS)
52
53 ; default segment ordering for linker
54 .area HOME
55 .area GSINIT
56 .area GSFINAL
57 .area CONST
58 .area INITIALIZER
59 .area CODE
60
61 ;--------------------------------------------------------
62 ; global & static initialisations
63 ;--------------------------------------------------------
64 .area HOME
65 .area GSINIT
66 .area GSFINAL
67 .area GSINIT
68 ;--------------------------------------------------------
69 ; Home
70 ;--------------------------------------------------------
71 .area HOME
72 .area HOME
73 ;--------------------------------------------------------
74 ; code
75 ;--------------------------------------------------------
76 .area CODE
77 ; ../src/stm8l15x_it.c: 67: INTERRUPT_HANDLER_TRAP(TRAP_IRQHandler)
78 ; -----------------------------------------
79 ; function TRAP_IRQHandler
80 ; -----------------------------------------
000000 81 _TRAP_IRQHandler:
82 ; ../src/stm8l15x_it.c: 72: }
000000 80 [11] 83 iret
84 ; ../src/stm8l15x_it.c: 78: INTERRUPT_HANDLER(FLASH_IRQHandler,1)
85 ; -----------------------------------------
86 ; function FLASH_IRQHandler
87 ; -----------------------------------------
000001 88 _FLASH_IRQHandler:
89 ; ../src/stm8l15x_it.c: 83: }
000001 80 [11] 90 iret
91 ; ../src/stm8l15x_it.c: 89: INTERRUPT_HANDLER(DMA1_CHANNEL0_1_IRQHandler,2)
92 ; -----------------------------------------
93 ; function DMA1_CHANNEL0_1_IRQHandler
94 ; -----------------------------------------
000002 95 _DMA1_CHANNEL0_1_IRQHandler:
96 ; ../src/stm8l15x_it.c: 94: }
000002 80 [11] 97 iret
98 ; ../src/stm8l15x_it.c: 100: INTERRUPT_HANDLER(DMA1_CHANNEL2_3_IRQHandler,3)
99 ; -----------------------------------------
100 ; function DMA1_CHANNEL2_3_IRQHandler
101 ; -----------------------------------------
000003 102 _DMA1_CHANNEL2_3_IRQHandler:
103 ; ../src/stm8l15x_it.c: 105: }
000003 80 [11] 104 iret
105 ; ../src/stm8l15x_it.c: 111: INTERRUPT_HANDLER(RTC_CSSLSE_IRQHandler,4)
106 ; -----------------------------------------
107 ; function RTC_CSSLSE_IRQHandler
108 ; -----------------------------------------
000004 109 _RTC_CSSLSE_IRQHandler:
110 ; ../src/stm8l15x_it.c: 116: }
000004 80 [11] 111 iret
112 ; ../src/stm8l15x_it.c: 122: INTERRUPT_HANDLER(EXTIE_F_PVD_IRQHandler,5)
113 ; -----------------------------------------
114 ; function EXTIE_F_PVD_IRQHandler
115 ; -----------------------------------------
000005 116 _EXTIE_F_PVD_IRQHandler:
117 ; ../src/stm8l15x_it.c: 127: }
000005 80 [11] 118 iret
119 ; ../src/stm8l15x_it.c: 134: INTERRUPT_HANDLER(EXTIB_G_IRQHandler,6)
120 ; -----------------------------------------
121 ; function EXTIB_G_IRQHandler
122 ; -----------------------------------------
000006 123 _EXTIB_G_IRQHandler:
124 ; ../src/stm8l15x_it.c: 139: }
000006 80 [11] 125 iret
126 ; ../src/stm8l15x_it.c: 146: INTERRUPT_HANDLER(EXTID_H_IRQHandler,7)
127 ; -----------------------------------------
128 ; function EXTID_H_IRQHandler
129 ; -----------------------------------------
000007 130 _EXTID_H_IRQHandler:
131 ; ../src/stm8l15x_it.c: 151: }
000007 80 [11] 132 iret
133 ; ../src/stm8l15x_it.c: 158: INTERRUPT_HANDLER(EXTI0_IRQHandler,8)
134 ; -----------------------------------------
135 ; function EXTI0_IRQHandler
136 ; -----------------------------------------
000008 137 _EXTI0_IRQHandler:
138 ; ../src/stm8l15x_it.c: 163: }
000008 80 [11] 139 iret
140 ; ../src/stm8l15x_it.c: 170: INTERRUPT_HANDLER(EXTI1_IRQHandler,9)
141 ; -----------------------------------------
142 ; function EXTI1_IRQHandler
143 ; -----------------------------------------
000009 144 _EXTI1_IRQHandler:
145 ; ../src/stm8l15x_it.c: 175: }
000009 80 [11] 146 iret
147 ; ../src/stm8l15x_it.c: 182: INTERRUPT_HANDLER(EXTI2_IRQHandler,10)
148 ; -----------------------------------------
149 ; function EXTI2_IRQHandler
150 ; -----------------------------------------
00000A 151 _EXTI2_IRQHandler:
152 ; ../src/stm8l15x_it.c: 187: }
00000A 80 [11] 153 iret
154 ; ../src/stm8l15x_it.c: 194: INTERRUPT_HANDLER(EXTI3_IRQHandler,11)
155 ; -----------------------------------------
156 ; function EXTI3_IRQHandler
157 ; -----------------------------------------
00000B 158 _EXTI3_IRQHandler:
159 ; ../src/stm8l15x_it.c: 199: }
00000B 80 [11] 160 iret
161 ; ../src/stm8l15x_it.c: 206: INTERRUPT_HANDLER(EXTI4_IRQHandler,12)
162 ; -----------------------------------------
163 ; function EXTI4_IRQHandler
164 ; -----------------------------------------
00000C 165 _EXTI4_IRQHandler:
166 ; ../src/stm8l15x_it.c: 211: }
00000C 80 [11] 167 iret
168 ; ../src/stm8l15x_it.c: 218: INTERRUPT_HANDLER(EXTI5_IRQHandler,13)
169 ; -----------------------------------------
170 ; function EXTI5_IRQHandler
171 ; -----------------------------------------
00000D 172 _EXTI5_IRQHandler:
173 ; ../src/stm8l15x_it.c: 223: }
00000D 80 [11] 174 iret
175 ; ../src/stm8l15x_it.c: 230: INTERRUPT_HANDLER(EXTI6_IRQHandler,14)
176 ; -----------------------------------------
177 ; function EXTI6_IRQHandler
178 ; -----------------------------------------
00000E 179 _EXTI6_IRQHandler:
180 ; ../src/stm8l15x_it.c: 235: }
00000E 80 [11] 181 iret
182 ; ../src/stm8l15x_it.c: 242: INTERRUPT_HANDLER(EXTI7_IRQHandler,15)
183 ; -----------------------------------------
184 ; function EXTI7_IRQHandler
185 ; -----------------------------------------
00000F 186 _EXTI7_IRQHandler:
187 ; ../src/stm8l15x_it.c: 247: }
00000F 80 [11] 188 iret
189 ; ../src/stm8l15x_it.c: 253: INTERRUPT_HANDLER(LCD_AES_IRQHandler,16)
190 ; -----------------------------------------
191 ; function LCD_AES_IRQHandler
192 ; -----------------------------------------
000010 193 _LCD_AES_IRQHandler:
194 ; ../src/stm8l15x_it.c: 258: }
000010 80 [11] 195 iret
196 ; ../src/stm8l15x_it.c: 264: INTERRUPT_HANDLER(SWITCH_CSS_BREAK_DAC_IRQHandler,17)
197 ; -----------------------------------------
198 ; function SWITCH_CSS_BREAK_DAC_IRQHandler
199 ; -----------------------------------------
000011 200 _SWITCH_CSS_BREAK_DAC_IRQHandler:
201 ; ../src/stm8l15x_it.c: 269: }
000011 80 [11] 202 iret
203 ; ../src/stm8l15x_it.c: 276: INTERRUPT_HANDLER(ADC1_COMP_IRQHandler,18)
204 ; -----------------------------------------
205 ; function ADC1_COMP_IRQHandler
206 ; -----------------------------------------
000012 207 _ADC1_COMP_IRQHandler:
208 ; ../src/stm8l15x_it.c: 281: }
000012 80 [11] 209 iret
210 ; ../src/stm8l15x_it.c: 288: INTERRUPT_HANDLER(TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler,19)
211 ; -----------------------------------------
212 ; function TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler
213 ; -----------------------------------------
000013 214 _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler:
215 ; ../src/stm8l15x_it.c: 293: }
000013 80 [11] 216 iret
217 ; ../src/stm8l15x_it.c: 300: INTERRUPT_HANDLER(TIM2_CC_USART2_RX_IRQHandler,20)
218 ; -----------------------------------------
219 ; function TIM2_CC_USART2_RX_IRQHandler
220 ; -----------------------------------------
000014 221 _TIM2_CC_USART2_RX_IRQHandler:
222 ; ../src/stm8l15x_it.c: 305: }
000014 80 [11] 223 iret
224 ; ../src/stm8l15x_it.c: 313: INTERRUPT_HANDLER(TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler,21)
225 ; -----------------------------------------
226 ; function TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler
227 ; -----------------------------------------
000015 228 _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler:
229 ; ../src/stm8l15x_it.c: 318: }
000015 80 [11] 230 iret
231 ; ../src/stm8l15x_it.c: 324: INTERRUPT_HANDLER(TIM3_CC_USART3_RX_IRQHandler,22)
232 ; -----------------------------------------
233 ; function TIM3_CC_USART3_RX_IRQHandler
234 ; -----------------------------------------
000016 235 _TIM3_CC_USART3_RX_IRQHandler:
236 ; ../src/stm8l15x_it.c: 329: }
000016 80 [11] 237 iret
238 ; ../src/stm8l15x_it.c: 335: INTERRUPT_HANDLER(TIM1_UPD_OVF_TRG_COM_IRQHandler,23)
239 ; -----------------------------------------
240 ; function TIM1_UPD_OVF_TRG_COM_IRQHandler
241 ; -----------------------------------------
000017 242 _TIM1_UPD_OVF_TRG_COM_IRQHandler:
243 ; ../src/stm8l15x_it.c: 340: }
000017 80 [11] 244 iret
245 ; ../src/stm8l15x_it.c: 346: INTERRUPT_HANDLER(TIM1_CC_IRQHandler,24)
246 ; -----------------------------------------
247 ; function TIM1_CC_IRQHandler
248 ; -----------------------------------------
000018 249 _TIM1_CC_IRQHandler:
250 ; ../src/stm8l15x_it.c: 351: }
000018 80 [11] 251 iret
252 ; ../src/stm8l15x_it.c: 358: INTERRUPT_HANDLER(TIM4_UPD_OVF_TRG_IRQHandler,25)
253 ; -----------------------------------------
254 ; function TIM4_UPD_OVF_TRG_IRQHandler
255 ; -----------------------------------------
000019 256 _TIM4_UPD_OVF_TRG_IRQHandler:
257 ; ../src/stm8l15x_it.c: 363: }
000019 80 [11] 258 iret
259 ; ../src/stm8l15x_it.c: 369: INTERRUPT_HANDLER(SPI1_IRQHandler,26)
260 ; -----------------------------------------
261 ; function SPI1_IRQHandler
262 ; -----------------------------------------
00001A 263 _SPI1_IRQHandler:
264 ; ../src/stm8l15x_it.c: 374: }
00001A 80 [11] 265 iret
266 ; ../src/stm8l15x_it.c: 381: INTERRUPT_HANDLER(USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler,27)
267 ; -----------------------------------------
268 ; function USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler
269 ; -----------------------------------------
00001B 270 _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler:
271 ; ../src/stm8l15x_it.c: 386: }
00001B 80 [11] 272 iret
273 ; ../src/stm8l15x_it.c: 393: INTERRUPT_HANDLER(USART1_RX_TIM5_CC_IRQHandler,28)
274 ; -----------------------------------------
275 ; function USART1_RX_TIM5_CC_IRQHandler
276 ; -----------------------------------------
00001C 277 _USART1_RX_TIM5_CC_IRQHandler:
278 ; ../src/stm8l15x_it.c: 398: }
00001C 80 [11] 279 iret
280 ; ../src/stm8l15x_it.c: 405: INTERRUPT_HANDLER(I2C1_SPI2_IRQHandler,29)
281 ; -----------------------------------------
282 ; function I2C1_SPI2_IRQHandler
283 ; -----------------------------------------
00001D 284 _I2C1_SPI2_IRQHandler:
285 ; ../src/stm8l15x_it.c: 410: }
00001D 80 [11] 286 iret
287 .area CODE
288 .area CONST
289 .area INITIALIZER
290 .area CABS (ABS)

165
firmware/STM8L15X_LD/stm8l15x_it.rel Normal file
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XH3
H B areas 1F global symbols
M stm8l15x_it
S .__.ABS. Def000000
A _CODE size 0 flags 0 addr 0
A DATA size 0 flags 0 addr 0
A INITIALIZED size 0 flags 0 addr 0
A DABS size 0 flags 8 addr 0
A HOME size 0 flags 0 addr 0
A GSINIT size 0 flags 0 addr 0
A GSFINAL size 0 flags 0 addr 0
A CONST size 0 flags 0 addr 0
A INITIALIZER size 0 flags 0 addr 0
A CODE size 1E flags 0 addr 0
S _DMA1_CHANNEL0_1_IRQHandler Def000002
S _SPI1_IRQHandler Def00001A
S _DMA1_CHANNEL2_3_IRQHandler Def000003
S _EXTIB_G_IRQHandler Def000006
S _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler Def000013
S _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler Def00001B
S _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler Def000015
S _EXTID_H_IRQHandler Def000007
S _TIM2_CC_USART2_RX_IRQHandler Def000014
S _EXTI0_IRQHandler Def000008
S _EXTI1_IRQHandler Def000009
S _I2C1_SPI2_IRQHandler Def00001D
S _USART1_RX_TIM5_CC_IRQHandler Def00001C
S _TIM3_CC_USART3_RX_IRQHandler Def000016
S _EXTI2_IRQHandler Def00000A
S _EXTI3_IRQHandler Def00000B
S _EXTIE_F_PVD_IRQHandler Def000005
S _EXTI4_IRQHandler Def00000C
S _FLASH_IRQHandler Def000001
S _EXTI5_IRQHandler Def00000D
S _EXTI6_IRQHandler Def00000E
S _EXTI7_IRQHandler Def00000F
S _TIM1_UPD_OVF_TRG_COM_IRQHandler Def000017
S _TRAP_IRQHandler Def000000
S _TIM4_UPD_OVF_TRG_IRQHandler Def000019
S _TIM1_CC_IRQHandler Def000018
S _SWITCH_CSS_BREAK_DAC_IRQHandler Def000011
S _ADC1_COMP_IRQHandler Def000012
S _LCD_AES_IRQHandler Def000010
S _RTC_CSSLSE_IRQHandler Def000004
A CABS size 0 flags 8 addr 0
T 00 00 00
R 00 00 00 09
T 00 00 00 80
R 00 00 00 09
T 00 00 01
R 00 00 00 09
T 00 00 01 80
R 00 00 00 09
T 00 00 02
R 00 00 00 09
T 00 00 02 80
R 00 00 00 09
T 00 00 03
R 00 00 00 09
T 00 00 03 80
R 00 00 00 09
T 00 00 04
R 00 00 00 09
T 00 00 04 80
R 00 00 00 09
T 00 00 05
R 00 00 00 09
T 00 00 05 80
R 00 00 00 09
T 00 00 06
R 00 00 00 09
T 00 00 06 80
R 00 00 00 09
T 00 00 07
R 00 00 00 09
T 00 00 07 80
R 00 00 00 09
T 00 00 08
R 00 00 00 09
T 00 00 08 80
R 00 00 00 09
T 00 00 09
R 00 00 00 09
T 00 00 09 80
R 00 00 00 09
T 00 00 0A
R 00 00 00 09
T 00 00 0A 80
R 00 00 00 09
T 00 00 0B
R 00 00 00 09
T 00 00 0B 80
R 00 00 00 09
T 00 00 0C
R 00 00 00 09
T 00 00 0C 80
R 00 00 00 09
T 00 00 0D
R 00 00 00 09
T 00 00 0D 80
R 00 00 00 09
T 00 00 0E
R 00 00 00 09
T 00 00 0E 80
R 00 00 00 09
T 00 00 0F
R 00 00 00 09
T 00 00 0F 80
R 00 00 00 09
T 00 00 10
R 00 00 00 09
T 00 00 10 80
R 00 00 00 09
T 00 00 11
R 00 00 00 09
T 00 00 11 80
R 00 00 00 09
T 00 00 12
R 00 00 00 09
T 00 00 12 80
R 00 00 00 09
T 00 00 13
R 00 00 00 09
T 00 00 13 80
R 00 00 00 09
T 00 00 14
R 00 00 00 09
T 00 00 14 80
R 00 00 00 09
T 00 00 15
R 00 00 00 09
T 00 00 15 80
R 00 00 00 09
T 00 00 16
R 00 00 00 09
T 00 00 16 80
R 00 00 00 09
T 00 00 17
R 00 00 00 09
T 00 00 17 80
R 00 00 00 09
T 00 00 18
R 00 00 00 09
T 00 00 18 80
R 00 00 00 09
T 00 00 19
R 00 00 00 09
T 00 00 19 80
R 00 00 00 09
T 00 00 1A
R 00 00 00 09
T 00 00 1A 80
R 00 00 00 09
T 00 00 1B
R 00 00 00 09
T 00 00 1B 80
R 00 00 00 09
T 00 00 1C
R 00 00 00 09
T 00 00 1C 80
R 00 00 00 09
T 00 00 1D
R 00 00 00 09
T 00 00 1D 80
R 00 00 00 09

290
firmware/STM8L15X_LD/stm8l15x_it.rst Normal file
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1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ISO C Compiler
3 ; Version 4.5.0 #15242 (Linux)
4 ;--------------------------------------------------------
5 .module stm8l15x_it
6
7 ;--------------------------------------------------------
8 ; Public variables in this module
9 ;--------------------------------------------------------
10 .globl _TRAP_IRQHandler
11 .globl _FLASH_IRQHandler
12 .globl _DMA1_CHANNEL0_1_IRQHandler
13 .globl _DMA1_CHANNEL2_3_IRQHandler
14 .globl _RTC_CSSLSE_IRQHandler
15 .globl _EXTIE_F_PVD_IRQHandler
16 .globl _EXTIB_G_IRQHandler
17 .globl _EXTID_H_IRQHandler
18 .globl _EXTI0_IRQHandler
19 .globl _EXTI1_IRQHandler
20 .globl _EXTI2_IRQHandler
21 .globl _EXTI3_IRQHandler
22 .globl _EXTI4_IRQHandler
23 .globl _EXTI5_IRQHandler
24 .globl _EXTI6_IRQHandler
25 .globl _EXTI7_IRQHandler
26 .globl _LCD_AES_IRQHandler
27 .globl _SWITCH_CSS_BREAK_DAC_IRQHandler
28 .globl _ADC1_COMP_IRQHandler
29 .globl _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler
30 .globl _TIM2_CC_USART2_RX_IRQHandler
31 .globl _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler
32 .globl _TIM3_CC_USART3_RX_IRQHandler
33 .globl _TIM1_UPD_OVF_TRG_COM_IRQHandler
34 .globl _TIM1_CC_IRQHandler
35 .globl _TIM4_UPD_OVF_TRG_IRQHandler
36 .globl _SPI1_IRQHandler
37 .globl _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler
38 .globl _USART1_RX_TIM5_CC_IRQHandler
39 .globl _I2C1_SPI2_IRQHandler
40 ;--------------------------------------------------------
41 ; ram data
42 ;--------------------------------------------------------
43 .area DATA
44 ;--------------------------------------------------------
45 ; ram data
46 ;--------------------------------------------------------
47 .area INITIALIZED
48 ;--------------------------------------------------------
49 ; absolute external ram data
50 ;--------------------------------------------------------
51 .area DABS (ABS)
52
53 ; default segment ordering for linker
54 .area HOME
55 .area GSINIT
56 .area GSFINAL
57 .area CONST
58 .area INITIALIZER
59 .area CODE
60
61 ;--------------------------------------------------------
62 ; global & static initialisations
63 ;--------------------------------------------------------
64 .area HOME
65 .area GSINIT
66 .area GSFINAL
67 .area GSINIT
68 ;--------------------------------------------------------
69 ; Home
70 ;--------------------------------------------------------
71 .area HOME
72 .area HOME
73 ;--------------------------------------------------------
74 ; code
75 ;--------------------------------------------------------
76 .area CODE
77 ; ../src/stm8l15x_it.c: 67: INTERRUPT_HANDLER_TRAP(TRAP_IRQHandler)
78 ; -----------------------------------------
79 ; function TRAP_IRQHandler
80 ; -----------------------------------------
00818F 81 _TRAP_IRQHandler:
82 ; ../src/stm8l15x_it.c: 72: }
00818F 80 [11] 83 iret
84 ; ../src/stm8l15x_it.c: 78: INTERRUPT_HANDLER(FLASH_IRQHandler,1)
85 ; -----------------------------------------
86 ; function FLASH_IRQHandler
87 ; -----------------------------------------
008190 88 _FLASH_IRQHandler:
89 ; ../src/stm8l15x_it.c: 83: }
008190 80 [11] 90 iret
91 ; ../src/stm8l15x_it.c: 89: INTERRUPT_HANDLER(DMA1_CHANNEL0_1_IRQHandler,2)
92 ; -----------------------------------------
93 ; function DMA1_CHANNEL0_1_IRQHandler
94 ; -----------------------------------------
008191 95 _DMA1_CHANNEL0_1_IRQHandler:
96 ; ../src/stm8l15x_it.c: 94: }
008191 80 [11] 97 iret
98 ; ../src/stm8l15x_it.c: 100: INTERRUPT_HANDLER(DMA1_CHANNEL2_3_IRQHandler,3)
99 ; -----------------------------------------
100 ; function DMA1_CHANNEL2_3_IRQHandler
101 ; -----------------------------------------
008192 102 _DMA1_CHANNEL2_3_IRQHandler:
103 ; ../src/stm8l15x_it.c: 105: }
008192 80 [11] 104 iret
105 ; ../src/stm8l15x_it.c: 111: INTERRUPT_HANDLER(RTC_CSSLSE_IRQHandler,4)
106 ; -----------------------------------------
107 ; function RTC_CSSLSE_IRQHandler
108 ; -----------------------------------------
008193 109 _RTC_CSSLSE_IRQHandler:
110 ; ../src/stm8l15x_it.c: 116: }
008193 80 [11] 111 iret
112 ; ../src/stm8l15x_it.c: 122: INTERRUPT_HANDLER(EXTIE_F_PVD_IRQHandler,5)
113 ; -----------------------------------------
114 ; function EXTIE_F_PVD_IRQHandler
115 ; -----------------------------------------
008194 116 _EXTIE_F_PVD_IRQHandler:
117 ; ../src/stm8l15x_it.c: 127: }
008194 80 [11] 118 iret
119 ; ../src/stm8l15x_it.c: 134: INTERRUPT_HANDLER(EXTIB_G_IRQHandler,6)
120 ; -----------------------------------------
121 ; function EXTIB_G_IRQHandler
122 ; -----------------------------------------
008195 123 _EXTIB_G_IRQHandler:
124 ; ../src/stm8l15x_it.c: 139: }
008195 80 [11] 125 iret
126 ; ../src/stm8l15x_it.c: 146: INTERRUPT_HANDLER(EXTID_H_IRQHandler,7)
127 ; -----------------------------------------
128 ; function EXTID_H_IRQHandler
129 ; -----------------------------------------
008196 130 _EXTID_H_IRQHandler:
131 ; ../src/stm8l15x_it.c: 151: }
008196 80 [11] 132 iret
133 ; ../src/stm8l15x_it.c: 158: INTERRUPT_HANDLER(EXTI0_IRQHandler,8)
134 ; -----------------------------------------
135 ; function EXTI0_IRQHandler
136 ; -----------------------------------------
008197 137 _EXTI0_IRQHandler:
138 ; ../src/stm8l15x_it.c: 163: }
008197 80 [11] 139 iret
140 ; ../src/stm8l15x_it.c: 170: INTERRUPT_HANDLER(EXTI1_IRQHandler,9)
141 ; -----------------------------------------
142 ; function EXTI1_IRQHandler
143 ; -----------------------------------------
008198 144 _EXTI1_IRQHandler:
145 ; ../src/stm8l15x_it.c: 175: }
008198 80 [11] 146 iret
147 ; ../src/stm8l15x_it.c: 182: INTERRUPT_HANDLER(EXTI2_IRQHandler,10)
148 ; -----------------------------------------
149 ; function EXTI2_IRQHandler
150 ; -----------------------------------------
008199 151 _EXTI2_IRQHandler:
152 ; ../src/stm8l15x_it.c: 187: }
008199 80 [11] 153 iret
154 ; ../src/stm8l15x_it.c: 194: INTERRUPT_HANDLER(EXTI3_IRQHandler,11)
155 ; -----------------------------------------
156 ; function EXTI3_IRQHandler
157 ; -----------------------------------------
00819A 158 _EXTI3_IRQHandler:
159 ; ../src/stm8l15x_it.c: 199: }
00819A 80 [11] 160 iret
161 ; ../src/stm8l15x_it.c: 206: INTERRUPT_HANDLER(EXTI4_IRQHandler,12)
162 ; -----------------------------------------
163 ; function EXTI4_IRQHandler
164 ; -----------------------------------------
00819B 165 _EXTI4_IRQHandler:
166 ; ../src/stm8l15x_it.c: 211: }
00819B 80 [11] 167 iret
168 ; ../src/stm8l15x_it.c: 218: INTERRUPT_HANDLER(EXTI5_IRQHandler,13)
169 ; -----------------------------------------
170 ; function EXTI5_IRQHandler
171 ; -----------------------------------------
00819C 172 _EXTI5_IRQHandler:
173 ; ../src/stm8l15x_it.c: 223: }
00819C 80 [11] 174 iret
175 ; ../src/stm8l15x_it.c: 230: INTERRUPT_HANDLER(EXTI6_IRQHandler,14)
176 ; -----------------------------------------
177 ; function EXTI6_IRQHandler
178 ; -----------------------------------------
00819D 179 _EXTI6_IRQHandler:
180 ; ../src/stm8l15x_it.c: 235: }
00819D 80 [11] 181 iret
182 ; ../src/stm8l15x_it.c: 242: INTERRUPT_HANDLER(EXTI7_IRQHandler,15)
183 ; -----------------------------------------
184 ; function EXTI7_IRQHandler
185 ; -----------------------------------------
00819E 186 _EXTI7_IRQHandler:
187 ; ../src/stm8l15x_it.c: 247: }
00819E 80 [11] 188 iret
189 ; ../src/stm8l15x_it.c: 253: INTERRUPT_HANDLER(LCD_AES_IRQHandler,16)
190 ; -----------------------------------------
191 ; function LCD_AES_IRQHandler
192 ; -----------------------------------------
00819F 193 _LCD_AES_IRQHandler:
194 ; ../src/stm8l15x_it.c: 258: }
00819F 80 [11] 195 iret
196 ; ../src/stm8l15x_it.c: 264: INTERRUPT_HANDLER(SWITCH_CSS_BREAK_DAC_IRQHandler,17)
197 ; -----------------------------------------
198 ; function SWITCH_CSS_BREAK_DAC_IRQHandler
199 ; -----------------------------------------
0081A0 200 _SWITCH_CSS_BREAK_DAC_IRQHandler:
201 ; ../src/stm8l15x_it.c: 269: }
0081A0 80 [11] 202 iret
203 ; ../src/stm8l15x_it.c: 276: INTERRUPT_HANDLER(ADC1_COMP_IRQHandler,18)
204 ; -----------------------------------------
205 ; function ADC1_COMP_IRQHandler
206 ; -----------------------------------------
0081A1 207 _ADC1_COMP_IRQHandler:
208 ; ../src/stm8l15x_it.c: 281: }
0081A1 80 [11] 209 iret
210 ; ../src/stm8l15x_it.c: 288: INTERRUPT_HANDLER(TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler,19)
211 ; -----------------------------------------
212 ; function TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler
213 ; -----------------------------------------
0081A2 214 _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler:
215 ; ../src/stm8l15x_it.c: 293: }
0081A2 80 [11] 216 iret
217 ; ../src/stm8l15x_it.c: 300: INTERRUPT_HANDLER(TIM2_CC_USART2_RX_IRQHandler,20)
218 ; -----------------------------------------
219 ; function TIM2_CC_USART2_RX_IRQHandler
220 ; -----------------------------------------
0081A3 221 _TIM2_CC_USART2_RX_IRQHandler:
222 ; ../src/stm8l15x_it.c: 305: }
0081A3 80 [11] 223 iret
224 ; ../src/stm8l15x_it.c: 313: INTERRUPT_HANDLER(TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler,21)
225 ; -----------------------------------------
226 ; function TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler
227 ; -----------------------------------------
0081A4 228 _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler:
229 ; ../src/stm8l15x_it.c: 318: }
0081A4 80 [11] 230 iret
231 ; ../src/stm8l15x_it.c: 324: INTERRUPT_HANDLER(TIM3_CC_USART3_RX_IRQHandler,22)
232 ; -----------------------------------------
233 ; function TIM3_CC_USART3_RX_IRQHandler
234 ; -----------------------------------------
0081A5 235 _TIM3_CC_USART3_RX_IRQHandler:
236 ; ../src/stm8l15x_it.c: 329: }
0081A5 80 [11] 237 iret
238 ; ../src/stm8l15x_it.c: 335: INTERRUPT_HANDLER(TIM1_UPD_OVF_TRG_COM_IRQHandler,23)
239 ; -----------------------------------------
240 ; function TIM1_UPD_OVF_TRG_COM_IRQHandler
241 ; -----------------------------------------
0081A6 242 _TIM1_UPD_OVF_TRG_COM_IRQHandler:
243 ; ../src/stm8l15x_it.c: 340: }
0081A6 80 [11] 244 iret
245 ; ../src/stm8l15x_it.c: 346: INTERRUPT_HANDLER(TIM1_CC_IRQHandler,24)
246 ; -----------------------------------------
247 ; function TIM1_CC_IRQHandler
248 ; -----------------------------------------
0081A7 249 _TIM1_CC_IRQHandler:
250 ; ../src/stm8l15x_it.c: 351: }
0081A7 80 [11] 251 iret
252 ; ../src/stm8l15x_it.c: 358: INTERRUPT_HANDLER(TIM4_UPD_OVF_TRG_IRQHandler,25)
253 ; -----------------------------------------
254 ; function TIM4_UPD_OVF_TRG_IRQHandler
255 ; -----------------------------------------
0081A8 256 _TIM4_UPD_OVF_TRG_IRQHandler:
257 ; ../src/stm8l15x_it.c: 363: }
0081A8 80 [11] 258 iret
259 ; ../src/stm8l15x_it.c: 369: INTERRUPT_HANDLER(SPI1_IRQHandler,26)
260 ; -----------------------------------------
261 ; function SPI1_IRQHandler
262 ; -----------------------------------------
0081A9 263 _SPI1_IRQHandler:
264 ; ../src/stm8l15x_it.c: 374: }
0081A9 80 [11] 265 iret
266 ; ../src/stm8l15x_it.c: 381: INTERRUPT_HANDLER(USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler,27)
267 ; -----------------------------------------
268 ; function USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler
269 ; -----------------------------------------
0081AA 270 _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler:
271 ; ../src/stm8l15x_it.c: 386: }
0081AA 80 [11] 272 iret
273 ; ../src/stm8l15x_it.c: 393: INTERRUPT_HANDLER(USART1_RX_TIM5_CC_IRQHandler,28)
274 ; -----------------------------------------
275 ; function USART1_RX_TIM5_CC_IRQHandler
276 ; -----------------------------------------
0081AB 277 _USART1_RX_TIM5_CC_IRQHandler:
278 ; ../src/stm8l15x_it.c: 398: }
0081AB 80 [11] 279 iret
280 ; ../src/stm8l15x_it.c: 405: INTERRUPT_HANDLER(I2C1_SPI2_IRQHandler,29)
281 ; -----------------------------------------
282 ; function I2C1_SPI2_IRQHandler
283 ; -----------------------------------------
0081AC 284 _I2C1_SPI2_IRQHandler:
285 ; ../src/stm8l15x_it.c: 410: }
0081AC 80 [11] 286 iret
287 .area CODE
288 .area CONST
289 .area INITIALIZER
290 .area CABS (ABS)

58
firmware/STM8L15X_LD/stm8l15x_it.sym Normal file
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ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 1
Hexadecimal [24-Bits]
Symbol Table
.__.$$$. = 002710 L
.__.ABS. = 000000 G
.__.CPU. = 000000 L
.__.H$L. = 000001 L
9 _ADC1_COMP_IRQHandler 000012 GR
9 _DMA1_CHANNEL0_1_IRQHandler 000002 GR
9 _DMA1_CHANNEL2_3_IRQHandler 000003 GR
9 _EXTI0_IRQHandler 000008 GR
9 _EXTI1_IRQHandler 000009 GR
9 _EXTI2_IRQHandler 00000A GR
9 _EXTI3_IRQHandler 00000B GR
9 _EXTI4_IRQHandler 00000C GR
9 _EXTI5_IRQHandler 00000D GR
9 _EXTI6_IRQHandler 00000E GR
9 _EXTI7_IRQHandler 00000F GR
9 _EXTIB_G_IRQHandler 000006 GR
9 _EXTID_H_IRQHandler 000007 GR
9 _EXTIE_F_PVD_IRQHandler 000005 GR
9 _FLASH_IRQHandler 000001 GR
9 _I2C1_SPI2_IRQHandler 00001D GR
9 _LCD_AES_IRQHandler 000010 GR
9 _RTC_CSSLSE_IRQHandler 000004 GR
9 _SPI1_IRQHandler 00001A GR
9 _SWITCH_CSS_BREAK_DAC_IRQHandler 000011 GR
9 _TIM1_CC_IRQHandler 000018 GR
9 _TIM1_UPD_OVF_TRG_COM_IRQHandler 000017 GR
9 _TIM2_CC_USART2_RX_IRQHandler 000014 GR
9 _TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQHandler 000013 GR
9 _TIM3_CC_USART3_RX_IRQHandler 000016 GR
9 _TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQHandler 000015 GR
9 _TIM4_UPD_OVF_TRG_IRQHandler 000019 GR
9 _TRAP_IRQHandler 000000 GR
9 _USART1_RX_TIM5_CC_IRQHandler 00001C GR
9 _USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQHandler 00001B GR
ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 2
Hexadecimal [24-Bits]
Area Table
0 _CODE size 0 flags 0
1 DATA size 0 flags 0
2 INITIALIZED size 0 flags 0
3 DABS size 0 flags 8
4 HOME size 0 flags 0
5 GSINIT size 0 flags 0
6 GSFINAL size 0 flags 0
7 CONST size 0 flags 0
8 INITIALIZER size 0 flags 0
9 CODE size 1E flags 0
A CABS size 0 flags 8

1969
firmware/STM8L15X_LD/stm8l15x_rtc.asm Normal file
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1969
firmware/STM8L15X_LD/stm8l15x_rtc.lst Normal file
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793
firmware/STM8L15X_LD/stm8l15x_rtc.rel Normal file
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XH3
H B areas 2B global symbols
M stm8l15x_rtc
S .__.ABS. Def000000
A _CODE size 0 flags 0 addr 0
A DATA size 0 flags 0 addr 0
A INITIALIZED size 0 flags 0 addr 0
A DABS size 0 flags 8 addr 0
A HOME size 0 flags 0 addr 0
A GSINIT size 0 flags 0 addr 0
A GSFINAL size 0 flags 0 addr 0
A CONST size 0 flags 0 addr 0
A INITIALIZER size 0 flags 0 addr 0
A CODE size 94A flags 0 addr 0
S _RTC_SetWakeUpCounter Def00064B
S _RTC_SetAlarm Def0003DF
S _RTC_StructInit Def000114
S _RTC_TamperPinsPrechargeDuration Def000831
S _RTC_GetFlagStatus Def0008C4
S _RTC_GetStoreOperation Def0006D3
S _RTC_GetDate Def000386
S _RTC_ClearFlag Def0008E9
S _RTC_WakeUpCmd Def00066E
S _RTC_WaitForSynchro Def00015B
S _RTC_TamperFilterConfig Def0007EF
S _RTC_GetSubSecond Def0002BA
S _RTC_OutputConfig Def0006D9
S _RTC_ClearITPendingBit Def00091A
S _RTC_TimeStructInit Def00025B
S _RTC_SetDate Def0002CB
S _RTC_SmoothCalibConfig Def00073B
S _RTC_BypassShadowCmd Def0001AB
S _RTC_GetTime Def000268
S _RTC_ITConfig Def00087C
S _RTC_ExitInitMode Def000156
S _RTC_TamperLevelConfig Def0007C5
S _RTC_SynchroShiftConfig Def000700
S _RTC_SetTime Def0001CF
S _RTC_TamperCmd Def000852
S _RTC_DeInit Def000000
S _RTC_CalibOutputCmd Def0007A1
S _RTC_GetITStatus Def0008F6
S _RTC_AlarmCmd Def0005A3
S _RTC_CalibOutputConfig Def00077D
S _RTC_AlarmStructInit Def0004D7
S _RTC_WriteProtectionCmd Def000124
S _RTC_TamperSamplingFreqConfig Def000810
S _RTC_AlarmSubSecondConfig Def0005EB
S _RTC_GetWakeUpCounter Def000660
S _RTC_GetAlarm Def0004F1
S _RTC_WakeUpClockConfig Def000626
S _RTC_RatioCmd Def000187
S _RTC_DayLightSavingConfig Def0006AC
S _RTC_Init Def0000CB
S _RTC_DateStructInit Def000372
S _RTC_EnterInitMode Def000135
A CABS size 0 flags 8 addr 0
T 00 00 00
R 00 00 00 09
T 00 00 00 35 CA 51 59 35 53 51 59 CD 01 35 4D 26
R 00 00 00 09 00 0C 00 09
T 00 00 0D 06 4F 35 FF 51 59 81
R 00 00 00 09
T 00 00 14
R 00 00 00 09
T 00 00 14 35 00 51 40 35 00 51 41 35 00 51 42 35
R 00 00 00 09
T 00 00 21 01 51 44 35 21 51 45 35 00 51 46 35 00
R 00 00 00 09
T 00 00 2E 51 50 35 FF 51 51 35 7F 51 52 35 00
R 00 00 00 09
T 00 00 3A 51 6C 35 00 51 6D 35 00 51 48 35 00
R 00 00 00 09
T 00 00 46 51 49 35 00 51 4A 5F
R 00 00 00 09
T 00 00 4D
R 00 00 00 09
T 00 00 4D 72 04 51 4C 0C A3 FF FF 27 07 5C 35 00
R 00 00 00 09
T 00 00 5A 51 4C 20 EF
R 00 00 00 09
T 00 00 5E
R 00 00 00 09
T 00 00 5E 72 04 51 4C 06 4F 35 FF 51 59 81
R 00 00 00 09
T 00 00 69
R 00 00 00 09
T 00 00 69 35 00 51 48 35 FF 51 54 35 FF 51 55 35
R 00 00 00 09
T 00 00 76 00 51 5C 35 00 51 5D 35 00 51 5E 35 00
R 00 00 00 09
T 00 00 83 51 5F 35 00 51 64 35 00 51 65 35 00
R 00 00 00 09
T 00 00 8F 51 66 35 00 51 4C 35 00 51 4D 72 03
R 00 00 00 09
T 00 00 9B 51 4C 0E 5F
R 00 00 00 09
T 00 00 9F
R 00 00 00 09
T 00 00 9F 72 03 51 4C 08 A3 FF FF 27 03 5C 20 F3
R 00 00 00 09
T 00 00 AC
R 00 00 00 09
T 00 00 AC 72 02 51 4C 14 35 00 51 6A 35 00 51 6B
R 00 00 00 09
T 00 00 B9 CD 01 5B 4D 26 03 4F 20 04
R 00 00 00 09 00 04 00 09
T 00 00 C2
R 00 00 00 09
T 00 00 C2 A6 01 21
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R 00 00 00 09
T 00 00 C5 4F
R 00 00 00 09
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T 00 00 C6 35 FF 51 59 81
R 00 00 00 09
T 00 00 CB
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T 00 00 CB 52 03 1F 02 35 CA 51 59 35 53 51 59 CD
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T 00 00 D8 01 35 4D 26 03 4F 20 2D
R 00 00 00 09 00 03 00 09
T 00 00 E0
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T 00 00 E0 72 1D 51 48 C6 51 48 6B 01 1E 02 F6 1A
R 00 00 00 09
T 00 00 ED 01 C7 51 48 1E 02 5C 5C E6 01 F6 C7
R 00 00 00 09
T 00 00 F9 51 50 E6 01 C7 51 51 1E 02 E6 01 C7
R 00 00 00 09
T 00 01 05 51 52 72 1F 51 4C A6 01
R 00 00 00 09
T 00 01 0D
R 00 00 00 09
T 00 01 0D 35 FF 51 59 5B 03 81
R 00 00 00 09
T 00 01 14
R 00 00 00 09
T 00 01 14 51 90 7F 93 5C A6 7F F7 93 90 AE 00 FF
R 00 00 00 09
T 00 01 21 EF 02 81
R 00 00 00 09
T 00 01 24
R 00 00 00 09
T 00 01 24 4D 27 05 35 FF 51 59 81
R 00 00 00 09
T 00 01 2C
R 00 00 00 09
T 00 01 2C 35 CA 51 59 35 53 51 59 81
R 00 00 00 09
T 00 01 35
R 00 00 00 09
T 00 01 35 72 0C 51 4C 12 35 80 51 4C 5F
R 00 00 00 09
T 00 01 3F
R 00 00 00 09
T 00 01 3F 72 0C 51 4C 08 A3 FF FF 27 03 5C 20 F3
R 00 00 00 09
T 00 01 4C
R 00 00 00 09
T 00 01 4C 72 0C 51 4C 02 4F 81
R 00 00 00 09
T 00 01 53
R 00 00 00 09
T 00 01 53 A6 01 81
R 00 00 00 09
T 00 01 56
R 00 00 00 09
T 00 01 56 72 1F 51 4C 81
R 00 00 00 09
T 00 01 5B
R 00 00 00 09
T 00 01 5B 35 CA 51 59 35 53 51 59 C6 51 4C A4 5F
R 00 00 00 09
T 00 01 68 C7 51 4C 5F
R 00 00 00 09
T 00 01 6C
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T 00 01 6C 72 0A 51 4C 08 A3 FF FF 27 03 5C 20 F3
R 00 00 00 09
T 00 01 79
R 00 00 00 09
T 00 01 79 72 0B 51 4C 03 A6 01 21
R 00 00 00 09
T 00 01 81
R 00 00 00 09
T 00 01 81 4F
R 00 00 00 09
T 00 01 82
R 00 00 00 09
T 00 01 82 35 FF 51 59 81
R 00 00 00 09
T 00 01 87
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T 00 01 87 88 6B 01 35 CA 51 59 35 53 51 59 C6
R 00 00 00 09
T 00 01 93 51 48 0D 01 27 07 AA 20 C7 51 48 20 05
R 00 00 00 09
T 00 01 A0
R 00 00 00 09
T 00 01 A0 A4 DF C7 51 48
R 00 00 00 09
T 00 01 A5
R 00 00 00 09
T 00 01 A5 35 FF 51 59 84 81
R 00 00 00 09
T 00 01 AB
R 00 00 00 09
T 00 01 AB 88 6B 01 35 CA 51 59 35 53 51 59 C6
R 00 00 00 09
T 00 01 B7 51 48 0D 01 27 07 AA 10 C7 51 48 20 05
R 00 00 00 09
T 00 01 C4
R 00 00 00 09
T 00 01 C4 A4 EF C7 51 48
R 00 00 00 09
T 00 01 C9
R 00 00 00 09
T 00 01 C9 35 FF 51 59 84 81
R 00 00 00 09
T 00 01 CF
R 00 00 00 09
T 00 01 CF 52 06 6B 06 1F 04 C6 51 48 35 CA 51 59
R 00 00 00 09
T 00 01 DC 35 53 51 59 CD 01 35 4D 26 07 4F 35 FF
R 00 00 00 09 00 08 00 09
T 00 01 E9 51 59 20 6B
R 00 00 00 09
T 00 01 ED
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T 00 01 ED 72 0D 51 48 07 1E 04 E6 03 6B 01 C5
R 00 00 00 09
T 00 01 F9
R 00 00 00 09
T 00 01 F9 0F 01
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T 00 01 FB
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T 00 01 FB 16 04 1E 04 5C 1F 02 1E 04 90 E6 02 0D
R 00 00 00 09
T 00 02 08 06 27 12 C7 51 40 16 02 90 F6 C7 51 41
R 00 00 00 09
T 00 02 15 F6 1A 01 C7 51 42 20 1D
R 00 00 00 09
T 00 02 1D
R 00 00 00 09
T 00 02 1D 89 CD 09 23 85 C7 51 40 16 02 90 F6 89
R 00 00 00 09 00 05 00 09
T 00 02 2A CD 09 23 85 C7 51 41 F6 CD 09 23 1A 01
R 00 00 00 09 00 04 00 09 00 0C 00 09
T 00 02 37 C7 51 42
R 00 00 00 09
T 00 02 3A
R 00 00 00 09
T 00 02 3A C6 51 46 72 1F 51 4C 35 FF 51 59 72 08
R 00 00 00 09
T 00 02 47 51 48 0C CD 01 5B 4D 26 03 4F 20 05
R 00 00 00 09 00 07 00 09
T 00 02 53
R 00 00 00 09
T 00 02 53 A6 01 C5
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T 00 02 56
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T 00 02 56 A6 01
R 00 00 00 09
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R 00 00 00 09
T 00 02 5B
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T 00 02 5B 90 93 6F 03 90 7F 93 6F 01 93 6F 02 81
R 00 00 00 09
T 00 02 68
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T 00 02 68 52 06 6B 06 90 93 5C 5C 1F 01 C6 51 40
R 00 00 00 09
T 00 02 75 1E 01 F7 93 5C 1F 03 C6 51 41 1E 03 F7
R 00 00 00 09
T 00 02 82 C6 51 42 6B 05 C6 51 46 93 7B 05 A4 BF
R 00 00 00 09
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R 00 00 00 09
T 00 02 9C 26 19 F6 89 CD 09 36 85 F7 1E 03 F6 CD
R 00 00 00 09 00 08 00 09
T 00 02 A9 09 36 1E 03 F7 1E 01 F6 CD 09 36 1E 01
R 00 00 00 09 00 03 00 09 00 0C 00 09
T 00 02 B6 F7
R 00 00 00 09
T 00 02 B7
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T 00 02 B7 5B 06 81
R 00 00 00 09
T 00 02 BA
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T 00 02 BA 89 C6 51 57 95 C6 51 58 97 C6 51 46 0F
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T 00 02 C7 02 5B 02 81
R 00 00 00 09
T 00 02 CB
R 00 00 00 09
T 00 02 CB 52 0A 6B 0A 1F 08 5C 1F 01 0D 0A 26 11
R 00 00 00 09
T 00 02 D8 1E 01 F6 97 43 A5 10 26 08 9F A4 EF AB
R 00 00 00 09
T 00 02 E5 0A 1E 01 F7
R 00 00 00 09
T 00 02 E9
R 00 00 00 09
T 00 02 E9 35 CA 51 59 35 53 51 59 CD 01 35 4D 26
R 00 00 00 09 00 0C 00 09
T 00 02 F6 07 4F 35 FF 51 59 20 71
R 00 00 00 09
T 00 02 FE
R 00 00 00 09
T 00 02 FE C6 51 40 1E 08 16 08 17 03 16 08 72 A9
R 00 00 00 09
T 00 03 0B 00 03 17 05 E6 02 0D 0A 27 1C C7 51 44
R 00 00 00 09
T 00 03 18 1E 01 F6 6B 07 1E 03 F6 4E A4 F0 48 1A
R 00 00 00 09
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R 00 00 00 09
T 00 03 31
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T 00 03 31 CD 09 23 C7 51 44 1E 01 F6 CD 09 23 6B
R 00 00 00 09 00 04 00 09 00 0D 00 09
T 00 03 3E 07 1E 03 F6 4E A4 F0 48 1A 07 C7 51 45
R 00 00 00 09
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R 00 00 00 09 00 07 00 09
T 00 03 54
R 00 00 00 09
T 00 03 54 72 1F 51 4C 35 FF 51 59 72 08 51 48 0C
R 00 00 00 09
T 00 03 61 CD 01 5B 4D 26 03 4F 20 05
R 00 00 00 09 00 04 00 09
T 00 03 6A
R 00 00 00 09
T 00 03 6A A6 01 C5
R 00 00 00 09
T 00 03 6D
R 00 00 00 09
T 00 03 6D A6 01
R 00 00 00 09
T 00 03 6F
R 00 00 00 09
T 00 03 6F 5B 0A 81
R 00 00 00 09
T 00 03 72
R 00 00 00 09
T 00 03 72 51 A6 01 90 F7 93 5C 5C A6 01 F7 93 5C
R 00 00 00 09
T 00 03 7F A6 01 F7 93 6F 03 81
R 00 00 00 09
T 00 03 86
R 00 00 00 09
T 00 03 86 52 06 6B 06 51 C6 51 40 93 5C 5C 1F 01
R 00 00 00 09
T 00 03 93 C6 51 44 1E 01 F7 C6 51 45 6B 03 93 1C
R 00 00 00 09
T 00 03 A0 00 03 1F 04 C6 51 46 1E 04 F7 93 5C 7B
R 00 00 00 09
T 00 03 AD 03 A4 1F F7 7B 03 A4 E0 4E A4 0F 44 90
R 00 00 00 09
T 00 03 BA F7 0D 06 26 1D 16 04 90 F6 89 CD 09 36
R 00 00 00 09 00 0E 00 09
T 00 03 C7 85 16 04 90 F7 F6 89 CD 09 36 85 F7 1E
R 00 00 00 09 00 0B 00 09
T 00 03 D4 01 F6 CD 09 36 1E 01 F7
R 00 00 00 09 00 06 00 09
T 00 03 DC
R 00 00 00 09
T 00 03 DC 5B 06 81
R 00 00 00 09
T 00 03 DF
R 00 00 00 09
T 00 03 DF 52 11 6B 11 51 C6 51 48 93 1C 00 04 1F
R 00 00 00 09
T 00 03 EC 05 35 CA 51 59 35 53 51 59 17 01 93 5C
R 00 00 00 09
T 00 03 F9 1F 03 17 07 93 1C 00 03 1F 09 93 1C
R 00 00 00 09
T 00 04 05 00 06 1F 0B 93 1C 00 05 1F 0D 1E 01 E6
R 00 00 00 09
T 00 04 12 02 6B 10 0D 11 27 47 1E 05 F6 97 A4 80
R 00 00 00 09
T 00 04 1F 1A 10 6B 0F 16 03 90 F6 6B 10 9F 48 A4
R 00 00 00 09
T 00 04 2C 80 1A 10 6B 10 16 07 90 F6 6B 06 16 09
R 00 00 00 09
T 00 04 39 90 F6 1A 06 6B 0A 9F 48 48 A4 80 1A 0A
R 00 00 00 09
T 00 04 46 6B 0A 16 0B 90 F6 6B 09 16 0D 90 F6 1A
R 00 00 00 09
T 00 04 53 09 6B 0E 9F 48 48 48 A4 80 1A 0E 20 55
R 00 00 00 09
T 00 04 60
R 00 00 00 09
T 00 04 60 7B 10 CD 09 23 6B 10 1E 05 F6 A4 80 1A
R 00 00 00 09 00 06 00 09
T 00 04 6D 10 6B 0F 1E 03 F6 CD 09 23 6B 10 1E 05
R 00 00 00 09 00 0A 00 09
T 00 04 7A F6 48 A4 80 1A 10 6B 10 1E 07 F6 CD
R 00 00 00 09
T 00 04 86 09 23 6B 08 1E 09 F6 1A 08 6B 0A 1E 05
R 00 00 00 09 00 03 00 09
T 00 04 93 F6 48 48 A4 80 1A 0A 6B 0A 1E 0B F6 CD
R 00 00 00 09
T 00 04 A0 09 23 6B 0C 1E 0D F6 1A 0C 6B 0E 1E 05
R 00 00 00 09 00 03 00 09
T 00 04 AD F6 48 48 48 A4 80 1A 0E
R 00 00 00 09
T 00 04 B5
R 00 00 00 09
T 00 04 B5 AE 51 5C 88 7B 10 F7 84 AE 51 5D 88 7B
R 00 00 00 09
T 00 04 C2 11 F7 84 AE 51 5E 88 7B 0B F7 84 C7
R 00 00 00 09
T 00 04 CE 51 5F 35 FF 51 59 5B 11 81
R 00 00 00 09
T 00 04 D7
R 00 00 00 09
T 00 04 D7 90 93 6F 03 90 7F 93 6F 01 93 6F 02 93
R 00 00 00 09
T 00 04 E4 6F 05 A6 01 90 E7 06 A6 F0 90 E7 04 81
R 00 00 00 09
T 00 04 F1
R 00 00 00 09
T 00 04 F1 52 0B 6B 0B 1F 09 C6 51 5C 6B 08 C6
R 00 00 00 09
T 00 04 FD 51 5D 6B 01 C6 51 5E 6B 02 C6 51 5F 6B
R 00 00 00 09
T 00 05 0A 03 1E 09 5C 5C 1F 04 7B 08 A4 7F 1E 04
R 00 00 00 09
T 00 05 17 F7 7B 08 A4 80 6B 08 1E 09 5C 1F 06 7B
R 00 00 00 09
T 00 05 24 01 A4 7F 1E 06 F7 7B 01 A4 80 44 1A 08
R 00 00 00 09
T 00 05 31 6B 08 16 09 7B 02 A4 3F 90 F7 1E 09 1C
R 00 00 00 09
T 00 05 3E 00 03 7B 02 A4 40 F7 7B 02 A4 80 44 44
R 00 00 00 09
T 00 05 4B 1A 08 6B 08 1E 09 1C 00 06 1F 01 7B 03
R 00 00 00 09
T 00 05 58 A4 3F 1E 01 F7 1E 09 1C 00 05 7B 03 A4
R 00 00 00 09
T 00 05 65 40 F7 7B 03 A4 80 44 44 44 1A 08 1E 09
R 00 00 00 09
T 00 05 72 1C 00 04 F7 0D 0B 26 26 90 F6 90 89 CD
R 00 00 00 09
T 00 05 7F 09 36 90 85 90 F7 1E 06 F6 CD 09 36 1E
R 00 00 00 09 00 03 00 09 00 0D 00 09
T 00 05 8C 06 F7 1E 04 F6 CD 09 36 1E 04 F7 1E 01
R 00 00 00 09 00 09 00 09
T 00 05 99 F6 CD 09 36 1E 01 F7
R 00 00 00 09 00 05 00 09
T 00 05 A0
R 00 00 00 09
T 00 05 A0 5B 0B 81
R 00 00 00 09
T 00 05 A3
R 00 00 00 09
T 00 05 A3 52 03 6B 03 5F 1F 01 35 CA 51 59 35 53
R 00 00 00 09
T 00 05 B0 51 59 C6 51 49 0D 03 27 09 AA 01 C7
R 00 00 00 09
T 00 05 BC 51 49 A6 01 20 22
R 00 00 00 09
T 00 05 C2
R 00 00 00 09
T 00 05 C2 A4 FE C7 51 49 C6 51 4C A4 01
R 00 00 00 09
T 00 05 CC
R 00 00 00 09
T 00 05 CC 1E 01 5C 27 0A 4D 26 07 1E 01 5C 1F 01
R 00 00 00 09
T 00 05 D9 20 F1
R 00 00 00 09
T 00 05 DB
R 00 00 00 09
T 00 05 DB 72 00 51 4C 02 4F C5
R 00 00 00 09
T 00 05 E2
R 00 00 00 09
T 00 05 E2 A6 01
R 00 00 00 09
T 00 05 E4
R 00 00 00 09
T 00 05 E4 35 FF 51 59 5B 03 81
R 00 00 00 09
T 00 05 EB
R 00 00 00 09
T 00 05 EB 89 6B 02 35 CA 51 59 35 53 51 59 72 0C
R 00 00 00 09
T 00 05 F8 51 4C 24 C6 51 49 AA 01 6B 01 72 11
R 00 00 00 09
T 00 06 04 51 49 9E C7 51 64 9F C7 51 65 AE 51 66
R 00 00 00 09
T 00 06 11 7B 02 F7 C6 51 49 1A 01 C7 51 49 A6 01
R 00 00 00 09
T 00 06 1E 21
R 00 00 00 09
T 00 06 1F
R 00 00 00 09
T 00 06 1F 4F
R 00 00 00 09
T 00 06 20
R 00 00 00 09
T 00 06 20 35 FF 51 59 85 81
R 00 00 00 09
T 00 06 26
R 00 00 00 09
T 00 06 26 88 6B 01 35 CA 51 59 35 53 51 59 72 15
R 00 00 00 09
T 00 06 33 51 49 C6 51 48 A4 F8 C7 51 48 C6 51 48
R 00 00 00 09
T 00 06 40 1A 01 C7 51 48 35 FF 51 59 84 81
R 00 00 00 09
T 00 06 4B
R 00 00 00 09
T 00 06 4B 35 CA 51 59 35 53 51 59 9E C7 51 54 9F
R 00 00 00 09
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R 00 00 00 09
T 00 06 60
R 00 00 00 09
T 00 06 60 89 C6 51 54 95 0F 02 C6 51 55 97 5B 02
R 00 00 00 09
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R 00 00 00 09
T 00 06 6E
R 00 00 00 09
T 00 06 6E 88 6B 01 35 CA 51 59 35 53 51 59 C6
R 00 00 00 09
T 00 06 7A 51 49 0D 01 27 09 AA 04 C7 51 49 A6 01
R 00 00 00 09
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R 00 00 00 09
T 00 06 89
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T 00 06 89 A4 FB C7 51 49 5F
R 00 00 00 09
T 00 06 8F
R 00 00 00 09
T 00 06 8F 72 04 51 4C 08 A3 FF FF 27 03 5C 20 F3
R 00 00 00 09
T 00 06 9C
R 00 00 00 09
T 00 06 9C 72 04 51 4C 02 4F C5
R 00 00 00 09
T 00 06 A3
R 00 00 00 09
T 00 06 A3 A6 01
R 00 00 00 09
T 00 06 A5
R 00 00 00 09
T 00 06 A5 35 FF 51 59 5B 01 81
R 00 00 00 09
T 00 06 AC
R 00 00 00 09
T 00 06 AC 88 97 35 CA 51 59 35 53 51 59 C6 51 4A
R 00 00 00 09
T 00 06 B9 A4 FB C7 51 4A C6 51 4A 6B 01 9F 1A 04
R 00 00 00 09
T 00 06 C6 1A 01 C7 51 4A 35 FF 51 59 84 85 84 FC
R 00 00 00 09
T 00 06 D3
R 00 00 00 09
T 00 06 D3 C6 51 4A A4 04 81
R 00 00 00 09
T 00 06 D9
R 00 00 00 09
T 00 06 D9 88 97 35 CA 51 59 35 53 51 59 C6 51 4A
R 00 00 00 09
T 00 06 E6 A4 8F C7 51 4A C6 51 4A 6B 01 9F 1A 04
R 00 00 00 09
T 00 06 F3 1A 01 C7 51 4A 35 FF 51 59 84 85 84 FC
R 00 00 00 09
T 00 07 00
R 00 00 00 09
T 00 07 00 88 6B 01 51 35 CA 51 59 35 53 51 59 72
R 00 00 00 09
T 00 07 0D 07 51 4C 0E 5F
R 00 00 00 09
T 00 07 12
R 00 00 00 09
T 00 07 12 72 07 51 4C 08 A3 FF FF 27 03 5C 20 F3
R 00 00 00 09
T 00 07 1F
R 00 00 00 09
T 00 07 1F 72 06 51 4C 0F 90 9E 1A 01 C7 51 5A 90
R 00 00 00 09
T 00 07 2C 9F C7 51 5B A6 01 21
R 00 00 00 09
T 00 07 33
R 00 00 00 09
T 00 07 33 4F
R 00 00 00 09
T 00 07 34
R 00 00 00 09
T 00 07 34 35 FF 51 59 5B 01 81
R 00 00 00 09
T 00 07 3B
R 00 00 00 09
T 00 07 3B 88 90 97 35 CA 51 59 35 53 51 59 72 03
R 00 00 00 09
T 00 07 48 51 4C 0E 5F
R 00 00 00 09
T 00 07 4C
R 00 00 00 09
T 00 07 4C 72 03 51 4C 08 A3 FF FF 27 03 5C 20 F3
R 00 00 00 09
T 00 07 59
R 00 00 00 09
T 00 07 59 72 02 51 4C 15 90 9F 1A 04 6B 01 7B 05
R 00 00 00 09
T 00 07 66 1A 01 C7 51 6A 7B 06 C7 51 6B A6 01 21
R 00 00 00 09
T 00 07 73
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R 00 00 00 09
T 00 07 74
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T 00 07 74 35 FF 51 59 1E 02 5B 06 FC
R 00 00 00 09
T 00 07 7D
R 00 00 00 09
T 00 07 7D 88 6B 01 35 CA 51 59 35 53 51 59 C6
R 00 00 00 09
T 00 07 89 51 4A 0D 01 27 07 AA 08 C7 51 4A 20 05
R 00 00 00 09
T 00 07 96
R 00 00 00 09
T 00 07 96 A4 F7 C7 51 4A
R 00 00 00 09
T 00 07 9B
R 00 00 00 09
T 00 07 9B 35 FF 51 59 84 81
R 00 00 00 09
T 00 07 A1
R 00 00 00 09
T 00 07 A1 88 6B 01 35 CA 51 59 35 53 51 59 C6
R 00 00 00 09
T 00 07 AD 51 4A 0D 01 27 07 AA 80 C7 51 4A 20 05
R 00 00 00 09
T 00 07 BA
R 00 00 00 09
T 00 07 BA A4 7F C7 51 4A
R 00 00 00 09
T 00 07 BF
R 00 00 00 09
T 00 07 BF 35 FF 51 59 84 81
R 00 00 00 09
T 00 07 C5
R 00 00 00 09
T 00 07 C5 88 97 35 CA 51 59 35 53 51 59 C6 51 6C
R 00 00 00 09
T 00 07 D2 6B 01 9F 48 0D 04 27 07 1A 01 C7 51 6C
R 00 00 00 09
T 00 07 DF 20 06
R 00 00 00 09
T 00 07 E1
R 00 00 00 09
T 00 07 E1 43 14 01 C7 51 6C
R 00 00 00 09
T 00 07 E7
R 00 00 00 09
T 00 07 E7 35 FF 51 59 84 85 84 FC
R 00 00 00 09
T 00 07 EF
R 00 00 00 09
T 00 07 EF 88 6B 01 35 CA 51 59 35 53 51 59 C6
R 00 00 00 09
T 00 07 FB 51 6D A4 E7 C7 51 6D C6 51 6D 1A 01 C7
R 00 00 00 09
T 00 08 08 51 6D 35 FF 51 59 84 81
R 00 00 00 09
T 00 08 10
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T 00 08 10 88 6B 01 35 CA 51 59 35 53 51 59 C6
R 00 00 00 09
T 00 08 1C 51 6D A4 F8 C7 51 6D C6 51 6D 1A 01 C7
R 00 00 00 09
T 00 08 29 51 6D 35 FF 51 59 84 81
R 00 00 00 09
T 00 08 31
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R 00 00 00 09
T 00 08 3D 51 6D A4 1F C7 51 6D C6 51 6D 1A 01 C7
R 00 00 00 09
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R 00 00 00 09
T 00 08 52
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T 00 08 52 88 35 CA 51 59 35 53 51 59 AE 51 6C 88
R 00 00 00 09
T 00 08 5F F6 6B 02 84 0D 04 27 07 1A 01 C7 51 6C
R 00 00 00 09
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R 00 00 00 09
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R 00 00 00 09
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R 00 00 00 09
T 00 08 74
R 00 00 00 09
T 00 08 74 35 FF 51 59 84 85 84 FC
R 00 00 00 09
T 00 08 7C
R 00 00 00 09
T 00 08 7C 52 03 6B 03 35 CA 51 59 35 53 51 59 C6
R 00 00 00 09
T 00 08 89 51 49 6B 02 9F A4 F0 88 9F A4 01 6B 02
R 00 00 00 09
T 00 08 96 84 0D 03 27 0F 1A 02 C7 51 49 C6 51 6C
R 00 00 00 09
T 00 08 A3 1A 01 C7 51 6C 20 13
R 00 00 00 09
T 00 08 AA
R 00 00 00 09
T 00 08 AA 43 14 02 C7 51 49 C6 51 6C 6B 02 7B 01
R 00 00 00 09
T 00 08 B7 43 14 02 C7 51 6C
R 00 00 00 09
T 00 08 BD
R 00 00 00 09
T 00 08 BD 35 FF 51 59 5B 03 81
R 00 00 00 09
T 00 08 C4
R 00 00 00 09
T 00 08 C4 52 06 C6 51 4C 90 97 0F 02 C6 51 4D 0F
R 00 00 00 09
T 00 08 D1 03 6B 06 61 6B 05 61 9F 14 06 02 14 05
R 00 00 00 09
T 00 08 DE 95 5D 27 03 A6 01 21
R 00 00 00 09
T 00 08 E5
R 00 00 00 09
T 00 08 E5 4F
R 00 00 00 09
T 00 08 E6
R 00 00 00 09
T 00 08 E6 5B 06 81
R 00 00 00 09
T 00 08 E9
R 00 00 00 09
T 00 08 E9 9F 43 C7 51 4D 9E 43 A4 7F C7 51 4C 81
R 00 00 00 09
T 00 08 F6
R 00 00 00 09
T 00 08 F6 88 C6 51 49 6B 01 9F 14 01 6B 01 C6
R 00 00 00 09
T 00 09 02 51 4D 54 54 54 54 89 14 02 85 0D 01 27
R 00 00 00 09
T 00 09 0F 06 4D 27 03 A6 01 21
R 00 00 00 09
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R 00 00 00 09
T 00 09 16 4F
R 00 00 00 09
T 00 09 17
R 00 00 00 09
T 00 09 17 5B 01 81
R 00 00 00 09
T 00 09 1A
R 00 00 00 09
T 00 09 1A A6 10 62 9F 43 C7 51 4D 81
R 00 00 00 09
T 00 09 23
R 00 00 00 09
T 00 09 23 5F
R 00 00 00 09
T 00 09 24
R 00 00 00 09
T 00 09 24 A1 0A 25 05 5C A0 0A 20 F7
R 00 00 00 09
T 00 09 2D
R 00 00 00 09
T 00 09 2D 58 58 58 58 89 1A 02 85 81
R 00 00 00 09
T 00 09 36
R 00 00 00 09
T 00 09 36 90 97 A4 F0 4E A4 0F 97 A6 0A 42 90 9F
R 00 00 00 09
T 00 09 43 A4 0F 89 1B 02 85 81
R 00 00 00 09

1969
firmware/STM8L15X_LD/stm8l15x_rtc.rst Normal file
View File

File diff suppressed because it is too large Load Diff

71
firmware/STM8L15X_LD/stm8l15x_rtc.sym Normal file
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@@ -0,0 +1,71 @@
ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 1
Hexadecimal [24-Bits]
Symbol Table
.__.$$$. = 002710 L
.__.ABS. = 000000 G
.__.CPU. = 000000 L
.__.H$L. = 000001 L
9 _Bcd2ToByte 000936 R
9 _ByteToBcd2 000923 R
9 _RTC_AlarmCmd 0005A3 GR
9 _RTC_AlarmStructInit 0004D7 GR
9 _RTC_AlarmSubSecondConfig 0005EB GR
9 _RTC_BypassShadowCmd 0001AB GR
9 _RTC_CalibOutputCmd 0007A1 GR
9 _RTC_CalibOutputConfig 00077D GR
9 _RTC_ClearFlag 0008E9 GR
9 _RTC_ClearITPendingBit 00091A GR
9 _RTC_DateStructInit 000372 GR
9 _RTC_DayLightSavingConfig 0006AC GR
9 _RTC_DeInit 000000 GR
9 _RTC_EnterInitMode 000135 GR
9 _RTC_ExitInitMode 000156 GR
9 _RTC_GetAlarm 0004F1 GR
9 _RTC_GetDate 000386 GR
9 _RTC_GetFlagStatus 0008C4 GR
9 _RTC_GetITStatus 0008F6 GR
9 _RTC_GetStoreOperation 0006D3 GR
9 _RTC_GetSubSecond 0002BA GR
9 _RTC_GetTime 000268 GR
9 _RTC_GetWakeUpCounter 000660 GR
9 _RTC_ITConfig 00087C GR
9 _RTC_Init 0000CB GR
9 _RTC_OutputConfig 0006D9 GR
9 _RTC_RatioCmd 000187 GR
9 _RTC_SetAlarm 0003DF GR
9 _RTC_SetDate 0002CB GR
9 _RTC_SetTime 0001CF GR
9 _RTC_SetWakeUpCounter 00064B GR
9 _RTC_SmoothCalibConfig 00073B GR
9 _RTC_StructInit 000114 GR
9 _RTC_SynchroShiftConfig 000700 GR
9 _RTC_TamperCmd 000852 GR
9 _RTC_TamperFilterConfig 0007EF GR
9 _RTC_TamperLevelConfig 0007C5 GR
9 _RTC_TamperPinsPrechargeDuration 000831 GR
9 _RTC_TamperSamplingFreqConfig 000810 GR
9 _RTC_TimeStructInit 00025B GR
9 _RTC_WaitForSynchro 00015B GR
9 _RTC_WakeUpClockConfig 000626 GR
9 _RTC_WakeUpCmd 00066E GR
9 _RTC_WriteProtectionCmd 000124 GR
ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 2
Hexadecimal [24-Bits]
Area Table
0 _CODE size 0 flags 0
1 DATA size 0 flags 0
2 INITIALIZED size 0 flags 0
3 DABS size 0 flags 8
4 HOME size 0 flags 0
5 GSINIT size 0 flags 0
6 GSFINAL size 0 flags 0
7 CONST size 0 flags 0
8 INITIALIZER size 0 flags 0
9 CODE size 94A flags 0
A CABS size 0 flags 8

899
firmware/STM8L15X_LD/stm8l15x_usart.asm Normal file
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@@ -0,0 +1,899 @@
;--------------------------------------------------------
; File Created by SDCC : free open source ISO C Compiler
; Version 4.5.0 #15242 (Linux)
;--------------------------------------------------------
.module stm8l15x_usart
;--------------------------------------------------------
; Public variables in this module
;--------------------------------------------------------
.globl _CLK_GetClockFreq
.globl _USART_DeInit
.globl _USART_Init
.globl _USART_ClockInit
.globl _USART_Cmd
.globl _USART_SetPrescaler
.globl _USART_SendBreak
.globl _USART_ReceiveData8
.globl _USART_ReceiveData9
.globl _USART_SendData8
.globl _USART_SendData9
.globl _USART_ReceiverWakeUpCmd
.globl _USART_SetAddress
.globl _USART_WakeUpConfig
.globl _USART_HalfDuplexCmd
.globl _USART_SmartCardCmd
.globl _USART_SmartCardNACKCmd
.globl _USART_SetGuardTime
.globl _USART_IrDAConfig
.globl _USART_IrDACmd
.globl _USART_DMACmd
.globl _USART_ITConfig
.globl _USART_GetFlagStatus
.globl _USART_ClearFlag
.globl _USART_GetITStatus
.globl _USART_ClearITPendingBit
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area DATA
;--------------------------------------------------------
; ram data
;--------------------------------------------------------
.area INITIALIZED
;--------------------------------------------------------
; absolute external ram data
;--------------------------------------------------------
.area DABS (ABS)
; default segment ordering for linker
.area HOME
.area GSINIT
.area GSFINAL
.area CONST
.area INITIALIZER
.area CODE
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area HOME
.area GSINIT
.area GSFINAL
.area GSINIT
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area HOME
.area HOME
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area CODE
; ../inc/stm8l151x/src/stm8l15x_usart.c: 148: void USART_DeInit(USART_TypeDef* USARTx)
; -----------------------------------------
; function USART_DeInit
; -----------------------------------------
_USART_DeInit:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 154: (void) USARTx->DR;
ldw y, x
ld a, (0x1, x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 156: USARTx->BRR2 = USART_BRR2_RESET_VALUE; /* Set USART_BRR2 to reset value 0x00 */
ldw x, y
clr (0x0003, x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 157: USARTx->BRR1 = USART_BRR1_RESET_VALUE; /* Set USART_BRR1 to reset value 0x00 */
ldw x, y
clr (0x02, x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 159: USARTx->CR1 = USART_CR1_RESET_VALUE; /* Set USART_CR1 to reset value 0x00 */
ldw x, y
clr (0x0004, x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 160: USARTx->CR2 = USART_CR2_RESET_VALUE; /* Set USART_CR2 to reset value 0x00 */
ldw x, y
clr (0x0005, x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 161: USARTx->CR3 = USART_CR3_RESET_VALUE; /* Set USART_CR3 to reset value 0x00 */
ldw x, y
clr (0x0006, x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 162: USARTx->CR4 = USART_CR4_RESET_VALUE; /* Set USART_CR4 to reset value 0x00 */
ldw x, y
clr (0x0007, x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 163: }
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 192: void USART_Init(USART_TypeDef* USARTx, uint32_t BaudRate, USART_WordLength_TypeDef
; -----------------------------------------
; function USART_Init
; -----------------------------------------
_USART_Init:
sub sp, #11
; ../inc/stm8l151x/src/stm8l15x_usart.c: 210: USARTx->CR1 &= (uint8_t)(~(USART_CR1_PCEN | USART_CR1_PS | USART_CR1_M));
ldw (0x0a, sp), x
addw x, #0x0004
ld a, (x)
and a, #0xe9
ld (0x09, sp), a
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 213: USARTx->CR1 |= (uint8_t)((uint8_t)USART_WordLength | (uint8_t)USART_Parity);
ld a, (0x12, sp)
or a, (0x14, sp)
or a, (0x09, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 216: USARTx->CR3 &= (uint8_t)(~USART_CR3_STOP);
ldw x, (0x0a, sp)
addw x, #0x0006
ld a, (x)
and a, #0xcf
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 218: USARTx->CR3 |= (uint8_t)USART_StopBits;
or a, (0x13, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 221: USARTx->BRR1 &= (uint8_t)(~USART_BRR1_DIVM);
ldw x, (0x0a, sp)
incw x
incw x
ldw (0x01, sp), x
ld a, (x)
ldw x, (0x01, sp)
clr (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 223: USARTx->BRR2 &= (uint8_t)(~USART_BRR2_DIVM);
ldw x, (0x0a, sp)
addw x, #0x0003
ldw (0x03, sp), x
ld a, (x)
and a, #0x0f
ldw x, (0x03, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 225: USARTx->BRR2 &= (uint8_t)(~USART_BRR2_DIVF);
ldw x, (0x03, sp)
clr (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 227: BaudRate_Mantissa = (uint32_t)(CLK_GetClockFreq() / BaudRate );
call _CLK_GetClockFreq
ldw (0x08, sp), x
ldw x, (0x10, sp)
pushw x
ldw x, (0x10, sp)
pushw x
ldw x, (0x0c, sp)
pushw x
pushw y
; ../inc/stm8l151x/src/stm8l15x_usart.c: 229: USARTx->BRR2 = (uint8_t)((BaudRate_Mantissa >> (uint8_t)8) & (uint8_t)0xF0);
call __divulong
addw sp, #8
ldw (0x05, sp), y
ld a, xh
and a, #0xf0
ld (0x09, sp), a
ldw y, (0x03, sp)
ld a, (0x09, sp)
ld (y), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 231: USARTx->BRR2 |= (uint8_t)(BaudRate_Mantissa & (uint8_t)0x0F);
ld a, xl
and a, #0x0f
or a, (0x09, sp)
ldw y, (0x03, sp)
ld (y), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 233: USARTx->BRR1 = (uint8_t)(BaudRate_Mantissa >> (uint8_t)4);
ld a, #0x10
div x, a
ld a, xl
ldw x, (0x01, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 236: USARTx->CR2 &= (uint8_t)~(USART_CR2_TEN | USART_CR2_REN);
ldw x, (0x0a, sp)
addw x, #0x0005
ld a, (x)
and a, #0xf3
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 238: USARTx->CR2 |= (uint8_t)USART_Mode;
or a, (0x15, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 239: }
ldw x, (12, sp)
addw sp, #21
jp (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 264: void USART_ClockInit(USART_TypeDef* USARTx, USART_Clock_TypeDef USART_Clock,
; -----------------------------------------
; function USART_ClockInit
; -----------------------------------------
_USART_ClockInit:
sub sp, #5
ld (0x05, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 275: USARTx->CR3 &= (uint8_t)~(USART_CR3_CPOL | USART_CR3_CPHA | USART_CR3_LBCL);
addw x, #0x0006
ldw (0x01, sp), x
ld a, (x)
and a, #0xf8
ld (0x03, sp), a
ldw x, (0x01, sp)
ld a, (0x03, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 277: USARTx->CR3 |= (uint8_t)((uint8_t)((uint8_t)(USART_CPOL | (uint8_t)USART_CPHA ) | USART_LastBit));
ld a, (0x08, sp)
or a, (0x09, sp)
ld (0x04, sp), a
ld a, (0x0a, sp)
or a, (0x04, sp)
or a, (0x03, sp)
ldw x, (0x01, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 275: USARTx->CR3 &= (uint8_t)~(USART_CR3_CPOL | USART_CR3_CPHA | USART_CR3_LBCL);
ldw x, (0x01, sp)
ld a, (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 279: if (USART_Clock != USART_Clock_Disable)
tnz (0x05, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 281: USARTx->CR3 |= (uint8_t)(USART_CR3_CLKEN); /* Set the Clock Enable bit */
or a, #0x08
ldw x, (0x01, sp)
ld (x), a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 285: USARTx->CR3 &= (uint8_t)(~USART_CR3_CLKEN); /* Clear the Clock Enable bit */
and a, #0xf7
ldw x, (0x01, sp)
ld (x), a
00104$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 287: }
ldw x, (6, sp)
addw sp, #10
jp (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 296: void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
; -----------------------------------------
; function USART_Cmd
; -----------------------------------------
_USART_Cmd:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 300: USARTx->CR1 &= (uint8_t)(~USART_CR1_USARTD); /**< USART Enable */
addw x, #0x0004
ld a, (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 298: if (NewState != DISABLE)
tnz (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 300: USARTx->CR1 &= (uint8_t)(~USART_CR1_USARTD); /**< USART Enable */
and a, #0xdf
ld (x), a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 304: USARTx->CR1 |= USART_CR1_USARTD; /**< USART Disable (for low power consumption) */
or a, #0x20
ld (x), a
00104$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 306: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 329: void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
; -----------------------------------------
; function USART_SetPrescaler
; -----------------------------------------
_USART_SetPrescaler:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 332: USARTx->PSCR = USART_Prescaler;
addw x, #0x000a
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 333: }
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 340: void USART_SendBreak(USART_TypeDef* USARTx)
; -----------------------------------------
; function USART_SendBreak
; -----------------------------------------
_USART_SendBreak:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 342: USARTx->CR2 |= USART_CR2_SBK;
addw x, #0x0005
ld a, (x)
or a, #0x01
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 343: }
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 382: uint8_t USART_ReceiveData8(USART_TypeDef* USARTx)
; -----------------------------------------
; function USART_ReceiveData8
; -----------------------------------------
_USART_ReceiveData8:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 384: return USARTx->DR;
ld a, (0x1, x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 385: }
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 392: uint16_t USART_ReceiveData9(USART_TypeDef* USARTx)
; -----------------------------------------
; function USART_ReceiveData9
; -----------------------------------------
_USART_ReceiveData9:
pushw x
; ../inc/stm8l151x/src/stm8l15x_usart.c: 396: temp = ((uint16_t)(((uint16_t)((uint16_t)USARTx->CR1 & (uint16_t)USART_CR1_R8)) << 1));
ldw y, x
ld a, (0x4, x)
and a, #0x80
ld xl, a
clr a
ld xh, a
sllw x
ldw (0x01, sp), x
; ../inc/stm8l151x/src/stm8l15x_usart.c: 397: return (uint16_t)( ((uint16_t)((uint16_t)USARTx->DR) | temp) & ((uint16_t)0x01FF));
ld a, (0x1, y)
or a, (0x02, sp)
ld xl, a
ld a, (0x01, sp)
and a, #0x01
ld xh, a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 398: }
addw sp, #2
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 405: void USART_SendData8(USART_TypeDef* USARTx, uint8_t Data)
; -----------------------------------------
; function USART_SendData8
; -----------------------------------------
_USART_SendData8:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 408: USARTx->DR = Data;
incw x
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 409: }
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 418: void USART_SendData9(USART_TypeDef* USARTx, uint16_t Data)
; -----------------------------------------
; function USART_SendData9
; -----------------------------------------
_USART_SendData9:
sub sp, #3
; ../inc/stm8l151x/src/stm8l15x_usart.c: 423: USARTx->CR1 &= ((uint8_t)~USART_CR1_T8);
ldw (0x02, sp), x
addw x, #0x0004
ld a, (x)
and a, #0xbf
ld (0x01, sp), a
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 426: USARTx->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & USART_CR1_T8);
ldw y, (0x06, sp)
srlw y
srlw y
ld a, yl
and a, #0x40
or a, (0x01, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 429: USARTx->DR = (uint8_t)(Data);
ldw x, (0x02, sp)
incw x
ld a, (0x07, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 430: }
ldw x, (4, sp)
addw sp, #7
jp (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 473: void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
; -----------------------------------------
; function USART_ReceiverWakeUpCmd
; -----------------------------------------
_USART_ReceiverWakeUpCmd:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 480: USARTx->CR2 |= USART_CR2_RWU;
addw x, #0x0005
ld a, (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 477: if (NewState != DISABLE)
tnz (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 480: USARTx->CR2 |= USART_CR2_RWU;
or a, #0x02
ld (x), a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 485: USARTx->CR2 &= ((uint8_t)~USART_CR2_RWU);
and a, #0xfd
ld (x), a
00104$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 487: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 496: void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
; -----------------------------------------
; function USART_SetAddress
; -----------------------------------------
_USART_SetAddress:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 502: USARTx->CR4 &= ((uint8_t)~USART_CR4_ADD);
addw x, #0x0007
ld a, (x)
and a, #0xf0
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 504: USARTx->CR4 |= USART_Address;
or a, (0x01, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 505: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 515: void USART_WakeUpConfig(USART_TypeDef* USARTx, USART_WakeUp_TypeDef USART_WakeUp)
; -----------------------------------------
; function USART_WakeUpConfig
; -----------------------------------------
_USART_WakeUpConfig:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 519: USARTx->CR1 &= ((uint8_t)~USART_CR1_WAKE);
addw x, #0x0004
ld a, (x)
and a, #0xf7
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 520: USARTx->CR1 |= (uint8_t)USART_WakeUp;
or a, (0x01, sp)
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 521: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 566: void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
; -----------------------------------------
; function USART_HalfDuplexCmd
; -----------------------------------------
_USART_HalfDuplexCmd:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 572: USARTx->CR5 |= USART_CR5_HDSEL; /**< USART Half Duplex Enable */
addw x, #0x0008
ld a, (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 570: if (NewState != DISABLE)
tnz (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 572: USARTx->CR5 |= USART_CR5_HDSEL; /**< USART Half Duplex Enable */
or a, #0x08
ld (x), a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 576: USARTx->CR5 &= (uint8_t)~USART_CR5_HDSEL; /**< USART Half Duplex Disable */
and a, #0xf7
ld (x), a
00104$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 578: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 644: void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
; -----------------------------------------
; function USART_SmartCardCmd
; -----------------------------------------
_USART_SmartCardCmd:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 651: USARTx->CR5 |= USART_CR5_SCEN;
addw x, #0x0008
ld a, (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 648: if (NewState != DISABLE)
tnz (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 651: USARTx->CR5 |= USART_CR5_SCEN;
or a, #0x20
ld (x), a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 656: USARTx->CR5 &= ((uint8_t)(~USART_CR5_SCEN));
and a, #0xdf
ld (x), a
00104$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 658: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 667: void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
; -----------------------------------------
; function USART_SmartCardNACKCmd
; -----------------------------------------
_USART_SmartCardNACKCmd:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 674: USARTx->CR5 |= USART_CR5_NACK;
addw x, #0x0008
ld a, (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 671: if (NewState != DISABLE)
tnz (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 674: USARTx->CR5 |= USART_CR5_NACK;
or a, #0x10
ld (x), a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 679: USARTx->CR5 &= ((uint8_t)~(USART_CR5_NACK));
and a, #0xef
ld (x), a
00104$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 681: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 690: void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
; -----------------------------------------
; function USART_SetGuardTime
; -----------------------------------------
_USART_SetGuardTime:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 693: USARTx->GTR = USART_GuardTime;
addw x, #0x0009
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 694: }
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 751: void USART_IrDAConfig(USART_TypeDef* USARTx, USART_IrDAMode_TypeDef USART_IrDAMode)
; -----------------------------------------
; function USART_IrDAConfig
; -----------------------------------------
_USART_IrDAConfig:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 757: USARTx->CR5 |= USART_CR5_IRLP;
addw x, #0x0008
ld a, (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 755: if (USART_IrDAMode != USART_IrDAMode_Normal)
tnz (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 757: USARTx->CR5 |= USART_CR5_IRLP;
or a, #0x04
ld (x), a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 761: USARTx->CR5 &= ((uint8_t)~USART_CR5_IRLP);
and a, #0xfb
ld (x), a
00104$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 763: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 772: void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
; -----------------------------------------
; function USART_IrDACmd
; -----------------------------------------
_USART_IrDACmd:
push a
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 781: USARTx->CR5 |= USART_CR5_IREN;
addw x, #0x0008
ld a, (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 778: if (NewState != DISABLE)
tnz (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 781: USARTx->CR5 |= USART_CR5_IREN;
or a, #0x02
ld (x), a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 786: USARTx->CR5 &= ((uint8_t)~USART_CR5_IREN);
and a, #0xfd
ld (x), a
00104$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 788: }
pop a
ret
; ../inc/stm8l151x/src/stm8l15x_usart.c: 818: void USART_DMACmd(USART_TypeDef* USARTx, USART_DMAReq_TypeDef USART_DMAReq,
; -----------------------------------------
; function USART_DMACmd
; -----------------------------------------
_USART_DMACmd:
push a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 829: USARTx->CR5 |= (uint8_t) USART_DMAReq;
addw x, #0x0008
push a
ld a, (x)
ld (0x02, sp), a
pop a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 825: if (NewState != DISABLE)
tnz (0x04, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 829: USARTx->CR5 |= (uint8_t) USART_DMAReq;
or a, (0x01, sp)
ld (x), a
jra 00104$
00102$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 835: USARTx->CR5 &= (uint8_t)~USART_DMAReq;
cpl a
and a, (0x01, sp)
ld (x), a
00104$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 837: }
pop a
popw x
pop a
jp (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 939: void USART_ITConfig(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT, FunctionalState NewState)
; -----------------------------------------
; function USART_ITConfig
; -----------------------------------------
_USART_ITConfig:
sub sp, #9
ldw (0x08, sp), x
; ../inc/stm8l151x/src/stm8l15x_usart.c: 946: usartreg = (uint8_t)((uint16_t)USART_IT >> 0x08);
ldw x, (0x0c, sp)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 948: itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)USART_IT & (uint8_t)0x0F));
ld a, (0x0d, sp)
and a, #0x0f
push a
ld a, #0x01
ld (0x08, sp), a
pop a
tnz a
jreq 00154$
00153$:
sll (0x07, sp)
dec a
jrne 00153$
00154$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 953: if (usartreg == 0x01)
ld a, xh
dec a
jrne 00156$
ld a, #0x01
ld (0x01, sp), a
.byte 0xc5
00156$:
clr (0x01, sp)
00157$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 955: USARTx->CR1 |= itpos;
ldw y, (0x08, sp)
addw y, #0x0004
ldw (0x02, sp), y
; ../inc/stm8l151x/src/stm8l15x_usart.c: 957: else if (usartreg == 0x05)
ld a, xh
sub a, #0x05
jrne 00159$
inc a
ld (0x04, sp), a
.byte 0xc5
00159$:
clr (0x04, sp)
00160$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 959: USARTx->CR5 |= itpos;
ldw x, (0x08, sp)
addw x, #0x0008
ldw (0x05, sp), x
; ../inc/stm8l151x/src/stm8l15x_usart.c: 964: USARTx->CR2 |= itpos;
ldw x, (0x08, sp)
addw x, #0x0005
; ../inc/stm8l151x/src/stm8l15x_usart.c: 950: if (NewState != DISABLE)
tnz (0x0e, sp)
jreq 00114$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 953: if (usartreg == 0x01)
tnz (0x01, sp)
jreq 00105$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 955: USARTx->CR1 |= itpos;
ldw x, (0x02, sp)
ld a, (x)
or a, (0x07, sp)
ldw x, (0x02, sp)
ld (x), a
jra 00116$
00105$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 957: else if (usartreg == 0x05)
tnz (0x04, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 959: USARTx->CR5 |= itpos;
ldw x, (0x05, sp)
ld a, (x)
or a, (0x07, sp)
ldw x, (0x05, sp)
ld (x), a
jra 00116$
00102$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 964: USARTx->CR2 |= itpos;
ld a, (x)
or a, (0x07, sp)
ld (x), a
jra 00116$
00114$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 972: USARTx->CR1 &= (uint8_t)(~itpos);
cpl (0x07, sp)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 970: if (usartreg == 0x01)
tnz (0x01, sp)
jreq 00111$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 972: USARTx->CR1 &= (uint8_t)(~itpos);
ldw x, (0x02, sp)
ld a, (x)
and a, (0x07, sp)
ldw x, (0x02, sp)
ld (x), a
jra 00116$
00111$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 974: else if (usartreg == 0x05)
tnz (0x04, sp)
jreq 00108$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 976: USARTx->CR5 &= (uint8_t)(~itpos);
ldw x, (0x05, sp)
ld a, (x)
and a, (0x07, sp)
ldw x, (0x05, sp)
ld (x), a
jra 00116$
00108$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 981: USARTx->CR2 &= (uint8_t)(~itpos);
ld a, (x)
and a, (0x07, sp)
ld (x), a
00116$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 984: }
ldw x, (10, sp)
addw sp, #14
jp (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1002: FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG)
; -----------------------------------------
; function USART_GetFlagStatus
; -----------------------------------------
_USART_GetFlagStatus:
push a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1009: if (USART_FLAG == USART_FLAG_SBK)
ldw y, (0x04, sp)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1011: if ((USARTx->CR2 & (uint8_t)USART_FLAG) != (uint8_t)0x00)
ld a, (0x05, sp)
ld (0x01, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1009: if (USART_FLAG == USART_FLAG_SBK)
cpw y, #0x0101
jrne 00108$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1011: if ((USARTx->CR2 & (uint8_t)USART_FLAG) != (uint8_t)0x00)
ld a, (0x5, x)
and a, (0x01, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1014: status = SET;
ld a, #0x01
jra 00109$
00102$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1019: status = RESET;
clr a
jra 00109$
00108$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1024: if ((USARTx->SR & (uint8_t)USART_FLAG) != (uint8_t)0x00)
ld a, (x)
and a, (0x01, sp)
jreq 00105$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1027: status = SET;
ld a, #0x01
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1032: status = RESET;
.byte 0x21
00105$:
clr a
00109$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1036: return status;
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1037: }
ldw x, (2, sp)
addw sp, #5
jp (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1060: void USART_ClearFlag(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG)
; -----------------------------------------
; function USART_ClearFlag
; -----------------------------------------
_USART_ClearFlag:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1065: USARTx->SR = (uint8_t)((uint16_t)~((uint16_t)USART_FLAG));
ldw y, (0x03, sp)
cplw y
ld a, yl
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1066: }
ldw x, (1, sp)
addw sp, #4
jp (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1083: ITStatus USART_GetITStatus(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT)
; -----------------------------------------
; function USART_GetITStatus
; -----------------------------------------
_USART_GetITStatus:
sub sp, #9
ldw (0x08, sp), x
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1096: itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)USART_IT & (uint8_t)0x0F));
ld a, (0x0d, sp)
ld xl, a
and a, #0x0f
push a
ld a, #0x01
ld (0x04, sp), a
pop a
tnz a
jreq 00179$
00178$:
sll (0x03, sp)
dec a
jrne 00178$
00179$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1098: itmask1 = (uint8_t)((uint8_t)USART_IT >> (uint8_t)4);
ld a, xl
swap a
and a, #0x0f
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1100: itmask2 = (uint8_t)((uint8_t)1 << itmask1);
push a
ld a, #0x01
ld (0x08, sp), a
pop a
tnz a
jreq 00181$
00180$:
sll (0x07, sp)
dec a
jrne 00180$
00181$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1103: if (USART_IT == USART_IT_PE)
ldw y, (0x0c, sp)
ldw (0x01, sp), y
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1109: if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
ldw y, (0x08, sp)
ldw (0x04, sp), y
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1103: if (USART_IT == USART_IT_PE)
ldw x, (0x01, sp)
cpw x, #0x0100
jrne 00118$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1106: enablestatus = (uint8_t)((uint8_t)USARTx->CR1 & itmask2);
ldw y, (0x08, sp)
ldw (0x01, sp), y
ldw x, y
ld a, (0x4, x)
and a, (0x07, sp)
ld (0x07, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1109: if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
ldw x, (0x04, sp)
ld a, (x)
and a, (0x03, sp)
jreq 00102$
tnz (0x07, sp)
jreq 00102$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1112: pendingbitstatus = SET;
ld a, #0x01
jra 00119$
00102$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1117: pendingbitstatus = RESET;
clr a
jra 00119$
00118$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1124: enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
ldw x, (0x08, sp)
ld a, (0x5, x)
and a, (0x07, sp)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1121: else if (USART_IT == USART_IT_OR)
ldw x, (0x01, sp)
cpw x, #0x0235
jrne 00115$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1124: enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
ld (0x06, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1127: temp = (uint8_t)(USARTx->CR5 & USART_CR5_EIE);
ldw x, (0x08, sp)
ld a, (0x8, x)
and a, #0x01
ld (0x07, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1129: if (( (USARTx->SR & itpos) != 0x00) && ((enablestatus || temp)))
ldw x, (0x04, sp)
ld a, (x)
and a, (0x03, sp)
jreq 00106$
tnz (0x06, sp)
jrne 00105$
tnz (0x07, sp)
jreq 00106$
00105$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1132: pendingbitstatus = SET;
ld a, #0x01
jra 00119$
00106$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1137: pendingbitstatus = RESET;
clr a
jra 00119$
00115$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1144: enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
ld (0x07, sp), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1146: if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
ldw x, (0x04, sp)
ld a, (x)
and a, (0x03, sp)
jreq 00111$
tnz (0x07, sp)
jreq 00111$
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1149: pendingbitstatus = SET;
ld a, #0x01
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1154: pendingbitstatus = RESET;
.byte 0x21
00111$:
clr a
00119$:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1159: return pendingbitstatus;
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1160: }
ldw x, (10, sp)
addw sp, #13
jp (x)
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1183: void USART_ClearITPendingBit(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT)
; -----------------------------------------
; function USART_ClearITPendingBit
; -----------------------------------------
_USART_ClearITPendingBit:
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1188: USARTx->SR &= (uint8_t)(~USART_SR_TC);
ld a, (x)
and a, #0xbf
ld (x), a
; ../inc/stm8l151x/src/stm8l15x_usart.c: 1189: }
ldw x, (1, sp)
addw sp, #4
jp (x)
.area CODE
.area CONST
.area INITIALIZER
.area CABS (ABS)

899
firmware/STM8L15X_LD/stm8l15x_usart.lst Normal file
View File

@@ -0,0 +1,899 @@
1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ISO C Compiler
3 ; Version 4.5.0 #15242 (Linux)
4 ;--------------------------------------------------------
5 .module stm8l15x_usart
6
7 ;--------------------------------------------------------
8 ; Public variables in this module
9 ;--------------------------------------------------------
10 .globl _CLK_GetClockFreq
11 .globl _USART_DeInit
12 .globl _USART_Init
13 .globl _USART_ClockInit
14 .globl _USART_Cmd
15 .globl _USART_SetPrescaler
16 .globl _USART_SendBreak
17 .globl _USART_ReceiveData8
18 .globl _USART_ReceiveData9
19 .globl _USART_SendData8
20 .globl _USART_SendData9
21 .globl _USART_ReceiverWakeUpCmd
22 .globl _USART_SetAddress
23 .globl _USART_WakeUpConfig
24 .globl _USART_HalfDuplexCmd
25 .globl _USART_SmartCardCmd
26 .globl _USART_SmartCardNACKCmd
27 .globl _USART_SetGuardTime
28 .globl _USART_IrDAConfig
29 .globl _USART_IrDACmd
30 .globl _USART_DMACmd
31 .globl _USART_ITConfig
32 .globl _USART_GetFlagStatus
33 .globl _USART_ClearFlag
34 .globl _USART_GetITStatus
35 .globl _USART_ClearITPendingBit
36 ;--------------------------------------------------------
37 ; ram data
38 ;--------------------------------------------------------
39 .area DATA
40 ;--------------------------------------------------------
41 ; ram data
42 ;--------------------------------------------------------
43 .area INITIALIZED
44 ;--------------------------------------------------------
45 ; absolute external ram data
46 ;--------------------------------------------------------
47 .area DABS (ABS)
48
49 ; default segment ordering for linker
50 .area HOME
51 .area GSINIT
52 .area GSFINAL
53 .area CONST
54 .area INITIALIZER
55 .area CODE
56
57 ;--------------------------------------------------------
58 ; global & static initialisations
59 ;--------------------------------------------------------
60 .area HOME
61 .area GSINIT
62 .area GSFINAL
63 .area GSINIT
64 ;--------------------------------------------------------
65 ; Home
66 ;--------------------------------------------------------
67 .area HOME
68 .area HOME
69 ;--------------------------------------------------------
70 ; code
71 ;--------------------------------------------------------
72 .area CODE
73 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 148: void USART_DeInit(USART_TypeDef* USARTx)
74 ; -----------------------------------------
75 ; function USART_DeInit
76 ; -----------------------------------------
000000 77 _USART_DeInit:
78 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 154: (void) USARTx->DR;
000000 90 93 [ 1] 79 ldw y, x
000002 E6 01 [ 1] 80 ld a, (0x1, x)
81 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 156: USARTx->BRR2 = USART_BRR2_RESET_VALUE; /* Set USART_BRR2 to reset value 0x00 */
000004 93 [ 1] 82 ldw x, y
000005 6F 03 [ 1] 83 clr (0x0003, x)
84 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 157: USARTx->BRR1 = USART_BRR1_RESET_VALUE; /* Set USART_BRR1 to reset value 0x00 */
000007 93 [ 1] 85 ldw x, y
000008 6F 02 [ 1] 86 clr (0x02, x)
87 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 159: USARTx->CR1 = USART_CR1_RESET_VALUE; /* Set USART_CR1 to reset value 0x00 */
00000A 93 [ 1] 88 ldw x, y
00000B 6F 04 [ 1] 89 clr (0x0004, x)
90 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 160: USARTx->CR2 = USART_CR2_RESET_VALUE; /* Set USART_CR2 to reset value 0x00 */
00000D 93 [ 1] 91 ldw x, y
00000E 6F 05 [ 1] 92 clr (0x0005, x)
93 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 161: USARTx->CR3 = USART_CR3_RESET_VALUE; /* Set USART_CR3 to reset value 0x00 */
000010 93 [ 1] 94 ldw x, y
000011 6F 06 [ 1] 95 clr (0x0006, x)
96 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 162: USARTx->CR4 = USART_CR4_RESET_VALUE; /* Set USART_CR4 to reset value 0x00 */
000013 93 [ 1] 97 ldw x, y
000014 6F 07 [ 1] 98 clr (0x0007, x)
99 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 163: }
000016 81 [ 4] 100 ret
101 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 192: void USART_Init(USART_TypeDef* USARTx, uint32_t BaudRate, USART_WordLength_TypeDef
102 ; -----------------------------------------
103 ; function USART_Init
104 ; -----------------------------------------
000017 105 _USART_Init:
000017 52 0B [ 2] 106 sub sp, #11
107 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 210: USARTx->CR1 &= (uint8_t)(~(USART_CR1_PCEN | USART_CR1_PS | USART_CR1_M));
000019 1F 0A [ 2] 108 ldw (0x0a, sp), x
00001B 1C 00 04 [ 2] 109 addw x, #0x0004
00001E F6 [ 1] 110 ld a, (x)
00001F A4 E9 [ 1] 111 and a, #0xe9
000021 6B 09 [ 1] 112 ld (0x09, sp), a
000023 F7 [ 1] 113 ld (x), a
114 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 213: USARTx->CR1 |= (uint8_t)((uint8_t)USART_WordLength | (uint8_t)USART_Parity);
000024 7B 12 [ 1] 115 ld a, (0x12, sp)
000026 1A 14 [ 1] 116 or a, (0x14, sp)
000028 1A 09 [ 1] 117 or a, (0x09, sp)
00002A F7 [ 1] 118 ld (x), a
119 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 216: USARTx->CR3 &= (uint8_t)(~USART_CR3_STOP);
00002B 1E 0A [ 2] 120 ldw x, (0x0a, sp)
00002D 1C 00 06 [ 2] 121 addw x, #0x0006
000030 F6 [ 1] 122 ld a, (x)
000031 A4 CF [ 1] 123 and a, #0xcf
000033 F7 [ 1] 124 ld (x), a
125 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 218: USARTx->CR3 |= (uint8_t)USART_StopBits;
000034 1A 13 [ 1] 126 or a, (0x13, sp)
000036 F7 [ 1] 127 ld (x), a
128 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 221: USARTx->BRR1 &= (uint8_t)(~USART_BRR1_DIVM);
000037 1E 0A [ 2] 129 ldw x, (0x0a, sp)
000039 5C [ 1] 130 incw x
00003A 5C [ 1] 131 incw x
00003B 1F 01 [ 2] 132 ldw (0x01, sp), x
00003D F6 [ 1] 133 ld a, (x)
00003E 1E 01 [ 2] 134 ldw x, (0x01, sp)
000040 7F [ 1] 135 clr (x)
136 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 223: USARTx->BRR2 &= (uint8_t)(~USART_BRR2_DIVM);
000041 1E 0A [ 2] 137 ldw x, (0x0a, sp)
000043 1C 00 03 [ 2] 138 addw x, #0x0003
000046 1F 03 [ 2] 139 ldw (0x03, sp), x
000048 F6 [ 1] 140 ld a, (x)
000049 A4 0F [ 1] 141 and a, #0x0f
00004B 1E 03 [ 2] 142 ldw x, (0x03, sp)
00004D F7 [ 1] 143 ld (x), a
144 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 225: USARTx->BRR2 &= (uint8_t)(~USART_BRR2_DIVF);
00004E 1E 03 [ 2] 145 ldw x, (0x03, sp)
000050 7F [ 1] 146 clr (x)
147 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 227: BaudRate_Mantissa = (uint32_t)(CLK_GetClockFreq() / BaudRate );
000051 CDr00r00 [ 4] 148 call _CLK_GetClockFreq
000054 1F 08 [ 2] 149 ldw (0x08, sp), x
000056 1E 10 [ 2] 150 ldw x, (0x10, sp)
000058 89 [ 2] 151 pushw x
000059 1E 10 [ 2] 152 ldw x, (0x10, sp)
00005B 89 [ 2] 153 pushw x
00005C 1E 0C [ 2] 154 ldw x, (0x0c, sp)
00005E 89 [ 2] 155 pushw x
00005F 90 89 [ 2] 156 pushw y
157 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 229: USARTx->BRR2 = (uint8_t)((BaudRate_Mantissa >> (uint8_t)8) & (uint8_t)0xF0);
000061 CDr00r00 [ 4] 158 call __divulong
000064 5B 08 [ 2] 159 addw sp, #8
000066 17 05 [ 2] 160 ldw (0x05, sp), y
000068 9E [ 1] 161 ld a, xh
000069 A4 F0 [ 1] 162 and a, #0xf0
00006B 6B 09 [ 1] 163 ld (0x09, sp), a
00006D 16 03 [ 2] 164 ldw y, (0x03, sp)
00006F 7B 09 [ 1] 165 ld a, (0x09, sp)
000071 90 F7 [ 1] 166 ld (y), a
167 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 231: USARTx->BRR2 |= (uint8_t)(BaudRate_Mantissa & (uint8_t)0x0F);
000073 9F [ 1] 168 ld a, xl
000074 A4 0F [ 1] 169 and a, #0x0f
000076 1A 09 [ 1] 170 or a, (0x09, sp)
000078 16 03 [ 2] 171 ldw y, (0x03, sp)
00007A 90 F7 [ 1] 172 ld (y), a
173 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 233: USARTx->BRR1 = (uint8_t)(BaudRate_Mantissa >> (uint8_t)4);
00007C A6 10 [ 1] 174 ld a, #0x10
00007E 62 [ 2] 175 div x, a
00007F 9F [ 1] 176 ld a, xl
000080 1E 01 [ 2] 177 ldw x, (0x01, sp)
000082 F7 [ 1] 178 ld (x), a
179 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 236: USARTx->CR2 &= (uint8_t)~(USART_CR2_TEN | USART_CR2_REN);
000083 1E 0A [ 2] 180 ldw x, (0x0a, sp)
000085 1C 00 05 [ 2] 181 addw x, #0x0005
000088 F6 [ 1] 182 ld a, (x)
000089 A4 F3 [ 1] 183 and a, #0xf3
00008B F7 [ 1] 184 ld (x), a
185 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 238: USARTx->CR2 |= (uint8_t)USART_Mode;
00008C 1A 15 [ 1] 186 or a, (0x15, sp)
00008E F7 [ 1] 187 ld (x), a
188 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 239: }
00008F 1E 0C [ 2] 189 ldw x, (12, sp)
000091 5B 15 [ 2] 190 addw sp, #21
000093 FC [ 2] 191 jp (x)
192 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 264: void USART_ClockInit(USART_TypeDef* USARTx, USART_Clock_TypeDef USART_Clock,
193 ; -----------------------------------------
194 ; function USART_ClockInit
195 ; -----------------------------------------
000094 196 _USART_ClockInit:
000094 52 05 [ 2] 197 sub sp, #5
000096 6B 05 [ 1] 198 ld (0x05, sp), a
199 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 275: USARTx->CR3 &= (uint8_t)~(USART_CR3_CPOL | USART_CR3_CPHA | USART_CR3_LBCL);
000098 1C 00 06 [ 2] 200 addw x, #0x0006
00009B 1F 01 [ 2] 201 ldw (0x01, sp), x
00009D F6 [ 1] 202 ld a, (x)
00009E A4 F8 [ 1] 203 and a, #0xf8
0000A0 6B 03 [ 1] 204 ld (0x03, sp), a
0000A2 1E 01 [ 2] 205 ldw x, (0x01, sp)
0000A4 7B 03 [ 1] 206 ld a, (0x03, sp)
0000A6 F7 [ 1] 207 ld (x), a
208 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 277: USARTx->CR3 |= (uint8_t)((uint8_t)((uint8_t)(USART_CPOL | (uint8_t)USART_CPHA ) | USART_LastBit));
0000A7 7B 08 [ 1] 209 ld a, (0x08, sp)
0000A9 1A 09 [ 1] 210 or a, (0x09, sp)
0000AB 6B 04 [ 1] 211 ld (0x04, sp), a
0000AD 7B 0A [ 1] 212 ld a, (0x0a, sp)
0000AF 1A 04 [ 1] 213 or a, (0x04, sp)
0000B1 1A 03 [ 1] 214 or a, (0x03, sp)
0000B3 1E 01 [ 2] 215 ldw x, (0x01, sp)
0000B5 F7 [ 1] 216 ld (x), a
217 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 275: USARTx->CR3 &= (uint8_t)~(USART_CR3_CPOL | USART_CR3_CPHA | USART_CR3_LBCL);
0000B6 1E 01 [ 2] 218 ldw x, (0x01, sp)
0000B8 F6 [ 1] 219 ld a, (x)
220 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 279: if (USART_Clock != USART_Clock_Disable)
0000B9 0D 05 [ 1] 221 tnz (0x05, sp)
0000BB 27 07 [ 1] 222 jreq 00102$
223 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 281: USARTx->CR3 |= (uint8_t)(USART_CR3_CLKEN); /* Set the Clock Enable bit */
0000BD AA 08 [ 1] 224 or a, #0x08
0000BF 1E 01 [ 2] 225 ldw x, (0x01, sp)
0000C1 F7 [ 1] 226 ld (x), a
0000C2 20 05 [ 2] 227 jra 00104$
0000C4 228 00102$:
229 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 285: USARTx->CR3 &= (uint8_t)(~USART_CR3_CLKEN); /* Clear the Clock Enable bit */
0000C4 A4 F7 [ 1] 230 and a, #0xf7
0000C6 1E 01 [ 2] 231 ldw x, (0x01, sp)
0000C8 F7 [ 1] 232 ld (x), a
0000C9 233 00104$:
234 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 287: }
0000C9 1E 06 [ 2] 235 ldw x, (6, sp)
0000CB 5B 0A [ 2] 236 addw sp, #10
0000CD FC [ 2] 237 jp (x)
238 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 296: void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
239 ; -----------------------------------------
240 ; function USART_Cmd
241 ; -----------------------------------------
0000CE 242 _USART_Cmd:
0000CE 88 [ 1] 243 push a
0000CF 6B 01 [ 1] 244 ld (0x01, sp), a
245 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 300: USARTx->CR1 &= (uint8_t)(~USART_CR1_USARTD); /**< USART Enable */
0000D1 1C 00 04 [ 2] 246 addw x, #0x0004
0000D4 F6 [ 1] 247 ld a, (x)
248 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 298: if (NewState != DISABLE)
0000D5 0D 01 [ 1] 249 tnz (0x01, sp)
0000D7 27 05 [ 1] 250 jreq 00102$
251 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 300: USARTx->CR1 &= (uint8_t)(~USART_CR1_USARTD); /**< USART Enable */
0000D9 A4 DF [ 1] 252 and a, #0xdf
0000DB F7 [ 1] 253 ld (x), a
0000DC 20 03 [ 2] 254 jra 00104$
0000DE 255 00102$:
256 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 304: USARTx->CR1 |= USART_CR1_USARTD; /**< USART Disable (for low power consumption) */
0000DE AA 20 [ 1] 257 or a, #0x20
0000E0 F7 [ 1] 258 ld (x), a
0000E1 259 00104$:
260 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 306: }
0000E1 84 [ 1] 261 pop a
0000E2 81 [ 4] 262 ret
263 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 329: void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
264 ; -----------------------------------------
265 ; function USART_SetPrescaler
266 ; -----------------------------------------
0000E3 267 _USART_SetPrescaler:
268 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 332: USARTx->PSCR = USART_Prescaler;
0000E3 1C 00 0A [ 2] 269 addw x, #0x000a
0000E6 F7 [ 1] 270 ld (x), a
271 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 333: }
0000E7 81 [ 4] 272 ret
273 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 340: void USART_SendBreak(USART_TypeDef* USARTx)
274 ; -----------------------------------------
275 ; function USART_SendBreak
276 ; -----------------------------------------
0000E8 277 _USART_SendBreak:
278 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 342: USARTx->CR2 |= USART_CR2_SBK;
0000E8 1C 00 05 [ 2] 279 addw x, #0x0005
0000EB F6 [ 1] 280 ld a, (x)
0000EC AA 01 [ 1] 281 or a, #0x01
0000EE F7 [ 1] 282 ld (x), a
283 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 343: }
0000EF 81 [ 4] 284 ret
285 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 382: uint8_t USART_ReceiveData8(USART_TypeDef* USARTx)
286 ; -----------------------------------------
287 ; function USART_ReceiveData8
288 ; -----------------------------------------
0000F0 289 _USART_ReceiveData8:
290 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 384: return USARTx->DR;
0000F0 E6 01 [ 1] 291 ld a, (0x1, x)
292 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 385: }
0000F2 81 [ 4] 293 ret
294 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 392: uint16_t USART_ReceiveData9(USART_TypeDef* USARTx)
295 ; -----------------------------------------
296 ; function USART_ReceiveData9
297 ; -----------------------------------------
0000F3 298 _USART_ReceiveData9:
0000F3 89 [ 2] 299 pushw x
300 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 396: temp = ((uint16_t)(((uint16_t)((uint16_t)USARTx->CR1 & (uint16_t)USART_CR1_R8)) << 1));
0000F4 90 93 [ 1] 301 ldw y, x
0000F6 E6 04 [ 1] 302 ld a, (0x4, x)
0000F8 A4 80 [ 1] 303 and a, #0x80
0000FA 97 [ 1] 304 ld xl, a
0000FB 4F [ 1] 305 clr a
0000FC 95 [ 1] 306 ld xh, a
0000FD 58 [ 2] 307 sllw x
0000FE 1F 01 [ 2] 308 ldw (0x01, sp), x
309 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 397: return (uint16_t)( ((uint16_t)((uint16_t)USARTx->DR) | temp) & ((uint16_t)0x01FF));
000100 90 E6 01 [ 1] 310 ld a, (0x1, y)
000103 1A 02 [ 1] 311 or a, (0x02, sp)
000105 97 [ 1] 312 ld xl, a
000106 7B 01 [ 1] 313 ld a, (0x01, sp)
000108 A4 01 [ 1] 314 and a, #0x01
00010A 95 [ 1] 315 ld xh, a
316 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 398: }
00010B 5B 02 [ 2] 317 addw sp, #2
00010D 81 [ 4] 318 ret
319 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 405: void USART_SendData8(USART_TypeDef* USARTx, uint8_t Data)
320 ; -----------------------------------------
321 ; function USART_SendData8
322 ; -----------------------------------------
00010E 323 _USART_SendData8:
324 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 408: USARTx->DR = Data;
00010E 5C [ 1] 325 incw x
00010F F7 [ 1] 326 ld (x), a
327 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 409: }
000110 81 [ 4] 328 ret
329 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 418: void USART_SendData9(USART_TypeDef* USARTx, uint16_t Data)
330 ; -----------------------------------------
331 ; function USART_SendData9
332 ; -----------------------------------------
000111 333 _USART_SendData9:
000111 52 03 [ 2] 334 sub sp, #3
335 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 423: USARTx->CR1 &= ((uint8_t)~USART_CR1_T8);
000113 1F 02 [ 2] 336 ldw (0x02, sp), x
000115 1C 00 04 [ 2] 337 addw x, #0x0004
000118 F6 [ 1] 338 ld a, (x)
000119 A4 BF [ 1] 339 and a, #0xbf
00011B 6B 01 [ 1] 340 ld (0x01, sp), a
00011D F7 [ 1] 341 ld (x), a
342 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 426: USARTx->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & USART_CR1_T8);
00011E 16 06 [ 2] 343 ldw y, (0x06, sp)
000120 90 54 [ 2] 344 srlw y
000122 90 54 [ 2] 345 srlw y
000124 90 9F [ 1] 346 ld a, yl
000126 A4 40 [ 1] 347 and a, #0x40
000128 1A 01 [ 1] 348 or a, (0x01, sp)
00012A F7 [ 1] 349 ld (x), a
350 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 429: USARTx->DR = (uint8_t)(Data);
00012B 1E 02 [ 2] 351 ldw x, (0x02, sp)
00012D 5C [ 1] 352 incw x
00012E 7B 07 [ 1] 353 ld a, (0x07, sp)
000130 F7 [ 1] 354 ld (x), a
355 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 430: }
000131 1E 04 [ 2] 356 ldw x, (4, sp)
000133 5B 07 [ 2] 357 addw sp, #7
000135 FC [ 2] 358 jp (x)
359 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 473: void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
360 ; -----------------------------------------
361 ; function USART_ReceiverWakeUpCmd
362 ; -----------------------------------------
000136 363 _USART_ReceiverWakeUpCmd:
000136 88 [ 1] 364 push a
000137 6B 01 [ 1] 365 ld (0x01, sp), a
366 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 480: USARTx->CR2 |= USART_CR2_RWU;
000139 1C 00 05 [ 2] 367 addw x, #0x0005
00013C F6 [ 1] 368 ld a, (x)
369 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 477: if (NewState != DISABLE)
00013D 0D 01 [ 1] 370 tnz (0x01, sp)
00013F 27 05 [ 1] 371 jreq 00102$
372 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 480: USARTx->CR2 |= USART_CR2_RWU;
000141 AA 02 [ 1] 373 or a, #0x02
000143 F7 [ 1] 374 ld (x), a
000144 20 03 [ 2] 375 jra 00104$
000146 376 00102$:
377 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 485: USARTx->CR2 &= ((uint8_t)~USART_CR2_RWU);
000146 A4 FD [ 1] 378 and a, #0xfd
000148 F7 [ 1] 379 ld (x), a
000149 380 00104$:
381 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 487: }
000149 84 [ 1] 382 pop a
00014A 81 [ 4] 383 ret
384 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 496: void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
385 ; -----------------------------------------
386 ; function USART_SetAddress
387 ; -----------------------------------------
00014B 388 _USART_SetAddress:
00014B 88 [ 1] 389 push a
00014C 6B 01 [ 1] 390 ld (0x01, sp), a
391 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 502: USARTx->CR4 &= ((uint8_t)~USART_CR4_ADD);
00014E 1C 00 07 [ 2] 392 addw x, #0x0007
000151 F6 [ 1] 393 ld a, (x)
000152 A4 F0 [ 1] 394 and a, #0xf0
000154 F7 [ 1] 395 ld (x), a
396 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 504: USARTx->CR4 |= USART_Address;
000155 1A 01 [ 1] 397 or a, (0x01, sp)
000157 F7 [ 1] 398 ld (x), a
399 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 505: }
000158 84 [ 1] 400 pop a
000159 81 [ 4] 401 ret
402 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 515: void USART_WakeUpConfig(USART_TypeDef* USARTx, USART_WakeUp_TypeDef USART_WakeUp)
403 ; -----------------------------------------
404 ; function USART_WakeUpConfig
405 ; -----------------------------------------
00015A 406 _USART_WakeUpConfig:
00015A 88 [ 1] 407 push a
00015B 6B 01 [ 1] 408 ld (0x01, sp), a
409 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 519: USARTx->CR1 &= ((uint8_t)~USART_CR1_WAKE);
00015D 1C 00 04 [ 2] 410 addw x, #0x0004
000160 F6 [ 1] 411 ld a, (x)
000161 A4 F7 [ 1] 412 and a, #0xf7
000163 F7 [ 1] 413 ld (x), a
414 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 520: USARTx->CR1 |= (uint8_t)USART_WakeUp;
000164 1A 01 [ 1] 415 or a, (0x01, sp)
000166 F7 [ 1] 416 ld (x), a
417 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 521: }
000167 84 [ 1] 418 pop a
000168 81 [ 4] 419 ret
420 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 566: void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
421 ; -----------------------------------------
422 ; function USART_HalfDuplexCmd
423 ; -----------------------------------------
000169 424 _USART_HalfDuplexCmd:
000169 88 [ 1] 425 push a
00016A 6B 01 [ 1] 426 ld (0x01, sp), a
427 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 572: USARTx->CR5 |= USART_CR5_HDSEL; /**< USART Half Duplex Enable */
00016C 1C 00 08 [ 2] 428 addw x, #0x0008
00016F F6 [ 1] 429 ld a, (x)
430 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 570: if (NewState != DISABLE)
000170 0D 01 [ 1] 431 tnz (0x01, sp)
000172 27 05 [ 1] 432 jreq 00102$
433 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 572: USARTx->CR5 |= USART_CR5_HDSEL; /**< USART Half Duplex Enable */
000174 AA 08 [ 1] 434 or a, #0x08
000176 F7 [ 1] 435 ld (x), a
000177 20 03 [ 2] 436 jra 00104$
000179 437 00102$:
438 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 576: USARTx->CR5 &= (uint8_t)~USART_CR5_HDSEL; /**< USART Half Duplex Disable */
000179 A4 F7 [ 1] 439 and a, #0xf7
00017B F7 [ 1] 440 ld (x), a
00017C 441 00104$:
442 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 578: }
00017C 84 [ 1] 443 pop a
00017D 81 [ 4] 444 ret
445 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 644: void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
446 ; -----------------------------------------
447 ; function USART_SmartCardCmd
448 ; -----------------------------------------
00017E 449 _USART_SmartCardCmd:
00017E 88 [ 1] 450 push a
00017F 6B 01 [ 1] 451 ld (0x01, sp), a
452 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 651: USARTx->CR5 |= USART_CR5_SCEN;
000181 1C 00 08 [ 2] 453 addw x, #0x0008
000184 F6 [ 1] 454 ld a, (x)
455 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 648: if (NewState != DISABLE)
000185 0D 01 [ 1] 456 tnz (0x01, sp)
000187 27 05 [ 1] 457 jreq 00102$
458 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 651: USARTx->CR5 |= USART_CR5_SCEN;
000189 AA 20 [ 1] 459 or a, #0x20
00018B F7 [ 1] 460 ld (x), a
00018C 20 03 [ 2] 461 jra 00104$
00018E 462 00102$:
463 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 656: USARTx->CR5 &= ((uint8_t)(~USART_CR5_SCEN));
00018E A4 DF [ 1] 464 and a, #0xdf
000190 F7 [ 1] 465 ld (x), a
000191 466 00104$:
467 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 658: }
000191 84 [ 1] 468 pop a
000192 81 [ 4] 469 ret
470 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 667: void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
471 ; -----------------------------------------
472 ; function USART_SmartCardNACKCmd
473 ; -----------------------------------------
000193 474 _USART_SmartCardNACKCmd:
000193 88 [ 1] 475 push a
000194 6B 01 [ 1] 476 ld (0x01, sp), a
477 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 674: USARTx->CR5 |= USART_CR5_NACK;
000196 1C 00 08 [ 2] 478 addw x, #0x0008
000199 F6 [ 1] 479 ld a, (x)
480 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 671: if (NewState != DISABLE)
00019A 0D 01 [ 1] 481 tnz (0x01, sp)
00019C 27 05 [ 1] 482 jreq 00102$
483 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 674: USARTx->CR5 |= USART_CR5_NACK;
00019E AA 10 [ 1] 484 or a, #0x10
0001A0 F7 [ 1] 485 ld (x), a
0001A1 20 03 [ 2] 486 jra 00104$
0001A3 487 00102$:
488 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 679: USARTx->CR5 &= ((uint8_t)~(USART_CR5_NACK));
0001A3 A4 EF [ 1] 489 and a, #0xef
0001A5 F7 [ 1] 490 ld (x), a
0001A6 491 00104$:
492 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 681: }
0001A6 84 [ 1] 493 pop a
0001A7 81 [ 4] 494 ret
495 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 690: void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
496 ; -----------------------------------------
497 ; function USART_SetGuardTime
498 ; -----------------------------------------
0001A8 499 _USART_SetGuardTime:
500 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 693: USARTx->GTR = USART_GuardTime;
0001A8 1C 00 09 [ 2] 501 addw x, #0x0009
0001AB F7 [ 1] 502 ld (x), a
503 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 694: }
0001AC 81 [ 4] 504 ret
505 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 751: void USART_IrDAConfig(USART_TypeDef* USARTx, USART_IrDAMode_TypeDef USART_IrDAMode)
506 ; -----------------------------------------
507 ; function USART_IrDAConfig
508 ; -----------------------------------------
0001AD 509 _USART_IrDAConfig:
0001AD 88 [ 1] 510 push a
0001AE 6B 01 [ 1] 511 ld (0x01, sp), a
512 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 757: USARTx->CR5 |= USART_CR5_IRLP;
0001B0 1C 00 08 [ 2] 513 addw x, #0x0008
0001B3 F6 [ 1] 514 ld a, (x)
515 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 755: if (USART_IrDAMode != USART_IrDAMode_Normal)
0001B4 0D 01 [ 1] 516 tnz (0x01, sp)
0001B6 27 05 [ 1] 517 jreq 00102$
518 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 757: USARTx->CR5 |= USART_CR5_IRLP;
0001B8 AA 04 [ 1] 519 or a, #0x04
0001BA F7 [ 1] 520 ld (x), a
0001BB 20 03 [ 2] 521 jra 00104$
0001BD 522 00102$:
523 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 761: USARTx->CR5 &= ((uint8_t)~USART_CR5_IRLP);
0001BD A4 FB [ 1] 524 and a, #0xfb
0001BF F7 [ 1] 525 ld (x), a
0001C0 526 00104$:
527 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 763: }
0001C0 84 [ 1] 528 pop a
0001C1 81 [ 4] 529 ret
530 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 772: void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
531 ; -----------------------------------------
532 ; function USART_IrDACmd
533 ; -----------------------------------------
0001C2 534 _USART_IrDACmd:
0001C2 88 [ 1] 535 push a
0001C3 6B 01 [ 1] 536 ld (0x01, sp), a
537 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 781: USARTx->CR5 |= USART_CR5_IREN;
0001C5 1C 00 08 [ 2] 538 addw x, #0x0008
0001C8 F6 [ 1] 539 ld a, (x)
540 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 778: if (NewState != DISABLE)
0001C9 0D 01 [ 1] 541 tnz (0x01, sp)
0001CB 27 05 [ 1] 542 jreq 00102$
543 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 781: USARTx->CR5 |= USART_CR5_IREN;
0001CD AA 02 [ 1] 544 or a, #0x02
0001CF F7 [ 1] 545 ld (x), a
0001D0 20 03 [ 2] 546 jra 00104$
0001D2 547 00102$:
548 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 786: USARTx->CR5 &= ((uint8_t)~USART_CR5_IREN);
0001D2 A4 FD [ 1] 549 and a, #0xfd
0001D4 F7 [ 1] 550 ld (x), a
0001D5 551 00104$:
552 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 788: }
0001D5 84 [ 1] 553 pop a
0001D6 81 [ 4] 554 ret
555 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 818: void USART_DMACmd(USART_TypeDef* USARTx, USART_DMAReq_TypeDef USART_DMAReq,
556 ; -----------------------------------------
557 ; function USART_DMACmd
558 ; -----------------------------------------
0001D7 559 _USART_DMACmd:
0001D7 88 [ 1] 560 push a
561 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 829: USARTx->CR5 |= (uint8_t) USART_DMAReq;
0001D8 1C 00 08 [ 2] 562 addw x, #0x0008
0001DB 88 [ 1] 563 push a
0001DC F6 [ 1] 564 ld a, (x)
0001DD 6B 02 [ 1] 565 ld (0x02, sp), a
0001DF 84 [ 1] 566 pop a
567 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 825: if (NewState != DISABLE)
0001E0 0D 04 [ 1] 568 tnz (0x04, sp)
0001E2 27 05 [ 1] 569 jreq 00102$
570 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 829: USARTx->CR5 |= (uint8_t) USART_DMAReq;
0001E4 1A 01 [ 1] 571 or a, (0x01, sp)
0001E6 F7 [ 1] 572 ld (x), a
0001E7 20 04 [ 2] 573 jra 00104$
0001E9 574 00102$:
575 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 835: USARTx->CR5 &= (uint8_t)~USART_DMAReq;
0001E9 43 [ 1] 576 cpl a
0001EA 14 01 [ 1] 577 and a, (0x01, sp)
0001EC F7 [ 1] 578 ld (x), a
0001ED 579 00104$:
580 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 837: }
0001ED 84 [ 1] 581 pop a
0001EE 85 [ 2] 582 popw x
0001EF 84 [ 1] 583 pop a
0001F0 FC [ 2] 584 jp (x)
585 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 939: void USART_ITConfig(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT, FunctionalState NewState)
586 ; -----------------------------------------
587 ; function USART_ITConfig
588 ; -----------------------------------------
0001F1 589 _USART_ITConfig:
0001F1 52 09 [ 2] 590 sub sp, #9
0001F3 1F 08 [ 2] 591 ldw (0x08, sp), x
592 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 946: usartreg = (uint8_t)((uint16_t)USART_IT >> 0x08);
0001F5 1E 0C [ 2] 593 ldw x, (0x0c, sp)
594 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 948: itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)USART_IT & (uint8_t)0x0F));
0001F7 7B 0D [ 1] 595 ld a, (0x0d, sp)
0001F9 A4 0F [ 1] 596 and a, #0x0f
0001FB 88 [ 1] 597 push a
0001FC A6 01 [ 1] 598 ld a, #0x01
0001FE 6B 08 [ 1] 599 ld (0x08, sp), a
000200 84 [ 1] 600 pop a
000201 4D [ 1] 601 tnz a
000202 27 05 [ 1] 602 jreq 00154$
000204 603 00153$:
000204 08 07 [ 1] 604 sll (0x07, sp)
000206 4A [ 1] 605 dec a
000207 26 FB [ 1] 606 jrne 00153$
000209 607 00154$:
608 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 953: if (usartreg == 0x01)
000209 9E [ 1] 609 ld a, xh
00020A 4A [ 1] 610 dec a
00020B 26 05 [ 1] 611 jrne 00156$
00020D A6 01 [ 1] 612 ld a, #0x01
00020F 6B 01 [ 1] 613 ld (0x01, sp), a
000211 C5 614 .byte 0xc5
000212 615 00156$:
000212 0F 01 [ 1] 616 clr (0x01, sp)
000214 617 00157$:
618 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 955: USARTx->CR1 |= itpos;
000214 16 08 [ 2] 619 ldw y, (0x08, sp)
000216 72 A9 00 04 [ 2] 620 addw y, #0x0004
00021A 17 02 [ 2] 621 ldw (0x02, sp), y
622 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 957: else if (usartreg == 0x05)
00021C 9E [ 1] 623 ld a, xh
00021D A0 05 [ 1] 624 sub a, #0x05
00021F 26 04 [ 1] 625 jrne 00159$
000221 4C [ 1] 626 inc a
000222 6B 04 [ 1] 627 ld (0x04, sp), a
000224 C5 628 .byte 0xc5
000225 629 00159$:
000225 0F 04 [ 1] 630 clr (0x04, sp)
000227 631 00160$:
632 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 959: USARTx->CR5 |= itpos;
000227 1E 08 [ 2] 633 ldw x, (0x08, sp)
000229 1C 00 08 [ 2] 634 addw x, #0x0008
00022C 1F 05 [ 2] 635 ldw (0x05, sp), x
636 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 964: USARTx->CR2 |= itpos;
00022E 1E 08 [ 2] 637 ldw x, (0x08, sp)
000230 1C 00 05 [ 2] 638 addw x, #0x0005
639 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 950: if (NewState != DISABLE)
000233 0D 0E [ 1] 640 tnz (0x0e, sp)
000235 27 22 [ 1] 641 jreq 00114$
642 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 953: if (usartreg == 0x01)
000237 0D 01 [ 1] 643 tnz (0x01, sp)
000239 27 0A [ 1] 644 jreq 00105$
645 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 955: USARTx->CR1 |= itpos;
00023B 1E 02 [ 2] 646 ldw x, (0x02, sp)
00023D F6 [ 1] 647 ld a, (x)
00023E 1A 07 [ 1] 648 or a, (0x07, sp)
000240 1E 02 [ 2] 649 ldw x, (0x02, sp)
000242 F7 [ 1] 650 ld (x), a
000243 20 36 [ 2] 651 jra 00116$
000245 652 00105$:
653 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 957: else if (usartreg == 0x05)
000245 0D 04 [ 1] 654 tnz (0x04, sp)
000247 27 0A [ 1] 655 jreq 00102$
656 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 959: USARTx->CR5 |= itpos;
000249 1E 05 [ 2] 657 ldw x, (0x05, sp)
00024B F6 [ 1] 658 ld a, (x)
00024C 1A 07 [ 1] 659 or a, (0x07, sp)
00024E 1E 05 [ 2] 660 ldw x, (0x05, sp)
000250 F7 [ 1] 661 ld (x), a
000251 20 28 [ 2] 662 jra 00116$
000253 663 00102$:
664 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 964: USARTx->CR2 |= itpos;
000253 F6 [ 1] 665 ld a, (x)
000254 1A 07 [ 1] 666 or a, (0x07, sp)
000256 F7 [ 1] 667 ld (x), a
000257 20 22 [ 2] 668 jra 00116$
000259 669 00114$:
670 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 972: USARTx->CR1 &= (uint8_t)(~itpos);
000259 03 07 [ 1] 671 cpl (0x07, sp)
672 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 970: if (usartreg == 0x01)
00025B 0D 01 [ 1] 673 tnz (0x01, sp)
00025D 27 0A [ 1] 674 jreq 00111$
675 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 972: USARTx->CR1 &= (uint8_t)(~itpos);
00025F 1E 02 [ 2] 676 ldw x, (0x02, sp)
000261 F6 [ 1] 677 ld a, (x)
000262 14 07 [ 1] 678 and a, (0x07, sp)
000264 1E 02 [ 2] 679 ldw x, (0x02, sp)
000266 F7 [ 1] 680 ld (x), a
000267 20 12 [ 2] 681 jra 00116$
000269 682 00111$:
683 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 974: else if (usartreg == 0x05)
000269 0D 04 [ 1] 684 tnz (0x04, sp)
00026B 27 0A [ 1] 685 jreq 00108$
686 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 976: USARTx->CR5 &= (uint8_t)(~itpos);
00026D 1E 05 [ 2] 687 ldw x, (0x05, sp)
00026F F6 [ 1] 688 ld a, (x)
000270 14 07 [ 1] 689 and a, (0x07, sp)
000272 1E 05 [ 2] 690 ldw x, (0x05, sp)
000274 F7 [ 1] 691 ld (x), a
000275 20 04 [ 2] 692 jra 00116$
000277 693 00108$:
694 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 981: USARTx->CR2 &= (uint8_t)(~itpos);
000277 F6 [ 1] 695 ld a, (x)
000278 14 07 [ 1] 696 and a, (0x07, sp)
00027A F7 [ 1] 697 ld (x), a
00027B 698 00116$:
699 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 984: }
00027B 1E 0A [ 2] 700 ldw x, (10, sp)
00027D 5B 0E [ 2] 701 addw sp, #14
00027F FC [ 2] 702 jp (x)
703 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1002: FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG)
704 ; -----------------------------------------
705 ; function USART_GetFlagStatus
706 ; -----------------------------------------
000280 707 _USART_GetFlagStatus:
000280 88 [ 1] 708 push a
709 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1009: if (USART_FLAG == USART_FLAG_SBK)
000281 16 04 [ 2] 710 ldw y, (0x04, sp)
711 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1011: if ((USARTx->CR2 & (uint8_t)USART_FLAG) != (uint8_t)0x00)
000283 7B 05 [ 1] 712 ld a, (0x05, sp)
000285 6B 01 [ 1] 713 ld (0x01, sp), a
714 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1009: if (USART_FLAG == USART_FLAG_SBK)
000287 90 A3 01 01 [ 2] 715 cpw y, #0x0101
00028B 26 0D [ 1] 716 jrne 00108$
717 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1011: if ((USARTx->CR2 & (uint8_t)USART_FLAG) != (uint8_t)0x00)
00028D E6 05 [ 1] 718 ld a, (0x5, x)
00028F 14 01 [ 1] 719 and a, (0x01, sp)
000291 27 04 [ 1] 720 jreq 00102$
721 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1014: status = SET;
000293 A6 01 [ 1] 722 ld a, #0x01
000295 20 0C [ 2] 723 jra 00109$
000297 724 00102$:
725 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1019: status = RESET;
000297 4F [ 1] 726 clr a
000298 20 09 [ 2] 727 jra 00109$
00029A 728 00108$:
729 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1024: if ((USARTx->SR & (uint8_t)USART_FLAG) != (uint8_t)0x00)
00029A F6 [ 1] 730 ld a, (x)
00029B 14 01 [ 1] 731 and a, (0x01, sp)
00029D 27 03 [ 1] 732 jreq 00105$
733 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1027: status = SET;
00029F A6 01 [ 1] 734 ld a, #0x01
735 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1032: status = RESET;
0002A1 21 736 .byte 0x21
0002A2 737 00105$:
0002A2 4F [ 1] 738 clr a
0002A3 739 00109$:
740 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1036: return status;
741 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1037: }
0002A3 1E 02 [ 2] 742 ldw x, (2, sp)
0002A5 5B 05 [ 2] 743 addw sp, #5
0002A7 FC [ 2] 744 jp (x)
745 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1060: void USART_ClearFlag(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG)
746 ; -----------------------------------------
747 ; function USART_ClearFlag
748 ; -----------------------------------------
0002A8 749 _USART_ClearFlag:
750 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1065: USARTx->SR = (uint8_t)((uint16_t)~((uint16_t)USART_FLAG));
0002A8 16 03 [ 2] 751 ldw y, (0x03, sp)
0002AA 90 53 [ 2] 752 cplw y
0002AC 90 9F [ 1] 753 ld a, yl
0002AE F7 [ 1] 754 ld (x), a
755 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1066: }
0002AF 1E 01 [ 2] 756 ldw x, (1, sp)
0002B1 5B 04 [ 2] 757 addw sp, #4
0002B3 FC [ 2] 758 jp (x)
759 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1083: ITStatus USART_GetITStatus(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT)
760 ; -----------------------------------------
761 ; function USART_GetITStatus
762 ; -----------------------------------------
0002B4 763 _USART_GetITStatus:
0002B4 52 09 [ 2] 764 sub sp, #9
0002B6 1F 08 [ 2] 765 ldw (0x08, sp), x
766 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1096: itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)USART_IT & (uint8_t)0x0F));
0002B8 7B 0D [ 1] 767 ld a, (0x0d, sp)
0002BA 97 [ 1] 768 ld xl, a
0002BB A4 0F [ 1] 769 and a, #0x0f
0002BD 88 [ 1] 770 push a
0002BE A6 01 [ 1] 771 ld a, #0x01
0002C0 6B 04 [ 1] 772 ld (0x04, sp), a
0002C2 84 [ 1] 773 pop a
0002C3 4D [ 1] 774 tnz a
0002C4 27 05 [ 1] 775 jreq 00179$
0002C6 776 00178$:
0002C6 08 03 [ 1] 777 sll (0x03, sp)
0002C8 4A [ 1] 778 dec a
0002C9 26 FB [ 1] 779 jrne 00178$
0002CB 780 00179$:
781 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1098: itmask1 = (uint8_t)((uint8_t)USART_IT >> (uint8_t)4);
0002CB 9F [ 1] 782 ld a, xl
0002CC 4E [ 1] 783 swap a
0002CD A4 0F [ 1] 784 and a, #0x0f
785 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1100: itmask2 = (uint8_t)((uint8_t)1 << itmask1);
0002CF 88 [ 1] 786 push a
0002D0 A6 01 [ 1] 787 ld a, #0x01
0002D2 6B 08 [ 1] 788 ld (0x08, sp), a
0002D4 84 [ 1] 789 pop a
0002D5 4D [ 1] 790 tnz a
0002D6 27 05 [ 1] 791 jreq 00181$
0002D8 792 00180$:
0002D8 08 07 [ 1] 793 sll (0x07, sp)
0002DA 4A [ 1] 794 dec a
0002DB 26 FB [ 1] 795 jrne 00180$
0002DD 796 00181$:
797 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1103: if (USART_IT == USART_IT_PE)
0002DD 16 0C [ 2] 798 ldw y, (0x0c, sp)
0002DF 17 01 [ 2] 799 ldw (0x01, sp), y
800 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1109: if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
0002E1 16 08 [ 2] 801 ldw y, (0x08, sp)
0002E3 17 04 [ 2] 802 ldw (0x04, sp), y
803 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1103: if (USART_IT == USART_IT_PE)
0002E5 1E 01 [ 2] 804 ldw x, (0x01, sp)
0002E7 A3 01 00 [ 2] 805 cpw x, #0x0100
0002EA 26 1D [ 1] 806 jrne 00118$
807 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1106: enablestatus = (uint8_t)((uint8_t)USARTx->CR1 & itmask2);
0002EC 16 08 [ 2] 808 ldw y, (0x08, sp)
0002EE 17 01 [ 2] 809 ldw (0x01, sp), y
0002F0 93 [ 1] 810 ldw x, y
0002F1 E6 04 [ 1] 811 ld a, (0x4, x)
0002F3 14 07 [ 1] 812 and a, (0x07, sp)
0002F5 6B 07 [ 1] 813 ld (0x07, sp), a
814 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1109: if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
0002F7 1E 04 [ 2] 815 ldw x, (0x04, sp)
0002F9 F6 [ 1] 816 ld a, (x)
0002FA 14 03 [ 1] 817 and a, (0x03, sp)
0002FC 27 08 [ 1] 818 jreq 00102$
0002FE 0D 07 [ 1] 819 tnz (0x07, sp)
000300 27 04 [ 1] 820 jreq 00102$
821 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1112: pendingbitstatus = SET;
000302 A6 01 [ 1] 822 ld a, #0x01
000304 20 41 [ 2] 823 jra 00119$
000306 824 00102$:
825 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1117: pendingbitstatus = RESET;
000306 4F [ 1] 826 clr a
000307 20 3E [ 2] 827 jra 00119$
000309 828 00118$:
829 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1124: enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
000309 1E 08 [ 2] 830 ldw x, (0x08, sp)
00030B E6 05 [ 1] 831 ld a, (0x5, x)
00030D 14 07 [ 1] 832 and a, (0x07, sp)
833 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1121: else if (USART_IT == USART_IT_OR)
00030F 1E 01 [ 2] 834 ldw x, (0x01, sp)
000311 A3 02 35 [ 2] 835 cpw x, #0x0235
000314 26 20 [ 1] 836 jrne 00115$
837 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1124: enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
000316 6B 06 [ 1] 838 ld (0x06, sp), a
839 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1127: temp = (uint8_t)(USARTx->CR5 & USART_CR5_EIE);
000318 1E 08 [ 2] 840 ldw x, (0x08, sp)
00031A E6 08 [ 1] 841 ld a, (0x8, x)
00031C A4 01 [ 1] 842 and a, #0x01
00031E 6B 07 [ 1] 843 ld (0x07, sp), a
844 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1129: if (( (USARTx->SR & itpos) != 0x00) && ((enablestatus || temp)))
000320 1E 04 [ 2] 845 ldw x, (0x04, sp)
000322 F6 [ 1] 846 ld a, (x)
000323 14 03 [ 1] 847 and a, (0x03, sp)
000325 27 0C [ 1] 848 jreq 00106$
000327 0D 06 [ 1] 849 tnz (0x06, sp)
000329 26 04 [ 1] 850 jrne 00105$
00032B 0D 07 [ 1] 851 tnz (0x07, sp)
00032D 27 04 [ 1] 852 jreq 00106$
00032F 853 00105$:
854 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1132: pendingbitstatus = SET;
00032F A6 01 [ 1] 855 ld a, #0x01
000331 20 14 [ 2] 856 jra 00119$
000333 857 00106$:
858 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1137: pendingbitstatus = RESET;
000333 4F [ 1] 859 clr a
000334 20 11 [ 2] 860 jra 00119$
000336 861 00115$:
862 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1144: enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
000336 6B 07 [ 1] 863 ld (0x07, sp), a
864 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1146: if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
000338 1E 04 [ 2] 865 ldw x, (0x04, sp)
00033A F6 [ 1] 866 ld a, (x)
00033B 14 03 [ 1] 867 and a, (0x03, sp)
00033D 27 07 [ 1] 868 jreq 00111$
00033F 0D 07 [ 1] 869 tnz (0x07, sp)
000341 27 03 [ 1] 870 jreq 00111$
871 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1149: pendingbitstatus = SET;
000343 A6 01 [ 1] 872 ld a, #0x01
873 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1154: pendingbitstatus = RESET;
000345 21 874 .byte 0x21
000346 875 00111$:
000346 4F [ 1] 876 clr a
000347 877 00119$:
878 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1159: return pendingbitstatus;
879 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1160: }
000347 1E 0A [ 2] 880 ldw x, (10, sp)
000349 5B 0D [ 2] 881 addw sp, #13
00034B FC [ 2] 882 jp (x)
883 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1183: void USART_ClearITPendingBit(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT)
884 ; -----------------------------------------
885 ; function USART_ClearITPendingBit
886 ; -----------------------------------------
00034C 887 _USART_ClearITPendingBit:
888 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1188: USARTx->SR &= (uint8_t)(~USART_SR_TC);
00034C F6 [ 1] 889 ld a, (x)
00034D A4 BF [ 1] 890 and a, #0xbf
00034F F7 [ 1] 891 ld (x), a
892 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1189: }
000350 1E 01 [ 2] 893 ldw x, (1, sp)
000352 5B 04 [ 2] 894 addw sp, #4
000354 FC [ 2] 895 jp (x)
896 .area CODE
897 .area CONST
898 .area INITIALIZER
899 .area CABS (ABS)

406
firmware/STM8L15X_LD/stm8l15x_usart.rel Normal file
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XH3
H B areas 1C global symbols
M stm8l15x_usart
S .__.ABS. Def000000
S __divulong Ref000000
S _CLK_GetClockFreq Ref000000
A _CODE size 0 flags 0 addr 0
A DATA size 0 flags 0 addr 0
A INITIALIZED size 0 flags 0 addr 0
A DABS size 0 flags 8 addr 0
A HOME size 0 flags 0 addr 0
A GSINIT size 0 flags 0 addr 0
A GSFINAL size 0 flags 0 addr 0
A CONST size 0 flags 0 addr 0
A INITIALIZER size 0 flags 0 addr 0
A CODE size 355 flags 0 addr 0
S _USART_ITConfig Def0001F1
S _USART_ReceiveData8 Def0000F0
S _USART_ReceiveData9 Def0000F3
S _USART_SendData8 Def00010E
S _USART_SendData9 Def000111
S _USART_DeInit Def000000
S _USART_ClockInit Def000094
S _USART_GetITStatus Def0002B4
S _USART_HalfDuplexCmd Def000169
S _USART_SetPrescaler Def0000E3
S _USART_IrDACmd Def0001C2
S _USART_Cmd Def0000CE
S _USART_Init Def000017
S _USART_SmartCardCmd Def00017E
S _USART_IrDAConfig Def0001AD
S _USART_ReceiverWakeUpCmd Def000136
S _USART_GetFlagStatus Def000280
S _USART_ClearFlag Def0002A8
S _USART_WakeUpConfig Def00015A
S _USART_DMACmd Def0001D7
S _USART_ClearITPendingBit Def00034C
S _USART_SetGuardTime Def0001A8
S _USART_SendBreak Def0000E8
S _USART_SmartCardNACKCmd Def000193
S _USART_SetAddress Def00014B
A CABS size 0 flags 8 addr 0
T 00 00 00
R 00 00 00 09
T 00 00 00 90 93 E6 01 93 6F 03 93 6F 02 93 6F 04
R 00 00 00 09
T 00 00 0D 93 6F 05 93 6F 06 93 6F 07 81
R 00 00 00 09
T 00 00 17
R 00 00 00 09
T 00 00 17 52 0B 1F 0A 1C 00 04 F6 A4 E9 6B 09 F7
R 00 00 00 09
T 00 00 24 7B 12 1A 14 1A 09 F7 1E 0A 1C 00 06 F6
R 00 00 00 09
T 00 00 31 A4 CF F7 1A 13 F7 1E 0A 5C 5C 1F 01 F6
R 00 00 00 09
T 00 00 3E 1E 01 7F 1E 0A 1C 00 03 1F 03 F6 A4 0F
R 00 00 00 09
T 00 00 4B 1E 03 F7 1E 03 7F CD 00 00 1F 08 1E 10
R 00 00 00 09 02 0A 00 02
T 00 00 58 89 1E 10 89 1E 0C 89 90 89 CD 00 00 5B
R 00 00 00 09 02 0D 00 01
T 00 00 65 08 17 05 9E A4 F0 6B 09 16 03 7B 09 90
R 00 00 00 09
T 00 00 72 F7 9F A4 0F 1A 09 16 03 90 F7 A6 10 62
R 00 00 00 09
T 00 00 7F 9F 1E 01 F7 1E 0A 1C 00 05 F6 A4 F3 F7
R 00 00 00 09
T 00 00 8C 1A 15 F7 1E 0C 5B 15 FC
R 00 00 00 09
T 00 00 94
R 00 00 00 09
T 00 00 94 52 05 6B 05 1C 00 06 1F 01 F6 A4 F8 6B
R 00 00 00 09
T 00 00 A1 03 1E 01 7B 03 F7 7B 08 1A 09 6B 04 7B
R 00 00 00 09
T 00 00 AE 0A 1A 04 1A 03 1E 01 F7 1E 01 F6 0D 05
R 00 00 00 09
T 00 00 BB 27 07 AA 08 1E 01 F7 20 05
R 00 00 00 09
T 00 00 C4
R 00 00 00 09
T 00 00 C4 A4 F7 1E 01 F7
R 00 00 00 09
T 00 00 C9
R 00 00 00 09
T 00 00 C9 1E 06 5B 0A FC
R 00 00 00 09
T 00 00 CE
R 00 00 00 09
T 00 00 CE 88 6B 01 1C 00 04 F6 0D 01 27 05 A4 DF
R 00 00 00 09
T 00 00 DB F7 20 03
R 00 00 00 09
T 00 00 DE
R 00 00 00 09
T 00 00 DE AA 20 F7
R 00 00 00 09
T 00 00 E1
R 00 00 00 09
T 00 00 E1 84 81
R 00 00 00 09
T 00 00 E3
R 00 00 00 09
T 00 00 E3 1C 00 0A F7 81
R 00 00 00 09
T 00 00 E8
R 00 00 00 09
T 00 00 E8 1C 00 05 F6 AA 01 F7 81
R 00 00 00 09
T 00 00 F0
R 00 00 00 09
T 00 00 F0 E6 01 81
R 00 00 00 09
T 00 00 F3
R 00 00 00 09
T 00 00 F3 89 90 93 E6 04 A4 80 97 4F 95 58 1F 01
R 00 00 00 09
T 00 01 00 90 E6 01 1A 02 97 7B 01 A4 01 95 5B 02
R 00 00 00 09
T 00 01 0D 81
R 00 00 00 09
T 00 01 0E
R 00 00 00 09
T 00 01 0E 5C F7 81
R 00 00 00 09
T 00 01 11
R 00 00 00 09
T 00 01 11 52 03 1F 02 1C 00 04 F6 A4 BF 6B 01 F7
R 00 00 00 09
T 00 01 1E 16 06 90 54 90 54 90 9F A4 40 1A 01 F7
R 00 00 00 09
T 00 01 2B 1E 02 5C 7B 07 F7 1E 04 5B 07 FC
R 00 00 00 09
T 00 01 36
R 00 00 00 09
T 00 01 36 88 6B 01 1C 00 05 F6 0D 01 27 05 AA 02
R 00 00 00 09
T 00 01 43 F7 20 03
R 00 00 00 09
T 00 01 46
R 00 00 00 09
T 00 01 46 A4 FD F7
R 00 00 00 09
T 00 01 49
R 00 00 00 09
T 00 01 49 84 81
R 00 00 00 09
T 00 01 4B
R 00 00 00 09
T 00 01 4B 88 6B 01 1C 00 07 F6 A4 F0 F7 1A 01 F7
R 00 00 00 09
T 00 01 58 84 81
R 00 00 00 09
T 00 01 5A
R 00 00 00 09
T 00 01 5A 88 6B 01 1C 00 04 F6 A4 F7 F7 1A 01 F7
R 00 00 00 09
T 00 01 67 84 81
R 00 00 00 09
T 00 01 69
R 00 00 00 09
T 00 01 69 88 6B 01 1C 00 08 F6 0D 01 27 05 AA 08
R 00 00 00 09
T 00 01 76 F7 20 03
R 00 00 00 09
T 00 01 79
R 00 00 00 09
T 00 01 79 A4 F7 F7
R 00 00 00 09
T 00 01 7C
R 00 00 00 09
T 00 01 7C 84 81
R 00 00 00 09
T 00 01 7E
R 00 00 00 09
T 00 01 7E 88 6B 01 1C 00 08 F6 0D 01 27 05 AA 20
R 00 00 00 09
T 00 01 8B F7 20 03
R 00 00 00 09
T 00 01 8E
R 00 00 00 09
T 00 01 8E A4 DF F7
R 00 00 00 09
T 00 01 91
R 00 00 00 09
T 00 01 91 84 81
R 00 00 00 09
T 00 01 93
R 00 00 00 09
T 00 01 93 88 6B 01 1C 00 08 F6 0D 01 27 05 AA 10
R 00 00 00 09
T 00 01 A0 F7 20 03
R 00 00 00 09
T 00 01 A3
R 00 00 00 09
T 00 01 A3 A4 EF F7
R 00 00 00 09
T 00 01 A6
R 00 00 00 09
T 00 01 A6 84 81
R 00 00 00 09
T 00 01 A8
R 00 00 00 09
T 00 01 A8 1C 00 09 F7 81
R 00 00 00 09
T 00 01 AD
R 00 00 00 09
T 00 01 AD 88 6B 01 1C 00 08 F6 0D 01 27 05 AA 04
R 00 00 00 09
T 00 01 BA F7 20 03
R 00 00 00 09
T 00 01 BD
R 00 00 00 09
T 00 01 BD A4 FB F7
R 00 00 00 09
T 00 01 C0
R 00 00 00 09
T 00 01 C0 84 81
R 00 00 00 09
T 00 01 C2
R 00 00 00 09
T 00 01 C2 88 6B 01 1C 00 08 F6 0D 01 27 05 AA 02
R 00 00 00 09
T 00 01 CF F7 20 03
R 00 00 00 09
T 00 01 D2
R 00 00 00 09
T 00 01 D2 A4 FD F7
R 00 00 00 09
T 00 01 D5
R 00 00 00 09
T 00 01 D5 84 81
R 00 00 00 09
T 00 01 D7
R 00 00 00 09
T 00 01 D7 88 1C 00 08 88 F6 6B 02 84 0D 04 27 05
R 00 00 00 09
T 00 01 E4 1A 01 F7 20 04
R 00 00 00 09
T 00 01 E9
R 00 00 00 09
T 00 01 E9 43 14 01 F7
R 00 00 00 09
T 00 01 ED
R 00 00 00 09
T 00 01 ED 84 85 84 FC
R 00 00 00 09
T 00 01 F1
R 00 00 00 09
T 00 01 F1 52 09 1F 08 1E 0C 7B 0D A4 0F 88 A6 01
R 00 00 00 09
T 00 01 FE 6B 08 84 4D 27 05
R 00 00 00 09
T 00 02 04
R 00 00 00 09
T 00 02 04 08 07 4A 26 FB
R 00 00 00 09
T 00 02 09
R 00 00 00 09
T 00 02 09 9E 4A 26 05 A6 01 6B 01 C5
R 00 00 00 09
T 00 02 12
R 00 00 00 09
T 00 02 12 0F 01
R 00 00 00 09
T 00 02 14
R 00 00 00 09
T 00 02 14 16 08 72 A9 00 04 17 02 9E A0 05 26 04
R 00 00 00 09
T 00 02 21 4C 6B 04 C5
R 00 00 00 09
T 00 02 25
R 00 00 00 09
T 00 02 25 0F 04
R 00 00 00 09
T 00 02 27
R 00 00 00 09
T 00 02 27 1E 08 1C 00 08 1F 05 1E 08 1C 00 05 0D
R 00 00 00 09
T 00 02 34 0E 27 22 0D 01 27 0A 1E 02 F6 1A 07 1E
R 00 00 00 09
T 00 02 41 02 F7 20 36
R 00 00 00 09
T 00 02 45
R 00 00 00 09
T 00 02 45 0D 04 27 0A 1E 05 F6 1A 07 1E 05 F7 20
R 00 00 00 09
T 00 02 52 28
R 00 00 00 09
T 00 02 53
R 00 00 00 09
T 00 02 53 F6 1A 07 F7 20 22
R 00 00 00 09
T 00 02 59
R 00 00 00 09
T 00 02 59 03 07 0D 01 27 0A 1E 02 F6 14 07 1E 02
R 00 00 00 09
T 00 02 66 F7 20 12
R 00 00 00 09
T 00 02 69
R 00 00 00 09
T 00 02 69 0D 04 27 0A 1E 05 F6 14 07 1E 05 F7 20
R 00 00 00 09
T 00 02 76 04
R 00 00 00 09
T 00 02 77
R 00 00 00 09
T 00 02 77 F6 14 07 F7
R 00 00 00 09
T 00 02 7B
R 00 00 00 09
T 00 02 7B 1E 0A 5B 0E FC
R 00 00 00 09
T 00 02 80
R 00 00 00 09
T 00 02 80 88 16 04 7B 05 6B 01 90 A3 01 01 26 0D
R 00 00 00 09
T 00 02 8D E6 05 14 01 27 04 A6 01 20 0C
R 00 00 00 09
T 00 02 97
R 00 00 00 09
T 00 02 97 4F 20 09
R 00 00 00 09
T 00 02 9A
R 00 00 00 09
T 00 02 9A F6 14 01 27 03 A6 01 21
R 00 00 00 09
T 00 02 A2
R 00 00 00 09
T 00 02 A2 4F
R 00 00 00 09
T 00 02 A3
R 00 00 00 09
T 00 02 A3 1E 02 5B 05 FC
R 00 00 00 09
T 00 02 A8
R 00 00 00 09
T 00 02 A8 16 03 90 53 90 9F F7 1E 01 5B 04 FC
R 00 00 00 09
T 00 02 B4
R 00 00 00 09
T 00 02 B4 52 09 1F 08 7B 0D 97 A4 0F 88 A6 01 6B
R 00 00 00 09
T 00 02 C1 04 84 4D 27 05
R 00 00 00 09
T 00 02 C6
R 00 00 00 09
T 00 02 C6 08 03 4A 26 FB
R 00 00 00 09
T 00 02 CB
R 00 00 00 09
T 00 02 CB 9F 4E A4 0F 88 A6 01 6B 08 84 4D 27 05
R 00 00 00 09
T 00 02 D8
R 00 00 00 09
T 00 02 D8 08 07 4A 26 FB
R 00 00 00 09
T 00 02 DD
R 00 00 00 09
T 00 02 DD 16 0C 17 01 16 08 17 04 1E 01 A3 01 00
R 00 00 00 09
T 00 02 EA 26 1D 16 08 17 01 93 E6 04 14 07 6B 07
R 00 00 00 09
T 00 02 F7 1E 04 F6 14 03 27 08 0D 07 27 04 A6 01
R 00 00 00 09
T 00 03 04 20 41
R 00 00 00 09
T 00 03 06
R 00 00 00 09
T 00 03 06 4F 20 3E
R 00 00 00 09
T 00 03 09
R 00 00 00 09
T 00 03 09 1E 08 E6 05 14 07 1E 01 A3 02 35 26 20
R 00 00 00 09
T 00 03 16 6B 06 1E 08 E6 08 A4 01 6B 07 1E 04 F6
R 00 00 00 09
T 00 03 23 14 03 27 0C 0D 06 26 04 0D 07 27 04
R 00 00 00 09
T 00 03 2F
R 00 00 00 09
T 00 03 2F A6 01 20 14
R 00 00 00 09
T 00 03 33
R 00 00 00 09
T 00 03 33 4F 20 11
R 00 00 00 09
T 00 03 36
R 00 00 00 09
T 00 03 36 6B 07 1E 04 F6 14 03 27 07 0D 07 27 03
R 00 00 00 09
T 00 03 43 A6 01 21
R 00 00 00 09
T 00 03 46
R 00 00 00 09
T 00 03 46 4F
R 00 00 00 09
T 00 03 47
R 00 00 00 09
T 00 03 47 1E 0A 5B 0D FC
R 00 00 00 09
T 00 03 4C
R 00 00 00 09
T 00 03 4C F6 A4 BF F7 1E 01 5B 04 FC
R 00 00 00 09

899
firmware/STM8L15X_LD/stm8l15x_usart.rst Normal file
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@@ -0,0 +1,899 @@
1 ;--------------------------------------------------------
2 ; File Created by SDCC : free open source ISO C Compiler
3 ; Version 4.5.0 #15242 (Linux)
4 ;--------------------------------------------------------
5 .module stm8l15x_usart
6
7 ;--------------------------------------------------------
8 ; Public variables in this module
9 ;--------------------------------------------------------
10 .globl _CLK_GetClockFreq
11 .globl _USART_DeInit
12 .globl _USART_Init
13 .globl _USART_ClockInit
14 .globl _USART_Cmd
15 .globl _USART_SetPrescaler
16 .globl _USART_SendBreak
17 .globl _USART_ReceiveData8
18 .globl _USART_ReceiveData9
19 .globl _USART_SendData8
20 .globl _USART_SendData9
21 .globl _USART_ReceiverWakeUpCmd
22 .globl _USART_SetAddress
23 .globl _USART_WakeUpConfig
24 .globl _USART_HalfDuplexCmd
25 .globl _USART_SmartCardCmd
26 .globl _USART_SmartCardNACKCmd
27 .globl _USART_SetGuardTime
28 .globl _USART_IrDAConfig
29 .globl _USART_IrDACmd
30 .globl _USART_DMACmd
31 .globl _USART_ITConfig
32 .globl _USART_GetFlagStatus
33 .globl _USART_ClearFlag
34 .globl _USART_GetITStatus
35 .globl _USART_ClearITPendingBit
36 ;--------------------------------------------------------
37 ; ram data
38 ;--------------------------------------------------------
39 .area DATA
40 ;--------------------------------------------------------
41 ; ram data
42 ;--------------------------------------------------------
43 .area INITIALIZED
44 ;--------------------------------------------------------
45 ; absolute external ram data
46 ;--------------------------------------------------------
47 .area DABS (ABS)
48
49 ; default segment ordering for linker
50 .area HOME
51 .area GSINIT
52 .area GSFINAL
53 .area CONST
54 .area INITIALIZER
55 .area CODE
56
57 ;--------------------------------------------------------
58 ; global & static initialisations
59 ;--------------------------------------------------------
60 .area HOME
61 .area GSINIT
62 .area GSFINAL
63 .area GSINIT
64 ;--------------------------------------------------------
65 ; Home
66 ;--------------------------------------------------------
67 .area HOME
68 .area HOME
69 ;--------------------------------------------------------
70 ; code
71 ;--------------------------------------------------------
72 .area CODE
73 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 148: void USART_DeInit(USART_TypeDef* USARTx)
74 ; -----------------------------------------
75 ; function USART_DeInit
76 ; -----------------------------------------
0081AD 77 _USART_DeInit:
78 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 154: (void) USARTx->DR;
0081AD 90 93 [ 1] 79 ldw y, x
0081AF E6 01 [ 1] 80 ld a, (0x1, x)
81 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 156: USARTx->BRR2 = USART_BRR2_RESET_VALUE; /* Set USART_BRR2 to reset value 0x00 */
0081B1 93 [ 1] 82 ldw x, y
0081B2 6F 03 [ 1] 83 clr (0x0003, x)
84 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 157: USARTx->BRR1 = USART_BRR1_RESET_VALUE; /* Set USART_BRR1 to reset value 0x00 */
0081B4 93 [ 1] 85 ldw x, y
0081B5 6F 02 [ 1] 86 clr (0x02, x)
87 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 159: USARTx->CR1 = USART_CR1_RESET_VALUE; /* Set USART_CR1 to reset value 0x00 */
0081B7 93 [ 1] 88 ldw x, y
0081B8 6F 04 [ 1] 89 clr (0x0004, x)
90 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 160: USARTx->CR2 = USART_CR2_RESET_VALUE; /* Set USART_CR2 to reset value 0x00 */
0081BA 93 [ 1] 91 ldw x, y
0081BB 6F 05 [ 1] 92 clr (0x0005, x)
93 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 161: USARTx->CR3 = USART_CR3_RESET_VALUE; /* Set USART_CR3 to reset value 0x00 */
0081BD 93 [ 1] 94 ldw x, y
0081BE 6F 06 [ 1] 95 clr (0x0006, x)
96 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 162: USARTx->CR4 = USART_CR4_RESET_VALUE; /* Set USART_CR4 to reset value 0x00 */
0081C0 93 [ 1] 97 ldw x, y
0081C1 6F 07 [ 1] 98 clr (0x0007, x)
99 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 163: }
0081C3 81 [ 4] 100 ret
101 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 192: void USART_Init(USART_TypeDef* USARTx, uint32_t BaudRate, USART_WordLength_TypeDef
102 ; -----------------------------------------
103 ; function USART_Init
104 ; -----------------------------------------
0081C4 105 _USART_Init:
0081C4 52 0B [ 2] 106 sub sp, #11
107 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 210: USARTx->CR1 &= (uint8_t)(~(USART_CR1_PCEN | USART_CR1_PS | USART_CR1_M));
0081C6 1F 0A [ 2] 108 ldw (0x0a, sp), x
0081C8 1C 00 04 [ 2] 109 addw x, #0x0004
0081CB F6 [ 1] 110 ld a, (x)
0081CC A4 E9 [ 1] 111 and a, #0xe9
0081CE 6B 09 [ 1] 112 ld (0x09, sp), a
0081D0 F7 [ 1] 113 ld (x), a
114 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 213: USARTx->CR1 |= (uint8_t)((uint8_t)USART_WordLength | (uint8_t)USART_Parity);
0081D1 7B 12 [ 1] 115 ld a, (0x12, sp)
0081D3 1A 14 [ 1] 116 or a, (0x14, sp)
0081D5 1A 09 [ 1] 117 or a, (0x09, sp)
0081D7 F7 [ 1] 118 ld (x), a
119 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 216: USARTx->CR3 &= (uint8_t)(~USART_CR3_STOP);
0081D8 1E 0A [ 2] 120 ldw x, (0x0a, sp)
0081DA 1C 00 06 [ 2] 121 addw x, #0x0006
0081DD F6 [ 1] 122 ld a, (x)
0081DE A4 CF [ 1] 123 and a, #0xcf
0081E0 F7 [ 1] 124 ld (x), a
125 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 218: USARTx->CR3 |= (uint8_t)USART_StopBits;
0081E1 1A 13 [ 1] 126 or a, (0x13, sp)
0081E3 F7 [ 1] 127 ld (x), a
128 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 221: USARTx->BRR1 &= (uint8_t)(~USART_BRR1_DIVM);
0081E4 1E 0A [ 2] 129 ldw x, (0x0a, sp)
0081E6 5C [ 1] 130 incw x
0081E7 5C [ 1] 131 incw x
0081E8 1F 01 [ 2] 132 ldw (0x01, sp), x
0081EA F6 [ 1] 133 ld a, (x)
0081EB 1E 01 [ 2] 134 ldw x, (0x01, sp)
0081ED 7F [ 1] 135 clr (x)
136 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 223: USARTx->BRR2 &= (uint8_t)(~USART_BRR2_DIVM);
0081EE 1E 0A [ 2] 137 ldw x, (0x0a, sp)
0081F0 1C 00 03 [ 2] 138 addw x, #0x0003
0081F3 1F 03 [ 2] 139 ldw (0x03, sp), x
0081F5 F6 [ 1] 140 ld a, (x)
0081F6 A4 0F [ 1] 141 and a, #0x0f
0081F8 1E 03 [ 2] 142 ldw x, (0x03, sp)
0081FA F7 [ 1] 143 ld (x), a
144 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 225: USARTx->BRR2 &= (uint8_t)(~USART_BRR2_DIVF);
0081FB 1E 03 [ 2] 145 ldw x, (0x03, sp)
0081FD 7F [ 1] 146 clr (x)
147 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 227: BaudRate_Mantissa = (uint32_t)(CLK_GetClockFreq() / BaudRate );
0081FE CD 85 D6 [ 4] 148 call _CLK_GetClockFreq
008201 1F 08 [ 2] 149 ldw (0x08, sp), x
008203 1E 10 [ 2] 150 ldw x, (0x10, sp)
008205 89 [ 2] 151 pushw x
008206 1E 10 [ 2] 152 ldw x, (0x10, sp)
008208 89 [ 2] 153 pushw x
008209 1E 0C [ 2] 154 ldw x, (0x0c, sp)
00820B 89 [ 2] 155 pushw x
00820C 90 89 [ 2] 156 pushw y
157 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 229: USARTx->BRR2 = (uint8_t)((BaudRate_Mantissa >> (uint8_t)8) & (uint8_t)0xF0);
00820E CD 92 5C [ 4] 158 call __divulong
008211 5B 08 [ 2] 159 addw sp, #8
008213 17 05 [ 2] 160 ldw (0x05, sp), y
008215 9E [ 1] 161 ld a, xh
008216 A4 F0 [ 1] 162 and a, #0xf0
008218 6B 09 [ 1] 163 ld (0x09, sp), a
00821A 16 03 [ 2] 164 ldw y, (0x03, sp)
00821C 7B 09 [ 1] 165 ld a, (0x09, sp)
00821E 90 F7 [ 1] 166 ld (y), a
167 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 231: USARTx->BRR2 |= (uint8_t)(BaudRate_Mantissa & (uint8_t)0x0F);
008220 9F [ 1] 168 ld a, xl
008221 A4 0F [ 1] 169 and a, #0x0f
008223 1A 09 [ 1] 170 or a, (0x09, sp)
008225 16 03 [ 2] 171 ldw y, (0x03, sp)
008227 90 F7 [ 1] 172 ld (y), a
173 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 233: USARTx->BRR1 = (uint8_t)(BaudRate_Mantissa >> (uint8_t)4);
008229 A6 10 [ 1] 174 ld a, #0x10
00822B 62 [ 2] 175 div x, a
00822C 9F [ 1] 176 ld a, xl
00822D 1E 01 [ 2] 177 ldw x, (0x01, sp)
00822F F7 [ 1] 178 ld (x), a
179 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 236: USARTx->CR2 &= (uint8_t)~(USART_CR2_TEN | USART_CR2_REN);
008230 1E 0A [ 2] 180 ldw x, (0x0a, sp)
008232 1C 00 05 [ 2] 181 addw x, #0x0005
008235 F6 [ 1] 182 ld a, (x)
008236 A4 F3 [ 1] 183 and a, #0xf3
008238 F7 [ 1] 184 ld (x), a
185 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 238: USARTx->CR2 |= (uint8_t)USART_Mode;
008239 1A 15 [ 1] 186 or a, (0x15, sp)
00823B F7 [ 1] 187 ld (x), a
188 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 239: }
00823C 1E 0C [ 2] 189 ldw x, (12, sp)
00823E 5B 15 [ 2] 190 addw sp, #21
008240 FC [ 2] 191 jp (x)
192 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 264: void USART_ClockInit(USART_TypeDef* USARTx, USART_Clock_TypeDef USART_Clock,
193 ; -----------------------------------------
194 ; function USART_ClockInit
195 ; -----------------------------------------
008241 196 _USART_ClockInit:
008241 52 05 [ 2] 197 sub sp, #5
008243 6B 05 [ 1] 198 ld (0x05, sp), a
199 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 275: USARTx->CR3 &= (uint8_t)~(USART_CR3_CPOL | USART_CR3_CPHA | USART_CR3_LBCL);
008245 1C 00 06 [ 2] 200 addw x, #0x0006
008248 1F 01 [ 2] 201 ldw (0x01, sp), x
00824A F6 [ 1] 202 ld a, (x)
00824B A4 F8 [ 1] 203 and a, #0xf8
00824D 6B 03 [ 1] 204 ld (0x03, sp), a
00824F 1E 01 [ 2] 205 ldw x, (0x01, sp)
008251 7B 03 [ 1] 206 ld a, (0x03, sp)
008253 F7 [ 1] 207 ld (x), a
208 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 277: USARTx->CR3 |= (uint8_t)((uint8_t)((uint8_t)(USART_CPOL | (uint8_t)USART_CPHA ) | USART_LastBit));
008254 7B 08 [ 1] 209 ld a, (0x08, sp)
008256 1A 09 [ 1] 210 or a, (0x09, sp)
008258 6B 04 [ 1] 211 ld (0x04, sp), a
00825A 7B 0A [ 1] 212 ld a, (0x0a, sp)
00825C 1A 04 [ 1] 213 or a, (0x04, sp)
00825E 1A 03 [ 1] 214 or a, (0x03, sp)
008260 1E 01 [ 2] 215 ldw x, (0x01, sp)
008262 F7 [ 1] 216 ld (x), a
217 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 275: USARTx->CR3 &= (uint8_t)~(USART_CR3_CPOL | USART_CR3_CPHA | USART_CR3_LBCL);
008263 1E 01 [ 2] 218 ldw x, (0x01, sp)
008265 F6 [ 1] 219 ld a, (x)
220 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 279: if (USART_Clock != USART_Clock_Disable)
008266 0D 05 [ 1] 221 tnz (0x05, sp)
008268 27 07 [ 1] 222 jreq 00102$
223 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 281: USARTx->CR3 |= (uint8_t)(USART_CR3_CLKEN); /* Set the Clock Enable bit */
00826A AA 08 [ 1] 224 or a, #0x08
00826C 1E 01 [ 2] 225 ldw x, (0x01, sp)
00826E F7 [ 1] 226 ld (x), a
00826F 20 05 [ 2] 227 jra 00104$
008271 228 00102$:
229 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 285: USARTx->CR3 &= (uint8_t)(~USART_CR3_CLKEN); /* Clear the Clock Enable bit */
008271 A4 F7 [ 1] 230 and a, #0xf7
008273 1E 01 [ 2] 231 ldw x, (0x01, sp)
008275 F7 [ 1] 232 ld (x), a
008276 233 00104$:
234 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 287: }
008276 1E 06 [ 2] 235 ldw x, (6, sp)
008278 5B 0A [ 2] 236 addw sp, #10
00827A FC [ 2] 237 jp (x)
238 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 296: void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
239 ; -----------------------------------------
240 ; function USART_Cmd
241 ; -----------------------------------------
00827B 242 _USART_Cmd:
00827B 88 [ 1] 243 push a
00827C 6B 01 [ 1] 244 ld (0x01, sp), a
245 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 300: USARTx->CR1 &= (uint8_t)(~USART_CR1_USARTD); /**< USART Enable */
00827E 1C 00 04 [ 2] 246 addw x, #0x0004
008281 F6 [ 1] 247 ld a, (x)
248 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 298: if (NewState != DISABLE)
008282 0D 01 [ 1] 249 tnz (0x01, sp)
008284 27 05 [ 1] 250 jreq 00102$
251 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 300: USARTx->CR1 &= (uint8_t)(~USART_CR1_USARTD); /**< USART Enable */
008286 A4 DF [ 1] 252 and a, #0xdf
008288 F7 [ 1] 253 ld (x), a
008289 20 03 [ 2] 254 jra 00104$
00828B 255 00102$:
256 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 304: USARTx->CR1 |= USART_CR1_USARTD; /**< USART Disable (for low power consumption) */
00828B AA 20 [ 1] 257 or a, #0x20
00828D F7 [ 1] 258 ld (x), a
00828E 259 00104$:
260 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 306: }
00828E 84 [ 1] 261 pop a
00828F 81 [ 4] 262 ret
263 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 329: void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
264 ; -----------------------------------------
265 ; function USART_SetPrescaler
266 ; -----------------------------------------
008290 267 _USART_SetPrescaler:
268 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 332: USARTx->PSCR = USART_Prescaler;
008290 1C 00 0A [ 2] 269 addw x, #0x000a
008293 F7 [ 1] 270 ld (x), a
271 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 333: }
008294 81 [ 4] 272 ret
273 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 340: void USART_SendBreak(USART_TypeDef* USARTx)
274 ; -----------------------------------------
275 ; function USART_SendBreak
276 ; -----------------------------------------
008295 277 _USART_SendBreak:
278 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 342: USARTx->CR2 |= USART_CR2_SBK;
008295 1C 00 05 [ 2] 279 addw x, #0x0005
008298 F6 [ 1] 280 ld a, (x)
008299 AA 01 [ 1] 281 or a, #0x01
00829B F7 [ 1] 282 ld (x), a
283 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 343: }
00829C 81 [ 4] 284 ret
285 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 382: uint8_t USART_ReceiveData8(USART_TypeDef* USARTx)
286 ; -----------------------------------------
287 ; function USART_ReceiveData8
288 ; -----------------------------------------
00829D 289 _USART_ReceiveData8:
290 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 384: return USARTx->DR;
00829D E6 01 [ 1] 291 ld a, (0x1, x)
292 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 385: }
00829F 81 [ 4] 293 ret
294 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 392: uint16_t USART_ReceiveData9(USART_TypeDef* USARTx)
295 ; -----------------------------------------
296 ; function USART_ReceiveData9
297 ; -----------------------------------------
0082A0 298 _USART_ReceiveData9:
0082A0 89 [ 2] 299 pushw x
300 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 396: temp = ((uint16_t)(((uint16_t)((uint16_t)USARTx->CR1 & (uint16_t)USART_CR1_R8)) << 1));
0082A1 90 93 [ 1] 301 ldw y, x
0082A3 E6 04 [ 1] 302 ld a, (0x4, x)
0082A5 A4 80 [ 1] 303 and a, #0x80
0082A7 97 [ 1] 304 ld xl, a
0082A8 4F [ 1] 305 clr a
0082A9 95 [ 1] 306 ld xh, a
0082AA 58 [ 2] 307 sllw x
0082AB 1F 01 [ 2] 308 ldw (0x01, sp), x
309 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 397: return (uint16_t)( ((uint16_t)((uint16_t)USARTx->DR) | temp) & ((uint16_t)0x01FF));
0082AD 90 E6 01 [ 1] 310 ld a, (0x1, y)
0082B0 1A 02 [ 1] 311 or a, (0x02, sp)
0082B2 97 [ 1] 312 ld xl, a
0082B3 7B 01 [ 1] 313 ld a, (0x01, sp)
0082B5 A4 01 [ 1] 314 and a, #0x01
0082B7 95 [ 1] 315 ld xh, a
316 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 398: }
0082B8 5B 02 [ 2] 317 addw sp, #2
0082BA 81 [ 4] 318 ret
319 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 405: void USART_SendData8(USART_TypeDef* USARTx, uint8_t Data)
320 ; -----------------------------------------
321 ; function USART_SendData8
322 ; -----------------------------------------
0082BB 323 _USART_SendData8:
324 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 408: USARTx->DR = Data;
0082BB 5C [ 1] 325 incw x
0082BC F7 [ 1] 326 ld (x), a
327 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 409: }
0082BD 81 [ 4] 328 ret
329 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 418: void USART_SendData9(USART_TypeDef* USARTx, uint16_t Data)
330 ; -----------------------------------------
331 ; function USART_SendData9
332 ; -----------------------------------------
0082BE 333 _USART_SendData9:
0082BE 52 03 [ 2] 334 sub sp, #3
335 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 423: USARTx->CR1 &= ((uint8_t)~USART_CR1_T8);
0082C0 1F 02 [ 2] 336 ldw (0x02, sp), x
0082C2 1C 00 04 [ 2] 337 addw x, #0x0004
0082C5 F6 [ 1] 338 ld a, (x)
0082C6 A4 BF [ 1] 339 and a, #0xbf
0082C8 6B 01 [ 1] 340 ld (0x01, sp), a
0082CA F7 [ 1] 341 ld (x), a
342 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 426: USARTx->CR1 |= (uint8_t)(((uint8_t)(Data >> 2)) & USART_CR1_T8);
0082CB 16 06 [ 2] 343 ldw y, (0x06, sp)
0082CD 90 54 [ 2] 344 srlw y
0082CF 90 54 [ 2] 345 srlw y
0082D1 90 9F [ 1] 346 ld a, yl
0082D3 A4 40 [ 1] 347 and a, #0x40
0082D5 1A 01 [ 1] 348 or a, (0x01, sp)
0082D7 F7 [ 1] 349 ld (x), a
350 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 429: USARTx->DR = (uint8_t)(Data);
0082D8 1E 02 [ 2] 351 ldw x, (0x02, sp)
0082DA 5C [ 1] 352 incw x
0082DB 7B 07 [ 1] 353 ld a, (0x07, sp)
0082DD F7 [ 1] 354 ld (x), a
355 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 430: }
0082DE 1E 04 [ 2] 356 ldw x, (4, sp)
0082E0 5B 07 [ 2] 357 addw sp, #7
0082E2 FC [ 2] 358 jp (x)
359 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 473: void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
360 ; -----------------------------------------
361 ; function USART_ReceiverWakeUpCmd
362 ; -----------------------------------------
0082E3 363 _USART_ReceiverWakeUpCmd:
0082E3 88 [ 1] 364 push a
0082E4 6B 01 [ 1] 365 ld (0x01, sp), a
366 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 480: USARTx->CR2 |= USART_CR2_RWU;
0082E6 1C 00 05 [ 2] 367 addw x, #0x0005
0082E9 F6 [ 1] 368 ld a, (x)
369 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 477: if (NewState != DISABLE)
0082EA 0D 01 [ 1] 370 tnz (0x01, sp)
0082EC 27 05 [ 1] 371 jreq 00102$
372 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 480: USARTx->CR2 |= USART_CR2_RWU;
0082EE AA 02 [ 1] 373 or a, #0x02
0082F0 F7 [ 1] 374 ld (x), a
0082F1 20 03 [ 2] 375 jra 00104$
0082F3 376 00102$:
377 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 485: USARTx->CR2 &= ((uint8_t)~USART_CR2_RWU);
0082F3 A4 FD [ 1] 378 and a, #0xfd
0082F5 F7 [ 1] 379 ld (x), a
0082F6 380 00104$:
381 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 487: }
0082F6 84 [ 1] 382 pop a
0082F7 81 [ 4] 383 ret
384 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 496: void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
385 ; -----------------------------------------
386 ; function USART_SetAddress
387 ; -----------------------------------------
0082F8 388 _USART_SetAddress:
0082F8 88 [ 1] 389 push a
0082F9 6B 01 [ 1] 390 ld (0x01, sp), a
391 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 502: USARTx->CR4 &= ((uint8_t)~USART_CR4_ADD);
0082FB 1C 00 07 [ 2] 392 addw x, #0x0007
0082FE F6 [ 1] 393 ld a, (x)
0082FF A4 F0 [ 1] 394 and a, #0xf0
008301 F7 [ 1] 395 ld (x), a
396 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 504: USARTx->CR4 |= USART_Address;
008302 1A 01 [ 1] 397 or a, (0x01, sp)
008304 F7 [ 1] 398 ld (x), a
399 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 505: }
008305 84 [ 1] 400 pop a
008306 81 [ 4] 401 ret
402 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 515: void USART_WakeUpConfig(USART_TypeDef* USARTx, USART_WakeUp_TypeDef USART_WakeUp)
403 ; -----------------------------------------
404 ; function USART_WakeUpConfig
405 ; -----------------------------------------
008307 406 _USART_WakeUpConfig:
008307 88 [ 1] 407 push a
008308 6B 01 [ 1] 408 ld (0x01, sp), a
409 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 519: USARTx->CR1 &= ((uint8_t)~USART_CR1_WAKE);
00830A 1C 00 04 [ 2] 410 addw x, #0x0004
00830D F6 [ 1] 411 ld a, (x)
00830E A4 F7 [ 1] 412 and a, #0xf7
008310 F7 [ 1] 413 ld (x), a
414 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 520: USARTx->CR1 |= (uint8_t)USART_WakeUp;
008311 1A 01 [ 1] 415 or a, (0x01, sp)
008313 F7 [ 1] 416 ld (x), a
417 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 521: }
008314 84 [ 1] 418 pop a
008315 81 [ 4] 419 ret
420 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 566: void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
421 ; -----------------------------------------
422 ; function USART_HalfDuplexCmd
423 ; -----------------------------------------
008316 424 _USART_HalfDuplexCmd:
008316 88 [ 1] 425 push a
008317 6B 01 [ 1] 426 ld (0x01, sp), a
427 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 572: USARTx->CR5 |= USART_CR5_HDSEL; /**< USART Half Duplex Enable */
008319 1C 00 08 [ 2] 428 addw x, #0x0008
00831C F6 [ 1] 429 ld a, (x)
430 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 570: if (NewState != DISABLE)
00831D 0D 01 [ 1] 431 tnz (0x01, sp)
00831F 27 05 [ 1] 432 jreq 00102$
433 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 572: USARTx->CR5 |= USART_CR5_HDSEL; /**< USART Half Duplex Enable */
008321 AA 08 [ 1] 434 or a, #0x08
008323 F7 [ 1] 435 ld (x), a
008324 20 03 [ 2] 436 jra 00104$
008326 437 00102$:
438 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 576: USARTx->CR5 &= (uint8_t)~USART_CR5_HDSEL; /**< USART Half Duplex Disable */
008326 A4 F7 [ 1] 439 and a, #0xf7
008328 F7 [ 1] 440 ld (x), a
008329 441 00104$:
442 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 578: }
008329 84 [ 1] 443 pop a
00832A 81 [ 4] 444 ret
445 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 644: void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
446 ; -----------------------------------------
447 ; function USART_SmartCardCmd
448 ; -----------------------------------------
00832B 449 _USART_SmartCardCmd:
00832B 88 [ 1] 450 push a
00832C 6B 01 [ 1] 451 ld (0x01, sp), a
452 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 651: USARTx->CR5 |= USART_CR5_SCEN;
00832E 1C 00 08 [ 2] 453 addw x, #0x0008
008331 F6 [ 1] 454 ld a, (x)
455 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 648: if (NewState != DISABLE)
008332 0D 01 [ 1] 456 tnz (0x01, sp)
008334 27 05 [ 1] 457 jreq 00102$
458 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 651: USARTx->CR5 |= USART_CR5_SCEN;
008336 AA 20 [ 1] 459 or a, #0x20
008338 F7 [ 1] 460 ld (x), a
008339 20 03 [ 2] 461 jra 00104$
00833B 462 00102$:
463 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 656: USARTx->CR5 &= ((uint8_t)(~USART_CR5_SCEN));
00833B A4 DF [ 1] 464 and a, #0xdf
00833D F7 [ 1] 465 ld (x), a
00833E 466 00104$:
467 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 658: }
00833E 84 [ 1] 468 pop a
00833F 81 [ 4] 469 ret
470 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 667: void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
471 ; -----------------------------------------
472 ; function USART_SmartCardNACKCmd
473 ; -----------------------------------------
008340 474 _USART_SmartCardNACKCmd:
008340 88 [ 1] 475 push a
008341 6B 01 [ 1] 476 ld (0x01, sp), a
477 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 674: USARTx->CR5 |= USART_CR5_NACK;
008343 1C 00 08 [ 2] 478 addw x, #0x0008
008346 F6 [ 1] 479 ld a, (x)
480 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 671: if (NewState != DISABLE)
008347 0D 01 [ 1] 481 tnz (0x01, sp)
008349 27 05 [ 1] 482 jreq 00102$
483 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 674: USARTx->CR5 |= USART_CR5_NACK;
00834B AA 10 [ 1] 484 or a, #0x10
00834D F7 [ 1] 485 ld (x), a
00834E 20 03 [ 2] 486 jra 00104$
008350 487 00102$:
488 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 679: USARTx->CR5 &= ((uint8_t)~(USART_CR5_NACK));
008350 A4 EF [ 1] 489 and a, #0xef
008352 F7 [ 1] 490 ld (x), a
008353 491 00104$:
492 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 681: }
008353 84 [ 1] 493 pop a
008354 81 [ 4] 494 ret
495 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 690: void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
496 ; -----------------------------------------
497 ; function USART_SetGuardTime
498 ; -----------------------------------------
008355 499 _USART_SetGuardTime:
500 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 693: USARTx->GTR = USART_GuardTime;
008355 1C 00 09 [ 2] 501 addw x, #0x0009
008358 F7 [ 1] 502 ld (x), a
503 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 694: }
008359 81 [ 4] 504 ret
505 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 751: void USART_IrDAConfig(USART_TypeDef* USARTx, USART_IrDAMode_TypeDef USART_IrDAMode)
506 ; -----------------------------------------
507 ; function USART_IrDAConfig
508 ; -----------------------------------------
00835A 509 _USART_IrDAConfig:
00835A 88 [ 1] 510 push a
00835B 6B 01 [ 1] 511 ld (0x01, sp), a
512 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 757: USARTx->CR5 |= USART_CR5_IRLP;
00835D 1C 00 08 [ 2] 513 addw x, #0x0008
008360 F6 [ 1] 514 ld a, (x)
515 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 755: if (USART_IrDAMode != USART_IrDAMode_Normal)
008361 0D 01 [ 1] 516 tnz (0x01, sp)
008363 27 05 [ 1] 517 jreq 00102$
518 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 757: USARTx->CR5 |= USART_CR5_IRLP;
008365 AA 04 [ 1] 519 or a, #0x04
008367 F7 [ 1] 520 ld (x), a
008368 20 03 [ 2] 521 jra 00104$
00836A 522 00102$:
523 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 761: USARTx->CR5 &= ((uint8_t)~USART_CR5_IRLP);
00836A A4 FB [ 1] 524 and a, #0xfb
00836C F7 [ 1] 525 ld (x), a
00836D 526 00104$:
527 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 763: }
00836D 84 [ 1] 528 pop a
00836E 81 [ 4] 529 ret
530 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 772: void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
531 ; -----------------------------------------
532 ; function USART_IrDACmd
533 ; -----------------------------------------
00836F 534 _USART_IrDACmd:
00836F 88 [ 1] 535 push a
008370 6B 01 [ 1] 536 ld (0x01, sp), a
537 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 781: USARTx->CR5 |= USART_CR5_IREN;
008372 1C 00 08 [ 2] 538 addw x, #0x0008
008375 F6 [ 1] 539 ld a, (x)
540 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 778: if (NewState != DISABLE)
008376 0D 01 [ 1] 541 tnz (0x01, sp)
008378 27 05 [ 1] 542 jreq 00102$
543 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 781: USARTx->CR5 |= USART_CR5_IREN;
00837A AA 02 [ 1] 544 or a, #0x02
00837C F7 [ 1] 545 ld (x), a
00837D 20 03 [ 2] 546 jra 00104$
00837F 547 00102$:
548 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 786: USARTx->CR5 &= ((uint8_t)~USART_CR5_IREN);
00837F A4 FD [ 1] 549 and a, #0xfd
008381 F7 [ 1] 550 ld (x), a
008382 551 00104$:
552 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 788: }
008382 84 [ 1] 553 pop a
008383 81 [ 4] 554 ret
555 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 818: void USART_DMACmd(USART_TypeDef* USARTx, USART_DMAReq_TypeDef USART_DMAReq,
556 ; -----------------------------------------
557 ; function USART_DMACmd
558 ; -----------------------------------------
008384 559 _USART_DMACmd:
008384 88 [ 1] 560 push a
561 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 829: USARTx->CR5 |= (uint8_t) USART_DMAReq;
008385 1C 00 08 [ 2] 562 addw x, #0x0008
008388 88 [ 1] 563 push a
008389 F6 [ 1] 564 ld a, (x)
00838A 6B 02 [ 1] 565 ld (0x02, sp), a
00838C 84 [ 1] 566 pop a
567 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 825: if (NewState != DISABLE)
00838D 0D 04 [ 1] 568 tnz (0x04, sp)
00838F 27 05 [ 1] 569 jreq 00102$
570 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 829: USARTx->CR5 |= (uint8_t) USART_DMAReq;
008391 1A 01 [ 1] 571 or a, (0x01, sp)
008393 F7 [ 1] 572 ld (x), a
008394 20 04 [ 2] 573 jra 00104$
008396 574 00102$:
575 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 835: USARTx->CR5 &= (uint8_t)~USART_DMAReq;
008396 43 [ 1] 576 cpl a
008397 14 01 [ 1] 577 and a, (0x01, sp)
008399 F7 [ 1] 578 ld (x), a
00839A 579 00104$:
580 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 837: }
00839A 84 [ 1] 581 pop a
00839B 85 [ 2] 582 popw x
00839C 84 [ 1] 583 pop a
00839D FC [ 2] 584 jp (x)
585 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 939: void USART_ITConfig(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT, FunctionalState NewState)
586 ; -----------------------------------------
587 ; function USART_ITConfig
588 ; -----------------------------------------
00839E 589 _USART_ITConfig:
00839E 52 09 [ 2] 590 sub sp, #9
0083A0 1F 08 [ 2] 591 ldw (0x08, sp), x
592 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 946: usartreg = (uint8_t)((uint16_t)USART_IT >> 0x08);
0083A2 1E 0C [ 2] 593 ldw x, (0x0c, sp)
594 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 948: itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)USART_IT & (uint8_t)0x0F));
0083A4 7B 0D [ 1] 595 ld a, (0x0d, sp)
0083A6 A4 0F [ 1] 596 and a, #0x0f
0083A8 88 [ 1] 597 push a
0083A9 A6 01 [ 1] 598 ld a, #0x01
0083AB 6B 08 [ 1] 599 ld (0x08, sp), a
0083AD 84 [ 1] 600 pop a
0083AE 4D [ 1] 601 tnz a
0083AF 27 05 [ 1] 602 jreq 00154$
0083B1 603 00153$:
0083B1 08 07 [ 1] 604 sll (0x07, sp)
0083B3 4A [ 1] 605 dec a
0083B4 26 FB [ 1] 606 jrne 00153$
0083B6 607 00154$:
608 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 953: if (usartreg == 0x01)
0083B6 9E [ 1] 609 ld a, xh
0083B7 4A [ 1] 610 dec a
0083B8 26 05 [ 1] 611 jrne 00156$
0083BA A6 01 [ 1] 612 ld a, #0x01
0083BC 6B 01 [ 1] 613 ld (0x01, sp), a
0083BE C5 614 .byte 0xc5
0083BF 615 00156$:
0083BF 0F 01 [ 1] 616 clr (0x01, sp)
0083C1 617 00157$:
618 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 955: USARTx->CR1 |= itpos;
0083C1 16 08 [ 2] 619 ldw y, (0x08, sp)
0083C3 72 A9 00 04 [ 2] 620 addw y, #0x0004
0083C7 17 02 [ 2] 621 ldw (0x02, sp), y
622 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 957: else if (usartreg == 0x05)
0083C9 9E [ 1] 623 ld a, xh
0083CA A0 05 [ 1] 624 sub a, #0x05
0083CC 26 04 [ 1] 625 jrne 00159$
0083CE 4C [ 1] 626 inc a
0083CF 6B 04 [ 1] 627 ld (0x04, sp), a
0083D1 C5 628 .byte 0xc5
0083D2 629 00159$:
0083D2 0F 04 [ 1] 630 clr (0x04, sp)
0083D4 631 00160$:
632 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 959: USARTx->CR5 |= itpos;
0083D4 1E 08 [ 2] 633 ldw x, (0x08, sp)
0083D6 1C 00 08 [ 2] 634 addw x, #0x0008
0083D9 1F 05 [ 2] 635 ldw (0x05, sp), x
636 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 964: USARTx->CR2 |= itpos;
0083DB 1E 08 [ 2] 637 ldw x, (0x08, sp)
0083DD 1C 00 05 [ 2] 638 addw x, #0x0005
639 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 950: if (NewState != DISABLE)
0083E0 0D 0E [ 1] 640 tnz (0x0e, sp)
0083E2 27 22 [ 1] 641 jreq 00114$
642 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 953: if (usartreg == 0x01)
0083E4 0D 01 [ 1] 643 tnz (0x01, sp)
0083E6 27 0A [ 1] 644 jreq 00105$
645 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 955: USARTx->CR1 |= itpos;
0083E8 1E 02 [ 2] 646 ldw x, (0x02, sp)
0083EA F6 [ 1] 647 ld a, (x)
0083EB 1A 07 [ 1] 648 or a, (0x07, sp)
0083ED 1E 02 [ 2] 649 ldw x, (0x02, sp)
0083EF F7 [ 1] 650 ld (x), a
0083F0 20 36 [ 2] 651 jra 00116$
0083F2 652 00105$:
653 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 957: else if (usartreg == 0x05)
0083F2 0D 04 [ 1] 654 tnz (0x04, sp)
0083F4 27 0A [ 1] 655 jreq 00102$
656 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 959: USARTx->CR5 |= itpos;
0083F6 1E 05 [ 2] 657 ldw x, (0x05, sp)
0083F8 F6 [ 1] 658 ld a, (x)
0083F9 1A 07 [ 1] 659 or a, (0x07, sp)
0083FB 1E 05 [ 2] 660 ldw x, (0x05, sp)
0083FD F7 [ 1] 661 ld (x), a
0083FE 20 28 [ 2] 662 jra 00116$
008400 663 00102$:
664 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 964: USARTx->CR2 |= itpos;
008400 F6 [ 1] 665 ld a, (x)
008401 1A 07 [ 1] 666 or a, (0x07, sp)
008403 F7 [ 1] 667 ld (x), a
008404 20 22 [ 2] 668 jra 00116$
008406 669 00114$:
670 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 972: USARTx->CR1 &= (uint8_t)(~itpos);
008406 03 07 [ 1] 671 cpl (0x07, sp)
672 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 970: if (usartreg == 0x01)
008408 0D 01 [ 1] 673 tnz (0x01, sp)
00840A 27 0A [ 1] 674 jreq 00111$
675 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 972: USARTx->CR1 &= (uint8_t)(~itpos);
00840C 1E 02 [ 2] 676 ldw x, (0x02, sp)
00840E F6 [ 1] 677 ld a, (x)
00840F 14 07 [ 1] 678 and a, (0x07, sp)
008411 1E 02 [ 2] 679 ldw x, (0x02, sp)
008413 F7 [ 1] 680 ld (x), a
008414 20 12 [ 2] 681 jra 00116$
008416 682 00111$:
683 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 974: else if (usartreg == 0x05)
008416 0D 04 [ 1] 684 tnz (0x04, sp)
008418 27 0A [ 1] 685 jreq 00108$
686 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 976: USARTx->CR5 &= (uint8_t)(~itpos);
00841A 1E 05 [ 2] 687 ldw x, (0x05, sp)
00841C F6 [ 1] 688 ld a, (x)
00841D 14 07 [ 1] 689 and a, (0x07, sp)
00841F 1E 05 [ 2] 690 ldw x, (0x05, sp)
008421 F7 [ 1] 691 ld (x), a
008422 20 04 [ 2] 692 jra 00116$
008424 693 00108$:
694 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 981: USARTx->CR2 &= (uint8_t)(~itpos);
008424 F6 [ 1] 695 ld a, (x)
008425 14 07 [ 1] 696 and a, (0x07, sp)
008427 F7 [ 1] 697 ld (x), a
008428 698 00116$:
699 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 984: }
008428 1E 0A [ 2] 700 ldw x, (10, sp)
00842A 5B 0E [ 2] 701 addw sp, #14
00842C FC [ 2] 702 jp (x)
703 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1002: FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG)
704 ; -----------------------------------------
705 ; function USART_GetFlagStatus
706 ; -----------------------------------------
00842D 707 _USART_GetFlagStatus:
00842D 88 [ 1] 708 push a
709 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1009: if (USART_FLAG == USART_FLAG_SBK)
00842E 16 04 [ 2] 710 ldw y, (0x04, sp)
711 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1011: if ((USARTx->CR2 & (uint8_t)USART_FLAG) != (uint8_t)0x00)
008430 7B 05 [ 1] 712 ld a, (0x05, sp)
008432 6B 01 [ 1] 713 ld (0x01, sp), a
714 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1009: if (USART_FLAG == USART_FLAG_SBK)
008434 90 A3 01 01 [ 2] 715 cpw y, #0x0101
008438 26 0D [ 1] 716 jrne 00108$
717 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1011: if ((USARTx->CR2 & (uint8_t)USART_FLAG) != (uint8_t)0x00)
00843A E6 05 [ 1] 718 ld a, (0x5, x)
00843C 14 01 [ 1] 719 and a, (0x01, sp)
00843E 27 04 [ 1] 720 jreq 00102$
721 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1014: status = SET;
008440 A6 01 [ 1] 722 ld a, #0x01
008442 20 0C [ 2] 723 jra 00109$
008444 724 00102$:
725 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1019: status = RESET;
008444 4F [ 1] 726 clr a
008445 20 09 [ 2] 727 jra 00109$
008447 728 00108$:
729 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1024: if ((USARTx->SR & (uint8_t)USART_FLAG) != (uint8_t)0x00)
008447 F6 [ 1] 730 ld a, (x)
008448 14 01 [ 1] 731 and a, (0x01, sp)
00844A 27 03 [ 1] 732 jreq 00105$
733 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1027: status = SET;
00844C A6 01 [ 1] 734 ld a, #0x01
735 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1032: status = RESET;
00844E 21 736 .byte 0x21
00844F 737 00105$:
00844F 4F [ 1] 738 clr a
008450 739 00109$:
740 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1036: return status;
741 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1037: }
008450 1E 02 [ 2] 742 ldw x, (2, sp)
008452 5B 05 [ 2] 743 addw sp, #5
008454 FC [ 2] 744 jp (x)
745 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1060: void USART_ClearFlag(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG)
746 ; -----------------------------------------
747 ; function USART_ClearFlag
748 ; -----------------------------------------
008455 749 _USART_ClearFlag:
750 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1065: USARTx->SR = (uint8_t)((uint16_t)~((uint16_t)USART_FLAG));
008455 16 03 [ 2] 751 ldw y, (0x03, sp)
008457 90 53 [ 2] 752 cplw y
008459 90 9F [ 1] 753 ld a, yl
00845B F7 [ 1] 754 ld (x), a
755 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1066: }
00845C 1E 01 [ 2] 756 ldw x, (1, sp)
00845E 5B 04 [ 2] 757 addw sp, #4
008460 FC [ 2] 758 jp (x)
759 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1083: ITStatus USART_GetITStatus(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT)
760 ; -----------------------------------------
761 ; function USART_GetITStatus
762 ; -----------------------------------------
008461 763 _USART_GetITStatus:
008461 52 09 [ 2] 764 sub sp, #9
008463 1F 08 [ 2] 765 ldw (0x08, sp), x
766 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1096: itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)USART_IT & (uint8_t)0x0F));
008465 7B 0D [ 1] 767 ld a, (0x0d, sp)
008467 97 [ 1] 768 ld xl, a
008468 A4 0F [ 1] 769 and a, #0x0f
00846A 88 [ 1] 770 push a
00846B A6 01 [ 1] 771 ld a, #0x01
00846D 6B 04 [ 1] 772 ld (0x04, sp), a
00846F 84 [ 1] 773 pop a
008470 4D [ 1] 774 tnz a
008471 27 05 [ 1] 775 jreq 00179$
008473 776 00178$:
008473 08 03 [ 1] 777 sll (0x03, sp)
008475 4A [ 1] 778 dec a
008476 26 FB [ 1] 779 jrne 00178$
008478 780 00179$:
781 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1098: itmask1 = (uint8_t)((uint8_t)USART_IT >> (uint8_t)4);
008478 9F [ 1] 782 ld a, xl
008479 4E [ 1] 783 swap a
00847A A4 0F [ 1] 784 and a, #0x0f
785 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1100: itmask2 = (uint8_t)((uint8_t)1 << itmask1);
00847C 88 [ 1] 786 push a
00847D A6 01 [ 1] 787 ld a, #0x01
00847F 6B 08 [ 1] 788 ld (0x08, sp), a
008481 84 [ 1] 789 pop a
008482 4D [ 1] 790 tnz a
008483 27 05 [ 1] 791 jreq 00181$
008485 792 00180$:
008485 08 07 [ 1] 793 sll (0x07, sp)
008487 4A [ 1] 794 dec a
008488 26 FB [ 1] 795 jrne 00180$
00848A 796 00181$:
797 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1103: if (USART_IT == USART_IT_PE)
00848A 16 0C [ 2] 798 ldw y, (0x0c, sp)
00848C 17 01 [ 2] 799 ldw (0x01, sp), y
800 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1109: if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
00848E 16 08 [ 2] 801 ldw y, (0x08, sp)
008490 17 04 [ 2] 802 ldw (0x04, sp), y
803 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1103: if (USART_IT == USART_IT_PE)
008492 1E 01 [ 2] 804 ldw x, (0x01, sp)
008494 A3 01 00 [ 2] 805 cpw x, #0x0100
008497 26 1D [ 1] 806 jrne 00118$
807 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1106: enablestatus = (uint8_t)((uint8_t)USARTx->CR1 & itmask2);
008499 16 08 [ 2] 808 ldw y, (0x08, sp)
00849B 17 01 [ 2] 809 ldw (0x01, sp), y
00849D 93 [ 1] 810 ldw x, y
00849E E6 04 [ 1] 811 ld a, (0x4, x)
0084A0 14 07 [ 1] 812 and a, (0x07, sp)
0084A2 6B 07 [ 1] 813 ld (0x07, sp), a
814 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1109: if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
0084A4 1E 04 [ 2] 815 ldw x, (0x04, sp)
0084A6 F6 [ 1] 816 ld a, (x)
0084A7 14 03 [ 1] 817 and a, (0x03, sp)
0084A9 27 08 [ 1] 818 jreq 00102$
0084AB 0D 07 [ 1] 819 tnz (0x07, sp)
0084AD 27 04 [ 1] 820 jreq 00102$
821 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1112: pendingbitstatus = SET;
0084AF A6 01 [ 1] 822 ld a, #0x01
0084B1 20 41 [ 2] 823 jra 00119$
0084B3 824 00102$:
825 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1117: pendingbitstatus = RESET;
0084B3 4F [ 1] 826 clr a
0084B4 20 3E [ 2] 827 jra 00119$
0084B6 828 00118$:
829 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1124: enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
0084B6 1E 08 [ 2] 830 ldw x, (0x08, sp)
0084B8 E6 05 [ 1] 831 ld a, (0x5, x)
0084BA 14 07 [ 1] 832 and a, (0x07, sp)
833 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1121: else if (USART_IT == USART_IT_OR)
0084BC 1E 01 [ 2] 834 ldw x, (0x01, sp)
0084BE A3 02 35 [ 2] 835 cpw x, #0x0235
0084C1 26 20 [ 1] 836 jrne 00115$
837 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1124: enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
0084C3 6B 06 [ 1] 838 ld (0x06, sp), a
839 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1127: temp = (uint8_t)(USARTx->CR5 & USART_CR5_EIE);
0084C5 1E 08 [ 2] 840 ldw x, (0x08, sp)
0084C7 E6 08 [ 1] 841 ld a, (0x8, x)
0084C9 A4 01 [ 1] 842 and a, #0x01
0084CB 6B 07 [ 1] 843 ld (0x07, sp), a
844 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1129: if (( (USARTx->SR & itpos) != 0x00) && ((enablestatus || temp)))
0084CD 1E 04 [ 2] 845 ldw x, (0x04, sp)
0084CF F6 [ 1] 846 ld a, (x)
0084D0 14 03 [ 1] 847 and a, (0x03, sp)
0084D2 27 0C [ 1] 848 jreq 00106$
0084D4 0D 06 [ 1] 849 tnz (0x06, sp)
0084D6 26 04 [ 1] 850 jrne 00105$
0084D8 0D 07 [ 1] 851 tnz (0x07, sp)
0084DA 27 04 [ 1] 852 jreq 00106$
0084DC 853 00105$:
854 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1132: pendingbitstatus = SET;
0084DC A6 01 [ 1] 855 ld a, #0x01
0084DE 20 14 [ 2] 856 jra 00119$
0084E0 857 00106$:
858 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1137: pendingbitstatus = RESET;
0084E0 4F [ 1] 859 clr a
0084E1 20 11 [ 2] 860 jra 00119$
0084E3 861 00115$:
862 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1144: enablestatus = (uint8_t)((uint8_t)USARTx->CR2 & itmask2);
0084E3 6B 07 [ 1] 863 ld (0x07, sp), a
864 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1146: if (((USARTx->SR & itpos) != (uint8_t)0x00) && enablestatus)
0084E5 1E 04 [ 2] 865 ldw x, (0x04, sp)
0084E7 F6 [ 1] 866 ld a, (x)
0084E8 14 03 [ 1] 867 and a, (0x03, sp)
0084EA 27 07 [ 1] 868 jreq 00111$
0084EC 0D 07 [ 1] 869 tnz (0x07, sp)
0084EE 27 03 [ 1] 870 jreq 00111$
871 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1149: pendingbitstatus = SET;
0084F0 A6 01 [ 1] 872 ld a, #0x01
873 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1154: pendingbitstatus = RESET;
0084F2 21 874 .byte 0x21
0084F3 875 00111$:
0084F3 4F [ 1] 876 clr a
0084F4 877 00119$:
878 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1159: return pendingbitstatus;
879 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1160: }
0084F4 1E 0A [ 2] 880 ldw x, (10, sp)
0084F6 5B 0D [ 2] 881 addw sp, #13
0084F8 FC [ 2] 882 jp (x)
883 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1183: void USART_ClearITPendingBit(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT)
884 ; -----------------------------------------
885 ; function USART_ClearITPendingBit
886 ; -----------------------------------------
0084F9 887 _USART_ClearITPendingBit:
888 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1188: USARTx->SR &= (uint8_t)(~USART_SR_TC);
0084F9 F6 [ 1] 889 ld a, (x)
0084FA A4 BF [ 1] 890 and a, #0xbf
0084FC F7 [ 1] 891 ld (x), a
892 ; ../inc/stm8l151x/src/stm8l15x_usart.c: 1189: }
0084FD 1E 01 [ 2] 893 ldw x, (1, sp)
0084FF 5B 04 [ 2] 894 addw sp, #4
008501 FC [ 2] 895 jp (x)
896 .area CODE
897 .area CONST
898 .area INITIALIZER
899 .area CABS (ABS)

55
firmware/STM8L15X_LD/stm8l15x_usart.sym Normal file
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@@ -0,0 +1,55 @@
ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 1
Hexadecimal [24-Bits]
Symbol Table
.__.$$$. = 002710 L
.__.ABS. = 000000 G
.__.CPU. = 000000 L
.__.H$L. = 000001 L
_CLK_GetClockFreq ****** GX
9 _USART_ClearFlag 0002A8 GR
9 _USART_ClearITPendingBit 00034C GR
9 _USART_ClockInit 000094 GR
9 _USART_Cmd 0000CE GR
9 _USART_DMACmd 0001D7 GR
9 _USART_DeInit 000000 GR
9 _USART_GetFlagStatus 000280 GR
9 _USART_GetITStatus 0002B4 GR
9 _USART_HalfDuplexCmd 000169 GR
9 _USART_ITConfig 0001F1 GR
9 _USART_Init 000017 GR
9 _USART_IrDACmd 0001C2 GR
9 _USART_IrDAConfig 0001AD GR
9 _USART_ReceiveData8 0000F0 GR
9 _USART_ReceiveData9 0000F3 GR
9 _USART_ReceiverWakeUpCmd 000136 GR
9 _USART_SendBreak 0000E8 GR
9 _USART_SendData8 00010E GR
9 _USART_SendData9 000111 GR
9 _USART_SetAddress 00014B GR
9 _USART_SetGuardTime 0001A8 GR
9 _USART_SetPrescaler 0000E3 GR
9 _USART_SmartCardCmd 00017E GR
9 _USART_SmartCardNACKCmd 000193 GR
9 _USART_WakeUpConfig 00015A GR
__divulong ****** GX
ASxxxx Assembler V02.00 + NoICE + SDCC mods (STMicroelectronics STM8) Page 2
Hexadecimal [24-Bits]
Area Table
0 _CODE size 0 flags 0
1 DATA size 0 flags 0
2 INITIALIZED size 0 flags 0
3 DABS size 0 flags 8
4 HOME size 0 flags 0
5 GSINIT size 0 flags 0
6 GSFINAL size 0 flags 0
7 CONST size 0 flags 0
8 INITIALIZER size 0 flags 0
9 CODE size 355 flags 0
A CABS size 0 flags 8

3091
firmware/inc/stm8l151x/inc/stm8l15x.h Normal file
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386
firmware/inc/stm8l151x/inc/stm8l15x_adc.h Normal file
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@@ -0,0 +1,386 @@
/**
******************************************************************************
* @file stm8l15x_adc.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the ADC
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_ADC_H
#define __STM8L15x_ADC_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Types
* @{
*/
/** @defgroup ADC_Channels
* @{
*/
typedef enum
{
ADC_Channel_0 = ((uint16_t)0x0301), /*!< Channel 00 */
ADC_Channel_1 = ((uint16_t)0x0302), /*!< Channel 01 */
ADC_Channel_2 = ((uint16_t)0x0304), /*!< Channel 02 */
ADC_Channel_3 = ((uint16_t)0x0308), /*!< Channel 03 */
ADC_Channel_4 = ((uint16_t)0x0310), /*!< Channel 04 */
ADC_Channel_5 = ((uint16_t)0x0320), /*!< Channel 05 */
ADC_Channel_6 = ((uint16_t)0x0340), /*!< Channel 06 */
ADC_Channel_7 = ((uint16_t)0x0380), /*!< Channel 07 */
ADC_Channel_8 = ((uint16_t)0x0201), /*!< Channel 08 */
ADC_Channel_9 = ((uint16_t)0x0202), /*!< Channel 09 */
ADC_Channel_10 = ((uint16_t)0x0204), /*!< Channel 10 */
ADC_Channel_11 = ((uint16_t)0x0208), /*!< Channel 11 */
ADC_Channel_12 = ((uint16_t)0x0210), /*!< Channel 12 */
ADC_Channel_13 = ((uint16_t)0x0220), /*!< Channel 13 */
ADC_Channel_14 = ((uint16_t)0x0240), /*!< Channel 14 */
ADC_Channel_15 = ((uint16_t)0x0280), /*!< Channel 15 */
ADC_Channel_16 = ((uint16_t)0x0101), /*!< Channel 16 */
ADC_Channel_17 = ((uint16_t)0x0102), /*!< Channel 17 */
ADC_Channel_18 = ((uint16_t)0x0104), /*!< Channel 18 */
ADC_Channel_19 = ((uint16_t)0x0108), /*!< Channel 19 */
ADC_Channel_20 = ((uint16_t)0x0110), /*!< Channel 20 */
ADC_Channel_21 = ((uint16_t)0x0120), /*!< Channel 21 */
ADC_Channel_22 = ((uint16_t)0x0140), /*!< Channel 22 */
ADC_Channel_23 = ((uint16_t)0x0180), /*!< Channel 23 */
ADC_Channel_24 = ((uint16_t)0x0001), /*!< Channel 24 */
ADC_Channel_25 = ((uint16_t)0x0002), /*!< Channel 25 */
ADC_Channel_26 = ((uint16_t)0x0004), /*!< Channel 26 */
ADC_Channel_27 = ((uint16_t)0x0008), /*!< Channel 27 */
ADC_Channel_Vrefint = ((uint16_t)0x0010), /*!< Vrefint Channel */
ADC_Channel_TempSensor = ((uint16_t)0x0020), /*!< Temperature sensor Channel */
/* combination*/
ADC_Channel_00To07 = ((uint16_t)0x03FF), /*!<select from channel00 to channel07 */
ADC_Channel_08To15 = ((uint16_t)0x02FF), /*!<select from channel08 to channel15 */
ADC_Channel_16To23 = ((uint16_t)0x01FF), /*!<select from channel16 to channel23 */
ADC_Channel_24To27 = ((uint16_t)0x00FF) /*!<select from channel24 to channel27 */
}ADC_Channel_TypeDef;
/**
* @}
*/
/** @defgroup ADC_Conversion_Mode
* @{
*/
typedef enum
{
ADC_ConversionMode_Single = ((uint8_t)0x00), /*!< Single Conversion Mode */
ADC_ConversionMode_Continuous = ((uint8_t)0x04) /*!< Continuous Conversion Mode */
}ADC_ConversionMode_TypeDef;
#define IS_ADC_CONVERSION_MODE(MODE) (((MODE) == ADC_ConversionMode_Single) || \
((MODE) == ADC_ConversionMode_Continuous))
/**
* @}
*/
/** @defgroup ADC_Resolution
* @{
*/
typedef enum
{
ADC_Resolution_12Bit = ((uint8_t)0x00), /*!< 12 bit resolution */
ADC_Resolution_10Bit = ((uint8_t)0x20), /*!< 10 bit resolution */
ADC_Resolution_8Bit = ((uint8_t)0x40), /*!< 8 bit resolution */
ADC_Resolution_6Bit = ((uint8_t)0x60) /*!< 6 bit resolution */
}ADC_Resolution_TypeDef;
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12Bit) || \
((RESOLUTION) == ADC_Resolution_10Bit) || \
((RESOLUTION) == ADC_Resolution_8Bit) || \
((RESOLUTION) == ADC_Resolution_6Bit))
/**
* @}
*/
/** @defgroup ADC_Clock_Prescaler
* @{
*/
typedef enum
{
ADC_Prescaler_1 = ((uint8_t)0x00), /*!< ADC Clock frequency is divided by 1 */
ADC_Prescaler_2 = ((uint8_t)0x80) /*!< ADC Clock frequency is divided by 2 */
}ADC_Prescaler_TypeDef;
#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_1) || \
((PRESCALER) == ADC_Prescaler_2))
/**
* @}
*/
/** @defgroup ADC_External_Trigger_Sensitivity
* @{
*/
typedef enum
{
ADC_ExtTRGSensitivity_Rising = ((uint8_t)0x20), /*!< External Trigger Sensitivity is Rising Edge */
ADC_ExtTRGSensitivity_Falling = ((uint8_t)0x40), /*!< External Trigger Sensitivity is Falling Edge */
ADC_ExtTRGSensitivity_All = ((uint8_t)0x60) /*!< External Trigger Sensitivity is Falling and Rising Edge */
}ADC_ExtTRGSensitivity_TypeDef;
#define IS_ADC_EXT_TRG_SENSITIVITY(SENSITIVITY) (((SENSITIVITY) == ADC_ExtTRGSensitivity_Rising) || \
((SENSITIVITY) == ADC_ExtTRGSensitivity_Falling) || \
((SENSITIVITY) == ADC_ExtTRGSensitivity_All))
/**
* @}
*/
/** @defgroup ADC_External_Event_Source_Selection
* @{
*/
typedef enum
{
ADC_ExtEventSelection_None = ((uint8_t)0x00), /*!< Conversion starts only by software start */
ADC_ExtEventSelection_Trigger1 = ((uint8_t)0x08), /*!< Trigger 1 Enables conversion */
ADC_ExtEventSelection_Trigger2 = ((uint8_t)0x10), /*!< Trigger 2 Enables conversion */
ADC_ExtEventSelection_Trigger3 = ((uint8_t)0x18) /*!< Trigger 3 Enables conversion */
}ADC_ExtEventSelection_TypeDef;
#define IS_ADC_EXT_EVENT_SELECTION(SELECTION) (((SELECTION) == ADC_ExtEventSelection_None) || \
((SELECTION) == ADC_ExtEventSelection_Trigger1) || \
((SELECTION) == ADC_ExtEventSelection_Trigger2) || \
((SELECTION) == ADC_ExtEventSelection_Trigger3))
/**
* @}
*/
/** @defgroup ADC_Group_Channel_Definition
* @{
*/
typedef enum
{
ADC_Group_SlowChannels = ((uint8_t)0x00), /*!<Slow Channels group(Channel 0 to 23) */
ADC_Group_FastChannels = ((uint8_t)0x01) /*!<Fast Channels group Channel 24 to 27,
Channel Vrefint, Channel TempSensor)*/
}ADC_Group_TypeDef;
#define IS_ADC_GROUP(GROUP) (((GROUP) == ADC_Group_SlowChannels) || \
((GROUP) == ADC_Group_FastChannels))
/**
* @}
*/
/** @defgroup ADC_Sampling_Time
* @{
*/
typedef enum
{
ADC_SamplingTime_4Cycles = ((uint8_t)0x00), /*!< Sampling Time Cycles is 4 */
ADC_SamplingTime_9Cycles = ((uint8_t)0x01), /*!< Sampling Time Cycles is 9 */
ADC_SamplingTime_16Cycles = ((uint8_t)0x02), /*!< Sampling Time Cycles is 16 */
ADC_SamplingTime_24Cycles = ((uint8_t)0x03), /*!< Sampling Time Cycles is 24 */
ADC_SamplingTime_48Cycles = ((uint8_t)0x04), /*!< Sampling Time Cycles is 48 */
ADC_SamplingTime_96Cycles = ((uint8_t)0x05), /*!< Sampling Time Cycles is 96 */
ADC_SamplingTime_192Cycles = ((uint8_t)0x06), /*!< Sampling Time Cycles is 192 */
ADC_SamplingTime_384Cycles = ((uint8_t)0x07) /*!< Sampling Time Cycles is 384 */
}ADC_SamplingTime_TypeDef;
#define IS_ADC_SAMPLING_TIME_CYCLES(TIME) (((TIME) == ADC_SamplingTime_4Cycles) || \
((TIME) == ADC_SamplingTime_9Cycles) || \
((TIME) == ADC_SamplingTime_16Cycles) || \
((TIME) == ADC_SamplingTime_24Cycles) || \
((TIME) == ADC_SamplingTime_48Cycles) || \
((TIME) == ADC_SamplingTime_96Cycles) || \
((TIME) == ADC_SamplingTime_192Cycles) || \
((TIME) == ADC_SamplingTime_384Cycles))
/**
* @}
*/
/** @defgroup ADC_Analog_Watchdog_Channel_selection
* @{
*/
typedef enum
{
ADC_AnalogWatchdogSelection_Channel0 = ((uint8_t)0x00), /*!< AWD affected to Channel 0 */
ADC_AnalogWatchdogSelection_Channel1 = ((uint8_t)0x01), /*!< AWD affected to Channel 1 */
ADC_AnalogWatchdogSelection_Channel2 = ((uint8_t)0x02), /*!< AWD affected to Channel 2 */
ADC_AnalogWatchdogSelection_Channel3 = ((uint8_t)0x03), /*!< AWD affected to Channel 3 */
ADC_AnalogWatchdogSelection_Channel4 = ((uint8_t)0x04), /*!< AWD affected to Channel 4 */
ADC_AnalogWatchdogSelection_Channel5 = ((uint8_t)0x05), /*!< AWD affected to Channel 5 */
ADC_AnalogWatchdogSelection_Channel6 = ((uint8_t)0x06), /*!< AWD affected to Channel 6 */
ADC_AnalogWatchdogSelection_Channel7 = ((uint8_t)0x07), /*!< AWD affected to Channel 7 */
ADC_AnalogWatchdogSelection_Channel8 = ((uint8_t)0x08), /*!< AWD affected to Channel 8 */
ADC_AnalogWatchdogSelection_Channel9 = ((uint8_t)0x09), /*!< AWD affected to Channel 9 */
ADC_AnalogWatchdogSelection_Channel10 = ((uint8_t)0x0A), /*!< AWD affected to Channel 10 */
ADC_AnalogWatchdogSelection_Channel11 = ((uint8_t)0x0B), /*!< AWD affected to Channel 11 */
ADC_AnalogWatchdogSelection_Channel12 = ((uint8_t)0x0C), /*!< AWD affected to Channel 12 */
ADC_AnalogWatchdogSelection_Channel13 = ((uint8_t)0x0D), /*!< AWD affected to Channel 13 */
ADC_AnalogWatchdogSelection_Channel14 = ((uint8_t)0x0E), /*!< AWD affected to Channel 14 */
ADC_AnalogWatchdogSelection_Channel15 = ((uint8_t)0x0F), /*!< AWD affected to Channel 15 */
ADC_AnalogWatchdogSelection_Channel16 = ((uint8_t)0x10), /*!< AWD affected to Channel 16 */
ADC_AnalogWatchdogSelection_Channel17 = ((uint8_t)0x11), /*!< AWD affected to Channel 17 */
ADC_AnalogWatchdogSelection_Channel18 = ((uint8_t)0x12), /*!< AWD affected to Channel 18 */
ADC_AnalogWatchdogSelection_Channel19 = ((uint8_t)0x13), /*!< AWD affected to Channel 19 */
ADC_AnalogWatchdogSelection_Channel20 = ((uint8_t)0x14), /*!< AWD affected to Channel 20 */
ADC_AnalogWatchdogSelection_Channel21 = ((uint8_t)0x15), /*!< AWD affected to Channel 21 */
ADC_AnalogWatchdogSelection_Channel22 = ((uint8_t)0x16), /*!< AWD affected to Channel 22 */
ADC_AnalogWatchdogSelection_Channel23 = ((uint8_t)0x17), /*!< AWD affected to Channel 23 */
ADC_AnalogWatchdogSelection_Channel24 = ((uint8_t)0x18), /*!< AWD affected to Channel 24 */
ADC_AnalogWatchdogSelection_Channel25 = ((uint8_t)0x19), /*!< AWD affected to Channel 25 */
ADC_AnalogWatchdogSelection_Channel26 = ((uint8_t)0x1A), /*!< AWD affected to Channel 26 */
ADC_AnalogWatchdogSelection_Channel27 = ((uint8_t)0x1B), /*!< AWD affected to Channel 27 */
ADC_AnalogWatchdogSelection_Vrefint = ((uint8_t)0x1C), /*!< AWD affected to Internal Vref Channel */
ADC_AnalogWatchdogSelection_TempSensor = ((uint8_t)0x1D) /*!< AWD affected to Temperature Sensor Channel */
}ADC_AnalogWatchdogSelection_TypeDef;
#define IS_ADC_ANALOGWATCHDOG_SELECTION(CHANNEL) (((CHANNEL) <= 0x1D))
/**
* @}
*/
/** @defgroup ADC_Interrupts
* @{
*/
typedef enum
{
ADC_IT_EOC = ((uint8_t)0x08), /*!< End of Conversion Interrupt */
ADC_IT_AWD = ((uint8_t)0x10), /*!< Analog Watchdog Interrupt */
ADC_IT_OVER = ((uint8_t)0x80) /*!< Over Run Interrupt */
}ADC_IT_TypeDef;
#define IS_ADC_IT(IT) ((((IT) & (uint8_t)0x67) == 0x00) && ((IT) != 0x00))
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
((IT) == ADC_IT_OVER))
/**
* @}
*/
/** @defgroup ADC_Flags
* @{
*/
typedef enum
{
ADC_FLAG_EOC = ((uint8_t)0x01), /*!< End of Conversion flag */
ADC_FLAG_AWD = ((uint8_t)0x02), /*!< Analog Watchdog flag */
ADC_FLAG_OVER = ((uint8_t)0x04) /*!< Over Run flag */
}ADC_FLAG_TypeDef;
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xF8) == 0x00) && ((FLAG) != 0x00))
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_AWD) || \
((FLAG) == ADC_FLAG_OVER))
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported Macros -----------------------------------------------------------*/
/** @defgroup ADC_Exported_Macros
* @{
*/
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the ADC configuration to the default reset state *****/
void ADC_DeInit(ADC_TypeDef* ADCx);
/* Initialization and Configuration functions *********************************/
void ADC_Init(ADC_TypeDef* ADCx,
ADC_ConversionMode_TypeDef ADC_ConversionMode,
ADC_Resolution_TypeDef ADC_Resolution,
ADC_Prescaler_TypeDef ADC_Prescaler);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
void ADC_ExternalTrigConfig(ADC_TypeDef* ADCx,
ADC_ExtEventSelection_TypeDef ADC_ExtEventSelection,
ADC_ExtTRGSensitivity_TypeDef ADC_ExtTRGSensitivity);
/* Analog Watchdog configuration functions ************************************/
void ADC_AnalogWatchdogChannelSelect(ADC_TypeDef* ADCx,
ADC_AnalogWatchdogSelection_TypeDef ADC_AnalogWatchdogSelection);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
uint16_t LowThreshold);
void ADC_AnalogWatchdogConfig(ADC_TypeDef* ADCx,
ADC_AnalogWatchdogSelection_TypeDef ADC_AnalogWatchdogSelection,
uint16_t HighThreshold,
uint16_t LowThreshold);
/* Temperature Sensor & Vrefint (Voltage Reference internal) management functions */
void ADC_TempSensorCmd(FunctionalState NewState);
void ADC_VrefintCmd(FunctionalState NewState);
/* Channels Configuration functions *******************************************/
void ADC_ChannelCmd(ADC_TypeDef* ADCx, ADC_Channel_TypeDef ADC_Channels,
FunctionalState NewState);
void ADC_SamplingTimeConfig(ADC_TypeDef* ADCx, ADC_Group_TypeDef ADC_GroupChannels,
ADC_SamplingTime_TypeDef ADC_SamplingTime);
void ADC_SchmittTriggerConfig(ADC_TypeDef* ADCx, ADC_Channel_TypeDef ADC_Channels,
FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
/* Channels DMA Configuration function ****************************************/
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void ADC_ITConfig(ADC_TypeDef* ADCx,
ADC_IT_TypeDef ADC_IT,
FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, ADC_FLAG_TypeDef ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, ADC_FLAG_TypeDef ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, ADC_IT_TypeDef ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, ADC_IT_TypeDef ADC_IT);
#endif /*__STM8L15x_ADC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
********************************************************************************
* @file stm8l15x_aes.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the AES firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_AES_H
#define __STM8L15x_AES_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup AES
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup AES_Exported_Types
* @{
*/
/** @defgroup AES_Operation_Mode
* @{
*/
typedef enum
{
AES_Operation_Encryp = (uint8_t)0x00, /*!< AES in Encryption mode */
AES_Operation_KeyDeriv = (uint8_t)0x02, /*!< AES in Key Derivation mode */
AES_Operation_Decryp = (uint8_t)0x04, /*!< AES in Decryption mode */
AES_Operation_KeyDerivAndDecryp = (uint8_t)0x06 /*!< AES in Key Derivation and Decryption mode */
} AES_Operation_TypeDef;
#define IS_AES_MODE(Operation) (((Operation) == AES_Operation_Encryp) || \
((Operation) == AES_Operation_KeyDeriv) || \
((Operation) == AES_Operation_Decryp) || \
((Operation) == AES_Operation_KeyDerivAndDecryp))
/**
* @}
*/
/** @defgroup AES_Flags
* @{
*/
typedef enum
{
AES_FLAG_CCF = (uint8_t)0x01, /*!< Computation Complete Flag */
AES_FLAG_RDERR = (uint8_t)0x02, /*!< Read Error Flag */
AES_FLAG_WRERR = (uint8_t)0x04 /*!< Write Error Flag */
}AES_FLAG_TypeDef;
#define IS_AES_FLAG(Flag) (((Flag) == AES_FLAG_CCF) || \
((Flag) == AES_FLAG_RDERR) || \
((Flag) == AES_FLAG_WRERR))
/**
* @}
*/
/** @defgroup AES_Interrupts
* @{
*/
typedef enum
{
AES_IT_CCIE = (uint16_t)0x20, /*!< Computation Complete interrupt enable */
AES_IT_ERRIE = (uint16_t)0x40 /*!< Error interrupt enable */
}AES_IT_TypeDef;
#define IS_AES_IT(IT) (((IT) == AES_IT_CCIE) || \
((IT) == AES_IT_ERRIE))
/**
* @}
*/
/** @defgroup AES_DMA_Transfer_Direction
* @{
*/
typedef enum
{
AES_DMATransfer_InOut = (uint8_t) 0x80 /*!< DMA requests enabled for input transfer phase
as well as for the output transfer phase */
}
AES_DMATransfer_TypeDef;
#define IS_AES_DMATRANSFER(Transfer) ((Transfer) == AES_DMATransfer_InOut)
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the AES configuration to the default reset state *****/
void AES_DeInit(void);
/* AES Configuration **********************************************************/
void AES_OperationModeConfig(AES_Operation_TypeDef AES_Operation);
void AES_Cmd(FunctionalState NewState);
/* AES Read and Write operations **********************************************/
void AES_WriteSubData(uint8_t Data);
void AES_WriteSubKey(uint8_t Key);
uint8_t AES_ReadSubData(void);
uint8_t AES_ReadSubKey(void);
/* DMA transfers management function ******************************************/
void AES_DMAConfig(AES_DMATransfer_TypeDef AES_DMATransfer, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void AES_ITConfig(AES_IT_TypeDef AES_IT, FunctionalState NewState);
FlagStatus AES_GetFlagStatus(AES_FLAG_TypeDef AES_FLAG);
void AES_ClearFlag(AES_FLAG_TypeDef AES_FLAG);
ITStatus AES_GetITStatus(AES_IT_TypeDef AES_IT);
void AES_ClearITPendingBit(AES_IT_TypeDef AES_IT);
#endif /* __STM8L15x_AES_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_beep.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the BEEP firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_BEEP_H
#define __STM8L15x_BEEP_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup BEEP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup BEEP_Exported_Types
* @{
*/
/** @defgroup BEEP_Frequency
* @{
*/
typedef enum {
BEEP_Frequency_1KHz = (uint8_t)0x00, /*!< Beep signal output frequency 1 KHz */
BEEP_Frequency_2KHz = (uint8_t)0x40, /*!< Beep signal output frequency 2 KHz */
BEEP_Frequency_4KHz = (uint8_t)0x80 /*!< Beep signal output frequency 4 KHz */
} BEEP_Frequency_TypeDef;
#define IS_BEEP_FREQUENCY(FREQ) (((FREQ) == BEEP_Frequency_1KHz) || \
((FREQ) == BEEP_Frequency_2KHz) || \
((FREQ) == BEEP_Frequency_4KHz))
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup BEEP_Exported_Constants
* @{
*/
#define BEEP_CALIBRATION_DEFAULT ((uint8_t)0x01) /*!< Default value when calibration is not done */
#define LSI_FREQUENCY_MIN ((uint32_t)25000) /*!< LSI minimum value in Hertz */
#define LSI_FREQUENCY_MAX ((uint32_t)75000) /*!< LSI maximum value in Hertz */
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup BEEP_Exported_Macros
* @{
*/
#define IS_LSI_FREQUENCY(FREQ) (((FREQ) >= LSI_FREQUENCY_MIN) && ((FREQ) <= LSI_FREQUENCY_MAX))
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the BEEP configuration to the default reset state *****/
void BEEP_DeInit(void);
/* Initialization and Configuration functions *********************************/
void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency);
void BEEP_Cmd(FunctionalState NewState);
/* Low Speed Internal Clock(LSI) Calibration functions ***********************/
void BEEP_LSClockToTIMConnectCmd(FunctionalState NewState);
void BEEP_LSICalibrationConfig(uint32_t LSIFreqHz);
#endif /* __STM8L15x_BEEP_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_clk.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the CLK firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_CLK_H
#define __STM8L15x_CLK_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup CLK
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup Exported_Types
* @{
*/
/** @defgroup CLK_HSE_Configuration
* @{
*/
typedef enum {
CLK_HSE_OFF = (uint8_t)0x00, /*!< HSE Disable */
CLK_HSE_ON = (uint8_t)0x01, /*!< HSE Enable */
CLK_HSE_Bypass = (uint8_t)0x11 /*!< HSE Bypass and enable */
} CLK_HSE_TypeDef;
#define IS_CLK_HSE(CONFIG) (((CONFIG) == CLK_HSE_ON) ||\
((CONFIG) == CLK_HSE_OFF)||\
((CONFIG) == CLK_HSE_Bypass))
/**
* @}
*/
/** @defgroup CLK_LSE_Configuration
* @{
*/
typedef enum {
CLK_LSE_OFF = (uint8_t)0x00, /*!< LSE Disable */
CLK_LSE_ON = (uint8_t)0x04, /*!< LSE Enable */
CLK_LSE_Bypass = (uint8_t)0x24 /*!< LSE Bypass and enable */
} CLK_LSE_TypeDef;
#define IS_CLK_LSE(CONFIG) (((CONFIG) == CLK_LSE_OFF) ||\
((CONFIG) == CLK_LSE_ON) ||\
((CONFIG) == CLK_LSE_Bypass))
/**
* @}
*/
/** @defgroup CLK_System_Clock_Sources
* @{
*/
typedef enum {
CLK_SYSCLKSource_HSI = (uint8_t)0x01, /*!< System Clock Source HSI */
CLK_SYSCLKSource_LSI = (uint8_t)0x02, /*!< System Clock Source LSI */
CLK_SYSCLKSource_HSE = (uint8_t)0x04, /*!< System Clock Source HSE */
CLK_SYSCLKSource_LSE = (uint8_t)0x08 /*!< System Clock Source LSE */
} CLK_SYSCLKSource_TypeDef;
#define IS_CLK_SOURCE(SOURCE) (((SOURCE) == CLK_SYSCLKSource_HSI) ||\
((SOURCE) == CLK_SYSCLKSource_LSI) ||\
((SOURCE) == CLK_SYSCLKSource_HSE) ||\
((SOURCE) == CLK_SYSCLKSource_LSE))
/**
* @}
*/
/** @defgroup CLK_Clock_Output_Selection
* @{
*/
typedef enum {
CLK_CCOSource_Off = (uint8_t)0x00, /*!< Clock Output Off */
CLK_CCOSource_HSI = (uint8_t)0x02, /*!< HSI Clock Output */
CLK_CCOSource_LSI = (uint8_t)0x04, /*!< LSI Clock Output */
CLK_CCOSource_HSE = (uint8_t)0x08, /*!< HSE Clock Output */
CLK_CCOSource_LSE = (uint8_t)0x10 /*!< LSE Clock Output */
} CLK_CCOSource_TypeDef;
#define IS_CLK_OUTPUT(OUTPUT) (((OUTPUT) == CLK_CCOSource_Off) ||\
((OUTPUT) == CLK_CCOSource_HSI) ||\
((OUTPUT) == CLK_CCOSource_LSI) ||\
((OUTPUT) == CLK_CCOSource_HSE) ||\
((OUTPUT) == CLK_CCOSource_LSE))
/**
* @}
*/
/** @defgroup CLK_Clock_Output_Prescaler
* @{
*/
typedef enum {
CLK_CCODiv_1 = (uint8_t)0x00, /*!< Clock Output Div 1 */
CLK_CCODiv_2 = (uint8_t)0x20, /*!< Clock Output Div 2 */
CLK_CCODiv_4 = (uint8_t)0x40, /*!< Clock Output Div 4 */
CLK_CCODiv_8 = (uint8_t)0x60, /*!< Clock Output Div 8 */
CLK_CCODiv_16 = (uint8_t)0x80, /*!< Clock Output Div 16 */
CLK_CCODiv_32 = (uint8_t)0xA0, /*!< Clock Output Div 32 */
CLK_CCODiv_64 = (uint8_t)0xC0 /*!< Clock Output Div 64 */
} CLK_CCODiv_TypeDef;
#define IS_CLK_OUTPUT_DIVIDER(PRESCALER) (((PRESCALER) == CLK_CCODiv_1) ||\
((PRESCALER) == CLK_CCODiv_2) ||\
((PRESCALER) == CLK_CCODiv_4) ||\
((PRESCALER) == CLK_CCODiv_8) ||\
((PRESCALER) == CLK_CCODiv_16) ||\
((PRESCALER) == CLK_CCODiv_32) ||\
((PRESCALER) == CLK_CCODiv_64))
/**
* @}
*/
/** @defgroup CLK_Beep_Selection
* @{
*/
typedef enum {
CLK_BEEPCLKSource_Off = (uint8_t)0x00, /*!< Clock BEEP Off */
CLK_BEEPCLKSource_LSI = (uint8_t)0x02, /*!< Clock BEEP : LSI */
CLK_BEEPCLKSource_LSE = (uint8_t)0x04 /*!< Clock BEEP : LSE */
} CLK_BEEPCLKSource_TypeDef;
#define IS_CLK_CLOCK_BEEP(OUTPUT) (((OUTPUT) == CLK_BEEPCLKSource_Off) ||\
((OUTPUT) == CLK_BEEPCLKSource_LSI) ||\
((OUTPUT) == CLK_BEEPCLKSource_LSE))
/**
* @}
*/
/** @defgroup CLK_RTC_Selection
* @{
*/
typedef enum {
CLK_RTCCLKSource_Off = (uint8_t)0x00, /*!< Clock RTC Off */
CLK_RTCCLKSource_HSI = (uint8_t)0x02, /*!< Clock RTC : HSI */
CLK_RTCCLKSource_LSI = (uint8_t)0x04, /*!< Clock RTC : LSI */
CLK_RTCCLKSource_HSE = (uint8_t)0x08, /*!< Clock RTC : HSE */
CLK_RTCCLKSource_LSE = (uint8_t)0x10 /*!< Clock RTC : LSE */
} CLK_RTCCLKSource_TypeDef;
#define IS_CLK_CLOCK_RTC(OUTPUT) (((OUTPUT) == CLK_RTCCLKSource_Off) ||\
((OUTPUT) == CLK_RTCCLKSource_HSI) ||\
((OUTPUT) == CLK_RTCCLKSource_LSI) ||\
((OUTPUT) == CLK_RTCCLKSource_HSE) ||\
((OUTPUT) == CLK_RTCCLKSource_LSE))
/**
* @}
*/
/** @defgroup CLK_RTC_Prescaler
* @{
*/
typedef enum {
CLK_RTCCLKDiv_1 = (uint8_t)0x00, /*!< Clock RTC Div 1 */
CLK_RTCCLKDiv_2 = (uint8_t)0x20, /*!< Clock RTC Div 2 */
CLK_RTCCLKDiv_4 = (uint8_t)0x40, /*!< Clock RTC Div 4 */
CLK_RTCCLKDiv_8 = (uint8_t)0x60, /*!< Clock RTC Div 8 */
CLK_RTCCLKDiv_16 = (uint8_t)0x80, /*!< Clock RTC Div 16 */
CLK_RTCCLKDiv_32 = (uint8_t)0xA0, /*!< Clock RTC Div 32 */
CLK_RTCCLKDiv_64 = (uint8_t)0xC0 /*!< Clock RTC Div 64 */
} CLK_RTCCLKDiv_TypeDef;
#define IS_CLK_CLOCK_RTC_DIV(DIV) (((DIV) == CLK_RTCCLKDiv_1) ||\
((DIV) == CLK_RTCCLKDiv_2) ||\
((DIV) == CLK_RTCCLKDiv_4) ||\
((DIV) == CLK_RTCCLKDiv_8) ||\
((DIV) == CLK_RTCCLKDiv_16) ||\
((DIV) == CLK_RTCCLKDiv_32) ||\
((DIV) == CLK_RTCCLKDiv_64))
/**
* @}
*/
/** @defgroup CLK_Peripherals
* @{
*/
/* Elements values convention: 0xXY
X = choice between the peripheral registers
X = 0 : PCKENR1
X = 1 : PCKENR2
X = 2 : PCKENR3
Y = Peripheral position in the register
*/
typedef enum {
CLK_Peripheral_TIM2 = (uint8_t)0x00, /*!< Peripheral Clock Enable 1, TIM2 */
CLK_Peripheral_TIM3 = (uint8_t)0x01, /*!< Peripheral Clock Enable 1, TIM3 */
CLK_Peripheral_TIM4 = (uint8_t)0x02, /*!< Peripheral Clock Enable 1, TIM4 */
CLK_Peripheral_I2C1 = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, I2C1 */
CLK_Peripheral_SPI1 = (uint8_t)0x04, /*!< Peripheral Clock Enable 1, SPI1 */
CLK_Peripheral_USART1 = (uint8_t)0x05, /*!< Peripheral Clock Enable 1, USART1 */
CLK_Peripheral_BEEP = (uint8_t)0x06, /*!< Peripheral Clock Enable 1, BEEP */
CLK_Peripheral_DAC = (uint8_t)0x07, /*!< Peripheral Clock Enable 1, DAC */
CLK_Peripheral_ADC1 = (uint8_t)0x10, /*!< Peripheral Clock Enable 2, ADC1 */
CLK_Peripheral_TIM1 = (uint8_t)0x11, /*!< Peripheral Clock Enable 2, TIM1 */
CLK_Peripheral_RTC = (uint8_t)0x12, /*!< Peripheral Clock Enable 2, RTC */
CLK_Peripheral_LCD = (uint8_t)0x13, /*!< Peripheral Clock Enable 2, LCD */
CLK_Peripheral_DMA1 = (uint8_t)0x14, /*!< Peripheral Clock Enable 2, DMA1 */
CLK_Peripheral_COMP = (uint8_t)0x15, /*!< Peripheral Clock Enable 2, COMP1 and COMP2 */
CLK_Peripheral_BOOTROM = (uint8_t)0x17,/*!< Peripheral Clock Enable 2, Boot ROM */
CLK_Peripheral_AES = (uint8_t)0x20, /*!< Peripheral Clock Enable 3, AES */
CLK_Peripheral_TIM5 = (uint8_t)0x21, /*!< Peripheral Clock Enable 3, TIM5 */
CLK_Peripheral_SPI2 = (uint8_t)0x22, /*!< Peripheral Clock Enable 3, SPI2 */
CLK_Peripheral_USART2 = (uint8_t)0x23, /*!< Peripheral Clock Enable 3, USART2 */
CLK_Peripheral_USART3 = (uint8_t)0x24, /*!< Peripheral Clock Enable 3, USART3 */
CLK_Peripheral_CSSLSE = (uint8_t)0x25 /*!< Peripheral Clock Enable 3, CSS on LSE */
} CLK_Peripheral_TypeDef;
#define IS_CLK_PERIPHERAL(PERIPHERAL) (((PERIPHERAL) == CLK_Peripheral_DAC) ||\
((PERIPHERAL) == CLK_Peripheral_ADC1) ||\
((PERIPHERAL) == CLK_Peripheral_DMA1) ||\
((PERIPHERAL) == CLK_Peripheral_RTC) ||\
((PERIPHERAL) == CLK_Peripheral_LCD) ||\
((PERIPHERAL) == CLK_Peripheral_COMP) ||\
((PERIPHERAL) == CLK_Peripheral_TIM1) ||\
((PERIPHERAL) == CLK_Peripheral_USART1) ||\
((PERIPHERAL) == CLK_Peripheral_SPI1) ||\
((PERIPHERAL) == CLK_Peripheral_I2C1) ||\
((PERIPHERAL) == CLK_Peripheral_TIM4) ||\
((PERIPHERAL) == CLK_Peripheral_TIM3) ||\
((PERIPHERAL) == CLK_Peripheral_BEEP) ||\
((PERIPHERAL) == CLK_Peripheral_BOOTROM) ||\
((PERIPHERAL) == CLK_Peripheral_AES) ||\
((PERIPHERAL) == CLK_Peripheral_TIM5) ||\
((PERIPHERAL) == CLK_Peripheral_SPI2) ||\
((PERIPHERAL) == CLK_Peripheral_USART2) ||\
((PERIPHERAL) == CLK_Peripheral_USART3) ||\
((PERIPHERAL) == CLK_Peripheral_CSSLSE) ||\
((PERIPHERAL) == CLK_Peripheral_TIM2))
/**
* @}
*/
/** @defgroup CLK_System_Clock_Divider
* @{
*/
typedef enum {
CLK_SYSCLKDiv_1 = (uint8_t)0x00, /*!< System Clock Divider: 1 */
CLK_SYSCLKDiv_2 = (uint8_t)0x01, /*!< System Clock Divider: 2 */
CLK_SYSCLKDiv_4 = (uint8_t)0x02, /*!< System Clock Divider: 4 */
CLK_SYSCLKDiv_8 = (uint8_t)0x03, /*!< System Clock Divider: 8 */
CLK_SYSCLKDiv_16 = (uint8_t)0x04, /*!< System Clock Divider: 16 */
CLK_SYSCLKDiv_32 = (uint8_t)0x05, /*!< System Clock Divider: 32 */
CLK_SYSCLKDiv_64 = (uint8_t)0x06, /*!< System Clock Divider: 64 */
CLK_SYSCLKDiv_128 = (uint8_t)0x07 /*!< System Clock Divider: 128 */
} CLK_SYSCLKDiv_TypeDef;
#define IS_CLK_SYSTEM_DIVIDER(DIV) (((DIV) == CLK_SYSCLKDiv_1) ||\
((DIV) == CLK_SYSCLKDiv_2) ||\
((DIV) == CLK_SYSCLKDiv_4) ||\
((DIV) == CLK_SYSCLKDiv_8) ||\
((DIV) == CLK_SYSCLKDiv_16) ||\
((DIV) == CLK_SYSCLKDiv_32) ||\
((DIV) == CLK_SYSCLKDiv_64) ||\
((DIV) == CLK_SYSCLKDiv_128))
/**
* @}
*/
/** @defgroup CLK_Flags
* @{
*/
/* Elements values convention: 0xXY
X = choice between the register's flags
X = 0 : CLK_CRTCR
X = 1 : CLK_ICKCR
X = 2 : CLK_CCOR
X = 3 : CLK_ECKCR
X = 4 : CLK_SWCR
X = 5 : CLK_CSSR
X = 6 : CLK_CBEEPR
X = 7 : CLK_REGCSRR
X = 8 : CSSLSE_CSR
Y = flag position in the register
*/
typedef enum {
CLK_FLAG_RTCSWBSY = (uint8_t)0x00, /*!< RTC clock busy in switch Flag */
CLK_FLAG_HSIRDY = (uint8_t)0x11, /*!< High speed internal oscillator ready Flag */
CLK_FLAG_LSIRDY = (uint8_t)0x13, /*!< Low speed internal oscillator ready Flag */
CLK_FLAG_CCOBSY = (uint8_t)0x20, /*!< Configurable clock output busy */
CLK_FLAG_HSERDY = (uint8_t)0x31, /*!< High speed external oscillator ready Flag */
CLK_FLAG_LSERDY = (uint8_t)0x33, /*!< Low speed external oscillator ready Flag */
CLK_FLAG_SWBSY = (uint8_t)0x40, /*!< Switch busy Flag */
CLK_FLAG_AUX = (uint8_t)0x51, /*!< Auxiliary oscillator connected to master clock */
CLK_FLAG_CSSD = (uint8_t)0x53, /*!< Clock security system detection Flag */
CLK_FLAG_BEEPSWBSY = (uint8_t)0x60, /*!< BEEP clock busy in switch Flag*/
CLK_FLAG_EEREADY = (uint8_t)0x77, /*!< Flash program memory and Data EEPROM ready Flag */
CLK_FLAG_EEBUSY = (uint8_t)0x76, /*!< Flash program memory and Data EEPROM busy Flag */
CLK_FLAG_LSEPD = (uint8_t)0x75, /*!< LSE power-down Flag */
CLK_FLAG_HSEPD = (uint8_t)0x74, /*!< HSE power-down Flag */
CLK_FLAG_LSIPD = (uint8_t)0x73, /*!< LSI power-down Flag */
CLK_FLAG_HSIPD = (uint8_t)0x72, /*!< HSI power-down Flag */
CLK_FLAG_REGREADY = (uint8_t)0x70, /*!< REGREADY Flag */
CLK_FLAG_LSECSSF = (uint8_t)0x83, /*!< CSS on LSE detection Flag */
CLK_FLAG_RTCCLKSWF = (uint8_t)0x84 /*!< RTCCLK switch completed flag on LSE failure */
}CLK_FLAG_TypeDef;
#define IS_CLK_FLAGS(FLAG) (((FLAG) == CLK_FLAG_LSIRDY) ||\
((FLAG) == CLK_FLAG_HSIRDY) ||\
((FLAG) == CLK_FLAG_HSERDY) ||\
((FLAG) == CLK_FLAG_SWBSY) ||\
((FLAG) == CLK_FLAG_CSSD) ||\
((FLAG) == CLK_FLAG_AUX) ||\
((FLAG) == CLK_FLAG_LSERDY) ||\
((FLAG) == CLK_FLAG_CCOBSY) ||\
((FLAG) == CLK_FLAG_RTCSWBSY) ||\
((FLAG) == CLK_FLAG_EEREADY) ||\
((FLAG) == CLK_FLAG_EEBUSY) ||\
((FLAG) == CLK_FLAG_LSEPD) ||\
((FLAG) == CLK_FLAG_LSIPD) ||\
((FLAG) == CLK_FLAG_HSEPD) ||\
((FLAG) == CLK_FLAG_HSIPD) ||\
((FLAG) == CLK_FLAG_REGREADY) ||\
((FLAG) == CLK_FLAG_BEEPSWBSY)||\
((FLAG) == CLK_FLAG_LSECSSF)||\
((FLAG) == CLK_FLAG_RTCCLKSWF))
/**
* @}
*/
/** @defgroup CLK_Interrupts
* @{
*/
typedef enum {
CLK_IT_CSSD = (uint8_t)0x0C, /*!< Clock security system detection Flag */
CLK_IT_SWIF = (uint8_t)0x1C, /*!< Clock switch interrupt Flag */
CLK_IT_LSECSSF = (uint8_t)0x2C /*!< LSE Clock security system detection Interrupt */
}CLK_IT_TypeDef;
#define IS_CLK_IT(IT) (((IT) == CLK_IT_CSSD) ||\
((IT) == CLK_IT_SWIF) ||\
((IT) == CLK_IT_LSECSSF))
#define IS_CLK_CLEAR_IT(IT) (((IT) == CLK_IT_SWIF)||\
((IT) == CLK_IT_LSECSSF))
/**
* @}
*/
/** @defgroup CLK_Halt_Configuration
* @{
*/
typedef enum {
CLK_Halt_BEEPRunning = (uint8_t)0x40, /*!< BEEP clock Halt/Active-halt mode */
CLK_Halt_FastWakeup = (uint8_t)0x20, /*!< Fast wakeup from Halt/Active-halt modes */
CLK_Halt_SlowWakeup = (uint8_t)0x10 /*!< Slow Active-halt mode */
}
CLK_Halt_TypeDef;
#define IS_CLK_HALT(HALT) (((HALT) == CLK_Halt_BEEPRunning) ||\
((HALT) == CLK_Halt_FastWakeup) ||\
((HALT) == CLK_Halt_SlowWakeup))
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the CLK configuration to the default reset state ******/
void CLK_DeInit(void);
/* Internal/external clocks, CSS and CCO configuration functions **************/
void CLK_HSICmd(FunctionalState NewState);
void CLK_AdjustHSICalibrationValue(uint8_t CLK_HSICalibrationValue);
void CLK_LSICmd(FunctionalState NewState);
void CLK_HSEConfig(CLK_HSE_TypeDef CLK_HSE);
void CLK_LSEConfig(CLK_LSE_TypeDef CLK_LSE);
void CLK_ClockSecuritySystemEnable(void);
void CLK_ClockSecuritySytemDeglitchCmd(FunctionalState NewState);
void CLK_CCOConfig(CLK_CCOSource_TypeDef CLK_CCOSource, CLK_CCODiv_TypeDef CLK_CCODiv);
/* System clocks configuration functions ******************/
void CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_TypeDef CLK_SYSCLKSource);
CLK_SYSCLKSource_TypeDef CLK_GetSYSCLKSource(void);
uint32_t CLK_GetClockFreq(void);
void CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_TypeDef CLK_SYSCLKDiv);
void CLK_SYSCLKSourceSwitchCmd(FunctionalState NewState);
/* Peripheral clocks configuration functions **********************************/
void CLK_RTCClockConfig(CLK_RTCCLKSource_TypeDef CLK_RTCCLKSource, CLK_RTCCLKDiv_TypeDef CLK_RTCCLKDiv);
void CLK_BEEPClockConfig(CLK_BEEPCLKSource_TypeDef CLK_BEEPCLKSource);
void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState);
/* CSS on LSE configuration functions *****************************************/
void CLK_LSEClockSecuritySystemEnable(void);
void CLK_RTCCLKSwitchOnLSEFailureEnable(void);
/* Low power clock configuration functions ************************************/
void CLK_HaltConfig(CLK_Halt_TypeDef CLK_Halt, FunctionalState NewState);
void CLK_MainRegulatorCmd(FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState);
FlagStatus CLK_GetFlagStatus(CLK_FLAG_TypeDef CLK_FLAG);
void CLK_ClearFlag(void);
ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT);
void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT);
#endif /* __STM8L15x_CLK_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_comp.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the COMP firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_COMP_H
#define __STM8L15x_COMP_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup COMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Types
* @{
*/
/** @defgroup COMP_Selection
* @{
*/
typedef enum
{
COMP_Selection_COMP1 = ((uint8_t)0x01), /*!< Selection of Comparator 1. */
COMP_Selection_COMP2 = ((uint8_t)0x02) /*!< Selection of Comparator 2. */
}COMP_Selection_TypeDef;
#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
((PERIPH) == COMP_Selection_COMP2))
/**
* @}
*/
/** @defgroup COMP_Edge
* @{
*/
typedef enum
{
COMP_Edge_Falling = ((uint8_t)0x01), /*!< Falling edge selection. */
COMP_Edge_Rising = ((uint8_t)0x02), /*!< Rising edge selection. */
COMP_Edge_Rising_Falling = ((uint8_t)0x03) /*!< Rising and Falling edge selection. */
}COMP_Edge_TypeDef;
#define IS_COMP_EDGE(EDGE) (((EDGE) == COMP_Edge_Falling) || \
((EDGE) == COMP_Edge_Rising) || \
((EDGE) == COMP_Edge_Rising_Falling))
/**
* @}
*/
/** @defgroup COMP_Inverting_Input_Selection
* @{
*/
typedef enum
{
COMP_InvertingInput_IO = ((uint8_t)0x08), /*!< Input/Output on comparator inverting input enable.*/
COMP_InvertingInput_VREFINT = ((uint8_t)0x10), /*!< VREFINT on comparator inverting input enable. */
COMP_InvertingInput_3_4VREFINT = ((uint8_t)0x18), /*!< 3/4 VREFINT on comparator inverting input enable. */
COMP_InvertingInput_1_2VREFINT = ((uint8_t)0x20), /*!< 1/2 VREFINT on comparator inverting input enable. */
COMP_InvertingInput_1_4VREFINT = ((uint8_t)0x28), /*!< 1/4 VREFINT on comparator inverting input enable. */
COMP_InvertingInput_DAC1 = ((uint8_t)0x30), /*!< DAC1 output on comparator inverting input enable. */
COMP_InvertingInput_DAC2 = ((uint8_t)0x38) /*!< DAC2 output on comparator inverting input enable. */
}COMP_InvertingInput_Typedef;
#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_IO) || \
((INPUT) == COMP_InvertingInput_VREFINT) || \
((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
((INPUT) == COMP_InvertingInput_DAC1) || \
((INPUT) == COMP_InvertingInput_DAC2))
/**
* @}
*/
/** @defgroup COMP2_Output_Selection
* @{
*/
typedef enum
{
COMP_OutputSelect_TIM2IC2 = ((uint8_t)0x00), /*!< COMP2 output connected to TIM2 Input Capture 2 */
COMP_OutputSelect_TIM3IC2 = ((uint8_t)0x40), /*!< COMP2 output connected to TIM3 Input Capture 2 */
COMP_OutputSelect_TIM1BRK = ((uint8_t)0x80), /*!< COMP2 output connected to TIM1 Break Input */
COMP_OutputSelect_TIM1OCREFCLR = ((uint8_t)0xC0) /*!< COMP2 output connected to TIM1 OCREF Clear */
}COMP_OutputSelect_Typedef;
#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC2) || \
((OUTPUT) == COMP_OutputSelect_TIM3IC2) || \
((OUTPUT) == COMP_OutputSelect_TIM1BRK) || \
((OUTPUT) == COMP_OutputSelect_TIM1OCREFCLR))
/**
* @}
*/
/** @defgroup COMP_Speed
* @{
*/
typedef enum
{
COMP_Speed_Slow = ((uint8_t)0x00), /*!< Comparator speed: slow */
COMP_Speed_Fast = ((uint8_t)0x04) /*!< Comparator speed: fast */
}COMP_Speed_TypeDef;
#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \
((SPEED) == COMP_Speed_Fast))
/**
* @}
*/
/** @defgroup COMP_Trigger_Group
* @{
*/
typedef enum
{
COMP_TriggerGroup_InvertingInput = ((uint8_t)0x01), /*!< Trigger on comparator 2 inverting input */
COMP_TriggerGroup_NonInvertingInput = ((uint8_t)0x02), /*!< Trigger on comparator 2 non inverting input */
COMP_TriggerGroup_VREFINTOutput = ((uint8_t)0x03), /*!< Trigger on VREFINT output */
COMP_TriggerGroup_DACOutput = ((uint8_t)0x04) /*!< Trigger on DAC output */
}COMP_TriggerGroup_TypeDef;
#define IS_COMP_TRIGGERGROUP(TRIGGERGROUP) (((TRIGGERGROUP) == COMP_TriggerGroup_NonInvertingInput) || \
((TRIGGERGROUP) == COMP_TriggerGroup_InvertingInput) || \
((TRIGGERGROUP) == COMP_TriggerGroup_VREFINTOutput) || \
((TRIGGERGROUP) == COMP_TriggerGroup_DACOutput)
/**
* @}
*/
/** @defgroup COMP_Trigger_Pin
* @{
*/
typedef enum
{
COMP_TriggerPin_0 = ((uint8_t)0x01), /*!< PE5 for the non inverting input Trigger Group
PC3 for the inverting input Trigger Group
PB6 for the DAC output Trigger Group
PC2 for the VREFINT output Trigger Group
*/
COMP_TriggerPin_1 = ((uint8_t)0x02), /*!< PD0 for the non inverting input Trigger Group
PC4 for the inverting input Trigger Group
PB5 for the DAC output Trigger Group
PD7 for the VREFINT output Trigger Group
*/
COMP_TriggerPin_2 = ((uint8_t)0x04) /*!< PD1 for the non inverting input Trigger Group
PC7 for the inverting input Trigger Group
PB4 for the DAC output Trigger Group
PD6 for the VREFINT output Trigger Group */
}COMP_TriggerPin_TypeDef;
#define IS_COMP_TRIGGERPIN(TRIGGERPIN) ((((uint8_t)(TRIGGERPIN) & (uint8_t)0xF8) == (uint8_t) 0x00) && \
((TRIGGERPIN) != (uint8_t)0x00))
/**
* @}
*/
/** @defgroup COMP_Output_Level
* @{
*/
typedef enum
{
COMP_OutputLevel_Low = ((uint8_t)0x00), /*!< Comparator output level is low */
COMP_OutputLevel_High = ((uint8_t)0x01) /*!< Comparator output level is high */
}COMP_OutputLevel_TypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Function used to set the CLK configuration to the default reset state ******/
void COMP_DeInit(void);
/* Initialization and Configuration functions ****************************/
void COMP_Init(COMP_InvertingInput_Typedef COMP_InvertingInput, COMP_OutputSelect_Typedef COMP_OutputSelect,
COMP_Speed_TypeDef COMP_Speed);
void COMP_VrefintToCOMP1Connect(FunctionalState NewState);
void COMP_EdgeConfig(COMP_Selection_TypeDef COMP_Selection, COMP_Edge_TypeDef COMP_Edge);
COMP_OutputLevel_TypeDef COMP_GetOutputLevel(COMP_Selection_TypeDef COMP_Selection);
/* Window mode control function ***********************************************/
void COMP_WindowCmd(FunctionalState NewState);
/* Internal Reference Voltage (VREFINT) output function ***********************/
void COMP_VrefintOutputCmd(FunctionalState NewState);
/* Comparator channels trigger configuration functions ************************/
void COMP_SchmittTriggerCmd(FunctionalState NewState);
void COMP_TriggerConfig(COMP_TriggerGroup_TypeDef COMP_TriggerGroup,
COMP_TriggerPin_TypeDef COMP_TriggerPin,
FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void COMP_ITConfig(COMP_Selection_TypeDef COMP_Selection, FunctionalState NewState);
FlagStatus COMP_GetFlagStatus(COMP_Selection_TypeDef COMP_Selection);
void COMP_ClearFlag(COMP_Selection_TypeDef COMP_Selection);
ITStatus COMP_GetITStatus(COMP_Selection_TypeDef COMP_Selection);
void COMP_ClearITPendingBit(COMP_Selection_TypeDef COMP_Selection);
/**
* @}
*/
#endif /* __STM8L15x_COMP_H */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_dac.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_DAC_H
#define __STM8L15x_DAC_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DAC_Exported_types
* @{
*/
/** @defgroup DAC_trigger_selection
* @{
*/
typedef enum
{
DAC_Trigger_None = ((uint8_t)0x30), /*!< DAC trigger None */
DAC_Trigger_T4_TRGO = ((uint8_t)0x00), /*!< DAC trigger TIM4 TRGO */
DAC_Trigger_T5_TRGO = ((uint8_t)0x08), /*!< DAC trigger TIM5 TRGO */
DAC_Trigger_Ext = ((uint8_t)0x10), /*!< DAC trigger External Trigger (PE4) */
DAC_Trigger_Software = ((uint8_t)0x38) /*!< DAC trigger software */
}DAC_Trigger_TypeDef;
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
((TRIGGER) == DAC_Trigger_Ext) || \
((TRIGGER) == DAC_Trigger_Software))
/**
* @}
*/
/** @defgroup DAC_data_alignment
* @{
*/
typedef enum
{
DAC_Align_12b_R = ((uint8_t)0x00), /*!< DAC alignment Right 12bit */
DAC_Align_12b_L = ((uint8_t)0x04), /*!< DAC alignment Left 12bit */
DAC_Align_8b_R = ((uint8_t)0x08) /*!< DAC alignment Right 8bit */
}DAC_Align_TypeDef;
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
((ALIGN) == DAC_Align_12b_L) || \
((ALIGN) == DAC_Align_8b_R))
/**
* @}
*/
/** @defgroup DAC_Channel_selection
* @{
*/
typedef enum
{
DAC_Channel_1 = ((uint8_t)0x00), /*!< DAC Channel 1 selection */
DAC_Channel_2 = ((uint8_t)0x01) /*!< DAC Channel 2 selection */
}DAC_Channel_TypeDef;
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
((CHANNEL) == DAC_Channel_2))
/**
* @}
*/
/** @defgroup DAC_wave_generation
* @{
*/
typedef enum
{
DAC_Wave_Noise = ((uint8_t)0x40), /*!< Noise Wave Generation */
DAC_Wave_Triangle = ((uint8_t)0x80) /*!< Triangle Wave Generation */
}DAC_Wave_TypeDef;
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
((WAVE) == DAC_Wave_Triangle))
/**
* @}
*/
/** @defgroup DAC_output_buffer
* @{
*/
typedef enum
{
DAC_OutputBuffer_Enable = ((uint8_t)0x00), /*!< DAC output buffer Enabled */
DAC_OutputBuffer_Disable = ((uint8_t)0x02) /*!< DAC output buffer Disabled */
}DAC_OutputBuffer_TypeDef;
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
((STATE) == DAC_OutputBuffer_Disable))
/**
* @}
*/
/** @defgroup DAC_interrupts_definition
* @{
*/
typedef enum
{
DAC_IT_DMAUDR = ((uint8_t)0x20) /*!< DMA Underrun Interrupt */
}DAC_IT_TypeDef;
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
/**
* @}
*/
/** @defgroup DAC_flags_definition
* @{
*/
typedef enum
{
DAC_FLAG_DMAUDR = ((uint8_t)0x01) /*!< DMA Underrun flag */
}DAC_FLAG_TypeDef;
#define IS_DAC_GET_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
/**
* @}
*/
/** @defgroup DAC_lfsrunmask
* @{
*/
typedef enum
{
DAC_LFSRUnmask_Bit0 = ((uint8_t)0x00), /*!< Noise LFSR Unmask 1 LSB */
DAC_LFSRUnmask_Bits1_0 = ((uint8_t)0x01), /*!< Noise LFSR Unmask 2 LSB */
DAC_LFSRUnmask_Bits2_0 = ((uint8_t)0x02), /*!< Noise LFSR Unmask 3 LSB */
DAC_LFSRUnmask_Bits3_0 = ((uint8_t)0x03), /*!< Noise LFSR Unmask 4 LSB */
DAC_LFSRUnmask_Bits4_0 = ((uint8_t)0x04), /*!< Noise LFSR Unmask 5 LSB */
DAC_LFSRUnmask_Bits5_0 = ((uint8_t)0x05), /*!< Noise LFSR Unmask 6 LSB */
DAC_LFSRUnmask_Bits6_0 = ((uint8_t)0x06), /*!< Noise LFSR Unmask 7 LSB */
DAC_LFSRUnmask_Bits7_0 = ((uint8_t)0x07), /*!< Noise LFSR Unmask 8 LSB */
DAC_LFSRUnmask_Bits8_0 = ((uint8_t)0x08), /*!< Noise LFSR Unmask 9 LSB */
DAC_LFSRUnmask_Bits9_0 = ((uint8_t)0x09), /*!< Noise LFSR Unmask 10 LSB */
DAC_LFSRUnmask_Bits10_0 = ((uint8_t)0x0A), /*!< Noise LFSR Unmask 11 LSB */
DAC_LFSRUnmask_Bits11_0 = ((uint8_t)0x0B) /*!< Noise LFSR Unmask 12 LSB */
}DAC_LFSRUnmask_TypeDef;
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) ((VALUE) <= 0x0F)
/**
* @}
*/
/** @defgroup DAC_triangleamplitude
* @{
*/
typedef enum
{
DAC_TriangleAmplitude_1 = ((uint8_t)0x00), /*!< Triangle Amplitude = Vref.(1/4096)*/
DAC_TriangleAmplitude_3 = ((uint8_t)0x01), /*!< Triangle Amplitude = Vref.(3/4096)*/
DAC_TriangleAmplitude_7 = ((uint8_t)0x02), /*!< Triangle Amplitude = Vref.(7/4096)*/
DAC_TriangleAmplitude_15 = ((uint8_t)0x03), /*!< Triangle Amplitude = Vref.(15/4096)*/
DAC_TriangleAmplitude_31 = ((uint8_t)0x04), /*!< Triangle Amplitude = Vref.(31/4096)*/
DAC_TriangleAmplitude_63 = ((uint8_t)0x05), /*!< Triangle Amplitude = Vref.(63/4096)*/
DAC_TriangleAmplitude_127 = ((uint8_t)0x06), /*!< Triangle Amplitude = Vref.(127/4096)*/
DAC_TriangleAmplitude_255 = ((uint8_t)0x07), /*!< Triangle Amplitude = Vref.(255/4096)*/
DAC_TriangleAmplitude_511 = ((uint8_t)0x08), /*!< Triangle Amplitude = Vref.(511/4096)*/
DAC_TriangleAmplitude_1023 = ((uint8_t)0x09), /*!< Triangle Amplitude = Vref.(1023/4096)*/
DAC_TriangleAmplitude_2047 = ((uint8_t)0x0A), /*!< Triangle Amplitude = Vref.(2047/4096)*/
DAC_TriangleAmplitude_4095 = ((uint8_t)0x0B) /*!< Triangle Amplitude = Vref.(4095/4096)*/
}DAC_TriangleAmplitude_TypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_Exported_Constants
* @{
*/
/** @defgroup DAC_data
* @{
*/
#define IS_DAC_DATA_08R(DATA) ((DATA) <= 0x00FF)
/**
* @}
*/
/** @defgroup DAC_Registers_Offset
* @{
*/
#define CR1_Offset ((uint8_t)0x00)
#define CR2_Offset ((uint8_t)0x01)
#define DCH1RDHRH_Offset ((uint8_t)0x20)
#define CH1RDHRH_Offset ((uint8_t)0x08)
#define CH2RDHRH_Offset ((uint8_t)0x14)
/**
* @}
*/
/** @defgroup DAC_legacy
* @{
*/
#define DAC_TriangleWaveAmplitude DAC_SetTriangleWaveAmplitude
#define DAC_NoiseWaveLFSR DAC_SetNoiseWaveLFSR
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the DAC configuration to the default reset state *****/
void DAC_DeInit(void);
/* DAC channels configuration: trigger, output buffer, data format functions */
void DAC_Init(DAC_Channel_TypeDef DAC_Channel,
DAC_Trigger_TypeDef DAC_Trigger,
DAC_OutputBuffer_TypeDef DAC_OutputBuffer);
void DAC_Cmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState);
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
void DAC_WaveGenerationCmd(DAC_Channel_TypeDef DAC_Channel, DAC_Wave_TypeDef DAC_Wave, FunctionalState NewState);
void DAC_SetNoiseWaveLFSR(DAC_Channel_TypeDef DAC_Channel, DAC_LFSRUnmask_TypeDef DAC_LFSRUnmask);
void DAC_SetTriangleWaveAmplitude(DAC_Channel_TypeDef DAC_Channel, DAC_TriangleAmplitude_TypeDef DAC_TriangleAmplitude);
void DAC_SetChannel1Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data);
void DAC_SetChannel2Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data);
void DAC_SetDualChannelData(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data2, uint16_t DAC_Data1);
uint16_t DAC_GetDataOutputValue(DAC_Channel_TypeDef DAC_Channel);
/* DMA management function ***************************************************/
void DAC_DMACmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void DAC_ITConfig(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT, FunctionalState NewState);
FlagStatus DAC_GetFlagStatus(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG);
void DAC_ClearFlag(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG);
ITStatus DAC_GetITStatus(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT);
void DAC_ClearITPendingBit(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT);
#endif /*__STM8L15x_DAC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_dma.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the DMA
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_DMA_H
#define __STM8L15x_DMA_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @addtogroup DMA_Exported_Types
* @{
*/
/** @defgroup DMA_Data_Transfer_Direction
* @{
*/
typedef enum
{
DMA_DIR_PeripheralToMemory = ((uint8_t)0x00), /*!< Data transfer direction is Peripheral To Memory */
DMA_DIR_MemoryToPeripheral = ((uint8_t)0x08), /*!< Data transfer direction is Memory To Peripheral */
DMA_DIR_Memory0ToMemory1 = ((uint8_t)0x40) /*!< Data transfer direction is Memory0 To Memory 1 */
}DMA_DIR_TypeDef;
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_MemoryToPeripheral) || \
((DIR) == DMA_DIR_PeripheralToMemory) || \
((DIR) == DMA_DIR_Memory0ToMemory1 ))
/**
* @}
*/
/** @defgroup DMA_Mode
* @{
*/
typedef enum
{
DMA_Mode_Normal = ((uint8_t)0x00), /*!< DMA normal buffer mode*/
DMA_Mode_Circular = ((uint8_t)0x10) /*!< DMA circular buffer mode */
}DMA_Mode_TypeDef;
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || \
((MODE) == DMA_Mode_Normal))
/**
* @}
*/
/** @defgroup DMA_Incremented_Mode
* @{
*/
typedef enum
{
DMA_MemoryIncMode_Dec = ((uint8_t)0x00), /*!< DMA memory incremented mode is decremental */
DMA_MemoryIncMode_Inc = ((uint8_t)0x20) /*!< DMA memory incremented mode is incremental */
}DMA_MemoryIncMode_TypeDef;
#define IS_DMA_MEMORY_INC_MODE(MODE) (((MODE) == DMA_MemoryIncMode_Inc) || \
((MODE) == DMA_MemoryIncMode_Dec))
/**
* @}
*/
/** @defgroup DMA_Priority
* @{
*/
typedef enum
{
DMA_Priority_Low = ((uint8_t)0x00), /*!< Software Priority is Low */
DMA_Priority_Medium = ((uint8_t)0x10), /*!< Software Priority is Medium */
DMA_Priority_High = ((uint8_t)0x20), /*!< Software Priority is High */
DMA_Priority_VeryHigh = ((uint8_t)0x30) /*!< Software Priority is Very High*/
}DMA_Priority_TypeDef;
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
((PRIORITY) == DMA_Priority_High) || \
((PRIORITY) == DMA_Priority_Medium) || \
((PRIORITY) == DMA_Priority_Low))
/**
* @}
*/
/** @defgroup DMA_Memory_Data_Size
* @{
*/
typedef enum
{
DMA_MemoryDataSize_Byte = ((uint8_t)0x00),/*!< Memory Data Size is 1 Byte */
DMA_MemoryDataSize_HalfWord = ((uint8_t)0x08) /*!< Memory Data Size is 2 Bytes */
}DMA_MemoryDataSize_TypeDef;
#define IS_DMA_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
((SIZE) == DMA_MemoryDataSize_HalfWord))
/**
* @}
*/
/** @defgroup DMA_Flags
* @{
*/
typedef enum
{
DMA1_FLAG_GB = ((uint16_t)0x0002), /*!< Global Busy Flag */
DMA1_FLAG_IFC0 = ((uint16_t)0x1001), /*!< Global Interrupt Flag Channel 0 */
DMA1_FLAG_IFC1 = ((uint16_t)0x1002), /*!< Global Interrupt Flag Channel 1 */
DMA1_FLAG_IFC2 = ((uint16_t)0x1004), /*!< Global Interrupt Flag Channel 2 */
DMA1_FLAG_IFC3 = ((uint16_t)0x1008), /*!< Global Interrupt Flag Channel 3 */
DMA1_FLAG_TC0 = ((uint16_t)0x0102), /*!< Transaction Complete Interrupt Flag Channel 0 */
DMA1_FLAG_TC1 = ((uint16_t)0x0202), /*!< Transaction Complete Interrupt Flag Channel 1 */
DMA1_FLAG_TC2 = ((uint16_t)0x0402), /*!< Transaction Complete Interrupt Flag Channel 2 */
DMA1_FLAG_TC3 = ((uint16_t)0x0802), /*!< Transaction Complete Interrupt Flag Channel 3 */
DMA1_FLAG_HT0 = ((uint16_t)0x0104), /*!< Half Transaction Interrupt Flag Channel 0 */
DMA1_FLAG_HT1 = ((uint16_t)0x0204), /*!< Half Transaction Interrupt Flag Channel 1 */
DMA1_FLAG_HT2 = ((uint16_t)0x0404), /*!< Half Transaction Interrupt Flag Channel 2 */
DMA1_FLAG_HT3 = ((uint16_t)0x0804), /*!< Half Transaction Interrupt Flag Channel 3 */
DMA1_FLAG_PEND0 = ((uint16_t)0x0140), /*!< DMA Request pending on Channel 0 */
DMA1_FLAG_PEND1 = ((uint16_t)0x0240), /*!< DMA Request pending on Channel 1 */
DMA1_FLAG_PEND2 = ((uint16_t)0x0440), /*!< DMA Request pending on Channel 2 */
DMA1_FLAG_PEND3 = ((uint16_t)0x0840), /*!< DMA Request pending on Channel 3 */
DMA1_FLAG_BUSY0 = ((uint16_t)0x0180), /*!< No DMA transfer on going in Channel 0 */
DMA1_FLAG_BUSY1 = ((uint16_t)0x0280), /*!< No DMA transfer on going in Channel 1 */
DMA1_FLAG_BUSY2 = ((uint16_t)0x0480), /*!< No DMA transfer on going in Channel 2 */
DMA1_FLAG_BUSY3 = ((uint16_t)0x0880) /*!< No DMA transfer on going in Channel 3 */
}DMA_FLAG_TypeDef;
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GB) || \
((FLAG) == DMA1_FLAG_IFC0) || \
((FLAG) == DMA1_FLAG_IFC1) || \
((FLAG) == DMA1_FLAG_IFC2) || \
((FLAG) == DMA1_FLAG_IFC3) || \
((FLAG) == DMA1_FLAG_TC0) || \
((FLAG) == DMA1_FLAG_TC1) || \
((FLAG) == DMA1_FLAG_TC2) || \
((FLAG) == DMA1_FLAG_TC3) || \
((FLAG) == DMA1_FLAG_HT0) || \
((FLAG) == DMA1_FLAG_HT1) || \
((FLAG) == DMA1_FLAG_HT2) || \
((FLAG) == DMA1_FLAG_HT3) || \
((FLAG) == DMA1_FLAG_PEND0) || \
((FLAG) == DMA1_FLAG_PEND1) || \
((FLAG) == DMA1_FLAG_PEND2) || \
((FLAG) == DMA1_FLAG_PEND3) || \
((FLAG) == DMA1_FLAG_BUSY0) || \
((FLAG) == DMA1_FLAG_BUSY1) || \
((FLAG) == DMA1_FLAG_BUSY2) || \
((FLAG) == DMA1_FLAG_BUSY3))
#define IS_DMA_CLEAR_FLAG(FLAG) (((FLAG) == DMA1_FLAG_TC0) || \
((FLAG) == DMA1_FLAG_TC1) || \
((FLAG) == DMA1_FLAG_TC2) || \
((FLAG) == DMA1_FLAG_TC3) || \
((FLAG) == DMA1_FLAG_HT0) || \
((FLAG) == DMA1_FLAG_HT1) || \
((FLAG) == DMA1_FLAG_HT2) || \
((FLAG) == DMA1_FLAG_HT3) || \
((FLAG) == (DMA1_FLAG_TC0 |DMA1_FLAG_HT0)) || \
((FLAG) == (DMA1_FLAG_TC1 |DMA1_FLAG_HT1)) || \
((FLAG) == (DMA1_FLAG_TC2 |DMA1_FLAG_HT2)) || \
((FLAG) == (DMA1_FLAG_TC3 |DMA1_FLAG_HT3)))
/**
* @}
*/
/** @defgroup DMA_One_Channel_Interrupts
* @{
*/
typedef enum
{
DMA_ITx_TC = ((uint8_t)0x02),/*!< Transaction Complete Interrupt */
DMA_ITx_HT = ((uint8_t)0x04) /*!< Half Transaction Interrupt*/
}DMA_ITx_TypeDef;
#define IS_DMA_CONFIG_ITX(IT) ((((IT) & 0xF9) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup DMA_Interrupts
* @{
*/
typedef enum
{
/* Transaction Complete Interrupts*/
DMA1_IT_TC0 = ((uint8_t)0x12), /*!< Transaction Complete Interrupt Channel 0 */
DMA1_IT_TC1 = ((uint8_t)0x22), /*!< Transaction Complete Interrupt Channel 1 */
DMA1_IT_TC2 = ((uint8_t)0x42), /*!< Transaction Complete Interrupt Channel 2 */
DMA1_IT_TC3 = ((uint8_t)0x82), /*!< Transaction Complete Interrupt Channel 3 */
/* Half Transaction Interrupts */
DMA1_IT_HT0 = ((uint8_t)0x14), /*!< Half Transaction Interrupt Channel 0 */
DMA1_IT_HT1 = ((uint8_t)0x24), /*!< Half Transaction Interrupt Channel 1 */
DMA1_IT_HT2 = ((uint8_t)0x44), /*!< Half Transaction Interrupt Channel 2 */
DMA1_IT_HT3 = ((uint8_t)0x84) /*!< Half Transaction Interrupt Channel 3 */
}DMA_IT_TypeDef;
#define IS_DMA_CLEAR_IT(IT) (((IT) == DMA1_IT_TC0) || \
((IT) == DMA1_IT_TC1) || \
((IT) == DMA1_IT_TC2) || \
((IT) == DMA1_IT_TC3) || \
((IT) == DMA1_IT_HT0) || \
((IT) == DMA1_IT_HT1) || \
((IT) == DMA1_IT_HT2) || \
((IT) == DMA1_IT_HT3) || \
((IT) == (DMA1_IT_TC0|DMA1_IT_HT0)) || \
((IT) == (DMA1_IT_TC1|DMA1_IT_HT1)) || \
((IT) == (DMA1_IT_TC2|DMA1_IT_HT2)) || \
((IT) == (DMA1_IT_TC3|DMA1_IT_HT3)))
#define IS_DMA_GET_IT(IT)(((IT) == DMA1_IT_TC0) || \
((IT) == DMA1_IT_TC1) || \
((IT) == DMA1_IT_TC2) || \
((IT) == DMA1_IT_TC3) || \
((IT) == DMA1_IT_HT0) || \
((IT) == DMA1_IT_HT1) || \
((IT) == DMA1_IT_HT2) || \
((IT) == DMA1_IT_HT3))
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @addtogroup DMA_Exported_Macros
* @{
*/
/** @defgroup DMA_Channels
* @{
*/
#define IS_DMA_CHANNEL(PERIPH) (((*(uint16_t*)&(PERIPH)) == DMA1_Channel0_BASE) || \
((*(uint16_t*)&(PERIPH)) == DMA1_Channel1_BASE) || \
((*(uint16_t*)&(PERIPH)) == DMA1_Channel2_BASE) || \
((*(uint16_t*)&(PERIPH)) == DMA1_Channel3_BASE))
/**
* @}
*/
/** @defgroup DMA_Buffer_Size
* @{
*/
#define IS_DMA_BUFFER_SIZE(SIZE) ((SIZE) > (uint8_t)0x0)
/**
* @}
*/
/** @defgroup DMA_Timeout
* @{
*/
#define IS_DMA_TIMEOUT(TIME) ((TIME) < (uint8_t)0x40)
/**
* @}
*/
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* Functions used to set the DMA configuration to the default reset state ****/
void DMA_GlobalDeInit(void);
void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx);
/* Initialization and Configuration functions *********************************/
void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx,
uint32_t DMA_Memory0BaseAddr,
uint16_t DMA_PeripheralMemory1BaseAddr,
uint8_t DMA_BufferSize,
DMA_DIR_TypeDef DMA_DIR,
DMA_Mode_TypeDef DMA_Mode,
DMA_MemoryIncMode_TypeDef DMA_MemoryIncMode,
DMA_Priority_TypeDef DMA_Priority,
DMA_MemoryDataSize_TypeDef DMA_MemoryDataSize );
void DMA_GlobalCmd(FunctionalState NewState);
void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState);
void DMA_SetTimeOut(uint8_t DMA_TimeOut);
/* Data Counter functions *****************************************************/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx, uint8_t DataNumber);
uint8_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx);
/* Interrupts and flags management functions **********************************/
void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, DMA_ITx_TypeDef DMA_ITx, FunctionalState NewState);
FlagStatus DMA_GetFlagStatus(DMA_FLAG_TypeDef DMA_FLAG);
void DMA_ClearFlag(DMA_FLAG_TypeDef DMA_FLAG);
ITStatus DMA_GetITStatus(DMA_IT_TypeDef DMA_IT);
void DMA_ClearITPendingBit(DMA_IT_TypeDef DMA_IT);
#endif /*__STM8L15x_DMA_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_exti.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the EXTI firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_EXTI_H
#define __STM8L15x_EXTI_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Types
* @{
*/
/** @defgroup EXTI_Trigger
* @{
*/
typedef enum
{
EXTI_Trigger_Falling_Low = (uint8_t)0x00, /*!< Interrupt on Falling edge and Low level */
EXTI_Trigger_Rising = (uint8_t)0x01, /*!< Interrupt on Rising edge only */
EXTI_Trigger_Falling = (uint8_t)0x02, /*!< Interrupt on Falling edge only */
EXTI_Trigger_Rising_Falling = (uint8_t)0x03 /*!< Interrupt on Rising and Falling edges */
} EXTI_Trigger_TypeDef;
/**
* @}
*/
/** @defgroup EXTI_Half_Port
*
* @brief EXTI halfPort possible values
* Values are coded as following:
* - Bit 7: 0 => the half port is in EXTI_CONF1 register
* 1 => the half port is in EXTI_CONF2 register
* - Bits[6:0] => the half port selection mask
* @{
*/
typedef enum
{
EXTI_HalfPort_B_LSB = (uint8_t)0x01, /*!< Interrupt selector PB(3:0) */
EXTI_HalfPort_B_MSB = (uint8_t)0x02, /*!< Interrupt selector PB(7:4) */
EXTI_HalfPort_D_LSB = (uint8_t)0x04, /*!< Interrupt selector PD(3:0) */
EXTI_HalfPort_D_MSB = (uint8_t)0x08, /*!< Interrupt selector PD(7:4) */
EXTI_HalfPort_E_LSB = (uint8_t)0x10, /*!< Interrupt selector PE(3:0) */
EXTI_HalfPort_E_MSB = (uint8_t)0x20, /*!< Interrupt selector PE(7:4) */
EXTI_HalfPort_F_LSB = (uint8_t)0x40, /*!< Interrupt selector PF(3:0) */
EXTI_HalfPort_F_MSB = (uint8_t)0x81, /*!< Interrupt selector PF(7:4) */
EXTI_HalfPort_G_LSB = (uint8_t)0x82, /*!< Interrupt selector PG(3:0) */
EXTI_HalfPort_G_MSB = (uint8_t)0x84, /*!< Interrupt selector PG(7:4) */
EXTI_HalfPort_H_LSB = (uint8_t)0x88, /*!< Interrupt selector PH(3:0) */
EXTI_HalfPort_H_MSB = (uint8_t)0x90 /*!< Interrupt selector PH(7:4) */
} EXTI_HalfPort_TypeDef;
/**
* @}
*/
/** @defgroup EXTI_Port
*
* @brief EXTI Port possible values
* Values are coded in 0xXY format where
* X: the register index
* X = 0: EXTI_CR3
* X = 1: EXTI_CR4
* Y: the number of shift to be performed
* @{
*/
typedef enum
{
EXTI_Port_B = (uint8_t)0x00, /*!< GPIO Port B */
EXTI_Port_D = (uint8_t)0x02, /*!< GPIO Port D */
EXTI_Port_E = (uint8_t)0x04, /*!< GPIO Port E */
EXTI_Port_F = (uint8_t)0x06, /*!< GPIO Port F */
EXTI_Port_G = (uint8_t)0x10, /*!< GPIO Port G */
EXTI_Port_H = (uint8_t)0x12 /*!< GPIO Port H */
} EXTI_Port_TypeDef;
/**
* @}
*/
/** @defgroup EXTI_Pin
*
* @brief EXTI PinNum possible values
* Values are coded in 0xXY format where
* X: the register index
* X = 0: EXTI_CR1
* X = 1: EXTI_CR2
* Y: the number of shift to be performed
* @{
*/
typedef enum
{
EXTI_Pin_0 = (uint8_t)0x00, /*!< GPIO Pin 0 */
EXTI_Pin_1 = (uint8_t)0x02, /*!< GPIO Pin 1 */
EXTI_Pin_2 = (uint8_t)0x04, /*!< GPIO Pin 2 */
EXTI_Pin_3 = (uint8_t)0x06, /*!< GPIO Pin 3 */
EXTI_Pin_4 = (uint8_t)0x10, /*!< GPIO Pin 4 */
EXTI_Pin_5 = (uint8_t)0x12, /*!< GPIO Pin 5 */
EXTI_Pin_6 = (uint8_t)0x14, /*!< GPIO Pin 6 */
EXTI_Pin_7 = (uint8_t)0x16 /*!< GPIO Pin 7 */
} EXTI_Pin_TypeDef;
/**
* @}
*/
/** @defgroup EXTI_Interrupts
*
* @brief EXTI IT pending bit possible values
* Values are coded in 0xXY format where
* X: the register index
* X = 00: EXTI_SR1
* X = 01: EXTI_SR2
* Y: the IT pending bit mask
* @{
*/
typedef enum
{
EXTI_IT_Pin0 = (uint16_t)0x0001, /*!< GPIO Pin pos 0 */
EXTI_IT_Pin1 = (uint16_t)0x0002, /*!< GPIO Pin pos 1 */
EXTI_IT_Pin2 = (uint16_t)0x0004, /*!< GPIO Pin pos 2 */
EXTI_IT_Pin3 = (uint16_t)0x0008, /*!< GPIO Pin pos 3 */
EXTI_IT_Pin4 = (uint16_t)0x0010, /*!< GPIO Pin pos 4 */
EXTI_IT_Pin5 = (uint16_t)0x0020, /*!< GPIO Pin pos 5 */
EXTI_IT_Pin6 = (uint16_t)0x0040, /*!< GPIO Pin pos 6 */
EXTI_IT_Pin7 = (uint16_t)0x0080, /*!< GPIO Pin pos 7 */
EXTI_IT_PortB = (uint16_t)0x0101, /*!< GPIO Port B */
EXTI_IT_PortD = (uint16_t)0x0102, /*!< GPIO Port D */
EXTI_IT_PortE = (uint16_t)0x0104, /*!< GPIO Port E */
EXTI_IT_PortF = (uint16_t)0x0108, /*!< GPIO Port F */
EXTI_IT_PortG = (uint16_t)0x0110, /*!< GPIO Port G */
EXTI_IT_PortH = (uint16_t)0x0120 /*!< GPIO Port H */
} EXTI_IT_TypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Macros
* @{
*/
/**
* @brief Macro used by the assert function to check the different functions parameters.
*/
/**
* @brief Macro used by the assert function in order to check the different values
* of EXTI Sensitivity
*/
#define IS_EXTI_TRIGGER(TRIGGER) \
(((TRIGGER) == EXTI_Trigger_Falling_Low) || \
((TRIGGER) == EXTI_Trigger_Rising) || \
((TRIGGER) == EXTI_Trigger_Falling) || \
((TRIGGER) == EXTI_Trigger_Rising_Falling))
/**
* @brief Macro used by the assert function in order to check the different
* half ports values for configuration.
*/
#define IS_EXTI_HALFPORT(HALFPORT) \
(((HALFPORT) == EXTI_HalfPort_B_LSB) ||\
((HALFPORT) == EXTI_HalfPort_B_MSB) ||\
((HALFPORT) == EXTI_HalfPort_D_LSB) ||\
((HALFPORT) == EXTI_HalfPort_D_MSB) ||\
((HALFPORT) == EXTI_HalfPort_E_LSB) ||\
((HALFPORT) == EXTI_HalfPort_E_MSB) ||\
((HALFPORT) == EXTI_HalfPort_F_LSB) ||\
((HALFPORT) == EXTI_HalfPort_F_MSB) ||\
((HALFPORT) == EXTI_HalfPort_G_LSB) ||\
((HALFPORT) == EXTI_HalfPort_G_MSB) ||\
((HALFPORT) == EXTI_HalfPort_H_LSB) ||\
((HALFPORT) == EXTI_HalfPort_H_MSB))
/**
* @brief Macro used by the assert function in order to check the different Port Number values
*/
#define IS_EXTI_PORT(PORT) (((PORT) == EXTI_Port_B) ||\
((PORT) == EXTI_Port_D) ||\
((PORT) == EXTI_Port_E) ||\
((PORT) == EXTI_Port_F) ||\
((PORT) == EXTI_Port_G) ||\
((PORT) == EXTI_Port_H))
/**
* @brief Macro used by the assert function in order to check the different Pin numbers values
*/
#define IS_EXTI_PINNUM(PINNUM) \
(((PINNUM) == EXTI_Pin_0) ||\
((PINNUM) == EXTI_Pin_1) ||\
((PINNUM) == EXTI_Pin_2) ||\
((PINNUM) == EXTI_Pin_3) ||\
((PINNUM) == EXTI_Pin_4) ||\
((PINNUM) == EXTI_Pin_5) ||\
((PINNUM) == EXTI_Pin_6) ||\
((PINNUM) == EXTI_Pin_7))
/**
* @brief Macro used by the assert function in order to check the different flags values
*/
#define IS_EXTI_ITPENDINGBIT(ITPENDINGBIT) \
(((ITPENDINGBIT) == EXTI_IT_Pin0) ||\
((ITPENDINGBIT) == EXTI_IT_Pin1) ||\
((ITPENDINGBIT) == EXTI_IT_Pin2) ||\
((ITPENDINGBIT) == EXTI_IT_Pin3) ||\
((ITPENDINGBIT) == EXTI_IT_Pin4) ||\
((ITPENDINGBIT) == EXTI_IT_Pin5) ||\
((ITPENDINGBIT) == EXTI_IT_Pin6) ||\
((ITPENDINGBIT) == EXTI_IT_Pin7) ||\
((ITPENDINGBIT) == EXTI_IT_PortB) ||\
((ITPENDINGBIT) == EXTI_IT_PortD) ||\
((ITPENDINGBIT) == EXTI_IT_PortE) ||\
((ITPENDINGBIT) == EXTI_IT_PortF) ||\
((ITPENDINGBIT) == EXTI_IT_PortG) ||\
((ITPENDINGBIT) == EXTI_IT_PortH))
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* EXTI configuration *********************************************************/
void EXTI_DeInit(void);
void EXTI_SetPinSensitivity(EXTI_Pin_TypeDef EXTI_Pin, EXTI_Trigger_TypeDef EXTI_Trigger);
void EXTI_SelectPort(EXTI_Port_TypeDef EXTI_Port);
void EXTI_SetHalfPortSelection(EXTI_HalfPort_TypeDef EXTI_HalfPort, FunctionalState NewState);
void EXTI_SetPortSensitivity(EXTI_Port_TypeDef EXTI_Port, EXTI_Trigger_TypeDef EXTI_Trigger);
EXTI_Trigger_TypeDef EXTI_GetPinSensitivity(EXTI_Pin_TypeDef EXTI_Pin);
EXTI_Trigger_TypeDef EXTI_GetPortSensitivity(EXTI_Port_TypeDef EXTI_Port);
/* EXTI Interrupt status management *******************************************/
ITStatus EXTI_GetITStatus(EXTI_IT_TypeDef EXTI_IT);
void EXTI_ClearITPendingBit(EXTI_IT_TypeDef EXTI_IT);
#endif /* __STM8L15x_EXTI_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_flash.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the FLASH firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_FLASH_H
#define __STM8L15x_FLASH_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/* Exported constants --------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Constants
* @{
*/
#define FLASH_PROGRAM_START_PHYSICAL_ADDRESS ((uint32_t)0x00008000) /*!< Flash: start address */
#define FLASH_DATA_EEPROM_START_PHYSICAL_ADDRESS ((uint32_t)0x00001000) /*!< Data Eeprom: start address */
/* STM8L15x High density devices */
#if defined (STM8L15X_HD) || defined (STM8L05X_HD_VL)
#define FLASH_PROGRAM_END_PHYSICAL_ADDRESS ((uint32_t)0x00017FFF) /*!< Flash: end address */
#define FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS ((uint32_t)0x000017FF) /*!< Data Eeprom: end address */
#define FLASH_PROGRAM_BLOCKS_NUMBER ((uint16_t)0x200) /*!< Flash memory: total number of Block */
#define FLASH_DATA_EEPROM_BLOCKS_NUMBER ((uint8_t)0x10) /*!< Data EEprom: total number of Block */
#define FLASH_BLOCK_SIZE ((uint8_t)0x80) /*!< Number of bytes in a Block
(common for Program and Data EEprom memories) */
/* STM8L15x Medium density and Medium density plus devices */
#elif defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8AL31_L_MD) || defined (STM8L05X_MD_VL)
#define FLASH_PROGRAM_END_PHYSICAL_ADDRESS ((uint32_t)0x0000FFFF) /*!< Flash: end address */
#define FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS ((uint32_t)0x000013FF) /*!< Data Eeprom: end address */
#define FLASH_PROGRAM_BLOCKS_NUMBER ((uint16_t)0x100) /*!< Flash memory: total number of Block */
#define FLASH_DATA_EEPROM_BLOCKS_NUMBER ((uint8_t)0x8) /*!< Data EEprom: total number of Block */
#define FLASH_BLOCK_SIZE ((uint8_t)0x80) /*!< Number of bytes in a Block
(common for Program and Data EEprom memories) */
/* STM8L15x Low density devices */
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
#define FLASH_PROGRAM_END_PHYSICAL_ADDRESS ((uint32_t)0x00009FFF) /*!< Flash: end address */
#define FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS ((uint32_t)0x000010FF) /*!< Data Eeprom: end address */
#define FLASH_PROGRAM_BLOCKS_NUMBER ((uint16_t)0x80) /*!< Flash memory: total number of Block */
#define FLASH_DATA_EEPROM_BLOCKS_NUMBER ((uint8_t)0x4) /*!< Data EEprom: total number of Block */
#define FLASH_BLOCK_SIZE ((uint8_t)0x40) /*!< Number of bytes in a Block
(common for Program and Data EEprom memories) */
#endif /* STM8L15X_HD or STM8L05X_HD_VL*/
/*Common defines for all STM8L15x devices */
#define FLASH_OPTION_BYTES_START_PHYSICAL_ADDRESS ((uint32_t)0x00004800) /*!< Option bytes: start address */
#define FLASH_OPTION_BYTES_END_PHYSICAL_ADDRESS ((uint32_t)0x0000480A) /*!< Option bytes: end address */
#define FLASH_RASS_KEY1 ((uint8_t)0x56) /*!< First RASS key */
#define FLASH_RASS_KEY2 ((uint8_t)0xAE) /*!< Second RASS key */
#define FLASH_READOUTPROTECTION_KEY ((uint8_t)0xAA) /*!< Read out protection key */
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Types
* @{
*/
/** @defgroup FLASH_Memory_Type
* @{
*/
typedef enum
{
FLASH_MemType_Program = (uint8_t)0xFD, /*!< Program memory */
FLASH_MemType_Data = (uint8_t)0xF7 /*!< Data EEPROM memory */
} FLASH_MemType_TypeDef;
/**
* @}
*/
/** @defgroup FLASH_Programming_Mode
* @{
*/
typedef enum
{
FLASH_ProgramMode_Standard = (uint8_t)0x00, /*!< Standard programming mode */
FLASH_ProgramMode_Fast = (uint8_t)0x10 /*!< Fast programming mode */
} FLASH_ProgramMode_TypeDef;
/**
* @}
*/
/** @defgroup FLASH_Programming_Time
* @{
*/
typedef enum
{
FLASH_ProgramTime_Standard = (uint8_t)0x00, /*!< Standard programming time fixed at 1/2 tprog */
FLASH_ProgramTime_TProg = (uint8_t)0x01 /*!< Programming time fixed at tprog */
} FLASH_ProgramTime_TypeDef;
/**
* @}
*/
/** @defgroup FLASH_Power_Mode
* @{
*/
typedef enum
{
FLASH_Power_IDDQ = (uint8_t)0x00, /*!< Flash program and data EEPROM in IDDQ */
FLASH_Power_On = (uint8_t)0x01 /*!< Flash program and data EEPROM not in IDDQ */
} FLASH_Power_TypeDef;
/**
* @}
*/
/** @defgroup FLASH_Status
* @{
*/
typedef enum
{
FLASH_Status_Write_Protection_Error = (uint8_t)0x01, /*!< Write attempted to protected Block */
FLASH_Status_TimeOut = (uint8_t)0x02, /*!< Time out error */
FLASH_Status_Successful_Operation = (uint8_t)0x04 /*!< End of operation flag */
} FLASH_Status_TypeDef;
/**
* @}
*/
/** @defgroup FLASH_Power_Status
* @{
*/
typedef enum
{
FLASH_PowerStatus_IDDQDuringWaitMode = (uint8_t)0x04, /*!< Flash program and data EEPROM
in IDDQ during Wait mode*/
FLASH_PowerStatus_IDDQDuringRunMode = (uint8_t)0x08, /*!< Flash program and data EEPROM
in IDDQ mode during Run mode*/
FLASH_PowerStatus_IDDQDuringWaitAndRunModes = (uint8_t)0x0C, /*!<Flash program and data EEPROM
in IDDQ during Wait and run modes*/
FLASH_PowerStatus_On = (uint8_t)0x00 /*!< Flash program and data EEPROM
is powered on during Wait and Run modes */
} FLASH_PowerStatus_TypeDef;
/**
* @}
*/
/** @defgroup FLASH_Flags
* @{
*/
typedef enum {
FLASH_FLAG_HVOFF = (uint8_t)0x40, /*!< End of high voltage flag */
FLASH_FLAG_DUL = (uint8_t)0x08, /*!< Data EEPROM unlocked flag */
FLASH_FLAG_EOP = (uint8_t)0x04, /*!< End of programming (write or erase operation) flag */
FLASH_FLAG_PUL = (uint8_t)0x02, /*!< Flash Program memory unlocked flag */
FLASH_FLAG_WR_PG_DIS = (uint8_t)0x01 /*!< Write attempted to protected page flag */
} FLASH_FLAG_TypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Macros
* @{
*/
/**
* @brief Macro used by the assert function in order to check the different
* sensitivity values for the flash Address
*/
#define IS_FLASH_PROGRAM_ADDRESS(Address) (((Address) >= FLASH_PROGRAM_START_PHYSICAL_ADDRESS) && \
((Address) <= FLASH_PROGRAM_END_PHYSICAL_ADDRESS))
/**
* @brief Macro used by the assert function in order to check the different
* sensitivity values for the data Eeprom Address
*/
#define IS_FLASH_DATA_EEPROM_ADDRESS(Address) (((Address) >= FLASH_DATA_EEPROM_START_PHYSICAL_ADDRESS) && \
((Address) <= FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS))
/**
* @brief Macro used by the assert function in order to check the different
* sensitivity values for the data eeprom and flash program Address
*/
#define IS_FLASH_ADDRESS(Address)((((Address) >= FLASH_PROGRAM_START_PHYSICAL_ADDRESS) && ((Address) <= FLASH_PROGRAM_END_PHYSICAL_ADDRESS)) || \
(((Address) >= FLASH_DATA_EEPROM_START_PHYSICAL_ADDRESS) && ((Address) <= FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS)))
/**
* @brief Macro used by the assert function in order to check the different
* sensitivity values for the option bytes Address
*/
#define IS_OPTION_BYTE_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OPTION_BYTES_START_PHYSICAL_ADDRESS) && \
((ADDRESS) <= FLASH_OPTION_BYTES_END_PHYSICAL_ADDRESS))
/**
* @brief Macro used by the assert function in order to check the different
* sensitivity values for the flash Block number
*/
#define IS_FLASH_PROGRAM_BLOCK_NUMBER(BlockNum) ((BlockNum) < FLASH_PROGRAM_BLOCKS_NUMBER)
/**
* @brief Macro used by the assert function in order to check the different
* sensitivity values for the data eeprom Block number
*/
#define IS_FLASH_DATA_EEPROM_BLOCK_NUMBER(BlockNum) ((BlockNum) < FLASH_DATA_EEPROM_BLOCKS_NUMBER)
/**
* @brief Macro used by the assert function in order to check the different
* sensitivity values for the flash memory type
*/
#define IS_FLASH_MEMORY_TYPE(MemType) (((MemType) == FLASH_MemType_Program) || \
((MemType) == FLASH_MemType_Data))
/**
* @brief Macro used by the assert function in order to check the different
* sensitivity values for the flash program block mode
*/
#define IS_FLASH_PROGRAM_MODE(Mode) (((Mode) == FLASH_ProgramMode_Standard) || \
((Mode) == FLASH_ProgramMode_Fast))
/**
* @brief Macro used by the assert function in order to check the program time mode
*/
#define IS_FLASH_PROGRAM_TIME(Time) (((Time) == FLASH_ProgramTime_Standard) || \
((Time) == FLASH_ProgramTime_TProg))
/**
* @brief Macro used by the assert function in order to check the power mode
*/
#define IS_FLASH_POWER(Power) (((Power) == FLASH_Power_IDDQ) || \
((Power) == FLASH_Power_On))
/**
* @brief Macro used by the assert function in order to check the power status during wait and run modes
*/
#define IS_FLASH_POWERSTATUS(PowerStatus) (((PowerStatus) == FLASH_PowerStatus_IDDQDuringWaitMode) || \
((PowerStatus) == FLASH_PowerStatus_IDDQDuringRunMode ) || \
((PowerStatus) == FLASH_PowerStatus_IDDQDuringWaitAndRunModes) || \
((PowerStatus) == FLASH_Power_On))
/**
* @brief Macro used by the assert function in order to check the different flags values
*/
#define IS_FLASH_FLAGS(FLAG) (((FLAG) == FLASH_FLAG_HVOFF) || \
((FLAG) == FLASH_FLAG_DUL) || \
((FLAG) == FLASH_FLAG_EOP) || \
((FLAG) == FLASH_FLAG_PUL) || \
((FLAG) == FLASH_FLAG_WR_PG_DIS))
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* FLASH program and Data EEPROM memories interface configuration functions ***/
FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime(void);
void FLASH_SetProgrammingTime(FLASH_ProgramTime_TypeDef FLASH_ProgTime);
void FLASH_PowerWaitModeConfig(FLASH_Power_TypeDef FLASH_Power);
/* FLASH program and Data EEPROM memories Programming functions ***************/
void FLASH_DeInit(void);
void FLASH_Unlock(FLASH_MemType_TypeDef FLASH_MemType);
void FLASH_Lock(FLASH_MemType_TypeDef FLASH_MemType);
void FLASH_ProgramByte(uint32_t Address, uint8_t Data);
void FLASH_EraseByte(uint32_t Address);
void FLASH_ProgramWord(uint32_t Address, uint32_t Data);
uint8_t FLASH_ReadByte(uint32_t Address);
/* Option Bytes Programming functions *****************************************/
uint16_t FLASH_GetBootSize(void);
uint16_t FLASH_GetCodeSize(void);
FunctionalState FLASH_GetReadOutProtectionStatus(void);
void FLASH_ProgramOptionByte(uint16_t Address, uint8_t Data);
void FLASH_EraseOptionByte(uint16_t Address);
/* Interrupts and flags management functions **********************************/
void FLASH_ITConfig(FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(FLASH_FLAG_TypeDef FLASH_FLAG);
/* Functions to be executed from RAM ******************************************/
/**
@code
All the functions declared below must be executed from RAM exclusively, except
for the FLASH_WaitForLastOperation function which can be executed from Flash.
Steps of the execution from RAM differs from one toolchain to another.
for more details refer to stm8l15x_flash.c file.
To enable execution from RAM you can either uncomment the following define
in the stm8s.h file or define it in your toolchain compiler preprocessor
- #define RAM_EXECUTION (1)
@endcode
*/
IN_RAM(void FLASH_PowerRunModeConfig(FLASH_Power_TypeDef FLASH_Power));
IN_RAM(FLASH_PowerStatus_TypeDef FLASH_GetPowerStatus(void));
IN_RAM(void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType,
FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer));
IN_RAM(void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType));
IN_RAM(FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType));
#endif /*__STM8L15x_FLASH_H*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_gpio.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the GPIO firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_GPIO_H
#define __STM8L15x_GPIO_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Types
* @{
*/
/**
* @defgroup GPIO_Modes
*
* @brief
*
* Bits definitions:
* - Bit 7: 0 = INPUT mode
* 1 = OUTPUT mode
* 1 = PULL-UP (input) or PUSH-PULL (output)
* - Bit 5: 0 = No external interrupt (input) or No slope control (output)
* 1 = External interrupt (input) or Slow control enabled (output)
* - Bit 4: 0 = Low level (output)
* 1 = High level (output push-pull) or HI-Z (output open-drain)
* @{
*/
typedef enum
{
GPIO_Mode_In_FL_No_IT = (uint8_t)0x00, /*!< Input floating, no external interrupt */
GPIO_Mode_In_PU_No_IT = (uint8_t)0x40, /*!< Input pull-up, no external interrupt */
GPIO_Mode_In_FL_IT = (uint8_t)0x20, /*!< Input floating, external interrupt */
GPIO_Mode_In_PU_IT = (uint8_t)0x60, /*!< Input pull-up, external interrupt */
GPIO_Mode_Out_OD_Low_Fast = (uint8_t)0xA0, /*!< Output open-drain, low level, 10MHz */
GPIO_Mode_Out_PP_Low_Fast = (uint8_t)0xE0, /*!< Output push-pull, low level, 10MHz */
GPIO_Mode_Out_OD_Low_Slow = (uint8_t)0x80, /*!< Output open-drain, low level, 2MHz */
GPIO_Mode_Out_PP_Low_Slow = (uint8_t)0xC0, /*!< Output push-pull, low level, 2MHz */
GPIO_Mode_Out_OD_HiZ_Fast = (uint8_t)0xB0, /*!< Output open-drain, high-impedance level, 10MHz */
GPIO_Mode_Out_PP_High_Fast = (uint8_t)0xF0, /*!< Output push-pull, high level, 10MHz */
GPIO_Mode_Out_OD_HiZ_Slow = (uint8_t)0x90, /*!< Output open-drain, high-impedance level, 2MHz */
GPIO_Mode_Out_PP_High_Slow = (uint8_t)0xD0 /*!< Output push-pull, high level, 2MHz */
}GPIO_Mode_TypeDef;
/**
* @}
*/
/** @defgroup GPIO_Pin
* @{
*/
typedef enum
{
GPIO_Pin_0 = ((uint8_t)0x01), /*!< Pin 0 selected */
GPIO_Pin_1 = ((uint8_t)0x02), /*!< Pin 1 selected */
GPIO_Pin_2 = ((uint8_t)0x04), /*!< Pin 2 selected */
GPIO_Pin_3 = ((uint8_t)0x08), /*!< Pin 3 selected */
GPIO_Pin_4 = ((uint8_t)0x10), /*!< Pin 4 selected */
GPIO_Pin_5 = ((uint8_t)0x20), /*!< Pin 5 selected */
GPIO_Pin_6 = ((uint8_t)0x40), /*!< Pin 6 selected */
GPIO_Pin_7 = ((uint8_t)0x80), /*!< Pin 7 selected */
GPIO_Pin_LNib = ((uint8_t)0x0F), /*!< Low nibble pins selected */
GPIO_Pin_HNib = ((uint8_t)0xF0), /*!< High nibble pins selected */
GPIO_Pin_All = ((uint8_t)0xFF) /*!< All pins selected */
}GPIO_Pin_TypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Macros
* @{
*/
/**
* @brief Macro used by the assert function to check the different functions parameters.
*/
/**
* @brief Macro used by the assert function in order to check the different
* values of GPIOMode_TypeDef.
*/
#define IS_GPIO_MODE(MODE) \
(((MODE) == GPIO_Mode_In_FL_No_IT) || \
((MODE) == GPIO_Mode_In_PU_No_IT) || \
((MODE) == GPIO_Mode_In_FL_IT) || \
((MODE) == GPIO_Mode_In_PU_IT) || \
((MODE) == GPIO_Mode_Out_OD_Low_Fast) || \
((MODE) == GPIO_Mode_Out_PP_Low_Fast) || \
((MODE) == GPIO_Mode_Out_OD_Low_Slow) || \
((MODE) == GPIO_Mode_Out_PP_Low_Slow) || \
((MODE) == GPIO_Mode_Out_OD_HiZ_Fast) || \
((MODE) == GPIO_Mode_Out_PP_High_Fast) || \
((MODE) == GPIO_Mode_Out_OD_HiZ_Slow) || \
((MODE) == GPIO_Mode_Out_PP_High_Slow))
/**
* @brief Macro used by the assert function in order to check the different
* values of GPIO_Pins.
*/
#define IS_GPIO_PIN(PIN) ((PIN) != (uint8_t)0x00)
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* Initialization and Configuration *******************************************/
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_Init(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode);
void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, FunctionalState NewState);
/* GPIO Read and Write ********************************************************/
void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t GPIO_PortVal);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction GPIO_BitVal);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin);
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin);
uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
BitStatus GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
BitStatus GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
#endif /* __STM8L15x_GPIO_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_i2c.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_I2C_H
#define __STM8L15x_I2C_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types
* @{
*/
/** @defgroup I2C_mode
* @{
*/
typedef enum
{
I2C_Mode_I2C = (uint8_t)0x00, /*!< I2C mode */
I2C_Mode_SMBusDevice = (uint8_t)0x02, /*!< SMBus Device mode */
I2C_Mode_SMBusHost = (uint8_t)0x0A /*!< SMBus Host mode */
} I2C_Mode_TypeDef;
/**
* @}
*/
/** @defgroup I2C_duty_cycle_in_fast_mode
* @{
*/
typedef enum
{
I2C_DutyCycle_2 = (uint8_t)0x00, /*!< Fast mode Tlow/THigh = 2 */
I2C_DutyCycle_16_9 = (uint8_t)0x40 /*!< Fast mode Tlow/Thigh = 16/9 */
} I2C_DutyCycle_TypeDef;
/**
* @}
*/
/** @defgroup I2C_acknowledgement
* @{
*/
typedef enum
{
I2C_Ack_Disable = (uint8_t)0x00, /*!< No acknowledge */
I2C_Ack_Enable = (uint8_t)0x04 /*!< Acknowledge Enabled */
} I2C_Ack_TypeDef;
/**
* @}
*/
/** @defgroup I2C_Position_Acknowledgement
* @{
*/
typedef enum
{
I2C_AckPosition_Current = (uint8_t)0x00, /*!< Acknowledge on the current byte */
I2C_AckPosition_Next = (uint8_t)0x08 /*!< Acknowledge on the next byte */
} I2C_AckPosition_TypeDef;
/**
* @}
*/
/** @defgroup I2C_acknowledged_address
* @{
*/
typedef enum
{
I2C_AcknowledgedAddress_7bit = (uint8_t)0x00, /*!< 7-bit slave address (10-bit address not acknowledged) */
I2C_AcknowledgedAddress_10bit = (uint8_t)0x80 /*!< 10-bit slave address (7-bit address not acknowledged) */
} I2C_AcknowledgedAddress_TypeDef;
/**
* @}
*/
/** @defgroup I2C_transfer_direction
* @{
*/
/**
* Warning: the values correspond to the ADD0 bit position in the OARL register
*/
typedef enum
{
I2C_Direction_Transmitter = (uint8_t)0x00, /*!< Transmission direction */
I2C_Direction_Receiver = (uint8_t)0x01 /*!< Reception direction */
} I2C_Direction_TypeDef;
/**
* @}
*/
/** @defgroup I2C_SMBus_alert_pin_level
* @{
*/
typedef enum
{
I2C_SMBusAlert_High = (uint8_t)0x00, /*!< SMBAlert pin high */
I2C_SMBusAlert_Low = (uint8_t)0x01 /*!< SMBAlert pin Low */
} I2C_SMBusAlert_TypeDef;
/**
* @}
*/
/** @defgroup I2C_PEC_position
* @{
*/
typedef enum
{
I2C_PECPosition_Current = (uint8_t)0x00, /*!< Current byte in shift register is PEC */
I2C_PECPosition_Next = (uint8_t)0x08 /*!< Next byte in shift register is PEC */
} I2C_PECPosition_TypeDef;
/**
* @}
*/
/** @defgroup I2C_flags_definition
* @{
*/
/**
* @brief Elements values convention: 0xXXYY
* X = SRx registers index
* X = 1 : SR1
* X = 2 : SR2
* X = 3 : SR3
* Y = Flag mask in the register
*/
typedef enum
{
/* SR1 register flags */
I2C_FLAG_TXE = (uint16_t)0x0180, /*!< Transmit Data Register Empty flag */
I2C_FLAG_RXNE = (uint16_t)0x0140, /*!< Read Data Register Not Empty flag */
I2C_FLAG_STOPF = (uint16_t)0x0110, /*!< Stop detected flag */
I2C_FLAG_ADD10 = (uint16_t)0x0108, /*!< 10-bit Header sent flag */
I2C_FLAG_BTF = (uint16_t)0x0104, /*!< Data Byte Transfer Finished flag */
I2C_FLAG_ADDR = (uint16_t)0x0102, /*!< Address Sent/Matched (master/slave) flag */
I2C_FLAG_SB = (uint16_t)0x0101, /*!< Start bit sent flag */
/* SR2 register flags */
I2C_FLAG_SMBALERT = (uint16_t)0x0280, /*!< SMBUS Alert flag */
I2C_FLAG_TIMEOUT = (uint16_t)0x0240, /*!< Time out flag */
I2C_FLAG_WUFH = (uint16_t)0x0220, /*!< Wake Up From Halt flag */
I2C_FLAG_PECERR = (uint16_t)0x0210, /*!< PEC error flag */
I2C_FLAG_OVR = (uint16_t)0x0208, /*!< Overrun/Underrun flag */
I2C_FLAG_AF = (uint16_t)0x0204, /*!< Acknowledge Failure flag */
I2C_FLAG_ARLO = (uint16_t)0x0202, /*!< Arbitration Loss flag */
I2C_FLAG_BERR = (uint16_t)0x0201, /*!< Misplaced Start or Stop condition */
/* SR3 register flags */
I2C_FLAG_DUALF = (uint16_t)0x0380, /*!< DUAL Flag */
I2C_FLAG_SMBHOST = (uint16_t)0x0340, /*!< SMBUS host Flag */
I2C_FLAG_SMBDEFAULT = (uint16_t)0x0320, /*!< SMBUS default flag */
I2C_FLAG_GENCALL = (uint16_t)0x0310, /*!< General Call header received Flag */
I2C_FLAG_TRA = (uint16_t)0x0304, /*!< Transmitter Receiver flag */
I2C_FLAG_BUSY = (uint16_t)0x0302, /*!< Bus Busy flag */
I2C_FLAG_MSL = (uint16_t)0x0301 /*!< Master Slave flag */
} I2C_FLAG_TypeDef;
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @{
*/
/**
* @brief I2C Pending bits
* Elements values convention: 0xXYZZ
* X = SRx registers index
* X = 0 : ITR
* X = 1 : SR1
* X = 2 : SR2
* Y = Position of the corresponding Interrupt
* ZZ = flag mask in the dedicated register(X register)
*/
typedef enum
{
I2C_IT_ERR = (uint16_t)0x0001, /*!< Error Interruption */
I2C_IT_EVT = (uint16_t)0x0002, /*!< Event Interruption */
I2C_IT_BUF = (uint16_t)0x0004, /*!< Buffer Interruption */
/* SR1 register*/
I2C_IT_TXE = (uint16_t)0x1680, /*!< Transmit Data Register Empty */
I2C_IT_RXNE = (uint16_t)0x1640, /*!< Read Data Register Not Empty */
I2C_IT_STOPF = (uint16_t)0x1210, /*!< Stop detected */
I2C_IT_ADD10 = (uint16_t)0x1208, /*!< 10-bit Header sent */
I2C_IT_BTF = (uint16_t)0x1204, /*!< Data Byte Transfer Finished */
I2C_IT_ADDR = (uint16_t)0x1202, /*!< Address Sent/Matched (master/slave) */
I2C_IT_SB = (uint16_t)0x1201, /*!< Start bit sent */
/* SR2 register*/
I2C_IT_SMBALERT = (uint16_t)0x2180, /*!< SMBUS alert */
I2C_IT_TIMEOUT = (uint16_t)0x2140, /*!< Time out */
I2C_IT_WUFH = (uint16_t)0x2220, /*!< PEC error */
I2C_IT_PECERR = (uint16_t)0x2110, /*!< Wake Up From Halt */
I2C_IT_OVR = (uint16_t)0x2108, /*!< Overrun/Underrun */
I2C_IT_AF = (uint16_t)0x2104, /*!< Acknowledge Failure */
I2C_IT_ARLO = (uint16_t)0x2102, /*!< Arbitration Loss */
I2C_IT_BERR = (uint16_t)0x2101 /*!< Misplaced Start or Stop condition */
} I2C_IT_TypeDef;
/**
* @}
*/
/** @defgroup I2C_Events
* @{
*/
/**
* @brief I2C possible events
* Values convention: 0xXXYY
* XX = Event SR3 corresponding value
* YY = Event SR1 corresponding value
* @note if Event = EV3_2 the rule above does not apply
* YY = Event SR2 corresponding value
*/
typedef enum
{
/**
===============================================================================
I2C Master Events (Events grouped in order of communication)
===============================================================================
*/
/**
* @brief Communication start
*
* After sending the START condition (I2C_GenerateSTART() function) the master
* has to wait for this event. It means that the Start condition has been correctly
* released on the I2C bus (the bus is free, no other devices is communicating).
*
*/
/* --EV5 */
I2C_EVENT_MASTER_MODE_SELECT = (uint16_t)0x0301, /*!< BUSY, MSL and SB flag */
/**
* @brief Address Acknowledge
*
* After checking on EV5 (start condition correctly released on the bus), the
* master sends the address of the slave(s) with which it will communicate
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
* Master transmitter or Receiver).
* Then the master has to wait that a slave acknowledges his address.
* If an acknowledge is sent on the bus, one of the following events will
* be set:
*
* 1) In case of Master Receiver (7-bit addressing):
* the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set.
*
* 2) In case of Master Transmitter (7-bit addressing):
* the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set
*
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
* function).
* Then master should wait on EV9. It means that the 10-bit addressing
* header has been correctly sent on the bus.
* Then master should send the second part of the 10-bit address (LSB) using
* the function I2C_Send7bitAddress(). Then master should wait for event EV6.
*
*/
/* --EV6 */
I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782, /*!< BUSY, MSL, ADDR, TXE and TRA flags */
I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = (uint16_t)0x0302, /*!< BUSY, MSL and ADDR flags */
/* --EV9 */
I2C_EVENT_MASTER_MODE_ADDRESS10 = (uint16_t)0x0308, /*!< BUSY, MSL and ADD10 flags */
/**
* @brief Communication events
*
* If a communication is established (START condition generated and slave address
* acknowledged) then the master has to check on one of the following events for
* communication procedures:
*
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
* the data received from the slave (I2C_ReceiveData() function).
*
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
* function) then to wait on event EV8 or EV8_2.
* These two events are similar:
* - EV8 means that the data has been written in the data register and is
* being shifted out.
* - EV8_2 means that the data has been physically shifted out and output
* on the bus.
* In most cases, using EV8 is sufficient for the application.
* Using EV8_2 leads to a slower communication but ensure more reliable test.
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
* (before Stop condition generation).
*
* @note In case the user software does not guarantee that this event EV7 is
* managed before the current byte end of transfer, then user may check on EV7
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
* In this case the communication may be slower.
*
*/
/* Master RECEIVER mode -----------------------------*/
/* --EV7 */
I2C_EVENT_MASTER_BYTE_RECEIVED = (uint16_t)0x0340, /*!< BUSY, MSL and RXNE flags */
/* Master TRANSMITTER mode --------------------------*/
/* --EV8 */
I2C_EVENT_MASTER_BYTE_TRANSMITTING = (uint16_t)0x0780, /*!< TRA, BUSY, MSL, TXE flags */
/* --EV8_2 */
I2C_EVENT_MASTER_BYTE_TRANSMITTED = (uint16_t)0x0784, /*!< EV8_2: TRA, BUSY, MSL, TXE and BTF flags */
/**
===============================================================================
I2C Slave Events (Events grouped in order of communication)
===============================================================================
*/
/**
* @brief Communication start events
*
* Wait on one of these events at the start of the communication. It means that
* the I2C peripheral detected a Start condition on the bus (generated by master
* device) followed by the peripheral address.
* The peripheral generates an ACK condition on the bus (if the acknowledge
* feature is enabled through function I2C_AcknowledgeConfig()) and the events
* listed above are set :
*
* 1) In normal case (only one address managed by the slave), when the address
* sent by the master matches the own address of the peripheral (configured by
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
* (where XXX could be TRANSMITTER or RECEIVER).
*
* 2) In case the address sent by the master matches the second address of the
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
* (where XXX could be TRANSMITTER or RECEIVER) are set.
*
* 3) In case the address sent by the master is General Call (address 0x00) and
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
*
*/
/* --EV1 (all the events below are variants of EV1) */
/* 1) Case of One Single Address managed by the slave */
I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = (uint16_t)0x0202, /*!< BUSY and ADDR flags */
I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682, /*!< TRA, BUSY, TXE and ADDR flags */
/* 2) Case of Dual address managed by the slave */
I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED = (uint16_t)0x8200, /*! DUALF and BUSY flags */
I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED = (uint16_t)0x8680, /*! DUALF, TRA, BUSY and TXE flags */
/* 3) Case of General Call enabled for the slave */
I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = (uint16_t)0x1200, /*!< EV2: GENCALL and BUSY flags */
/**
* @brief Communication events
*
* Wait on one of these events when EV1 has already been checked :
*
* - Slave RECEIVER mode:
* - EV2: When the application is expecting a data byte to be received.
* - EV4: When the application is expecting the end of the communication:
* master sends a stop condition and data transmission is stopped.
*
* - Slave Transmitter mode:
* - EV3: When a byte has been transmitted by the slave and the application
* is expecting the end of the byte transmission.
* The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING
* are similar. The second one can optionally be used when the user software
* doesn't guarantee the EV3 is managed before the current byte end of transfer.
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
* shall end (before sending the STOP condition).
* In this case slave has to stop sending data bytes and expect a Stop
* condition on the bus.
*
* @note In case the user software does not guarantee that the event EV2 is
* managed before the current byte end of transfer, then user may check on EV2
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
* In this case the communication may be slower.
*
*/
/* Slave RECEIVER mode --------------------------*/
/* --EV2 */
I2C_EVENT_SLAVE_BYTE_RECEIVED = (uint16_t)0x0240, /*!< BUSY and RXNE flags */
/* --EV4 */
I2C_EVENT_SLAVE_STOP_DETECTED = (uint16_t)0x0010, /*!< STOPF flag */
/* Slave TRANSMITTER mode -----------------------*/
/* --EV3 */
I2C_EVENT_SLAVE_BYTE_TRANSMITTED = (uint16_t)0x0684, /*!< TRA, BUSY, TXE and BTF flags */
I2C_EVENT_SLAVE_BYTE_TRANSMITTING = (uint16_t)0x0680, /*!< TRA, BUSY and TXE flags */
/* --EV3_2 */
I2C_EVENT_SLAVE_ACK_FAILURE = (uint16_t)0x0004 /*!< AF flag */
} I2C_Event_TypeDef;
/**
* @}
*/
/** @defgroup I2C_Registers
* @{
*/
typedef enum
{
I2C_Register_CR1 = (uint8_t)0x00, /*!< Control register 1 */
I2C_Register_CR2 = (uint8_t)0x01, /*!< Control register 2 */
I2C_Register_FREQR = (uint8_t)0x02, /*!< Frequency register */
I2C_Register_OARL = (uint8_t)0x03, /*!< Own address register LSB */
I2C_Register_OARH = (uint8_t)0x04, /*!< Own address register MSB */
I2C_Register_DR = (uint8_t)0x06, /*!< Data register */
I2C_Register_SR1 = (uint8_t)0x07, /*!< Status register 1 */
I2C_Register_SR2 = (uint8_t)0x08, /*!< Status register 2 */
I2C_Register_SR3 = (uint8_t)0x09, /*!< Status register 3 */
I2C_Register_ITR = (uint8_t)0x0A, /*!< Interrupt and DMA register */
I2C_Register_CCRL = (uint8_t)0x0B, /*!< Clock control register low */
I2C_Register_CCRH = (uint8_t)0x0C, /*!< Clock control register high */
I2C_Register_TRISER = (uint8_t)0x0D, /*!< TRISE register */
I2C_Register_PECR = (uint8_t)0x0E /*!< PEC register */
} I2C_Register_TypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants
* @{
*/
#define I2C_MAX_STANDARD_FREQ ((uint32_t)100000)
#define I2C_MAX_FAST_FREQ ((uint32_t)400000)
/**
*@}
*/
/* Exported macro -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros
* @{
*/
/**
* @brief Macro used by the assert function to check the different functions parameters.
*/
/**
* @brief Macro used by the assert function to check the different I2C modes.
*/
#define IS_I2C_MODE(MODE)(((MODE) == I2C_Mode_I2C) || \
((MODE) == I2C_Mode_SMBusDevice) || \
((MODE) == I2C_Mode_SMBusHost))
/**
* @brief Macro used by the assert function to check the different I2C duty cycles.
*/
#define IS_I2C_DUTY_CYCLE(CYCLE)(((CYCLE) == I2C_DutyCycle_2) || \
((CYCLE) == I2C_DutyCycle_16_9))
/**
* @brief Macro used by the assert function to check the different acknowledgement configuration
*/
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Disable) || \
((STATE) == I2C_Ack_Enable))
/**
* @brief Macro used by the assert function to check the different acknowledgement position
*/
#define IS_I2C_ACK_POSITION(POSITION) (((POSITION) == I2C_AckPosition_Next) || \
((POSITION) == I2C_AckPosition_Current))
/**
* @brief Macro used by the assert function to check the different I2C PEC positions.
*/
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Current) || \
((POSITION) == I2C_PECPosition_Next))
/**
* @brief Macro used by the assert function to check the different I2C addressing modes.
*/
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDMODE) (((ADDMODE) == I2C_AcknowledgedAddress_7bit) || \
((ADDMODE) == I2C_AcknowledgedAddress_10bit))
/**
* @brief Macro used by the assert function to check the different I2C SMBus Alert pin configuration.
*/
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_High) || \
((ALERT) == I2C_SMBusAlert_Low))
/**
* @brief Macro used by the assert function to check the different I2C communication direction.
*/
#define IS_I2C_DIRECTION(DIR)(((DIR) == I2C_Direction_Transmitter) || \
((DIR) == I2C_Direction_Receiver ))
/**
* @brief Macro used by the assert function to check the different I2C flags.
*/
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || \
((FLAG) == I2C_FLAG_RXNE) || \
((FLAG) == I2C_FLAG_STOPF) || \
((FLAG) == I2C_FLAG_ADD10) || \
((FLAG) == I2C_FLAG_BTF) || \
((FLAG) == I2C_FLAG_ADDR) || \
((FLAG) == I2C_FLAG_SB) || \
((FLAG) == I2C_FLAG_SMBALERT) || \
((FLAG) == I2C_FLAG_TIMEOUT) || \
((FLAG) == I2C_FLAG_WUFH) || \
((FLAG) == I2C_FLAG_PECERR) || \
((FLAG) == I2C_FLAG_OVR) || \
((FLAG) == I2C_FLAG_AF) || \
((FLAG) == I2C_FLAG_ARLO) || \
((FLAG) == I2C_FLAG_BERR) || \
((FLAG) == I2C_FLAG_DUALF) || \
((FLAG) == I2C_FLAG_SMBHOST) || \
((FLAG) == I2C_FLAG_SMBDEFAULT) || \
((FLAG) == I2C_FLAG_GENCALL) || \
((FLAG) == I2C_FLAG_TRA) || \
((FLAG) == I2C_FLAG_BUSY) || \
((FLAG) == I2C_FLAG_MSL))
/**
* @brief Macro used by the assert function to check the I2C flags to clear.
*/
#define IS_I2C_CLEAR_FLAG(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xFD00) == 0x00) && ((uint16_t)(FLAG) != 0x00))
/**
* @brief Macro used by the assert_param function in order to check the different
* sensitivity values for the Interrupts
*/
#define IS_I2C_CONFIG_IT(IT) ((((uint16_t)(IT) & (uint16_t)0xFFF8) == 0x00) && ((uint16_t)(IT) != 0x00))
/**
* @brief Macro used by the assert function to check the different I2C possible
* pending bits to clear by writing 0.
*/
#define IS_I2C_CLEAR_IT(IT) ((((uint16_t)(IT) & (uint16_t)0xDC00) == 0x00) && ((uint16_t)(IT) != 0x00))
/**
* @brief Macro used by the assert function to check the different I2C possible pending bits.
*/
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_OVR) ||\
((IT) == I2C_IT_AF) ||\
((IT) == I2C_IT_ARLO) ||\
((IT) == I2C_IT_BERR) ||\
((IT) == I2C_IT_TXE) ||\
((IT) == I2C_IT_RXNE) ||\
((IT) == I2C_IT_STOPF) ||\
((IT) == I2C_IT_ADD10) ||\
((IT) == I2C_IT_BTF) ||\
((IT) == I2C_IT_ADDR) ||\
((IT) == I2C_IT_PECERR) ||\
((IT) == I2C_IT_TIMEOUT) ||\
((IT) == I2C_IT_SMBALERT) ||\
((IT) == I2C_IT_WUFH) ||\
((IT) == I2C_IT_SB))
/**
* @brief Macro used by the assert function to check the different I2C possible events.
*/
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_DUALF)) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_GENCALL)) || \
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_DUALF)) || \
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_GENCALL)) || \
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE) || \
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10))
/**
* @brief Macro used by the assert function to check the different I2C registers.
*/
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
((REGISTER) == I2C_Register_CR2) || \
((REGISTER) == I2C_Register_FREQR) || \
((REGISTER) == I2C_Register_OARL) || \
((REGISTER) == I2C_Register_OARH) || \
((REGISTER) == I2C_Register_DR) || \
((REGISTER) == I2C_Register_SR1) || \
((REGISTER) == I2C_Register_SR2) || \
((REGISTER) == I2C_Register_SR3) || \
((REGISTER) == I2C_Register_ITR) || \
((REGISTER) == I2C_Register_CCRL) || \
((REGISTER) == I2C_Register_CCRH) || \
((REGISTER) == I2C_Register_TRISER) || \
((REGISTER) == I2C_Register_PECR))
/**
* @brief Macro used by the assert function to check the different I2C possible own address.
*/
#define IS_I2C_OWN_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
/**
* @brief Macro used by the assert function to check the different I2C address
* The address must be even
*/
#define IS_I2C_ADDRESS(ADD) (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)
/**
* @brief Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.
*/
#define IS_I2C_OUTPUT_CLOCK_FREQ(FREQ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the I2C configuration to the default reset state *****/
void I2C_DeInit(I2C_TypeDef* I2Cx);
/* Initialization and Configuration functions *********************************/
void I2C_Init(I2C_TypeDef* I2Cx, uint32_t OutputClockFrequency, uint16_t OwnAddress,
I2C_Mode_TypeDef I2C_Mode, I2C_DutyCycle_TypeDef I2C_DutyCycle,
I2C_Ack_TypeDef I2C_Ack, I2C_AcknowledgedAddress_TypeDef I2C_AcknowledgedAddress);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AckPositionConfig(I2C_TypeDef* I2Cx, I2C_AckPosition_TypeDef I2C_AckPosition);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, I2C_DutyCycle_TypeDef I2C_DutyCycle);
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, I2C_SMBusAlert_TypeDef I2C_SMBusAlert);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, I2C_Direction_TypeDef I2C_Direction);
/* Data transfers functions ***************************************************/
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
/* PEC management functions ***************************************************/
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, I2C_PECPosition_TypeDef I2C_PECPosition);
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
/* DMA transfers management functions *****************************************/
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
/* Interrupts, events and flags management functions **************************/
void I2C_ITConfig(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT, FunctionalState NewState);
uint8_t I2C_ReadRegister(I2C_TypeDef* I2Cx, I2C_Register_TypeDef I2C_Register);
/**
* @brief
*
@verbatim
================================================================================
I2C State Monitoring Functions
================================================================================
This I2C driver provides three different ways for I2C state monitoring
depending on the application requirements and constraints:
1) Basic state monitoring:
Using I2C_CheckEvent() function:
It compares the status registers (SR1, SR2 and SR3) content to a given event
(can be the combination of one or more flags).
It returns SUCCESS if the current status includes the given flags
and returns ERROR if one or more flags are missing in the current status.
- When to use:
- This function is suitable for most applications as well as for startup
activity since the events are fully described in the product reference manual
(RM0031).
- It is also suitable for users who need to define their own events.
- Limitations:
- If an error occurs (ie. error flags are set besides to the monitored flags),
the I2C_CheckEvent() function may return SUCCESS despite the communication
hold or corrupted real state.
In this case, it is advised to use error interrupts to monitor the error
events and handle them in the interrupt IRQ handler.
@note
For error management, it is advised to use the following functions:
- I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
- I2Cx_IRQHandler() which is called when the I2C interrupts occur.
Where x is the peripheral instance (I2C1,...)
- I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
I2Cx_IRQHandler() function in order to determine which error occurred.
- I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
and/or I2C_GenerateStop() in order to clear the error flag and
source and return to correct communication status.
2) Advanced state monitoring:
Using the function I2C_GetLastEvent() which returns the image of both SR1
& SR3 status registers in a single word (uint16_t) (Status Register 3 value
is shifted left by 8 bits and concatenated to Status Register 1).
- When to use:
- This function is suitable for the same applications above but it allows to
overcome the limitations of I2C_GetFlagStatus() function (see below).
The returned value could be compared to events already defined in the
library (stm8l15x_i2c.h) or to custom values defined by user.
- This function is suitable when multiple flags are monitored at the same time.
- At the opposite of I2C_CheckEvent() function, this function allows user to
choose when an event is accepted (when all events flags are set and no
other flags are set or just when the needed flags are set like
I2C_CheckEvent() function).
- Limitations:
- User may need to define his own events.
- Same remark concerning the error management is applicable for this
function if user decides to check only regular communication flags (and
ignores error flags).
3) Flag-based state monitoring:
Using the function I2C_GetFlagStatus() which simply returns the status of
one single flag (ie. I2C_FLAG_RXNE ...).
- When to use:
- This function could be used for specific applications or in debug phase.
- It is suitable when only one flag checking is needed (most I2C events
are monitored through multiple flags).
- Limitations:
- When calling this function, the Status register is accessed. Some flags are
cleared when the status register is accessed. So checking the status
of one Flag, may clear other ones.
- Function may need to be called twice or more in order to monitor one
single event.
@endverbatim
*
*/
/**
===============================================================================
1. Basic state monitoring
===============================================================================
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, I2C_Event_TypeDef I2C_Event);
/**
===============================================================================
2. Advanced state monitoring
===============================================================================
*/
I2C_Event_TypeDef I2C_GetLastEvent(I2C_TypeDef* I2Cx);
/**
===============================================================================
3. Flag-based state monitoring
===============================================================================
*/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, I2C_FLAG_TypeDef I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef* I2Cx, I2C_FLAG_TypeDef I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT);
#endif /* __STM8L15x_I2C_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_irtim.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the IRTIM firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_IRTIM_H
#define __STM8L15x_IRTIM_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup IRTIM
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* IRTIM configuration ********************************************************/
void IRTIM_DeInit(void);
void IRTIM_Cmd(FunctionalState NewState);
void IRTIM_HighSinkODCmd(FunctionalState NewState);
/* IRITM status management ****************************************************/
FunctionalState IRTIM_GetStatus(void);
FunctionalState IRTIM_GetHighSinkODStatus(void);
/**
* @}
*/
#endif /* __STM8L15x_IRTIM_H */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_itc.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the ITC firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_ITC_H
#define __STM8L15x_ITC_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup ITC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ITC_Exported_Types
* @{
*/
/** @defgroup ITC_Interrupt_Lines_selection
* @{
*/
typedef enum {
FLASH_IRQn = (uint8_t)1, /*!< Flash interrupt */
DMA1_CHANNEL0_1_IRQn = (uint8_t)2, /*!< DMA Channels 0/1 */
DMA1_CHANNEL2_3_IRQn = (uint8_t)3, /*!< DMA Channels 2/3 */
EXTIE_F_PVD_IRQn = (uint8_t)5, /*!< GPIOE/F and PVD interrupt */
EXTI0_IRQn = (uint8_t)8, /*!< PIN0 interrupt */
EXTI1_IRQn = (uint8_t)9, /*!< PIN1 interrupt */
EXTI2_IRQn = (uint8_t)10, /*!< PIN2 interrupt */
EXTI3_IRQn = (uint8_t)11, /*!< PIN3 interrupt */
EXTI4_IRQn = (uint8_t)12, /*!< PIN4 interrupt */
EXTI5_IRQn = (uint8_t)13, /*!< PIN5 interrupt */
EXTI6_IRQn = (uint8_t)14, /*!< PIN6 interrupt */
EXTI7_IRQn = (uint8_t)15, /*!< PIN7 interrupt */
ADC1_COMP_IRQn = (uint8_t)18, /*!< ADC1/Comparator interrupt */
TIM4_UPD_OVF_TRG_IRQn = (uint8_t)25, /*!< TIM4 Update/Overflow/Trigger interrupt */
SPI1_IRQn = (uint8_t)26, /*!< SPI1 interrupt */
#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
RTC_IRQn = (uint8_t)4, /*!< RTC interrupt */
EXTIB_IRQn = (uint8_t)6, /*!< GPIOB interrupt */
EXTID_IRQn = (uint8_t)7, /*!< GPIOD interrupt */
LCD_IRQn = (uint8_t)16, /*!< LCD Driver interrupt */
SWITCH_CSS_BREAK_DAC_IRQn = (uint8_t)17, /*!< Clock switch/CSS interrupt/TIM1 Break /DAC interrupt */
TIM2_UPD_OVF_TRG_BRK_IRQn = (uint8_t)19, /*!< TIM2 Update/Overflow/Trigger/Break interrupt*/
TIM2_CC_IRQn = (uint8_t)20, /*!< TIM2 input captute/output compare interrupt */
TIM3_UPD_OVF_TRG_BRK_IRQn = (uint8_t)21, /*!< TIM3 Update/Overflow/Trigger/Break interrupt */
TIM3_CC_IRQn = (uint8_t)22, /*!< TIM3 capture/compare interrupt */
TIM1_UPD_OVF_TRG_IRQn = (uint8_t)23, /*!< TIM1 TIM1 Update/Overflow/Trigger interrupt */
TIM1_CC_IRQn = (uint8_t)24, /*!< TIM1 capture/compare interrupt */
USART1_TX_IRQn = (uint8_t)27, /*!< USART1 TX interrupt */
USART1_RX_IRQn = (uint8_t)28, /*!< USART1 RX interrupt */
I2C1_IRQn = (uint8_t)29 /*!< I2C1 interrupt */
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
RTC_CSSLSE_IRQn = (uint8_t)4, /*!< RTC / CSSLSE interrupt */
EXTIB_IRQn = (uint8_t)6, /*!< GPIOB interrupt */
EXTID_IRQn = (uint8_t)7, /*!< GPIOD interrupt */
SWITCH_CSS_IRQn = (uint8_t)17, /*!< Clock switch/CSS interrupt/TIM1 Break /DAC interrupt */
TIM2_UPD_OVF_TRG_BRK_IRQn = (uint8_t)19, /*!< TIM2 Update/Overflow/Trigger/Break interrupt*/
TIM2_CC_IRQn = (uint8_t)20, /*!< TIM2 input captute/output compare interrupt */
TIM3_UPD_OVF_TRG_BRK_IRQn = (uint8_t)21, /*!< TIM3 Update/Overflow/Trigger/Break interrupt */
TIM3_CC_IRQn = (uint8_t)22, /*!< TIM3 capture/compare interrupt */
USART1_TX_IRQn = (uint8_t)27, /*!< USART1 TX interrupt */
USART1_RX_IRQn = (uint8_t)28, /*!< USART1 RX interrupt */
I2C1_IRQn = (uint8_t)29 /*!< I2C1 interrupt */
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
RTC_CSSLSE_IRQn = (uint8_t)4, /*!< RTC / CSSLSE interrupt */
EXTIB_G_IRQn = (uint8_t)6, /*!< GPIOB / G interrupt */
EXTID_H_IRQn = (uint8_t)7, /*!< GPIOD / H interrupt */
LCD_AES_IRQn = (uint8_t)16, /*!< LCD / AES interrupt */
SWITCH_CSS_BREAK_DAC_IRQn = (uint8_t)17, /*!< Clock switch/CSS interrupt/TIM1 Break /DAC interrupt */
TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn = (uint8_t)19, /*!< TIM2 Update/Overflow/Trigger/Break /USART2 TX interrupt*/
TIM2_CC_USART2_RX_IRQn = (uint8_t)20, /*!< TIM2 capture/compare / USART2 RX interrupt */
TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn = (uint8_t)21, /*!< TIM3 Update/Overflow/Trigger/Break / USART3 TX interrupt */
TIM3_CC_USART3_RX_IRQn = (uint8_t)22, /*!< TIM3 capture/compare / USART3 RX interrupt */
TIM1_UPD_OVF_TRG_IRQn = (uint8_t)23, /*!< TIM1 TIM1 Update/Overflow/Trigger interrupt */
TIM1_CC_IRQn = (uint8_t)24, /*!< TIM1 capture/compare interrupt */
USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn = (uint8_t)27, /*!< USART1 TX / TIM5 Update/Overflow/Trigger/Break interrupt */
USART1_RX_TIM5_CC_IRQn = (uint8_t)28, /*!< USART1 RX / TIM5 capture/compare interrupt */
I2C1_SPI2_IRQn = (uint8_t)29 /*!< I2C1 / SPI2 interrupt */
#endif /* STM8L15X_MD */
}IRQn_TypeDef;
#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
#define IS_ITC_IRQ(Irq) (((Irq) == FLASH_IRQn) || \
((Irq) == DMA1_CHANNEL0_1_IRQn) || \
((Irq) == DMA1_CHANNEL2_3_IRQn) || \
((Irq) == RTC_IRQn) || \
((Irq) == EXTIE_F_PVD_IRQn) || \
((Irq) == EXTIB_IRQn) || \
((Irq) == EXTID_IRQn) || \
((Irq) == EXTI0_IRQn) || \
((Irq) == EXTI1_IRQn) || \
((Irq) == EXTI2_IRQn) || \
((Irq) == EXTI3_IRQn) || \
((Irq) == EXTI4_IRQn) || \
((Irq) == EXTI5_IRQn) || \
((Irq) == EXTI6_IRQn) || \
((Irq) == EXTI7_IRQn) || \
((Irq) == LCD_IRQn) || \
((Irq) == SWITCH_CSS_BREAK_DAC_IRQn) || \
((Irq) == ADC1_COMP_IRQn) || \
((Irq) == TIM2_UPD_OVF_TRG_BRK_IRQn) || \
((Irq) == TIM2_CC_IRQn) || \
((Irq) == TIM3_UPD_OVF_TRG_BRK_IRQn) || \
((Irq) == TIM3_CC_IRQn) || \
((Irq) == TIM1_UPD_OVF_TRG_IRQn) || \
((Irq) == TIM1_CC_IRQn) || \
((Irq) == TIM4_UPD_OVF_TRG_IRQn) || \
((Irq) == SPI1_IRQn) || \
((Irq) == USART1_TX_IRQn) || \
((Irq) == USART1_RX_IRQn) || \
((Irq) == I2C1_IRQn))
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
#define IS_ITC_IRQ(Irq) (((Irq) == FLASH_IRQn) || \
((Irq) == DMA1_CHANNEL0_1_IRQn) || \
((Irq) == DMA1_CHANNEL2_3_IRQn) || \
((Irq) == RTC_CSSLSE_IRQn) || \
((Irq) == EXTIE_F_PVD_IRQn) || \
((Irq) == EXTIB_IRQn) || \
((Irq) == EXTID_IRQn) || \
((Irq) == EXTI0_IRQn) || \
((Irq) == EXTI1_IRQn) || \
((Irq) == EXTI2_IRQn) || \
((Irq) == EXTI3_IRQn) || \
((Irq) == EXTI4_IRQn) || \
((Irq) == EXTI5_IRQn) || \
((Irq) == EXTI6_IRQn) || \
((Irq) == EXTI7_IRQn) || \
((Irq) == SWITCH_CSS_IRQn) || \
((Irq) == ADC1_COMP_IRQn) || \
((Irq) == TIM2_UPD_OVF_TRG_BRK_IRQn) || \
((Irq) == TIM2_CC_IRQn) || \
((Irq) == TIM3_UPD_OVF_TRG_BRK_IRQn) || \
((Irq) == TIM3_CC_IRQn) || \
((Irq) == TIM4_UPD_OVF_TRG_IRQn) || \
((Irq) == SPI1_IRQn) || \
((Irq) == USART1_TX_IRQn) || \
((Irq) == USART1_RX_IRQn) || \
((Irq) == I2C1_IRQn))
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
#define IS_ITC_IRQ(Irq) (((Irq) == FLASH_IRQn) || \
((Irq) == DMA1_CHANNEL0_1_IRQn) || \
((Irq) == DMA1_CHANNEL2_3_IRQn) || \
((Irq) == RTC_CSSLSE_IRQn) || \
((Irq) == EXTIE_F_PVD_IRQn) || \
((Irq) == EXTIB_G_IRQn) || \
((Irq) == EXTID_H_IRQn) || \
((Irq) == EXTI0_IRQn) || \
((Irq) == EXTI1_IRQn) || \
((Irq) == EXTI2_IRQn) || \
((Irq) == EXTI3_IRQn) || \
((Irq) == EXTI4_IRQn) || \
((Irq) == EXTI5_IRQn) || \
((Irq) == EXTI6_IRQn) || \
((Irq) == EXTI7_IRQn) || \
((Irq) == LCD_AES_IRQn) || \
((Irq) == SWITCH_CSS_BREAK_DAC_IRQn) || \
((Irq) == ADC1_COMP_IRQn) || \
((Irq) == TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn) || \
((Irq) == TIM2_CC_USART2_RX_IRQn) || \
((Irq) == TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn) || \
((Irq) == TIM3_CC_USART3_RX_IRQn) || \
((Irq) == TIM1_UPD_OVF_TRG_IRQn) || \
((Irq) == TIM1_CC_IRQn) || \
((Irq) == TIM4_UPD_OVF_TRG_IRQn) || \
((Irq) == SPI1_IRQn) || \
((Irq) == USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn) || \
((Irq) == USART1_RX_TIM5_CC_IRQn) || \
((Irq) == I2C1_SPI2_IRQn))
#endif /* STM8L15X_MD */
/**
* @}
*/
/** @defgroup ITC_Priority_Level_selection
* @{
*/
typedef enum {
ITC_PriorityLevel_0 = (uint8_t)0x02, /*!< Software priority level 0 (cannot be written) */
ITC_PriorityLevel_1 = (uint8_t)0x01, /*!< Software priority level 1 */
ITC_PriorityLevel_2 = (uint8_t)0x00, /*!< Software priority level 2 */
ITC_PriorityLevel_3 = (uint8_t)0x03 /*!< Software priority level 3 */
} ITC_PriorityLevel_TypeDef;
#define IS_ITC_PRIORITY(PriorityValue) \
(((PriorityValue) == ITC_PriorityLevel_0) || \
((PriorityValue) == ITC_PriorityLevel_1) || \
((PriorityValue) == ITC_PriorityLevel_2) || \
((PriorityValue) == ITC_PriorityLevel_3))
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ITC_Exported_Constants
* @{
*/
#define CPU_SOFT_INT_DISABLED ((uint8_t)0x28) /*!< Mask for I1 and I0 bits in CPU_CC register */
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup ITC_Exported_Constants
* @{
*/
#define IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED)
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the ITC configuration to the default reset state ******/
void ITC_DeInit(void);
/* ITC configuration and management functions ******/
uint8_t ITC_GetCPUCC(void);
uint8_t ITC_GetSoftIntStatus(void);
void ITC_SetSoftwarePriority(IRQn_TypeDef IRQn, ITC_PriorityLevel_TypeDef ITC_PriorityLevel);
ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(IRQn_TypeDef IRQn);
#endif /* __STM8L15x_ITC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/*******************************************************************************
* @file stm8l15x_iwdg.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_IWDG_H
#define __STM8L15x_IWDG_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup IWDG
* @{
*/
/* Exported variables ------------------------------------------------------- */
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Constants
* @{
*/
/** @defgroup IWDG_KeyRefresh
* @{
*/
#define IWDG_KEY_REFRESH ((uint8_t)0xAA) /*!< This value written in the Key
register prevent the watchdog reset */
/**
* @}
*/
/** @defgroup IWDG_KeyEnable
* @{
*/
#define IWDG_KEY_ENABLE ((uint8_t)0xCC) /*!< This value written in the Key
register start the watchdog counting down*/
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IWDG_Exported_Types
* @{
*/
/** @defgroup IWDG_WriteAccess
* @{
*/
typedef enum
{
IWDG_WriteAccess_Enable = (uint8_t)0x55,
IWDG_WriteAccess_Disable = (uint8_t)0x00
} IWDG_WriteAccess_TypeDef;
#define IS_IWDG_WRITE_ACCESS_MODE(MODE) (((MODE) == IWDG_WriteAccess_Enable) || \
((MODE) == IWDG_WriteAccess_Disable))
/**
* @}
*/
/** @defgroup IWDG_prescaler
* @{
*/
typedef enum
{
IWDG_Prescaler_4 = (uint8_t)0x00, /*!< Used to set prescaler register to 4 */
IWDG_Prescaler_8 = (uint8_t)0x01, /*!< Used to set prescaler register to 8 */
IWDG_Prescaler_16 = (uint8_t)0x02, /*!< Used to set prescaler register to 16 */
IWDG_Prescaler_32 = (uint8_t)0x03, /*!< Used to set prescaler register to 32 */
IWDG_Prescaler_64 = (uint8_t)0x04, /*!< Used to set prescaler register to 64 */
IWDG_Prescaler_128 = (uint8_t)0x05, /*!< Used to set prescaler register to 128 */
IWDG_Prescaler_256 = (uint8_t)0x06 /*!< Used to set prescaler register to 256 */
} IWDG_Prescaler_TypeDef;
#define IS_IWDG_PRESCALER_VALUE(VALUE) (((VALUE) == IWDG_Prescaler_4) || \
((VALUE) == IWDG_Prescaler_8) || \
((VALUE) == IWDG_Prescaler_16) || \
((VALUE) == IWDG_Prescaler_32) || \
((VALUE) == IWDG_Prescaler_64) || \
((VALUE) == IWDG_Prescaler_128) || \
((VALUE) == IWDG_Prescaler_256))
/**
* @}
*/
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* Prescaler and Counter configuration functions ******************************/
void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess);
void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler);
void IWDG_SetReload(uint8_t IWDG_Reload);
void IWDG_ReloadCounter(void);
/* IWDG activation function ***************************************************/
void IWDG_Enable(void);
#endif /* __STM8L15x_IWDG_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_lcd.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the LCD firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_LCD_H
#define __STM8L15x_LCD_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup LCD
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup LCD_Exported_Types
* @{
*/
/** @defgroup LCD_Duty
* @brief element values correspond to the bits position
* @{
*/
typedef enum {
LCD_Duty_Static = (uint8_t)0x00, /*!< Static duty */
LCD_Duty_1_2 = (uint8_t)0x02, /*!< 1/2 duty */
LCD_Duty_1_3 = (uint8_t)0x04, /*!< 1/3 duty */
LCD_Duty_1_4 = (uint8_t)0x06, /*!< 1/4 duty */
LCD_Duty_1_8 = (uint8_t)0x20 /*!< 1/8 duty */
} LCD_Duty_TypeDef;
#define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_Duty_Static) || ((DUTY) == LCD_Duty_1_2) || \
((DUTY) == LCD_Duty_1_3) || ((DUTY) == LCD_Duty_1_4) || \
((DUTY) == LCD_Duty_1_8))
/**
* @}
*/
/** @defgroup LCD_Bias
* @brief element values correspond to the bits position
* @{
*/
typedef enum {
LCD_Bias_1_4 = (uint8_t)0x10, /*!< 1/4 bias */
LCD_Bias_1_3 = (uint8_t)0x00, /*!< 1/3 bias */
LCD_Bias_1_2 = (uint8_t)0x01 /*!< 1/2 bias */
} LCD_Bias_TypeDef;
#define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_Bias_1_4) || \
((BIAS) == LCD_Bias_1_3) || \
((BIAS) == LCD_Bias_1_2))
/**
* @}
*/
/** @defgroup LCD_Clock_Prescaler
* @brief element values correspond to the bits position
* @{
*/
typedef enum {
LCD_Prescaler_1 = (uint8_t)0x00, /*!< CLKprescaler = ClKinput */
LCD_Prescaler_2 = (uint8_t)0x10, /*!< CLKprescaler = ClKinput/2 */
LCD_Prescaler_4 = (uint8_t)0x20, /*!< CLKprescaler = ClKinput/4 */
LCD_Prescaler_8 = (uint8_t)0x30, /*!< CLKprescaler = ClKinput/8 */
LCD_Prescaler_16 = (uint8_t)0x40, /*!< CLKprescaler = ClKinput/16 */
LCD_Prescaler_32 = (uint8_t)0x50, /*!< CLKprescaler = ClKinput/32 */
LCD_Prescaler_64 = (uint8_t)0x60, /*!< CLKprescaler = ClKinput/64 */
LCD_Prescaler_128 = (uint8_t)0x70, /*!< CLKprescaler = ClKinput/128 */
LCD_Prescaler_256 = (uint8_t)0x80, /*!< CLKprescaler = ClKinput/256 */
LCD_Prescaler_512 = (uint8_t)0x90, /*!< CLKprescaler = ClKinput/512 */
LCD_Prescaler_1024 = (uint8_t)0xA0, /*!< CLKprescaler = ClKinput/1024 */
LCD_Prescaler_2048 = (uint8_t)0xB0, /*!< CLKprescaler = ClKinput/2048 */
LCD_Prescaler_4096 = (uint8_t)0xC0, /*!< CLKprescaler = ClKinput/4096 */
LCD_Prescaler_8192 = (uint8_t)0xD0, /*!< CLKprescaler = ClKinput/8192 */
LCD_Prescaler_16384 = (uint8_t)0xE0, /*!< CLKprescaler = ClKinput/16384 */
LCD_Prescaler_32768 = (uint8_t)0xF0 /*!< CLKprescaler = ClKinput/32768 */
} LCD_Prescaler_TypeDef;
#define IS_LCD_CLOCK_PRESCALER(PRESCALER) (((PRESCALER) == LCD_Prescaler_1) || \
((PRESCALER) == LCD_Prescaler_2) || \
((PRESCALER) == LCD_Prescaler_4) || \
((PRESCALER) == LCD_Prescaler_8) || \
((PRESCALER) == LCD_Prescaler_16) || \
((PRESCALER) == LCD_Prescaler_32) || \
((PRESCALER) == LCD_Prescaler_64) || \
((PRESCALER) == LCD_Prescaler_128) || \
((PRESCALER) == LCD_Prescaler_256) || \
((PRESCALER) == LCD_Prescaler_512) || \
((PRESCALER) == LCD_Prescaler_1024) || \
((PRESCALER) == LCD_Prescaler_2048) || \
((PRESCALER) == LCD_Prescaler_4096) || \
((PRESCALER) == LCD_Prescaler_8192) || \
((PRESCALER) == LCD_Prescaler_16384) || \
((PRESCALER) == LCD_Prescaler_32768))
/**
* @}
*/
/** @defgroup LCD_Clock_Divider
* @brief element values correspond to the bits position
* @{
*/
typedef enum {
LCD_Divider_16 = (uint8_t)0x00, /*!< LCD frequency = CLKprescaler/16 */
LCD_Divider_17 = (uint8_t)0x01, /*!< LCD frequency = CLKprescaler/17 */
LCD_Divider_18 = (uint8_t)0x02, /*!< LCD frequency = CLKprescaler/18 */
LCD_Divider_19 = (uint8_t)0x03, /*!< LCD frequency = CLKprescaler/19 */
LCD_Divider_20 = (uint8_t)0x04, /*!< LCD frequency = CLKprescaler/20 */
LCD_Divider_21 = (uint8_t)0x05, /*!< LCD frequency = CLKprescaler/21 */
LCD_Divider_22 = (uint8_t)0x06, /*!< LCD frequency = CLKprescaler/22 */
LCD_Divider_23 = (uint8_t)0x07, /*!< LCD frequency = CLKprescaler/23 */
LCD_Divider_24 = (uint8_t)0x08, /*!< LCD frequency = CLKprescaler/24 */
LCD_Divider_25 = (uint8_t)0x09, /*!< LCD frequency = CLKprescaler/25 */
LCD_Divider_26 = (uint8_t)0x0A, /*!< LCD frequency = CLKprescaler/26 */
LCD_Divider_27 = (uint8_t)0x0B, /*!< LCD frequency = CLKprescaler/27 */
LCD_Divider_28 = (uint8_t)0x0C, /*!< LCD frequency = CLKprescaler/28 */
LCD_Divider_29 = (uint8_t)0x0D, /*!< LCD frequency = CLKprescaler/29 */
LCD_Divider_30 = (uint8_t)0x0E, /*!< LCD frequency = CLKprescaler/30 */
LCD_Divider_31 = (uint8_t)0x0F /*!< LCD frequency = CLKprescaler/31 */
} LCD_Divider_TypeDef;
#define IS_LCD_CLOCK_DIVIDER(DIVIDER) (((DIVIDER) == LCD_Divider_16) || \
((DIVIDER) == LCD_Divider_17) || \
((DIVIDER) == LCD_Divider_18) || \
((DIVIDER) == LCD_Divider_19) || \
((DIVIDER) == LCD_Divider_20) || \
((DIVIDER) == LCD_Divider_21) || \
((DIVIDER) == LCD_Divider_22) || \
((DIVIDER) == LCD_Divider_23) || \
((DIVIDER) == LCD_Divider_24) || \
((DIVIDER) == LCD_Divider_25) || \
((DIVIDER) == LCD_Divider_26) || \
((DIVIDER) == LCD_Divider_27) || \
((DIVIDER) == LCD_Divider_28) || \
((DIVIDER) == LCD_Divider_29) || \
((DIVIDER) == LCD_Divider_30) || \
((DIVIDER) == LCD_Divider_31))
/**
* @}
*/
/** @defgroup LCD_Contrast
* @brief element values correspond to the bits position
* @{
*/
typedef enum {
LCD_Contrast_Level_0 = (uint8_t)0x00, /*!< Medium Density / High Density Maximum Voltage = 2.60V / 2.60V */
LCD_Contrast_Level_1 = (uint8_t)0x02, /*!< Medium Density / High Density Maximum Voltage = 2.70V / 2.73V */
LCD_Contrast_Level_2 = (uint8_t)0x04, /*!< Medium Density / High Density Maximum Voltage = 2.80V / 2.86V */
LCD_Contrast_Level_3 = (uint8_t)0x06, /*!< Medium Density / High Density Maximum Voltage = 2.90V / 2.99V */
LCD_Contrast_Level_4 = (uint8_t)0x08, /*!< Medium Density / High Density Maximum Voltage = 3.00V / 3.12V */
LCD_Contrast_Level_5 = (uint8_t)0x0A, /*!< Medium Density / High Density Maximum Voltage = 3.10V / 3.25V */
LCD_Contrast_Level_6 = (uint8_t)0x0C, /*!< Medium Density / High Density Maximum Voltage = 3.20V / 3.38V */
LCD_Contrast_Level_7 = (uint8_t)0x0E /*!< Medium Density / High Density Maximum Voltage = 3.30V / 3.51V */
} LCD_Contrast_TypeDef;
#define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_Contrast_Level_0) || \
((CONTRAST) == LCD_Contrast_Level_1) || \
((CONTRAST) == LCD_Contrast_Level_2) || \
((CONTRAST) == LCD_Contrast_Level_3) || \
((CONTRAST) == LCD_Contrast_Level_4) || \
((CONTRAST) == LCD_Contrast_Level_5) || \
((CONTRAST) == LCD_Contrast_Level_6) || \
((CONTRAST) == LCD_Contrast_Level_7))
/**
* @}
*/
/** @defgroup LCD_Voltage_Source
* @brief element values correspond to the bits position
* @{
*/
typedef enum {
LCD_VoltageSource_Internal = (uint8_t)0x00, /*!< Internal voltage source for the LCD */
LCD_VoltageSource_External = (uint8_t)0x01 /*!< External voltage source for the LCD */
} LCD_VoltageSource_TypeDef;
#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VoltageSource_Internal) || \
((SOURCE) == LCD_VoltageSource_External))
/**
* @}
*/
/** @defgroup LCD_Pulse_On_Duration
* @brief element values correspond to the bits position
* @{
*/
typedef enum {
LCD_PulseOnDuration_0 = (uint8_t)0x00, /*!< Pulse on duration = 0/CLKprescaler */
LCD_PulseOnDuration_1 = (uint8_t)0x20, /*!< Pulse on duration = 1/CLKprescaler */
LCD_PulseOnDuration_2 = (uint8_t)0x40, /*!< Pulse on duration = 2/CLKprescaler */
LCD_PulseOnDuration_3 = (uint8_t)0x60, /*!< Pulse on duration = 3/CLKprescaler */
LCD_PulseOnDuration_4 = (uint8_t)0x80, /*!< Pulse on duration = 4/CLKprescaler */
LCD_PulseOnDuration_5 = (uint8_t)0xA0, /*!< Pulse on duration = 5/CLKprescaler */
LCD_PulseOnDuration_6 = (uint8_t)0xC0, /*!< Pulse on duration = 6/CLKprescaler */
LCD_PulseOnDuration_7 = (uint8_t)0xE0 /*!< Pulse on duration = 7/CLKprescaler */
} LCD_PulseOnDuration_TypeDef;
#define IS_LCD_PULSE_DURATION(DURATION) (((DURATION) == LCD_PulseOnDuration_0) || \
((DURATION) == LCD_PulseOnDuration_1) || \
((DURATION) == LCD_PulseOnDuration_2) || \
((DURATION) == LCD_PulseOnDuration_3) || \
((DURATION) == LCD_PulseOnDuration_4) || \
((DURATION) == LCD_PulseOnDuration_5) || \
((DURATION) == LCD_PulseOnDuration_6) || \
((DURATION) == LCD_PulseOnDuration_7))
/**
* @}
*/
/** @defgroup LCD_Dead_Time
* @brief element values correspond to the bits position
* @{
*/
typedef enum {
LCD_DeadTime_0 = (uint8_t)0x00, /*!< No dead Time */
LCD_DeadTime_1 = (uint8_t)0x01, /*!< One Phase between different couple of Frame */
LCD_DeadTime_2 = (uint8_t)0x02, /*!< Two Phase between different couple of Frame */
LCD_DeadTime_3 = (uint8_t)0x03, /*!< Tree Phase between different couple of Frame */
LCD_DeadTime_4 = (uint8_t)0x04, /*!< Four Phase between different couple of Frame */
LCD_DeadTime_5 = (uint8_t)0x05, /*!< Five Phase between different couple of Frame */
LCD_DeadTime_6 = (uint8_t)0x06, /*!< Six Phase between different couple of Frame */
LCD_DeadTime_7 = (uint8_t)0x07 /*!< Seven Phase between different couple of Frame */
} LCD_DeadTime_TypeDef;
#define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DeadTime_0) || \
((TIME) == LCD_DeadTime_1) || \
((TIME) == LCD_DeadTime_2) || \
((TIME) == LCD_DeadTime_3) || \
((TIME) == LCD_DeadTime_4) || \
((TIME) == LCD_DeadTime_5) || \
((TIME) == LCD_DeadTime_6) || \
((TIME) == LCD_DeadTime_7))
/**
* @}
*/
/** @defgroup LCD_BlinkMode
* @{
*/
typedef enum {
LCD_BlinkMode_Off = (uint8_t)0x00, /*!< Blink inactive */
LCD_BlinkMode_SEG0_COM0 = (uint8_t)0x40, /*!< SEG0 on COM0 blink */
LCD_BlinkMode_SEG0_AllCOM = (uint8_t)0x80, /*!< SEG0 on All COM blink */
LCD_BlinkMode_AllSEG_AllCOM = (uint8_t)0xC0 /*!< All SEG on All COm Blink */
} LCD_BlinkMode_TypeDef;
#define IS_LCD_BLINK_MODE(BLINK) (((BLINK) == LCD_BlinkMode_Off) || \
((BLINK) == LCD_BlinkMode_SEG0_COM0) || \
((BLINK) == LCD_BlinkMode_SEG0_AllCOM) || \
((BLINK) == LCD_BlinkMode_AllSEG_AllCOM))
/**
* @}
*/
/** @defgroup LCD_Blink_Frequency
* @brief element values correspond to the bits position
* @{
*/
typedef enum {
LCD_BlinkFrequency_Div8 = (uint8_t)0x00, /*!< The Blink frequency = fLcd/8 */
LCD_BlinkFrequency_Div16 = (uint8_t)0x08, /*!< The Blink frequency = fLcd/16 */
LCD_BlinkFrequency_Div32 = (uint8_t)0x10, /*!< The Blink frequency = fLcd/32 */
LCD_BlinkFrequency_Div64 = (uint8_t)0x18, /*!< The Blink frequency = fLcd/64 */
LCD_BlinkFrequency_Div128 = (uint8_t)0x20, /*!< The Blink frequency = fLcd/128 */
LCD_BlinkFrequency_Div256 = (uint8_t)0x28, /*!< The Blink frequency = fLcd/256 */
LCD_BlinkFrequency_Div512 = (uint8_t)0x30, /*!< The Blink frequency = fLcd/512 */
LCD_BlinkFrequency_Div1024 = (uint8_t)0x38 /*!< The Blink frequency = fLcd/1024 */
} LCD_BlinkFrequency_TypeDef;
#define IS_LCD_BLINK_FREQUENCY(BLINKF) (((BLINKF) == LCD_BlinkFrequency_Div8) || \
((BLINKF) == LCD_BlinkFrequency_Div16) || \
((BLINKF) == LCD_BlinkFrequency_Div32) || \
((BLINKF) == LCD_BlinkFrequency_Div64) || \
((BLINKF) == LCD_BlinkFrequency_Div128) || \
((BLINKF) == LCD_BlinkFrequency_Div256) || \
((BLINKF) == LCD_BlinkFrequency_Div512) || \
((BLINKF) == LCD_BlinkFrequency_Div1024))
/**
* @}
*/
/** @defgroup LCD_RAMRegister
* @{
*/
typedef enum {
LCD_RAMRegister_0 = (uint8_t)0x00, /*!< RAM Register 0 */
LCD_RAMRegister_1 = (uint8_t)0x01, /*!< RAM Register 1 */
LCD_RAMRegister_2 = (uint8_t)0x02, /*!< RAM Register 2 */
LCD_RAMRegister_3 = (uint8_t)0x03, /*!< RAM Register 3 */
LCD_RAMRegister_4 = (uint8_t)0x04, /*!< RAM Register 4 */
LCD_RAMRegister_5 = (uint8_t)0x05, /*!< RAM Register 5 */
LCD_RAMRegister_6 = (uint8_t)0x06, /*!< RAM Register 6 */
LCD_RAMRegister_7 = (uint8_t)0x07, /*!< RAM Register 7 */
LCD_RAMRegister_8 = (uint8_t)0x08, /*!< RAM Register 8 */
LCD_RAMRegister_9 = (uint8_t)0x09, /*!< RAM Register 9 */
LCD_RAMRegister_10 = (uint8_t)0x0A, /*!< RAM Register 10 */
LCD_RAMRegister_11 = (uint8_t)0x0B, /*!< RAM Register 11 */
LCD_RAMRegister_12 = (uint8_t)0x0C, /*!< RAM Register 12 */
LCD_RAMRegister_13 = (uint8_t)0x0D, /*!< RAM Register 13 */
LCD_RAMRegister_14 = (uint8_t)0x0E, /*!< RAM Register 14 */
LCD_RAMRegister_15 = (uint8_t)0x0F, /*!< RAM Register 15 */
LCD_RAMRegister_16 = (uint8_t)0x10, /*!< RAM Register 16 */
LCD_RAMRegister_17 = (uint8_t)0x11, /*!< RAM Register 17 */
LCD_RAMRegister_18 = (uint8_t)0x12, /*!< RAM Register 18 */
LCD_RAMRegister_19 = (uint8_t)0x13, /*!< RAM Register 19 */
LCD_RAMRegister_20 = (uint8_t)0x14, /*!< RAM Register 20 */
LCD_RAMRegister_21 = (uint8_t)0x15 /*!< RAM Register 21 */
} LCD_RAMRegister_TypeDef;
#define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAMRegister_0) || \
((REGISTER) == LCD_RAMRegister_1) || \
((REGISTER) == LCD_RAMRegister_2) || \
((REGISTER) == LCD_RAMRegister_3) || \
((REGISTER) == LCD_RAMRegister_4) || \
((REGISTER) == LCD_RAMRegister_5) || \
((REGISTER) == LCD_RAMRegister_6) || \
((REGISTER) == LCD_RAMRegister_7) || \
((REGISTER) == LCD_RAMRegister_8) || \
((REGISTER) == LCD_RAMRegister_9) || \
((REGISTER) == LCD_RAMRegister_10) || \
((REGISTER) == LCD_RAMRegister_11) || \
((REGISTER) == LCD_RAMRegister_12) || \
((REGISTER) == LCD_RAMRegister_13) || \
((REGISTER) == LCD_RAMRegister_14) || \
((REGISTER) == LCD_RAMRegister_15) || \
((REGISTER) == LCD_RAMRegister_16) || \
((REGISTER) == LCD_RAMRegister_17) || \
((REGISTER) == LCD_RAMRegister_18) || \
((REGISTER) == LCD_RAMRegister_19) || \
((REGISTER) == LCD_RAMRegister_20) || \
((REGISTER) == LCD_RAMRegister_21))
/**
* @}
*/
/** @defgroup LCD_Port_Mask_Register
* @{
*/
typedef enum {
LCD_PortMaskRegister_0 = (uint8_t)0x00, /*!< PortMask Register 0 */
LCD_PortMaskRegister_1 = (uint8_t)0x01, /*!< PortMask Register 1 */
LCD_PortMaskRegister_2 = (uint8_t)0x02, /*!< PortMask Register 2 */
LCD_PortMaskRegister_3 = (uint8_t)0x03, /*!< PortMask Register 3 */
LCD_PortMaskRegister_4 = (uint8_t)0x04, /*!< PortMask Register 4 */
LCD_PortMaskRegister_5 = (uint8_t)0x05 /*!< PortMask Register 5 */
} LCD_PortMaskRegister_TypeDef;
#define IS_LCD_PORT_MASK(MASK) (((MASK) == LCD_PortMaskRegister_0) || \
((MASK) == LCD_PortMaskRegister_1) || \
((MASK) == LCD_PortMaskRegister_2) || \
((MASK) == LCD_PortMaskRegister_3) || \
((MASK) == LCD_PortMaskRegister_4) || \
((MASK) == LCD_PortMaskRegister_5))
/**
* @}
*/
/** @defgroup LCD_Page_Selection
* @{
*/
typedef enum {
LCD_PageSelection_FirstPage = (uint8_t)0x00, /*!< The LCD RAM is selected as the first page */
LCD_PageSelection_SecondPage = (uint8_t)0x04 /*!< The LCD RAM is selected as the second page */
} LCD_PageSelection_TypeDef;
#define IS_LCD_PAGE_SELECT(PAGE) (((PAGE) == LCD_PageSelection_FirstPage) || \
((PAGE) == LCD_PageSelection_SecondPage))
/**
* @}
*/
/**
* @}
*/
/* Private define ------------------------------------------------------------*/
/* LCD Legacy defines */
/** @defgroup LCD_Private_Define
* @ brief LCD Legacy defines
* @{
*/
#define LCD_Contrast_2V6 ((uint8_t)LCD_Contrast_Level_0)
#define LCD_Contrast_2V7 ((uint8_t)LCD_Contrast_Level_1)
#define LCD_Contrast_2V8 ((uint8_t)LCD_Contrast_Level_2)
#define LCD_Contrast_2V9 ((uint8_t)LCD_Contrast_Level_3)
#define LCD_Contrast_3V0 ((uint8_t)LCD_Contrast_Level_4)
#define LCD_Contrast_3V1 ((uint8_t)LCD_Contrast_Level_5)
#define LCD_Contrast_3V2 ((uint8_t)LCD_Contrast_Level_6)
#define LCD_Contrast_3V3 ((uint8_t)LCD_Contrast_Level_7)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the LCD configuration to the default reset state *****/
void LCD_DeInit(void);
/* Initialization and Configuration functions *********************************/
void LCD_Init(LCD_Prescaler_TypeDef LCD_Prescaler, LCD_Divider_TypeDef LCD_Divider,
LCD_Duty_TypeDef LCD_Duty, LCD_Bias_TypeDef LCD_Bias, LCD_VoltageSource_TypeDef LCD_VoltageSource);
void LCD_PortMaskConfig(LCD_PortMaskRegister_TypeDef LCD_PortMaskRegister, uint8_t LCD_Mask);
void LCD_Cmd(FunctionalState NewState);
void LCD_HighDriveCmd(FunctionalState NewState);
void LCD_PulseOnDurationConfig(LCD_PulseOnDuration_TypeDef LCD_PulseOnDuration);
void LCD_DeadTimeConfig(LCD_DeadTime_TypeDef LCD_DeadTime);
void LCD_BlinkConfig(LCD_BlinkMode_TypeDef LCD_BlinkMode, LCD_BlinkFrequency_TypeDef LCD_BlinkFrequency);
void LCD_ContrastConfig(LCD_Contrast_TypeDef LCD_Contrast);
/* LCD RAM memory write functions *********************************************/
void LCD_WriteRAM(LCD_RAMRegister_TypeDef LCD_RAMRegister, uint8_t LCD_Data);
void LCD_PageSelect(LCD_PageSelection_TypeDef LCD_PageSelection);
/* Interrupts and flags management functions **********************************/
void LCD_ITConfig(FunctionalState NewState);
FlagStatus LCD_GetFlagStatus(void);
void LCD_ClearFlag(void);
ITStatus LCD_GetITStatus(void);
void LCD_ClearITPendingBit(void);
#endif /* __STM8L15x_LCD_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_pwr.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_PWR_H
#define __STM8L15x_PWR_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types
* @{
*/
/** @defgroup PVD_detection_level
* @{
*/
typedef enum {
PWR_PVDLevel_1V85 = (uint8_t)0x00, /*!< PVD threshold = 1.85 V */
PWR_PVDLevel_2V05 = (uint8_t)0x02, /*!< PVD threshold = 2.05 V */
PWR_PVDLevel_2V26 = (uint8_t)0x04, /*!< PVD threshold = 2.26 V */
PWR_PVDLevel_2V45 = (uint8_t)0x06, /*!< PVD threshold = 2.45 V */
PWR_PVDLevel_2V65 = (uint8_t)0x08, /*!< PVD threshold = 2.65 V */
PWR_PVDLevel_2V85 = (uint8_t)0x0A, /*!< PVD threshold = 2.85 V */
PWR_PVDLevel_3V05 = (uint8_t)0x0C, /*!< PVD threshold = 3.05 V */
PWR_PVDLevel_PVDIn = (uint8_t)0x0E /*!< PVD threshold = PVD_IN input pin */
} PWR_PVDLevel_TypeDef;
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_1V85) || \
((LEVEL) == PWR_PVDLevel_2V05) || \
((LEVEL) == PWR_PVDLevel_2V26) || \
((LEVEL) == PWR_PVDLevel_2V45) || \
((LEVEL) == PWR_PVDLevel_2V65) || \
((LEVEL) == PWR_PVDLevel_2V85) || \
((LEVEL) == PWR_PVDLevel_3V05) || \
((LEVEL) == PWR_PVDLevel_PVDIn))
/**
* @}
*/
/** @defgroup PWR_Flag
* @{
*/
typedef enum {
PWR_FLAG_PVDOF = (uint8_t)0x40,/*!< PVD output flag */
PWR_FLAG_PVDIF = (uint8_t)0x20, /*!< PVD Interrupt flag */
PWR_FLAG_VREFINTF = (uint8_t)0x01 /*!< Internal reference voltage status flag */
} PWR_FLAG_TypeDef;
#define IS_PWR_FLAG(FLAG) (((FLAG) == PWR_FLAG_PVDOF) || \
((FLAG) == PWR_FLAG_PVDIF) || \
((FLAG) == PWR_FLAG_VREFINTF))
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the PWR configuration to the default reset state ******/
void PWR_DeInit(void);
/* PVD configuration functions ************************************************/
void PWR_PVDLevelConfig(PWR_PVDLevel_TypeDef PWR_PVDLevel);
void PWR_PVDCmd(FunctionalState NewState);
/* Ultra Low Power mode configuration functions *******************************/
void PWR_FastWakeUpCmd(FunctionalState NewState);
void PWR_UltraLowPowerCmd(FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void PWR_PVDITConfig(FunctionalState NewState);
ITStatus PWR_PVDGetITStatus(void);
FlagStatus PWR_GetFlagStatus(PWR_FLAG_TypeDef PWR_FLAG);
void PWR_PVDClearFlag(void);
void PWR_PVDClearITPendingBit(void);
#endif /* __STM8L15x_PWR_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_rst.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the RST firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_RST_H
#define __STM8L15x_RST_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup RST
* @{
*/
/* Exported variables ------------------------------------------------------- */
/* Exported types ------------------------------------------------------------*/
/** @defgroup RST_Exported_Types
* @{
*/
/** @defgroup RST_Flags
* @{
*/
typedef enum {
RST_FLAG_PORF = (uint8_t)0x01, /*!< POR reset flag */
RST_FLAG_SWIMF = (uint8_t)0x08, /*!< SWIM reset flag */
RST_FLAG_ILLOPF = (uint8_t)0x04, /*!< Illegal opcode reset flag */
RST_FLAG_IWDGF = (uint8_t)0x02, /*!< Independent watchdog reset flag */
RST_FLAG_WWDGF = (uint8_t)0x10, /*!< Window watchdog reset flag */
RST_FLAG_BORF = (uint8_t)0x20 /*!< BOR reset flag */
} RST_FLAG_TypeDef;
#define IS_RST_FLAG(FLAG) (((FLAG) == RST_FLAG_PORF) || ((FLAG) == RST_FLAG_BORF) || \
((FLAG) == RST_FLAG_IWDGF) || ((FLAG) == RST_FLAG_ILLOPF) || \
((FLAG) == RST_FLAG_WWDGF) || ((FLAG) == RST_FLAG_SWIMF))
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Flag management functions **************************************************/
FlagStatus RST_GetFlagStatus(RST_FLAG_TypeDef RST_Flag);
void RST_ClearFlag(RST_FLAG_TypeDef RST_Flag);
/* NRST Pin configuration function ********************************************/
void RST_GPOutputEnable(void);
#endif /* __STM8L15x_RST_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_rtc.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the RTC
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_RTC_H
#define __STM8L15x_RTC_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup RTC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Types
* @{
*/
/** @defgroup RTC_Weekdays
* @{
*/
typedef enum
{
RTC_Weekday_Monday = ((uint8_t)0x01), /*!< WeekDay is Monday */
RTC_Weekday_Tuesday = ((uint8_t)0x02), /*!< WeekDay is Tuesday */
RTC_Weekday_Wednesday = ((uint8_t)0x03), /*!< WeekDay is Wednesday */
RTC_Weekday_Thursday = ((uint8_t)0x04), /*!< WeekDay is Thursday */
RTC_Weekday_Friday = ((uint8_t)0x05), /*!< WeekDay is Friday */
RTC_Weekday_Saturday = ((uint8_t)0x06), /*!< WeekDay is Saturday */
RTC_Weekday_Sunday = ((uint8_t)0x07) /*!< WeekDay is Sunday */
}
RTC_Weekday_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Months
* @{
*/
typedef enum
{
RTC_Month_January = ((uint8_t)0x01), /*!< Month is January */
RTC_Month_February = ((uint8_t)0x02), /*!< Month is February */
RTC_Month_March = ((uint8_t)0x03), /*!< Month is March */
RTC_Month_April = ((uint8_t)0x04), /*!< Month is April */
RTC_Month_May = ((uint8_t)0x05), /*!< Month is May */
RTC_Month_June = ((uint8_t)0x06), /*!< Month is June */
RTC_Month_July = ((uint8_t)0x07), /*!< Month is July */
RTC_Month_August = ((uint8_t)0x08), /*!< Month is August */
RTC_Month_September = ((uint8_t)0x09), /*!< Month is September */
RTC_Month_October = ((uint8_t)0x10), /*!< Month is October */
RTC_Month_November = ((uint8_t)0x11), /*!< Month is November */
RTC_Month_December = ((uint8_t)0x12) /*!< Month is December */
}
RTC_Month_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Hour_Format
* @{
*/
typedef enum
{
RTC_HourFormat_24 = ((uint8_t)0x00), /*!< Hour Format is 24H */
RTC_HourFormat_12 = ((uint8_t)0x40) /*!< Hour Format is 12H (using AM/PM) */
}
RTC_HourFormat_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Time
* @{
*/
typedef enum
{
RTC_H12_AM = ((uint8_t)0x00), /*!< AM/PM notation is AM or 24 hour format */
RTC_H12_PM = ((uint8_t)0x40) /*!< AM/PM notation is PM */
}
RTC_H12_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Alarm_WeekDay_Selection
* @{
*/
typedef enum
{
RTC_AlarmDateWeekDaySel_Date = ((uint8_t)0x00), /*!< Date/WeekDay selection is Date */
RTC_AlarmDateWeekDaySel_WeekDay = ((uint8_t)0x40) /*!< Date/WeekDay selection is WeekDay */
}
RTC_AlarmDateWeekDaySel_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Alarm_Mask
* @{
*/
typedef enum
{
RTC_AlarmMask_None = ((uint8_t)0x00), /*!< Alarm Masks disabled */
RTC_AlarmMask_Seconds = ((uint8_t)0x80), /*!< Alarm Seconds Mask */
RTC_AlarmMask_Minutes = ((uint8_t)0x40), /*!< Alarm Minutes Mask */
RTC_AlarmMask_Hours = ((uint8_t)0x20), /*!< Alarm Hours Mask */
RTC_AlarmMask_DateWeekDay = ((uint8_t)0x10), /*!< Alarm Date/WeekDay Mask */
RTC_AlarmMask_All = ((uint8_t)0xF0) /*!< Alarm All Mask are enabled */
}
RTC_AlarmMask_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Sub_Second_Alarm_Mask
* @{
*/
typedef enum
{
RTC_AlarmSubSecondMask_All = ((uint8_t)0x00), /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
RTC_AlarmSubSecondMask_None = ((uint8_t)0x0F), /*!< SS[14:0] are compared and must match to activate alarm. */
RTC_AlarmSubSecondMask_SS14_1 = ((uint8_t)0x01), /*!< SS[14:1] are not used in Alarm comparison. Only SS[0] is compared. */
RTC_AlarmSubSecondMask_SS14_2 = ((uint8_t)0x02), /*!< SS[14:2] are not used in Alarm comparison. Only SS[1:0] are compared */
RTC_AlarmSubSecondMask_SS14_3 = ((uint8_t)0x03), /*!< SS[14:3] are not used in Alarm comparison. Only SS[1:0] are compared */
RTC_AlarmSubSecondMask_SS14_4 = ((uint8_t)0x04), /*!< SS[14:4] are not used in Alarm comparison. Only SS[1:0] are compared */
RTC_AlarmSubSecondMask_SS14_5 = ((uint8_t)0x05), /*!< SS[14:5] are not used in Alarm comparison. Only SS[1:0] are compared */
RTC_AlarmSubSecondMask_SS14_6 = ((uint8_t)0x06), /*!< SS[14:6] are not used in Alarm comparison. Only SS[1:0] are compared */
RTC_AlarmSubSecondMask_SS14_7 = ((uint8_t)0x07), /*!< SS[14:7] are not used in Alarm comparison. Only SS[1:0] are compared */
RTC_AlarmSubSecondMask_SS14_8 = ((uint8_t)0x08), /*!< SS[14:8] are not used in Alarm comparison. Only SS[1:0] are compared */
RTC_AlarmSubSecondMask_SS14_9 = ((uint8_t)0x09), /*!< SS[14:9] are not used in Alarm comparison. Only SS[1:0] are compared */
RTC_AlarmSubSecondMask_SS14_10 = ((uint8_t)0x0A), /*!< SS[14:10] are not used in Alarm comparison. Only SS[1:0] are compared */
RTC_AlarmSubSecondMask_SS14_11 = ((uint8_t)0x0B), /*!< SS[14:11] are not used in Alarm comparison. Only SS[1:0] are compared */
RTC_AlarmSubSecondMask_SS14_12 = ((uint8_t)0x0C), /*!< SS[14:12] are not used in Alarm comparison. Only SS[1:0] are compared */
RTC_AlarmSubSecondMask_SS14_13 = ((uint8_t)0x0D), /*!< SS[14:13] are not used in Alarm comparison. Only SS[1:0] are compared */
RTC_AlarmSubSecondMask_SS14 = ((uint8_t)0x0E) /*!< SS[14] is not used in Alarm comparison. Only SS[13:0] are compared */
}
RTC_AlarmSubSecondMask_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Wakeup_Clock
* @{
*/
typedef enum
{
RTC_WakeUpClock_RTCCLK_Div16 = ((uint8_t)0x00), /*!< (RTC clock) div 16*/
RTC_WakeUpClock_RTCCLK_Div8 = ((uint8_t)0x01), /*!< (RTC clock) div 8*/
RTC_WakeUpClock_RTCCLK_Div4 = ((uint8_t)0x02), /*!< (RTC clock) div 4*/
RTC_WakeUpClock_RTCCLK_Div2 = ((uint8_t)0x03), /*!< (RTC clock) div 2*/
RTC_WakeUpClock_CK_SPRE_16bits = ((uint8_t)0x04), /*!< CK SPRE with a counter from 0x0000 to 0xFFFF */
RTC_WakeUpClock_CK_SPRE_17bits = ((uint8_t)0x06) /*!< CK SPRE with a counter from 0x10000 to 0x1FFFF */
}
RTC_WakeUpClock_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Output_Selection
* @{
*/
typedef enum
{
RTC_Output_Disable = ((uint8_t)0x00), /*!< RTC Alternate function Output is disabled */
RTC_Output_Alarm = ((uint8_t)0x20), /*!< RTC Alternate function Output is the Alarm A event*/
RTC_Output_WakeUp = ((uint8_t)0x60) /*!< RTC Alternate function Output is the WakeUp event */
}
RTC_Output_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Output_Polarity
* @{
*/
typedef enum
{
RTC_OutputPolarity_High = ((uint8_t)0x00), /*!< RTC Alternate function Output Polarity is High */
RTC_OutputPolarity_Low = ((uint8_t)0x10) /*!< RTC Alternate function Output Polarity is Low */
}
RTC_OutputPolarity_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Calibration_Output
* @{
*/
typedef enum
{
RTC_CalibOutput_512Hz = ((uint8_t)0x00), /*!< RTC Calibration Output is 512Hz */
RTC_CalibOutput_1Hz = ((uint8_t)0x80) /*!< RTC Calibration Output is 1Hz */
}
RTC_CalibOutput_TypeDef;
/**
* @}
*/
/** @defgroup RTC_DayLight_Saving
* @{
*/
typedef enum
{
RTC_DayLightSaving_SUB1H = ((uint8_t)0x02), /*!< Substract 1 hour to the current Time (Winter Time Adjustment) */
RTC_DayLightSaving_ADD1H = ((uint8_t)0x01) /*!< Add 1 hour to the current Time (Summer Time Adjustment) */
}
RTC_DayLightSaving_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Store_Operation
* @{
*/
typedef enum
{
RTC_StoreOperation_Set = ((uint8_t)0x04), /*!< Store Operation Set */
RTC_StoreOperation_Reset = ((uint8_t)0x00) /*!< Store Operation Reset */
}
RTC_StoreOperation_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Input_Parameter_Format
* @{
*/
typedef enum
{
RTC_Format_BIN = ((uint8_t)0x00), /*!< Binary Format is used */
RTC_Format_BCD = ((uint8_t)0x01) /*!< BCD Format is used */
}
RTC_Format_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Flags
* @{
*/
typedef enum
{
RTC_FLAG_TAMP3F = ((uint16_t)0x0080), /*!< TAMPER3 detection Flag. If set, tamper detection event is detected on tamper input 3 */
RTC_FLAG_TAMP2F = ((uint16_t)0x0040), /*!< TAMPER2 detection Flag. If set, tamper detection event is detected on tamper input 2 */
RTC_FLAG_TAMP1F = ((uint16_t)0x0020), /*!< TAMPER1 detection Flag. If set, tamper detection event is detected on tamper input 1 */
RTC_FLAG_WUTF = ((uint16_t)0x0004), /*!< Wake up Timer Flag. If set, the Wake Up down counter reaches 0 */
RTC_FLAG_ALRAF = ((uint16_t)0x0001), /*!< Alarm A Flag. If set, the Time/Date registers matches Alarm A registers */
RTC_FLAG_INITF = ((uint16_t)0x4000), /*!< Initialisation Flag. If set,Calender registers has been initialized */
RTC_FLAG_RSF = ((uint16_t)0x2000), /*!< Registers Synchronization Flag. If set,Calender registers synchronized */
RTC_FLAG_INITS = ((uint16_t)0x1000), /*!< Initialisation Status Flag. If set,Calender update is allowed */
RTC_FLAG_SHPF = ((uint16_t)0x0800), /*!< Shift operation pending Flag. This flag is set by hardware as soon as a shift operation is
initiated by a write to the RTC_SHIFTRL. It is cleared by hardware as soon as the corresponding
shift operation has completed. */
RTC_FLAG_WUTWF = ((uint16_t)0x0400), /*!< Wake up Timer write Flag. If set, Wake up Timer update is allowed */
RTC_FLAG_RECALPF = ((uint16_t)0x0200), /*!< Recalibration pending Flag, The status flag RECALPF is automatically set to <20>1<EFBFBD> when software
writes to the register RTC_CALRL, indicating that the RTC_CALRx registers are blocked.
When the new calibration settings are taken into account, this Flag returns by hardware to <20>0<EFBFBD>. */
RTC_FLAG_ALRAWF = ((uint16_t)0x0100) /*!< Alarm A write Flag. If set, Alarm A update is allowed */
}
RTC_Flag_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Interrupts
* @{
*/
typedef enum
{
RTC_IT_WUT = ((uint16_t)0x0040), /*!< Wake up Timer Interrupt */
RTC_IT_ALRA = ((uint16_t)0x0010), /*!< Alarm A Interrupt */
RTC_IT_TAMP = ((uint16_t)0x0F01) /*!< Tamper Interrupt */
}
RTC_IT_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Tamper_Level
* @{
*/
typedef enum
{
RTC_TamperLevel_Low = ((uint8_t)0x00), /*!< Tamper staying low triggers a tamper detection event. */
RTC_TamperLevel_High = ((uint8_t)0x54) /*!< Tamper staying high triggers a tamper detection event. */
}
RTC_TamperLevel_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Tamper_State
* @{
*/
typedef enum
{
RTC_TamperState_Disable = ((uint8_t)0x00), /*!< Tamper State is Disable */
RTC_TamperState_Enable = ((uint8_t)0x01) /*!< Tamper State is Enable */
}
RTC_TamperState_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Tamper_definition
* @{
*/
typedef enum
{
RTC_Tamper_1 = ((uint8_t)0x02), /*!< Tamper 1 selection */
RTC_Tamper_2 = ((uint8_t)0x08), /*!< Tamper 2 selection */
RTC_Tamper_3 = ((uint8_t)0x20) /*!< Tamper 3 selection */
}
RTC_Tamper_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Tamper_Precharge_Duration
* @{
*/
typedef enum
{
RTC_TamperPrechargeDuration_None = ((uint8_t)0x80), /*!< Tamper pins are not precharged before sampling */
RTC_TamperPrechargeDuration_1RTCCLK = ((uint8_t)0x00), /*!< Tamper pins are precharged before sampling during 1 RTCCLK cycle */
RTC_TamperPrechargeDuration_2RTCCLK = ((uint8_t)0x20), /*!< Tamper pins are precharged before sampling during 2 RTCCLK cycles */
RTC_TamperPrechargeDuration_4RTCCLK = ((uint8_t)0x40), /*!< Tamper pins are precharged before sampling during 4 RTCCLK cycles */
RTC_TamperPrechargeDuration_8RTCCLK = ((uint8_t)0x60) /*!< Tamper pins are precharged before sampling during 8 RTCCLK cycles */
}
RTC_TamperPrechargeDuration_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Tamper_Filter
* @{
*/
typedef enum
{
RTC_TamperFilter_1Sample = ((uint8_t)0x00), /*!< Tamper is activated after 1 sample at the active level */
RTC_TamperFilter_2Sample = ((uint8_t)0x08), /*!< Tamper is activated after 2 consecutive samples at the active level. */
RTC_TamperFilter_4Sample = ((uint8_t)0x10), /*!< Tamper is activated after 4 consecutive samples at the active level. */
RTC_TamperFilter_8Sample = ((uint8_t)0x18) /*!< Tamper is activated after 8 consecutive samples at the active level. */
}
RTC_TamperFilter_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Tamper_Sampling_Frequency
* @{
*/
typedef enum
{
RTC_TamperSamplingFreq_RTCCLK_Div32768 = ((uint8_t)0x00), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 32768 */
RTC_TamperSamplingFreq_RTCCLK_Div16384 = ((uint8_t)0x01), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 16384 */
RTC_TamperSamplingFreq_RTCCLK_Div8192 = ((uint8_t)0x02), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 8192 */
RTC_TamperSamplingFreq_RTCCLK_Div4096 = ((uint8_t)0x03), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 4096 */
RTC_TamperSamplingFreq_RTCCLK_Div2048 = ((uint8_t)0x04), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 2048 */
RTC_TamperSamplingFreq_RTCCLK_Div1024 = ((uint8_t)0x05), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 1024 */
RTC_TamperSamplingFreq_RTCCLK_Div512 = ((uint8_t)0x06), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 512 */
RTC_TamperSamplingFreq_RTCCLK_Div256 = ((uint8_t)0x07) /*!< Tamper inputs are sampled with a frequency = RTCCLK / 256 */
}
RTC_TamperSamplingFreq_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Shift_Add_1s
* @{
*/
typedef enum
{
RTC_ShiftAdd1S_Set = ((uint8_t)0x80), /*!< Add 1 Second */
RTC_ShiftAdd1S_Reset = ((uint8_t)0x00) /*!< Do not Add 1 Second */
}
RTC_ShiftAdd1S_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Smooth_Calibration_Period
* @{
*/
typedef enum
{
RTC_SmoothCalibPeriod_32sec = ((uint8_t)0x00), /*!< if RTCCLK = 32768 Hz, Smooth calibration period is 32s, else 2exp20 RTCCLK seconds */
RTC_SmoothCalibPeriod_16sec = ((uint8_t)0x20), /*!< if RTCCLK = 32768 Hz, Smooth calibration period is 16s, else 2exp19 RTCCLK seconds */
RTC_SmoothCalibPeriod_8sec = ((uint8_t)0x40) /*!< if RTCCLK = 32768 Hz, Smooth calibration period is 8s, else 2exp18 RTCCLK seconds */
}
RTC_SmoothCalibPeriod_TypeDef;
/**
* @}
*/
/** @defgroup RTC_Smooth_Calibration_Pulses
* @{
*/
typedef enum
{
RTC_SmoothCalibPlusPulses_Set = ((uint8_t)0x80), /*!< The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0].
with Y = 512, 256, 128 when X = 32, 16, 8 */
RTC_SmoothCalibPlusPulses_Reset = ((uint8_t)0x00) /*!< The number of RTCCLK pulses substituted during a 32-second window = CALM[8:0]. */
}
RTC_SmoothCalibPlusPulses_TypeDef;
/**
* @}
*/
/**
* @brief RTC Init structure definition
*/
typedef struct
{
RTC_HourFormat_TypeDef RTC_HourFormat; /*!< RTC Hour Format */
uint8_t RTC_AsynchPrediv; /*!< RTC Asynchronous Predivider.
This parameter can be any value from
0x00 to 0x7F.*/
uint16_t RTC_SynchPrediv; /*!< RTC Synchronous Predivider.
This parameter can be any value from
0x0000 to 0x7FFF.*/
}
RTC_InitTypeDef;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
uint8_t RTC_Hours; /*!< RTC Hours.
If Binary format is selected :
- If RTC_Hour format is RTC_Hour format_12,
this parameter can be any value from 1 to 12.
- If RTC_Hour format is RTC_Hour format_24,
this parameter can be any value from 0 to 23.
If BCD format is selected :
- If RTC_Hour format is RTC_Hour format_12,
this parameter can be any BCD value from
0x01 to 0x12.
- If RTC_Hour format is RTC_Hour format_24,
this parameter can be any BCD value from
0x00 to 0x23.*/
uint8_t RTC_Minutes; /*!< RTC Minutes.
If Binary format is selected, this parameter can
be any value from 0 to 59.
If BCD format is selected, this parameter can
be any BCD value from 0x00 to 0x59.*/
uint8_t RTC_Seconds; /*!< RTC Seconds.
If Binary format is selected, this parameter can
be any value from 0 to 59.
If BCD format is selected, this parameter can
be any BCD value from 0x00 to 0x59.*/
RTC_H12_TypeDef RTC_H12; /*!< RTC 12-hour clock period (AM/PM) */
}
RTC_TimeTypeDef;
/**
* @brief RTC Date structure definition
*/
typedef struct
{
RTC_Weekday_TypeDef RTC_WeekDay; /*!< The RTC Calender Weekday. */
RTC_Month_TypeDef RTC_Month; /*!< The RTC Calender Month. */
uint8_t RTC_Date; /*!< The RTC Calender Date.
If Binary format is selected, this
parameter can be any value from 1 to 31.
If BCD format is selected, this parameter
can be any BCD value from 0x01 to 0x31.*/
uint8_t RTC_Year; /*!< The RTC Calender Date.
If Binary format is selected, this parameter
can be any value from 0 to 99.
If BCD format is selected, this parameter
can be any BCD value from 0x00 to 0x99.*/
}
RTC_DateTypeDef;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
RTC_TimeTypeDef RTC_AlarmTime; /*!< RTC Alarm Time */
uint8_t RTC_AlarmMask; /*!< The RTC Alarm Fields Masks. */
RTC_AlarmDateWeekDaySel_TypeDef RTC_AlarmDateWeekDaySel; /*!< The RTC Alarm Date/WeekDay selection. */
uint8_t RTC_AlarmDateWeekDay; /*!< The RTC Alarm Date/WeekDay value.
- If RTC Alarm Date/WeekDay selection is Date
and if If Binary format is selected, this
parameter can be any value from 1 to 31.
- If RTC Alarm Date/WeekDay selection is WeekDay,
this parameter can be one of the
@ref RTC_Weekday_TypeDef enumeration.*/
}
RTC_AlarmTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RTC_Exported_Macros
* @{
*/
/**
* @brief Macro used by the assert_param function in order to check the used
* Calender Hour format
*/
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
((FORMAT) == RTC_HourFormat_24))
/**
* @brief Macro used by the assert_param function in order to check the used
* Asynchronous Predivider
*/
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
/**
* @brief Macro used by the assert_param function in order to check the used
* Synchronous Predivider
*/
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
/**
* @brief Macro used by the assert_param function in order to check the used
* Calender Hours value (format 12h)
*/
#define IS_RTC_HOUR12_MAX(HOUR) ((HOUR) <= (uint8_t)12)
#define IS_RTC_HOUR12_MIN(HOUR) ((HOUR) > (uint8_t)0)
/**
* @brief Macro used by the assert_param function in order to check the used
* Calender Hours value (format 24h)
*/
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
/**
* @brief Macro used by the assert_param function in order to check the used
* Calender minutes value
*/
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
/**
* @brief Macro used by the assert_param function in order to check the used
* Calender seconds value
*/
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
/**
* @brief Macro used by the assert_param function in order to check the used
* Calender H12 mode
*/
#define IS_RTC_H12(PM) (((PM) == (RTC_H12_AM)) || ((PM) == (RTC_H12_PM)))
/**
* @brief Macro used by the assert_param function in order to check the used
* Calender Year value
*/
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
/**
* @brief Macro used by the assert_param function in order to check the used
* Calender month value
*/
#define IS_RTC_MONTH_MAX(MONTH) ((MONTH) <= (uint8_t)12)
#define IS_RTC_MONTH_MIN(MONTH) ((MONTH) >= (uint8_t)1)
/**
* @brief Macro used by the assert_param function in order to check the used
* Calender Date value
*/
#define IS_RTC_DATE_MAX(DATE) ((DATE) <= (uint8_t)31)
#define IS_RTC_DATE_MIN(DATE) ((DATE) >= (uint8_t)1)
/**
* @brief Macro used by the assert_param function in order to check the used
* Calender Week day value
*/
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
((WEEKDAY) == RTC_Weekday_Tuesday) || \
((WEEKDAY) == RTC_Weekday_Wednesday) || \
((WEEKDAY) == RTC_Weekday_Thursday) || \
((WEEKDAY) == RTC_Weekday_Friday) || \
((WEEKDAY) == RTC_Weekday_Saturday) || \
((WEEKDAY) == RTC_Weekday_Sunday))
/**
* @brief Macro used by the assert_param function in order to check the used
* Alarm Date/week day selection
*/
#define IS_RTC_ALARM_DATEWEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
/**
* @brief Macro used by the assert_param function in order to check the used
* Alarm Mask
*/
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x0F) == (uint8_t)(RESET))
/**
* @brief Macro used by the assert_param function in order to check the used
* wakeup clock source
*/
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
/**
* @brief Macro used by the assert_param function in order to check the used
* Output selection
*/
#define IS_RTC_OUTPUT_SEL(SEL) (((SEL) == RTC_Output_Disable) || \
((SEL) == RTC_Output_Alarm) || \
((SEL) == RTC_Output_WakeUp))
/**
* @brief Macro used by the assert_param function in order to check the used
* Output polarity
*/
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
((POL) == RTC_OutputPolarity_Low))
/**
* @brief Macro used by the assert_param function in order to check the used
* Daylight saving mode
*/
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
((SAVE) == RTC_DayLightSaving_ADD1H))
/**
* @brief Macro used by the assert_param function in order to check the used
* Store Operation status
*/
#define IS_RTC_STORE_OPERATION(OP) (((OP) == RTC_StoreOperation_Set) || \
((OP) == RTC_StoreOperation_Reset))
/**
* @brief Macro used by the assert_param function in order to check the used
* format (bin/bcd) for data user insert
*/
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || \
((FORMAT) == RTC_Format_BCD))
/**
* @brief Macro used by the assert_param function in order to check the used
* Flag to get
*/
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_WUTF) || \
((FLAG) == RTC_FLAG_ALRAF) || \
((FLAG) == RTC_FLAG_INITF) || \
((FLAG) == RTC_FLAG_RSF) || \
((FLAG) == RTC_FLAG_INITS) || \
((FLAG) == RTC_FLAG_WUTWF) || \
((FLAG) == RTC_FLAG_TAMP3F)|| \
((FLAG) == RTC_FLAG_TAMP2F)|| \
((FLAG) == RTC_FLAG_TAMP1F)|| \
((FLAG) == RTC_FLAG_SHPF) || \
((FLAG) == RTC_FLAG_RECALPF) || \
((FLAG) == RTC_FLAG_ALRAWF))
/* RTC_FLAG_ALRAWF is for Medium Density only but supported by High Density
Devices*/
/**
* @brief Macro used by the assert_param function in order to check the used
* Flag to clear
*/
#define RTC_FLAG_CLRBLE (RTC_FLAG_RSF | RTC_FLAG_ALRAF | RTC_FLAG_WUTF| RTC_FLAG_TAMP1F|RTC_FLAG_TAMP2F|RTC_FLAG_TAMP3F)
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != RESET) && ((uint16_t)((FLAG) & (uint16_t)(~(RTC_FLAG_CLRBLE))) == RESET))
/**
* @brief Macro used by the assert_param function in order to check the used
* Interrupt to configure
*/
#define IS_RTC_CONFIG_IT(IT) (((uint16_t)(IT) != (uint8_t)RESET) && ((uint16_t)((uint16_t)(IT) & (uint16_t)(~(uint16_t)(RTC_IT_WUT|RTC_IT_ALRA|RTC_IT_TAMP))) == (uint8_t)RESET))
/**
* @brief Macro used by the assert_param function in order to check the used
* Interrupt to get
*/
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_WUT) || \
((IT) == RTC_IT_ALRA)|| \
((IT) == RTC_IT_TAMP) )
/**
* @brief Macro used by the assert_param function in order to check the used
* Interrupt to clear
*/
#define IS_RTC_CLEAR_IT(IT) (((IT) != RESET) && ((uint16_t)((IT) & (uint16_t)(~(uint16_t)(RTC_IT_WUT|RTC_IT_ALRA|RTC_IT_TAMP))) == RESET))
/**
* @brief Macro used by the assert_param function in order to check the used
* Tamper Levels
*/
#define IS_RTC_TAMPER_LEVEL(LEVEL) (((LEVEL) == RTC_TamperLevel_Low) || \
((LEVEL) == RTC_TamperLevel_High))
/**
* @brief Macro used by the assert_param function in order to check the used
* Tamper
*/
#define NOT_CORRECT_TAMPER (uint8_t)~(uint8_t)( RTC_Tamper_1 | \
RTC_Tamper_2 | \
RTC_Tamper_3)
#define IS_RTC_TAMPER(TAMPER) (((uint8_t)((TAMPER) & NOT_CORRECT_TAMPER) == RESET) && ((TAMPER) != RESET))
/**
* @brief Macro used by the assert_param function in order to check the used
* Tampers Filter
*/
#define IS_RTC_TAMPER_FILTER(SEL) (((SEL) == RTC_TamperFilter_1Sample) || \
((SEL) == RTC_TamperFilter_2Sample) || \
((SEL) == RTC_TamperFilter_4Sample) || \
((SEL) == RTC_TamperFilter_8Sample))
/**
* @brief Macro used by the assert_param function in order to check the used
* Tampers Sampling Frequencies
*/
#define IS_RTC_TAMPER_SAMPLING_FREQ(SEL) ((SEL) <= RTC_TamperSamplingFreq_RTCCLK_Div256)
/**
* @brief Macro used by the assert_param function in order to check the used
* Tampers Pins precharge duration
*/
#define IS_RTC_TAMPER_PINS_PRECHAR_DURATION(SEL) (((SEL) == RTC_TamperPrechargeDuration_None) || \
((SEL) == RTC_TamperPrechargeDuration_1RTCCLK) || \
((SEL) == RTC_TamperPrechargeDuration_2RTCCLK) || \
((SEL) == RTC_TamperPrechargeDuration_4RTCCLK) || \
((SEL) == RTC_TamperPrechargeDuration_8RTCCLK))
/**
* @brief Macro used by the assert_param function in order to check the used
* Smooth calibration period
*/
#define IS_RTC_SMOOTH_CALIB_PERIOD(SEL) (((SEL) == RTC_SmoothCalibPeriod_32sec) || \
((SEL) == RTC_SmoothCalibPeriod_16sec) || \
((SEL) == RTC_SmoothCalibPeriod_8sec))
/**
* @brief Macro used by the assert_param function in order to check the used
* Smooth calibration Plus pulses
*/
#define IS_RTC_SMOOTH_CALIB_PLUS(SEL) (((SEL) == RTC_SmoothCalibPlusPulses_Set) || \
((SEL) == RTC_SmoothCalibPlusPulses_Reset))
/**
* @brief Macro used by the assert_param function in order to check the used
* Smooth calibration Minus pulses
*/
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x01FF)
/**
* @brief Macro used by the assert_param function in order to check the used
* Output Selection
*/
#define IS_RTC_OUTPUT_SELECT(SEL) (((SEL) == RTC_Output_Disable) || \
((SEL) == RTC_Output_Alarm) || \
((SEL) == RTC_Output_WakeUp))
/**
* @brief Macro used by the assert_param function in order to check the
* used calibration Output Selection
*/
#define IS_RTC_CALOUTPUT_SELECT(SEL) (((SEL) == RTC_CalibOutput_512Hz) || \
((SEL) == RTC_CalibOutput_1Hz))
/**
* @brief Macro used by the assert_param function in order to check the used
* Alarm sub second value
*/
#define IS_RTC_ALARM_SS_VALUE(SS) ((SS) <= 0x7FFF)
/**
* @brief Macro used by the assert_param function in order to check the used
* Alarm sub second mask
*/
#define IS_RTC_ALARM_SS_MASK(MASK) ((MASK) <= 0x0F)
/**
* @brief Macro used by the assert_param function in order to check the used
* fraction of seconds to sub
*/
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x7FFF)
/**
* @brief Macro used by the assert_param function in order to check the
* parameter of 1 second to add
*/
#define IS_RTC_SHIFT_ADD1S(VAL) (((VAL) == RTC_ShiftAdd1S_Set) || \
((VAL) == RTC_ShiftAdd1S_Reset))
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the RTC configuration to the default reset state *****/
ErrorStatus RTC_DeInit(void);
/* Initialization and Configuration functions *********************************/
ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
void RTC_WriteProtectionCmd(FunctionalState NewState);
ErrorStatus RTC_EnterInitMode(void);
void RTC_ExitInitMode(void);
ErrorStatus RTC_WaitForSynchro(void);
void RTC_RatioCmd(FunctionalState NewState);
void RTC_BypassShadowCmd(FunctionalState NewState);
/* Time and Date configuration functions **************************************/
ErrorStatus RTC_SetTime(RTC_Format_TypeDef RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
void RTC_GetTime(RTC_Format_TypeDef RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
uint16_t RTC_GetSubSecond(void);
ErrorStatus RTC_SetDate(RTC_Format_TypeDef RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
void RTC_GetDate(RTC_Format_TypeDef RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
/* Alarm configuration functions *********************************************/
void RTC_SetAlarm(RTC_Format_TypeDef RTC_Format, RTC_AlarmTypeDef* RTC_AlarmStruct);
void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
void RTC_GetAlarm(RTC_Format_TypeDef RTC_Format, RTC_AlarmTypeDef* RTC_AlarmStruct);
ErrorStatus RTC_AlarmCmd(FunctionalState NewState);
ErrorStatus RTC_AlarmSubSecondConfig(uint16_t RTC_AlarmSubSecondValue,
RTC_AlarmSubSecondMask_TypeDef RTC_AlarmSubSecondMask);
/* WakeUp Timer configuration functions ***************************************/
void RTC_WakeUpClockConfig(RTC_WakeUpClock_TypeDef RTC_WakeUpClock);
void RTC_SetWakeUpCounter(uint16_t RTC_WakeupCounter);
uint16_t RTC_GetWakeUpCounter(void);
ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
/* Daylight Saving configuration functions ************************************/
void RTC_DayLightSavingConfig(RTC_DayLightSaving_TypeDef RTC_DayLightSaving,
RTC_StoreOperation_TypeDef RTC_StoreOperation);
RTC_StoreOperation_TypeDef RTC_GetStoreOperation(void);
/* Output pin Configuration function ******************************************/
void RTC_OutputConfig(RTC_Output_TypeDef RTC_Output,
RTC_OutputPolarity_TypeDef RTC_OutputPolarity);
/* Shift control synchronisation function ************************************/
ErrorStatus RTC_SynchroShiftConfig(RTC_ShiftAdd1S_TypeDef RTC_ShiftAdd1S,
uint16_t RTC_ShiftSubFS);
/* Smooth Calibration functions **********************************************/
ErrorStatus RTC_SmoothCalibConfig(RTC_SmoothCalibPeriod_TypeDef RTC_SmoothCalibPeriod,
RTC_SmoothCalibPlusPulses_TypeDef RTC_SmoothCalibPlusPulses,
uint16_t RTC_SmouthCalibMinusPulsesValue);
/* Calibration configuration functions ****************************************/
void RTC_CalibOutputConfig(RTC_CalibOutput_TypeDef RTC_CalibOutput);
void RTC_CalibOutputCmd(FunctionalState NewState);
/* Tampers configuration functions ********************************************/
void RTC_TamperLevelConfig(RTC_Tamper_TypeDef RTC_Tamper,
RTC_TamperLevel_TypeDef RTC_TamperLevel);
void RTC_TamperFilterConfig(RTC_TamperFilter_TypeDef RTC_TamperFilter);
void RTC_TamperSamplingFreqConfig(RTC_TamperSamplingFreq_TypeDef RTC_TamperSamplingFreq);
void RTC_TamperPinsPrechargeDuration(RTC_TamperPrechargeDuration_TypeDef RTC_TamperPrechargeDuration);
void RTC_TamperCmd(RTC_Tamper_TypeDef RTC_Tamper,
FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void RTC_ITConfig(RTC_IT_TypeDef RTC_IT, FunctionalState NewState);
FlagStatus RTC_GetFlagStatus(RTC_Flag_TypeDef RTC_FLAG);
void RTC_ClearFlag(RTC_Flag_TypeDef RTC_FLAG);
ITStatus RTC_GetITStatus(RTC_IT_TypeDef RTC_IT);
void RTC_ClearITPendingBit(RTC_IT_TypeDef RTC_IT);
#endif /*__STM8L15x_RTC_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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firmware/inc/stm8l151x/inc/stm8l15x_spi.h Normal file
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/**
******************************************************************************
* @file stm8l15x_spi.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the SPI firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_SPI_H
#define __STM8L15x_SPI_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SPI_Exported_Types
* @{
*/
/** @defgroup SPI_Direction_Mode
* @brief element values correspond to BDM, BDOE, RXONLY bits position
* @{
*/
typedef enum {
SPI_Direction_2Lines_FullDuplex = (uint8_t)0x00, /*!< 2-line uni-directional data mode enable */
SPI_Direction_2Lines_RxOnly = (uint8_t)0x04, /*!< Receiver only in 2 line uni-directional data mode */
SPI_Direction_1Line_Rx = (uint8_t)0x80, /*!< Receiver only in 1 line bi-directional data mode */
SPI_Direction_1Line_Tx = (uint8_t)0xC0 /*!< Transmit only in 1 line bi-directional data mode */
} SPI_DirectionMode_TypeDef;
/**
* @}
*/
/** @defgroup SPI_SlaveSelect_Management
* @brief element values correspond to LSBFIRST bit position
* @{
*/
typedef enum
{
SPI_NSS_Soft = (uint8_t)0x02, /*!< Software slave management disabled */
SPI_NSS_Hard = (uint8_t)0x00 /*!< Software slave management enabled */
} SPI_NSS_TypeDef;
/**
* @}
*/
/** @defgroup SPI_Direction
* @{
*/
typedef enum
{
SPI_Direction_Rx = (uint8_t)0x00, /*!< Select Rx receive direction in bi-directional mode */
SPI_Direction_Tx = (uint8_t)0x01 /*!< Select Tx transmission direction in bi-directional mode */
} SPI_Direction_TypeDef;
/**
* @}
*/
/** @defgroup SPI_Mode
* @{
*/
typedef enum
{
SPI_Mode_Master = (uint8_t)0x04, /*!< SPI Master configuration */
SPI_Mode_Slave = (uint8_t)0x00 /*!< SPI Slave configuration */
} SPI_Mode_TypeDef;
/**
* @}
*/
/** @defgroup SPI_BaudRate_Prescaler
* @{
*/
typedef enum {
SPI_BaudRatePrescaler_2 = (uint8_t)0x00, /*!< SPI frequency = frequency(CPU)/2 */
SPI_BaudRatePrescaler_4 = (uint8_t)0x08, /*!< SPI frequency = frequency(CPU)/4 */
SPI_BaudRatePrescaler_8 = (uint8_t)0x10, /*!< SPI frequency = frequency(CPU)/8 */
SPI_BaudRatePrescaler_16 = (uint8_t)0x18, /*!< SPI frequency = frequency(CPU)/16 */
SPI_BaudRatePrescaler_32 = (uint8_t)0x20, /*!< SPI frequency = frequency(CPU)/32 */
SPI_BaudRatePrescaler_64 = (uint8_t)0x28, /*!< SPI frequency = frequency(CPU)/64 */
SPI_BaudRatePrescaler_128 = (uint8_t)0x30, /*!< SPI frequency = frequency(CPU)/128 */
SPI_BaudRatePrescaler_256 = (uint8_t)0x38 /*!< SPI frequency = frequency(CPU)/256 */
} SPI_BaudRatePrescaler_TypeDef;
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity
* @{
*/
typedef enum
{
SPI_CPOL_Low = (uint8_t)0x00, /*!< Clock to 0 when idle */
SPI_CPOL_High = (uint8_t)0x02 /*!< Clock to 1 when idle */
} SPI_CPOL_TypeDef;
/**
* @}
*/
/** @defgroup SPI_Clock_Phase
* @{
*/
typedef enum
{
SPI_CPHA_1Edge = (uint8_t)0x00, /*!< The first clock transition is the first data capture edge */
SPI_CPHA_2Edge = (uint8_t)0x01 /*!< The second clock transition is the first data capture edge */
} SPI_CPHA_TypeDef;
/**
* @}
*/
/** @defgroup SPI_Frame_Format
* @{
*/
typedef enum
{
SPI_FirstBit_MSB = (uint8_t)0x00, /*!< MSB bit will be transmitted first */
SPI_FirstBit_LSB = (uint8_t)0x80 /*!< LSB bit will be transmitted first */
} SPI_FirstBit_TypeDef;
/**
* @}
*/
/** @defgroup SPI_DMA_requests
* @{
*/
typedef enum {
SPI_DMAReq_RX = (uint8_t)0x01, /*!< SPI DMA Rx transfer requests */
SPI_DMAReq_TX = (uint8_t)0x02 /*!< SPI DMA Tx transfer requests */
} SPI_DMAReq_TypeDef;
/**
* @}
*/
/** @defgroup SPI_CRC
* @{
*/
typedef enum {
SPI_CRC_RX = (uint8_t)0x00, /*!< Select Tx CRC register */
SPI_CRC_TX = (uint8_t)0x01 /*!< Select Rx CRC register */
} SPI_CRC_TypeDef;
/**
* @}
*/
/** @defgroup SPI_Flags
* @{
*/
typedef enum {
SPI_FLAG_BSY = (uint8_t)0x80, /*!< Busy flag */
SPI_FLAG_OVR = (uint8_t)0x40, /*!< Overrun flag */
SPI_FLAG_MODF = (uint8_t)0x20, /*!< Mode fault */
SPI_FLAG_CRCERR = (uint8_t)0x10, /*!< CRC error flag */
SPI_FLAG_WKUP = (uint8_t)0x08, /*!< Wake-up flag */
SPI_FLAG_TXE = (uint8_t)0x02, /*!< Transmit buffer empty */
SPI_FLAG_RXNE = (uint8_t)0x01 /*!< Receive buffer empty */
} SPI_FLAG_TypeDef;
/**
* @}
*/
/** @defgroup SPI_Interrupts
* @brief SPI_IT possible values
* Elements values convention: 0xYX
* X: Position of the corresponding Interrupt
* Y: ITPENDINGBIT position
* @{
*/
typedef enum
{
SPI_IT_WKUP = (uint8_t)0x34, /*!< Wake-up interrupt*/
SPI_IT_OVR = (uint8_t)0x65, /*!< Overrun interrupt*/
SPI_IT_MODF = (uint8_t)0x55, /*!< Mode fault interrupt*/
SPI_IT_CRCERR = (uint8_t)0x45, /*!< CRC error interrupt*/
SPI_IT_TXE = (uint8_t)0x17, /*!< Transmit buffer empty interrupt*/
SPI_IT_RXNE = (uint8_t)0x06, /*!< Receive buffer not empty interrupt*/
SPI_IT_ERR = (uint8_t)0x05 /*!< Error interrupt*/
} SPI_IT_TypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup SPI_Exported_Macros
* @brief Macros used by the assert_param function to check the different functions parameters.
* @{
*/
/**
* @brief Macro used by the assert_param function in order to check the data direction mode values
*/
#define IS_SPI_DATA_DIRECTION(Mode) (((Mode) == SPI_Direction_2Lines_FullDuplex) || \
((Mode) == SPI_Direction_2Lines_RxOnly) || \
((Mode) == SPI_Direction_1Line_Rx) || \
((Mode) == SPI_Direction_1Line_Tx))
/**
* @brief Macro used by the assert_param function in order to check the mode half duplex data direction values
*/
#define IS_SPI_DIRECTION(Direction) (((Direction) == SPI_Direction_Rx) || \
((Direction) == SPI_Direction_Tx))
/**
* @brief Macro used by the assert_param function in order to check the NSS management values
*/
#define IS_SPI_SLAVEMANAGEMENT(NSS) (((NSS) == SPI_NSS_Soft) || \
((NSS) == SPI_NSS_Hard))
/**
* @brief Macro used by the assert_param function in order to check the different
* sensitivity values for the CRC polynomial
*/
#define IS_SPI_CRC_POLYNOMIAL(Polynomial) ((Polynomial) > (uint8_t)0x00)
/**
* @brief Macro used by the assert_param function in order to check the SPI Mode values
*/
#define IS_SPI_MODE(Mode) (((Mode) == SPI_Mode_Master) || \
((Mode) == SPI_Mode_Slave))
/**
* @brief Macro used by the assert_param function in order to check the baudrate values
*/
#define IS_SPI_BAUDRATE_PRESCALER(Prescaler) (((Prescaler) == SPI_BaudRatePrescaler_2) || \
((Prescaler) == SPI_BaudRatePrescaler_4) || \
((Prescaler) == SPI_BaudRatePrescaler_8) || \
((Prescaler) == SPI_BaudRatePrescaler_16) || \
((Prescaler) == SPI_BaudRatePrescaler_32) || \
((Prescaler) == SPI_BaudRatePrescaler_64) || \
((Prescaler) == SPI_BaudRatePrescaler_128) || \
((Prescaler) == SPI_BaudRatePrescaler_256))
/**
* @brief Macro used by the assert_param function in order to check the polarity values
*/
#define IS_SPI_POLARITY(ClkPol) (((ClkPol) == SPI_CPOL_Low) || \
((ClkPol) == SPI_CPOL_High))
/**
* @brief Macro used by the assert_param function in order to check the phase values
*/
#define IS_SPI_PHASE(ClkPha) (((ClkPha) == SPI_CPHA_1Edge) || \
((ClkPha) == SPI_CPHA_2Edge))
/**
* @brief Macro used by the assert_param function in order to check the first bit
* to be transmitted values
*/
#define IS_SPI_FIRSTBIT(Bit) (((Bit) == SPI_FirstBit_MSB) || \
((Bit) == SPI_FirstBit_LSB))
/**
* @brief Macro used by the assert_param function in order to check the CRC Transmit/Receive
*/
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || \
((CRC) == SPI_CRC_RX))
/**
* @brief Macro used by the assert_param function in order to check the DMA transfer requests
*/
#define IS_SPI_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
/**
* @brief Macro used by the assert_param function in order to check the different flags values
*/
#define IS_SPI_FLAG(Flag) (((Flag) == SPI_FLAG_OVR) || \
((Flag) == SPI_FLAG_MODF) || \
((Flag) == SPI_FLAG_CRCERR) || \
((Flag) == SPI_FLAG_WKUP) || \
((Flag) == SPI_FLAG_TXE) || \
((Flag) == SPI_FLAG_RXNE) || \
((Flag) == SPI_FLAG_BSY))
/**
* @brief Macro used by the assert_param function in order to check the different
* sensitivity values for the flag that can be cleared by writing 0
*/
#define IS_SPI_CLEAR_FLAG(Flag) (((Flag) == SPI_FLAG_CRCERR) || \
((Flag) == SPI_FLAG_WKUP))
/**
* @brief Macro used by the assert_param function in order to check the different
* sensitivity values for the Interrupts
*/
#define IS_SPI_CONFIG_IT(Interrupt) (((Interrupt) == SPI_IT_TXE) || \
((Interrupt) == SPI_IT_RXNE) || \
((Interrupt) == SPI_IT_ERR) || \
((Interrupt) == SPI_IT_WKUP))
/**
* @brief Macro used by the assert_param function in order to check the different
* sensitivity values for the pending bit
*/
#define IS_SPI_GET_IT(ITPendingBit) (((ITPendingBit) == SPI_IT_OVR) || \
((ITPendingBit) == SPI_IT_MODF) || \
((ITPendingBit) == SPI_IT_CRCERR) || \
((ITPendingBit) == SPI_IT_WKUP) || \
((ITPendingBit) == SPI_IT_TXE) || \
((ITPendingBit) == SPI_IT_RXNE))
/**
* @brief Macro used by the assert_param function in order to check the different
* sensitivity values for the pending bit that can be cleared by writing 0
*/
#define IS_SPI_CLEAR_IT(ITPendingBit) (((ITPendingBit) == SPI_IT_CRCERR) || \
((ITPendingBit) == SPI_IT_WKUP))
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the SPI configuration to the default reset state *****/
void SPI_DeInit(SPI_TypeDef* SPIx);
/* Initialization and Configuration functions *********************************/
void SPI_Init(SPI_TypeDef* SPIx, SPI_FirstBit_TypeDef SPI_FirstBit,
SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler,
SPI_Mode_TypeDef SPI_Mode, SPI_CPOL_TypeDef SPI_CPOL,
SPI_CPHA_TypeDef SPI_CPHA, SPI_DirectionMode_TypeDef SPI_Data_Direction,
SPI_NSS_TypeDef SPI_Slave_Management, uint8_t CRCPolynomial);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_NSSInternalSoftwareCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, SPI_Direction_TypeDef SPI_Direction);
/* Data transfers functions ***************************************************/
void SPI_SendData(SPI_TypeDef* SPIx, uint8_t Data);
uint8_t SPI_ReceiveData(SPI_TypeDef* SPIx);
/* Hardware CRC Calculation functions *****************************************/
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
void SPI_CalculateCRCCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
uint8_t SPI_GetCRC(SPI_TypeDef* SPIx, SPI_CRC_TypeDef SPI_CRC);
void SPI_ResetCRC(SPI_TypeDef* SPIx);
uint8_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
/* DMA transfer management functions *****************************************/
void SPI_DMACmd(SPI_TypeDef* SPIx, SPI_DMAReq_TypeDef SPI_DMAReq, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void SPI_ITConfig(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT, FunctionalState NewState);
FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG);
void SPI_ClearFlag(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG);
ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT);
void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT);
#endif /* __STM8L15x_SPI_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -0,0 +1,424 @@
/**
******************************************************************************
* @file stm8l15x_syscfg.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the SYSCFG firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_SYSCFG_H
#define __STM8L15x_SYSCFG_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup SYSCFG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SYSCFG_Exported_Types
* @{
*/
/** @defgroup RI_Input_Capture
* @{
*/
typedef enum
{
RI_InputCapture_IC2 = ((uint8_t) 0x02), /*!< TIM1 Input Capture 2 is routed */
RI_InputCapture_IC3 = ((uint8_t) 0x03) /*!< TIM1 Input Capture 3 is routed */
}RI_InputCapture_TypeDef;
/**
* @}
*/
/** @defgroup RI_Input_Capture_Routing
* @{
*/
typedef enum
{
RI_InputCaptureRouting_0 = ((uint8_t) 0x00), /*!< TIM1 IC2 is routed to PD4, IC3 to PD5 */
RI_InputCaptureRouting_1 = ((uint8_t) 0x01), /*!< TIM1 IC2 is routed to PF0, IC3 to PF1 */
RI_InputCaptureRouting_2 = ((uint8_t) 0x02), /*!< TIM1 IC2 is routed to PF2, IC3 to PF3 */
RI_InputCaptureRouting_3 = ((uint8_t) 0x03), /*!< TIM1 IC2 is routed to PE0, IC3 to PE1 */
RI_InputCaptureRouting_4 = ((uint8_t) 0x04), /*!< TIM1 IC2 is routed to PE2, IC3 to PE3 */
RI_InputCaptureRouting_5 = ((uint8_t) 0x05), /*!< TIM1 IC2 is routed to PE4, IC3 to PE5 */
RI_InputCaptureRouting_6 = ((uint8_t) 0x06), /*!< TIM1 IC2 is routed to PE6, IC3 to PE7 */
RI_InputCaptureRouting_7 = ((uint8_t) 0x07), /*!< TIM1 IC2 is routed to PD0, IC3 to PD1 */
RI_InputCaptureRouting_8 = ((uint8_t) 0x08), /*!< TIM1 IC2 is routed to PD2, IC3 to PD3 */
RI_InputCaptureRouting_9 = ((uint8_t) 0x09), /*!< TIM1 IC2 is routed to PD4, IC3 to PD5 */
RI_InputCaptureRouting_10 = ((uint8_t) 0x0A), /*!< TIM1 IC2 is routed to PD6, IC3 to PD7 */
RI_InputCaptureRouting_11 = ((uint8_t) 0x0B), /*!< TIM1 IC2 is routed to PC0, IC3 to PC1 */
RI_InputCaptureRouting_12 = ((uint8_t) 0x0C), /*!< TIM1 IC2 is routed to PC2, IC3 to PC3 */
RI_InputCaptureRouting_13 = ((uint8_t) 0x0D), /*!< TIM1 IC2 is routed to PC4, IC3 to PC5 */
RI_InputCaptureRouting_14 = ((uint8_t) 0x0E), /*!< TIM1 IC2 is routed to PC6, IC3 to PC7 */
RI_InputCaptureRouting_15 = ((uint8_t) 0x0F), /*!< TIM1 IC2 is routed to PB0, IC3 to PB1 */
RI_InputCaptureRouting_16 = ((uint8_t) 0x10), /*!< TIM1 IC2 is routed to PB2, IC3 to PB3 */
RI_InputCaptureRouting_17 = ((uint8_t) 0x11), /*!< TIM1 IC2 is routed to PB4, IC3 to PB5 */
RI_InputCaptureRouting_18 = ((uint8_t) 0x12), /*!< TIM1 IC2 is routed to PB6, IC3 to PB7 */
RI_InputCaptureRouting_19 = ((uint8_t) 0x13), /*!< TIM1 IC2 is routed to PA0, IC3 to PA2 */
RI_InputCaptureRouting_20 = ((uint8_t) 0x14), /*!< TIM1 IC2 is routed to PA3, IC3 to PA4 */
RI_InputCaptureRouting_21 = ((uint8_t) 0x15), /*!< TIM1 IC2 is routed to PA5, IC3 to PA6 */
RI_InputCaptureRouting_22 = ((uint8_t) 0x16) /*!< TIM1 IC2 is routed to PA7, IC3 to PD5 */
}RI_InputCaptureRouting_TypeDef;
/**
* @}
*/
/** @defgroup RI_Analog_Switch
* @{
*/
/**
* @brief Definition of the Analog Switch to be controlled.
* Values are coded in 0xXY format where
* X: the register index (1: RI_ASCR1, 2: RI_ASCR2)
* Y: the bit position which corresponds with the Analog Switch
*/
typedef enum
{
RI_AnalogSwitch_0 = ((uint8_t) 0x10), /*!< Analog switch 0 */
RI_AnalogSwitch_1 = ((uint8_t) 0x11), /*!< Analog switch 1 */
RI_AnalogSwitch_2 = ((uint8_t) 0x12), /*!< Analog switch 2 */
RI_AnalogSwitch_3 = ((uint8_t) 0x13), /*!< Analog switch 3 */
RI_AnalogSwitch_4 = ((uint8_t) 0x14), /*!< Analog switch 4 */
RI_AnalogSwitch_5 = ((uint8_t) 0x15), /*!< Analog switch 5 */
RI_AnalogSwitch_6 = ((uint8_t) 0x16), /*!< Analog switch 6 */
RI_AnalogSwitch_7 = ((uint8_t) 0x17), /*!< Analog switch 7 */
RI_AnalogSwitch_8 = ((uint8_t) 0x20), /*!< Analog switch 8 */
RI_AnalogSwitch_9 = ((uint8_t) 0x21), /*!< Analog switch 9 */
RI_AnalogSwitch_10 = ((uint8_t) 0x22), /*!< Analog switch 10 */
RI_AnalogSwitch_11 = ((uint8_t) 0x23), /*!< Analog switch 11 */
RI_AnalogSwitch_14 = ((uint8_t) 0x26) /*!< Analog switch 14 */
}RI_AnalogSwitch_TypeDef;
/**
* @}
*/
/** @defgroup RI_IO_Switch
* @{
*/
/**
* @brief Definition of the I/O Switch to be controlled.
* Values are coded in 0xXY format where
* X: the register index (1: RI_IOSR1, 2: RI_IOSR2, 3: RI_IOSR3 or 4: RI_IOSR4)
* Y: the bit index of the Input Output Switch in RI_IOSRx register
*/
typedef enum
{
RI_IOSwitch_1 = ((uint8_t) 0x10), /*!< Input Output Switch switch 1 */
RI_IOSwitch_2 = ((uint8_t) 0x20), /*!< Input Output Switch switch 2 */
RI_IOSwitch_3 = ((uint8_t) 0x30), /*!< Input Output Switch switch 3 */
RI_IOSwitch_4 = ((uint8_t) 0x11), /*!< Input Output Switch switch 4 */
RI_IOSwitch_5 = ((uint8_t) 0x21), /*!< Input Output Switch switch 4 */
RI_IOSwitch_6 = ((uint8_t) 0x31), /*!< Input Output Switch switch 6 */
RI_IOSwitch_7 = ((uint8_t) 0x12), /*!< Input Output Switch switch 7 */
RI_IOSwitch_8 = ((uint8_t) 0x22), /*!< Input Output Switch switch 8 */
RI_IOSwitch_9 = ((uint8_t) 0x32), /*!< Input Output Switch switch 9 */
RI_IOSwitch_10 = ((uint8_t) 0x13), /*!< Input Output Switch switch 10 */
RI_IOSwitch_11 = ((uint8_t) 0x23), /*!< Input Output Switch switch 11 */
RI_IOSwitch_12 = ((uint8_t) 0x33), /*!< Input Output Switch switch 12 */
RI_IOSwitch_13 = ((uint8_t) 0x14), /*!< Input Output Switch switch 13 */
RI_IOSwitch_14 = ((uint8_t) 0x24), /*!< Input Output Switch switch 14 */
RI_IOSwitch_15 = ((uint8_t) 0x34), /*!< Input Output Switch switch 15 */
RI_IOSwitch_16 = ((uint8_t) 0x15), /*!< Input Output Switch switch 16 */
RI_IOSwitch_17 = ((uint8_t) 0x25), /*!< Input Output Switch switch 17 */
RI_IOSwitch_18 = ((uint8_t) 0x35), /*!< Input Output Switch switch 18 */
RI_IOSwitch_19 = ((uint8_t) 0x16), /*!< Input Output Switch switch 19 */
RI_IOSwitch_20 = ((uint8_t) 0x26), /*!< Input Output Switch switch 20 */
RI_IOSwitch_21 = ((uint8_t) 0x36), /*!< Input Output Switch switch 21 */
RI_IOSwitch_22 = ((uint8_t) 0x17), /*!< Input Output Switch switch 22 */
RI_IOSwitch_23 = ((uint8_t) 0x27), /*!< Input Output Switch switch 23 */
RI_IOSwitch_24 = ((uint8_t) 0x37), /*!< Input Output Switch switch 24 */
RI_IOSwitch_26 = ((uint8_t) 0x41), /*!< Input Output Switch switch 26 */
RI_IOSwitch_27 = ((uint8_t) 0x46), /*!< Input Output Switch switch 27 */
RI_IOSwitch_28 = ((uint8_t) 0x47), /*!< Input Output Switch switch 28 */
RI_IOSwitch_29 = ((uint8_t) 0x40) /*!< Input Output Switch switch 29 */
}RI_IOSwitch_TypeDef;
/**
* @}
*/
/** @defgroup RI_Resistor
* @{
*/
/**
* @brief Definition of the pull-up and pull-down resistors for COMP1 and ADC.
*/
typedef enum
{
RI_Resistor_10KPU = ((uint8_t) 0x01),
RI_Resistor_400KPU = ((uint8_t) 0x02),
RI_Resistor_10KPD = ((uint8_t) 0x04),
RI_Resistor_400KPD = ((uint8_t) 0x08)
}RI_Resistor_TypeDef;
/**
* @}
*/
/** @defgroup REMAP_Pin
* @{
*/
/**
* @brief Definition of the REMAP pins.
* Elements values convention: 0xXY
* X = RMPCRx registers index
* X = 0x01 : RMPCR1
* X = 0x02 : RMPCR2
* X = 0x03 : RMPCR3
* Y = Mask for setting/resetting bits in RMPCRx register
*/
typedef enum
{
/* RMPCR1 register bits */
REMAP_Pin_USART1TxRxPortA = ((uint16_t)0x011C), /*!< USART1 Tx- Rx (PC3- PC2) remapping to PA2- PA3 */
REMAP_Pin_USART1TxRxPortC = ((uint16_t)0x012C), /*!< USART1 Tx- Rx (PC3- PC2) remapping to PC5- PC6 */
REMAP_Pin_USART1Clk = ((uint16_t)0x014B), /*!< USART1 CK (PC4) remapping to PA0 */
REMAP_Pin_SPI1Full = ((uint16_t)0x0187), /*!< SPI1 MISO- MOSI- SCK- NSS(PB7- PB6- PB5- PB4)
remapping to PA2- PA3- PC6- PC5 */
/* RMPCR2 register bits */
REMAP_Pin_ADC1ExtTRIG1 = ((uint16_t)0x0201), /*!< ADC1 External Trigger 1 (PA6) remapping to PD0 */
REMAP_Pin_TIM2TRIGPortA = ((uint16_t)0x0202), /*!< TIM2 Trigger (PB3) remapping to PA4 */
REMAP_Pin_TIM3TRIGPortA = ((uint16_t)0x0204), /*!< TIM3 Trigger (PD1) remapping to PA5 */
REMAP_Pin_TIM2TRIGLSE = ((uint16_t)0x0208), /*!< TIM2 Trigger remapping to LSE */
REMAP_Pin_TIM3TRIGLSE = ((uint16_t)0x0210), /*!< TIM3 Trigger remapping to LSE */
REMAP_Pin_SPI2Full = ((uint16_t)0x0220), /*!< SPI2 MISO- MOSI- SCK- NSS(PG7- PG6- PG5- PG4)
remapping to PI3- PI2- PI1- PI0 */
REMAP_Pin_TIM3TRIGPortG = ((uint16_t)0x0240), /*!< TIM3 Trigger (PD1) remapping to PG3 */
REMAP_Pin_TIM23BKIN = ((uint16_t)0x0280), /*!< TIM2 Break Input (PA4) remapping to PG0
and TIM3 Break Input (PA5) remapping to PG1 */
/* RMPCR3 register bits */
REMAP_Pin_SPI1PortF = ((uint16_t)0x0301), /*!< SPI1 MISO- MOSI- SCK- NSS(PB7- PB6- PB5- PB4)
remapping to PF0- PF1- PF2- PF3 */
REMAP_Pin_USART3TxRxPortF = ((uint16_t)0x0302), /*!< USART3 Tx- Rx (PG1- PG0) remapping to PF0- PF1 */
REMAP_Pin_USART3Clk = ((uint16_t)0x0304), /*!< USART3 CK (PG2) remapping to PF2 */
REMAP_Pin_TIM3Channel1 = ((uint16_t)0x0308), /*!< TIM3 Channel 1 (PB1) remapping to PI0 */
REMAP_Pin_TIM3Channel2 = ((uint16_t)0x0310), /*!< TIM3 Channel 2 (PD0) remapping to PI3 */
REMAP_Pin_CCO = ((uint16_t)0x0320), /*!< CCO (PC4) remapping to PE2 */
REMAP_Pin_TIM2Channel1 = ((uint16_t)0x0340), /*!< TIM2 Channel 1 (PB0) remapping to PC5 */
REMAP_Pin_TIM2Channel2 = ((uint16_t)0x0380) /*!< TIM2 Channel 2 (PB2) remapping to PC6 */
}REMAP_Pin_TypeDef;
/**
* @}
*/
/** @defgroup REMAP_DMA_Channel
* @{
*/
typedef enum
{
REMAP_DMA1Channel_ADC1ToChannel0 = ((uint8_t)0x00), /*!< ADC1 DMA1 req/ack mapped on DMA1 channel 0 */
REMAP_DMA1Channel_ADC1ToChannel1 = ((uint8_t)0x01), /*!< ADC1 DMA1 req/ack mapped on DMA1 channel 1 */
REMAP_DMA1Channel_ADC1ToChannel2 = ((uint8_t)0x02), /*!< ADC1 DMA1 req/ack mapped on DMA1 channel 2 */
REMAP_DMA1Channel_ADC1ToChannel3 = ((uint8_t)0x03), /*!< ADC1 DMA1 req/ack mapped on DMA1 channel 3 */
REMAP_DMA1Channel_TIM4ToChannel0 = ((uint8_t)0xF0), /*!< TIM4 DMA1 req/ack mapped on DMA1 channel 0 */
REMAP_DMA1Channel_TIM4ToChannel1 = ((uint8_t)0xF4), /*!< TIM4 DMA1 req/ack mapped on DMA1 channel 1 */
REMAP_DMA1Channel_TIM4ToChannel2 = ((uint8_t)0xF8), /*!< TIM4 DMA1 req/ack mapped on DMA1 channel 2 */
REMAP_DMA1Channel_TIM4ToChannel3 = ((uint8_t)0xFC) /*!< TIM4 DMA1 req/ack mapped on DMA1 channel 3 */
}REMAP_DMAChannel_TypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup SYSCFG_Exported_Macros
* @{
*/
/**
* @brief Macro used by the assert function in order to check the different
* values of @ref RI_InputCaptureTypeDef enum.
*/
#define IS_RI_INPUTCAPTURE(RI_IC) (((RI_IC) == RI_InputCapture_IC2) || \
((RI_IC) == RI_InputCapture_IC3))
/**
* @brief Macro used by the assert function in order to check the different
* values of @ref RI_InputCaptureRoutingTypeDef enum.
*/
#define IS_RI_INPUTCAPTUREROUTING(RI_IC_ROUTING) (((RI_IC_ROUTING) == RI_InputCaptureRouting_0) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_1) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_2) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_3) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_4) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_5) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_6) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_7) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_8) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_9) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_10) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_11) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_12) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_13) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_14) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_15) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_16) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_17) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_18) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_19) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_20) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_21) || \
((RI_IC_ROUTING) == RI_InputCaptureRouting_22))
/**
* @brief Macro used by the assert function in order to check the different
* values of @ref RI_AnalogSwitch_TypeDef enum.
*/
#define IS_RI_ANALOGSWITCH(RI_ANALOGSWITCH) (((RI_ANALOGSWITCH) == RI_AnalogSwitch_0) || \
((RI_ANALOGSWITCH) == RI_AnalogSwitch_1) || \
((RI_ANALOGSWITCH) == RI_AnalogSwitch_2) || \
((RI_ANALOGSWITCH) == RI_AnalogSwitch_3) || \
((RI_ANALOGSWITCH) == RI_AnalogSwitch_4) || \
((RI_ANALOGSWITCH) == RI_AnalogSwitch_5) || \
((RI_ANALOGSWITCH) == RI_AnalogSwitch_6) || \
((RI_ANALOGSWITCH) == RI_AnalogSwitch_7) || \
((RI_ANALOGSWITCH) == RI_AnalogSwitch_8) || \
((RI_ANALOGSWITCH) == RI_AnalogSwitch_9) || \
((RI_ANALOGSWITCH) == RI_AnalogSwitch_10)|| \
((RI_ANALOGSWITCH) == RI_AnalogSwitch_11)|| \
((RI_ANALOGSWITCH) == RI_AnalogSwitch_14))
/**
* @brief Macro used by the assert function in order to check the different
* values of @ref RI_IOSwitch_TypeDef enum.
*/
#define IS_RI_IOSWITCH(RI_IOSWITCH) (((RI_IOSWITCH) == RI_IOSwitch_1) || \
((RI_IOSWITCH) == RI_IOSwitch_2) || \
((RI_IOSWITCH) == RI_IOSwitch_3) || \
((RI_IOSWITCH) == RI_IOSwitch_4) || \
((RI_IOSWITCH) == RI_IOSwitch_5) || \
((RI_IOSWITCH) == RI_IOSwitch_6) || \
((RI_IOSWITCH) == RI_IOSwitch_7) || \
((RI_IOSWITCH) == RI_IOSwitch_8) || \
((RI_IOSWITCH) == RI_IOSwitch_9) || \
((RI_IOSWITCH) == RI_IOSwitch_10) || \
((RI_IOSWITCH) == RI_IOSwitch_11) || \
((RI_IOSWITCH) == RI_IOSwitch_12) || \
((RI_IOSWITCH) == RI_IOSwitch_13) || \
((RI_IOSWITCH) == RI_IOSwitch_14) || \
((RI_IOSWITCH) == RI_IOSwitch_15) || \
((RI_IOSWITCH) == RI_IOSwitch_16) || \
((RI_IOSWITCH) == RI_IOSwitch_17) || \
((RI_IOSWITCH) == RI_IOSwitch_18) || \
((RI_IOSWITCH) == RI_IOSwitch_19) || \
((RI_IOSWITCH) == RI_IOSwitch_20) || \
((RI_IOSWITCH) == RI_IOSwitch_21) || \
((RI_IOSWITCH) == RI_IOSwitch_22) || \
((RI_IOSWITCH) == RI_IOSwitch_23) || \
((RI_IOSWITCH) == RI_IOSwitch_24) || \
((RI_IOSWITCH) == RI_IOSwitch_26) || \
((RI_IOSWITCH) == RI_IOSwitch_27) || \
((RI_IOSWITCH) == RI_IOSwitch_28) || \
((RI_IOSWITCH) == RI_IOSwitch_29))
/**
* @brief Macro used by the assert function in order to check the different
* values of @ref RI_ResistorTypeDef enum.
*/
#define IS_RI_RESISTOR(RI_RESISTOR) (((RI_RESISTOR) == RI_Resistor_10KPU) || \
((RI_RESISTOR) == RI_Resistor_400KPU) || \
((RI_RESISTOR) == RI_Resistor_10KPD) || \
((RI_RESISTOR) == RI_Resistor_400KPD))
/**
* @brief Macro used by the assert function in order to check the different
* values of @ref REMAP_Pin_TypeDef enum.
*/
#define IS_REMAP_PIN(PIN) (((PIN) == REMAP_Pin_USART1TxRxPortA) || \
((PIN) == REMAP_Pin_USART1TxRxPortC) || \
((PIN) == REMAP_Pin_USART1Clk) || \
((PIN) == REMAP_Pin_SPI1Full) || \
((PIN) == REMAP_Pin_ADC1ExtTRIG1) || \
((PIN) == REMAP_Pin_TIM2TRIGPortA) || \
((PIN) == REMAP_Pin_TIM3TRIGPortA) || \
((PIN) == REMAP_Pin_TIM2TRIGLSE) || \
((PIN) == REMAP_Pin_TIM3TRIGLSE) || \
((PIN) == REMAP_Pin_SPI2Full) || \
((PIN) == REMAP_Pin_TIM3TRIGPortG) || \
((PIN) == REMAP_Pin_TIM23BKIN) || \
((PIN) == REMAP_Pin_SPI1PortF) || \
((PIN) == REMAP_Pin_USART3TxRxPortF) || \
((PIN) == REMAP_Pin_USART3Clk) || \
((PIN) == REMAP_Pin_TIM3Channel1) || \
((PIN) == REMAP_Pin_TIM3Channel2) || \
((PIN) == REMAP_Pin_CCO) || \
((PIN) == REMAP_Pin_TIM2Channel1) || \
((PIN) == REMAP_Pin_TIM2Channel2))
/**
* @brief Macro used by the assert function in order to check the different
* values of the @ref REMAP_DMAChannel_TypeDef enum.
*/
#define IS_REMAP_DMACHANNEL(MAP) (((MAP) == REMAP_DMA1Channel_ADC1ToChannel0) || \
((MAP) == REMAP_DMA1Channel_ADC1ToChannel1) || \
((MAP) == REMAP_DMA1Channel_ADC1ToChannel2) || \
((MAP) == REMAP_DMA1Channel_ADC1ToChannel3) || \
((MAP) == REMAP_DMA1Channel_TIM4ToChannel0) || \
((MAP) == REMAP_DMA1Channel_TIM4ToChannel1) || \
((MAP) == REMAP_DMA1Channel_TIM4ToChannel2) || \
((MAP) == REMAP_DMA1Channel_TIM4ToChannel3))
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* Routing Interface (RI) configuration ***************************************/
void SYSCFG_RIDeInit(void);
void SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_TypeDef RI_InputCapture,
RI_InputCaptureRouting_TypeDef RI_InputCaptureRouting);
void SYSCFG_RIAnalogSwitchConfig(RI_AnalogSwitch_TypeDef RI_AnalogSwitch,
FunctionalState NewState);
void SYSCFG_RIIOSwitchConfig(RI_IOSwitch_TypeDef RI_IOSwitch, FunctionalState NewState);
void SYSCFG_RIResistorConfig(RI_Resistor_TypeDef RI_Resistor, FunctionalState NewState);
/* SYSCFG configuration *******************************************************/
void SYSCFG_REMAPDeInit(void);
void SYSCFG_REMAPPinConfig(REMAP_Pin_TypeDef REMAP_Pin, FunctionalState NewState);
void SYSCFG_REMAPDMAChannelConfig(REMAP_DMAChannel_TypeDef REMAP_DMAChannel);
#endif /* __STM8L15x_SYSCFG_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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firmware/inc/stm8l151x/inc/stm8l15x_tim1.h Normal file
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firmware/inc/stm8l151x/inc/stm8l15x_tim2.h Normal file
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/**
******************************************************************************
* @file stm8l15x_tim2.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the TIM2 firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_TIM2_H
#define __STM8L15x_TIM2_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup TIM2
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIM2_Exported_Types
* @{
*/
/** @defgroup TIM2_Forced_Action
* @{
*/
typedef enum
{
TIM2_ForcedAction_Active = ((uint8_t)0x50), /*!< Output Reference is forced low */
TIM2_ForcedAction_Inactive = ((uint8_t)0x40) /*!< Output Reference is forced high */
}
TIM2_ForcedAction_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Prescaler
* @{
*/
typedef enum
{
TIM2_Prescaler_1 = ((uint8_t)0x00), /*!< Time base Prescaler = 1 (No effect)*/
TIM2_Prescaler_2 = ((uint8_t)0x01), /*!< Time base Prescaler = 2 */
TIM2_Prescaler_4 = ((uint8_t)0x02), /*!< Time base Prescaler = 4 */
TIM2_Prescaler_8 = ((uint8_t)0x03), /*!< Time base Prescaler = 8 */
TIM2_Prescaler_16 = ((uint8_t)0x04), /*!< Time base Prescaler = 16 */
TIM2_Prescaler_32 = ((uint8_t)0x05), /*!< Time base Prescaler = 32 */
TIM2_Prescaler_64 = ((uint8_t)0x06), /*!< Time base Prescaler = 64 */
TIM2_Prescaler_128 = ((uint8_t)0x07) /*!< Time base Prescaler = 128 */
}TIM2_Prescaler_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_OCMode
* @{
*/
typedef enum
{
TIM2_OCMode_Timing = ((uint8_t)0x00), /*!< Timing (Frozen) Mode*/
TIM2_OCMode_Active = ((uint8_t)0x10), /*!< Active Mode*/
TIM2_OCMode_Inactive = ((uint8_t)0x20), /*!< Inactive Mode*/
TIM2_OCMode_Toggle = ((uint8_t)0x30), /*!< Toggle Mode*/
TIM2_OCMode_PWM1 = ((uint8_t)0x60), /*!< PWM Mode 1*/
TIM2_OCMode_PWM2 = ((uint8_t)0x70) /*!< PWM Mode 2*/
}TIM2_OCMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_OnePulseMode
* @{
*/
typedef enum
{
TIM2_OPMode_Single = ((uint8_t)0x01), /*!< Single one Pulse mode (OPM Active) */
TIM2_OPMode_Repetitive = ((uint8_t)0x00) /*!< Repetitive Pulse mode (OPM inactive) */
}TIM2_OPMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Channel
* @{
*/
typedef enum
{
TIM2_Channel_1 = ((uint8_t)0x00), /*!< Channel 1*/
TIM2_Channel_2 = ((uint8_t)0x01) /*!< Channel 2*/
}TIM2_Channel_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_CounterMode
* @{
*/
typedef enum
{
TIM2_CounterMode_Up = ((uint8_t)0x00), /*!< Counter Up Mode */
TIM2_CounterMode_Down = ((uint8_t)0x10), /*!< Counter Down Mode */
TIM2_CounterMode_CenterAligned1 = ((uint8_t)0x20), /*!< Counter Central aligned Mode 1 */
TIM2_CounterMode_CenterAligned2 = ((uint8_t)0x40), /*!< Counter Central aligned Mode 2 */
TIM2_CounterMode_CenterAligned3 = ((uint8_t)0x60) /*!< Counter Central aligned Mode 3 */
}TIM2_CounterMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Output_Compare_Polarity
* @{
*/
typedef enum
{
TIM2_OCPolarity_High = ((uint8_t)0x00), /*!< Output compare polarity = High */
TIM2_OCPolarity_Low = ((uint8_t)0x01) /*!< Output compare polarity = Low */
}TIM2_OCPolarity_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Output_State
* @{
*/
typedef enum
{
TIM2_OutputState_Disable = ((uint8_t)0x00), /*!< Output compare State disabled (channel output disabled) */
TIM2_OutputState_Enable = ((uint8_t)0x01) /*!< Output compare State enabled (channel output enabled) */
}TIM2_OutputState_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Break_State
* @{
*/
typedef enum
{
TIM2_BreakState_Disable = ((uint8_t)0x00), /*!< Break State disabled (break option disabled) */
TIM2_BreakState_Enable = ((uint8_t)0x10) /*!< Break State enabled (break option enabled) */
}TIM2_BreakState_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Break_Polarity
* @{
*/
typedef enum
{
TIM2_BreakPolarity_High = ((uint8_t)0x20), /*!< if Break, channel polarity = High */
TIM2_BreakPolarity_Low = ((uint8_t)0x00) /*!< if Break, channel polarity = Low */
}TIM2_BreakPolarity_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Automatic_Output
* @{
*/
typedef enum
{
TIM2_AutomaticOutput_Enable = ((uint8_t)0x40), /*!< Automatic Output option enabled */
TIM2_AutomaticOutput_Disable = ((uint8_t)0x00) /*!< Automatic Output option disabled */
}TIM2_AutomaticOutput_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Lock_Level
* @{
*/
typedef enum
{
TIM2_LockLevel_Off = ((uint8_t)0x00), /*!< Lock option disabled */
TIM2_LockLevel_1 = ((uint8_t)0x01), /*!< Select Lock Level 1 */
TIM2_LockLevel_2 = ((uint8_t)0x02), /*!< Select Lock Level 2 */
TIM2_LockLevel_3 = ((uint8_t)0x03) /*!< Select Lock Level 3 */
}TIM2_LockLevel_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_OSSI_State
* @{
*/
typedef enum
{
TIM2_OSSIState_Enable = ((uint8_t)0x04), /*!< Off-State Selection for Idle mode enabled */
TIM2_OSSIState_Disable = ((uint8_t)0x00) /*!< Off-State Selection for Idle mode disabled */
}TIM2_OSSIState_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Output_Compare_Idle_state
* @{
*/
typedef enum
{
TIM2_OCIdleState_Reset = ((uint8_t)0x00), /*!< Output Compare Idle state = Reset */
TIM2_OCIdleState_Set = ((uint8_t)0x01) /*!< Output Compare Idle state = Set */
}TIM2_OCIdleState_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Input_Capture_Polarity
* @{
*/
typedef enum
{
TIM2_ICPolarity_Rising = ((uint8_t)0x00), /*!< Input Capture on Rising Edge*/
TIM2_ICPolarity_Falling = ((uint8_t)0x01) /*!< Input Capture on Falling Edge*/
}TIM2_ICPolarity_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Input_Capture_Selection
* @{
*/
typedef enum
{
TIM2_ICSelection_DirectTI = ((uint8_t)0x01), /*!< Input Capture mapped on the direct input*/
TIM2_ICSelection_IndirectTI = ((uint8_t)0x02), /*!< Input Capture mapped on the indirect input*/
TIM2_ICSelection_TRGI = ((uint8_t)0x03) /*!< Input Capture mapped on the Trigger Input*/
}TIM2_ICSelection_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Input_Capture_Prescaler
* @{
*/
typedef enum
{
TIM2_ICPSC_DIV1 = ((uint8_t)0x00), /*!< Input Capture Prescaler = 1 (one capture every 1 event) */
TIM2_ICPSC_DIV2 = ((uint8_t)0x04), /*!< Input Capture Prescaler = 2 (one capture every 2 events) */
TIM2_ICPSC_DIV4 = ((uint8_t)0x08), /*!< Input Capture Prescaler = 4 (one capture every 4 events) */
TIM2_ICPSC_DIV8 = ((uint8_t)0x0C) /*!< Input Capture Prescaler = 8 (one capture every 8 events) */
}TIM2_ICPSC_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Interrupts
* @{
*/
typedef enum
{
TIM2_IT_Update = ((uint8_t)0x01), /*!< Update Interrupt*/
TIM2_IT_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Interrupt*/
TIM2_IT_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Interrupt*/
TIM2_IT_Trigger = ((uint8_t)0x40), /*!< Trigger Interrupt*/
TIM2_IT_Break = ((uint8_t)0x80) /*!< Break Interrupt*/
}TIM2_IT_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_External_Trigger_Prescaler
* @{
*/
typedef enum
{
TIM2_ExtTRGPSC_OFF = ((uint8_t)0x00), /*!< No External Trigger prescaler */
TIM2_ExtTRGPSC_DIV2 = ((uint8_t)0x10), /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */
TIM2_ExtTRGPSC_DIV4 = ((uint8_t)0x20), /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */
TIM2_ExtTRGPSC_DIV8 = ((uint8_t)0x30) /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */
}TIM2_ExtTRGPSC_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Internal_Trigger_Selection
* @{
*/
typedef enum
{
TIM2_TRGSelection_TIM4 = ((uint8_t)0x00), /*!< TRIG Input source = TIM TRIG Output */
TIM2_TRGSelection_TIM1 = ((uint8_t)0x10), /*!< TRIG Input source = TIM TRIG Output */
TIM2_TRGSelection_TIM3 = ((uint8_t)0x20), /*!< TRIG Input source = TIM TRIG Output */
TIM2_TRGSelection_TIM5 = ((uint8_t)0x30), /*!< TRIG Input source = TIM TRIG Output */
TIM2_TRGSelection_TI1F_ED = ((uint8_t)0x40), /*!< TRIG Input source = TI1F_ED (TI1 Edge Detector) */
TIM2_TRGSelection_TI1FP1 = ((uint8_t)0x50), /*!< TRIG Input source = TI1FP1 (Filtered Timer Input 1) */
TIM2_TRGSelection_TI2FP2 = ((uint8_t)0x60), /*!< TRIG Input source = TI2FP2 (Filtered Timer Input 2) */
TIM2_TRGSelection_ETRF = ((uint8_t)0x70) /*!< TRIG Input source = ETRF (External Trigger Input ) */
}TIM2_TRGSelection_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_TI_External_Clock_Source
* @{
*/
typedef enum
{
TIM2_TIxExternalCLK1Source_TI1ED = ((uint8_t)0x40), /*!< External Clock mode 1 source = TI1ED */
TIM2_TIxExternalCLK1Source_TI1 = ((uint8_t)0x50), /*!< External Clock mode 1 source = TI1 */
TIM2_TIxExternalCLK1Source_TI2 = ((uint8_t)0x60) /*!< External Clock mode 1 source = TI2 */
}TIM2_TIxExternalCLK1Source_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_External_Trigger_Polarity
* @{
*/
typedef enum
{
TIM2_ExtTRGPolarity_Inverted = ((uint8_t)0x80), /*!< External Trigger Polarity = inverted */
TIM2_ExtTRGPolarity_NonInverted = ((uint8_t)0x00) /*!< External Trigger Polarity = non inverted */
}TIM2_ExtTRGPolarity_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Prescaler_Reload_Mode
* @{
*/
typedef enum
{
TIM2_PSCReloadMode_Update = ((uint8_t)0x00), /*!< Prescaler value is reloaded at every update*/
TIM2_PSCReloadMode_Immediate = ((uint8_t)0x01) /*!< Prescaler value is reloaded immediatly*/
}TIM2_PSCReloadMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Encoder_Mode
* @{
*/
typedef enum
{
TIM2_EncoderMode_TI1 = ((uint8_t)0x01), /*!< Encoder mode 1*/
TIM2_EncoderMode_TI2 = ((uint8_t)0x02), /*!< Encoder mode 2*/
TIM2_EncoderMode_TI12 = ((uint8_t)0x03) /*!< Encoder mode 3*/
}TIM2_EncoderMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Event_Source
* @{
*/
typedef enum
{
TIM2_EventSource_Update = ((uint8_t)0x01), /*!< Update Event*/
TIM2_EventSource_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Event*/
TIM2_EventSource_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Event*/
TIM2_EventSource_Trigger = ((uint8_t)0x40), /*!< Trigger Event*/
TIM2_EventSource_Break = ((uint8_t)0x80) /*!< Break Event*/
}TIM2_EventSource_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Update_Source
* @{
*/
typedef enum
{
TIM2_UpdateSource_Global = ((uint8_t)0x00), /*!< Global Update request source */
TIM2_UpdateSource_Regular = ((uint8_t)0x01) /*!< Regular Update request source */
}TIM2_UpdateSource_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Trigger_Output_Source
* @{
*/
typedef enum
{
TIM2_TRGOSource_Reset = ((uint8_t)0x00), /*!< Trigger Output source = Reset*/
TIM2_TRGOSource_Enable = ((uint8_t)0x10), /*!< Trigger Output source = TIM2 is enabled*/
TIM2_TRGOSource_Update = ((uint8_t)0x20), /*!< Trigger Output source = Update event*/
TIM2_TRGOSource_OC1 = ((uint8_t)0x30), /*!< Trigger Output source = output compare channel1 */
TIM2_TRGOSource_OC1REF = ((uint8_t)0x40), /*!< Trigger Output source = output compare channel 1 reference */
TIM2_TRGOSource_OC2REF = ((uint8_t)0x50) /*!< Trigger Output source = output compare channel 2 reference */
}TIM2_TRGOSource_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Slave_Mode
* @{
*/
typedef enum
{
TIM2_SlaveMode_Reset = ((uint8_t)0x04), /*!< Slave Mode Selection = Reset*/
TIM2_SlaveMode_Gated = ((uint8_t)0x05), /*!< Slave Mode Selection = Gated*/
TIM2_SlaveMode_Trigger = ((uint8_t)0x06), /*!< Slave Mode Selection = Trigger*/
TIM2_SlaveMode_External1 = ((uint8_t)0x07) /*!< Slave Mode Selection = External 1*/
}TIM2_SlaveMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_Flags
* @{
*/
typedef enum
{
TIM2_FLAG_Update = ((uint16_t)0x0001), /*!< Update Flag */
TIM2_FLAG_CC1 = ((uint16_t)0x0002), /*!< Capture compare 1 Flag */
TIM2_FLAG_CC2 = ((uint16_t)0x0004), /*!< Capture compare 2 Flag */
TIM2_FLAG_Trigger = ((uint16_t)0x0040), /*!< Trigger Flag */
TIM2_FLAG_Break = ((uint16_t)0x0080), /*!< Break Flag */
TIM2_FLAG_CC1OF = ((uint16_t)0x0200), /*!< Capture compare 1 over capture Flag */
TIM2_FLAG_CC2OF = ((uint16_t)0x0400) /*!< Capture compare 2 over capture Flag */
}TIM2_FLAG_TypeDef;
/**
* @}
*/
/** @defgroup TIM2_DMA_Source_Requests
* @{
*/
typedef enum
{
TIM2_DMASource_Update = ((uint8_t)0x01), /*!< TIM2 DMA Update Request*/
TIM2_DMASource_CC1 = ((uint8_t)0x02), /*!< TIM2 DMA CC1 Request*/
TIM2_DMASource_CC2 = ((uint8_t)0x04) /*!< TIM2 DMA CC2 Request*/
}TIM2_DMASource_TypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup TIM2_Exported_Macros
* @{
*/
/**
* @brief Macro used by the assert function to check the different functions parameters.
*/
/**
* @brief Macro TIM2 Forced Action
*/
#define IS_TIM2_FORCED_ACTION(ACTION) \
(((ACTION) == TIM2_ForcedAction_Active) || \
((ACTION) == TIM2_ForcedAction_Inactive))
/**
* @brief Macro TIM2 Prescaler
*/
#define IS_TIM2_PRESCALER(PRESCALER) \
(((PRESCALER) == TIM2_Prescaler_1) || \
((PRESCALER) == TIM2_Prescaler_2) || \
((PRESCALER) == TIM2_Prescaler_4) || \
((PRESCALER) == TIM2_Prescaler_8) || \
((PRESCALER) == TIM2_Prescaler_16) || \
((PRESCALER) == TIM2_Prescaler_32) || \
((PRESCALER) == TIM2_Prescaler_64) || \
((PRESCALER) == TIM2_Prescaler_128))
/**
* @brief Macro TIM2 Output Compare and PWM modes
*/
#define IS_TIM2_OC_MODE(MODE) \
(((MODE) == TIM2_OCMode_Timing) || \
((MODE) == TIM2_OCMode_Active) || \
((MODE) == TIM2_OCMode_Inactive) || \
((MODE) == TIM2_OCMode_Toggle) || \
((MODE) == TIM2_OCMode_PWM1) || \
((MODE) == TIM2_OCMode_PWM2))
#define IS_TIM2_OCM(MODE) \
(((MODE) == TIM2_OCMode_Timing) || \
((MODE) == TIM2_OCMode_Active) || \
((MODE) == TIM2_OCMode_Inactive) || \
((MODE) == TIM2_OCMode_Toggle) || \
((MODE) == TIM2_OCMode_PWM1) || \
((MODE) == TIM2_OCMode_PWM2) || \
((MODE) == (uint8_t)TIM2_ForcedAction_Active) || \
((MODE) == (uint8_t)TIM2_ForcedAction_Inactive))
/**
* @brief Macro TIM2 One Pulse Mode
*/
#define IS_TIM2_OPM_MODE(MODE) \
(((MODE) == TIM2_OPMode_Single) || \
((MODE) == TIM2_OPMode_Repetitive))
/**
* @brief Macro TIM2 Channel
*/
#define IS_TIM2_CHANNEL(CHANNEL) \
(((CHANNEL) == TIM2_Channel_1) || \
((CHANNEL) == TIM2_Channel_2) )
/**
* @brief Macro TIM2 Counter Mode
*/
#define IS_TIM2_COUNTER_MODE(MODE) \
(((MODE) == TIM2_CounterMode_Up) || \
((MODE) == TIM2_CounterMode_Down) || \
((MODE) == TIM2_CounterMode_CenterAligned1) || \
((MODE) == TIM2_CounterMode_CenterAligned2) || \
((MODE) == TIM2_CounterMode_CenterAligned3))
/**
* @brief Macro TIM2 Output Compare Polarity
*/
#define IS_TIM2_OC_POLARITY(POLARITY) \
(((POLARITY) == TIM2_OCPolarity_High) || \
((POLARITY) == TIM2_OCPolarity_Low))
/**
* @brief Macro TIM2 Output Compare states
*/
#define IS_TIM2_OUTPUT_STATE(STATE) \
(((STATE) == TIM2_OutputState_Disable) || \
((STATE) == TIM2_OutputState_Enable))
/**
* @brief Macro Break Input enable/disable
*/
#define IS_TIM2_BREAK_STATE(STATE) \
(((STATE) == TIM2_BreakState_Enable) || \
((STATE) == TIM2_BreakState_Disable))
/**
* @brief Macro Break Polarity
*/
#define IS_TIM2_BREAK_POLARITY(POLARITY) \
(((POLARITY) == TIM2_BreakPolarity_Low) || \
((POLARITY) == TIM2_BreakPolarity_High))
/**
* @brief Macro TIM2 AOE Bit Set/Reset
*/
#define IS_TIM2_AUTOMATIC_OUTPUT_STATE(STATE) \
(((STATE) == TIM2_AutomaticOutput_Enable) || \
((STATE) == TIM2_AutomaticOutput_Disable))
/**
* @brief Macro Lock levels
*/
#define IS_TIM2_LOCK_LEVEL(LEVEL) \
(((LEVEL) == TIM2_LockLevel_Off) || \
((LEVEL) == TIM2_LockLevel_1) || \
((LEVEL) == TIM2_LockLevel_2) || \
((LEVEL) == TIM2_LockLevel_3))
/**
* @brief Macro OSSI: Off-State Selection for Idle mode states
*/
#define IS_TIM2_OSSI_STATE(STATE) \
(((STATE) == TIM2_OSSIState_Enable) || \
((STATE) == TIM2_OSSIState_Disable))
/**
* @brief Macro TIM2 OC IDLE STATE
*/
#define IS_TIM2_OCIDLE_STATE(STATE) \
(((STATE) == TIM2_OCIdleState_Set) || \
((STATE) == TIM2_OCIdleState_Reset))
/**
* @brief Macro TIM2 IC POLARITY
*/
#define IS_TIM2_IC_POLARITY(POLARITY) \
(((POLARITY) == TIM2_ICPolarity_Rising) || \
((POLARITY) == TIM2_ICPolarity_Falling))
/**
* @brief Macro TIM2 IC SELECTION
*/
#define IS_TIM2_IC_SELECTION(SELECTION) \
(((SELECTION) == TIM2_ICSelection_DirectTI) || \
((SELECTION) == TIM2_ICSelection_IndirectTI) || \
((SELECTION) == TIM2_ICSelection_TRGI))
/**
* @brief Macro TIM2 IC PRESCALER
*/
#define IS_TIM2_IC_PRESCALER(PRESCALER) \
(((PRESCALER) == TIM2_ICPSC_DIV1) || \
((PRESCALER) == TIM2_ICPSC_DIV2) || \
((PRESCALER) == TIM2_ICPSC_DIV4) || \
((PRESCALER) == TIM2_ICPSC_DIV8))
/**
* @brief Macro TIM2 Input Capture Filter Value
*/
#define IS_TIM2_IC_FILTER(ICFILTER) \
((ICFILTER) <= 0x0F)
/**
* @brief Macro TIM2 Interrupts
*/
#define IS_TIM2_IT(IT) \
((IT) != 0x00)
#define IS_TIM2_GET_IT(IT) \
(((IT) == TIM2_IT_Update) || \
((IT) == TIM2_IT_CC1) || \
((IT) == TIM2_IT_CC2) || \
((IT) == TIM2_IT_Trigger) || \
((IT) == TIM2_IT_Break))
/**
* @brief Macro TIM2 external trigger prescaler
*/
#define IS_TIM2_EXT_PRESCALER(PRESCALER) \
(((PRESCALER) == TIM2_ExtTRGPSC_OFF) || \
((PRESCALER) == TIM2_ExtTRGPSC_DIV2) || \
((PRESCALER) == TIM2_ExtTRGPSC_DIV4) || \
((PRESCALER) == TIM2_ExtTRGPSC_DIV8))
/**
* @brief Macro TIM2 Trigger Selection
*/
#define IS_TIM2_TRIGGER_SELECTION(SELECTION) \
(((SELECTION) == TIM2_TRGSelection_TIM4) || \
((SELECTION) == TIM2_TRGSelection_TIM1) || \
((SELECTION) == TIM2_TRGSelection_TIM3) || \
((SELECTION) == TIM2_TRGSelection_TIM5) || \
((SELECTION) == TIM2_TRGSelection_TI1F_ED) || \
((SELECTION) == TIM2_TRGSelection_TI1FP1) || \
((SELECTION) == TIM2_TRGSelection_TI2FP2) || \
((SELECTION) == TIM2_TRGSelection_ETRF))
#define IS_TIM2_TIX_TRIGGER_SELECTION(SELECTION) \
(((SELECTION) == TIM2_TRGSelection_TI1F_ED) || \
((SELECTION) == TIM2_TRGSelection_TI1FP1) || \
((SELECTION) == TIM2_TRGSelection_TI2FP2))
/**
* @brief Macro TIM2 TIx external Clock Selection
*/
#define IS_TIM2_TIXCLK_SOURCE(SOURCE) \
(((SOURCE) == TIM2_TIxExternalCLK1Source_TI1ED) || \
((SOURCE) == TIM2_TIxExternalCLK1Source_TI2) || \
((SOURCE) == TIM2_TIxExternalCLK1Source_TI1))
/**
* @brief Macro TIM2 Trigger Polarity
*/
#define IS_TIM2_EXT_POLARITY(POLARITY) \
(((POLARITY) == TIM2_ExtTRGPolarity_Inverted) || \
((POLARITY) == TIM2_ExtTRGPolarity_NonInverted))
/**
* @brief Macro TIM2 External Trigger Filter
*/
#define IS_TIM2_EXT_FILTER(EXTFILTER) \
((EXTFILTER) <= 0x0F)
/**
* @brief Macro TIM2 Prescaler Reload
*/
#define IS_TIM2_PRESCALER_RELOAD(RELOAD) \
(((RELOAD) == TIM2_PSCReloadMode_Update) || \
((RELOAD) == TIM2_PSCReloadMode_Immediate))
/**
* @brief Macro TIM2 encoder mode
*/
#define IS_TIM2_ENCODER_MODE(MODE) \
(((MODE) == TIM2_EncoderMode_TI1) || \
((MODE) == TIM2_EncoderMode_TI2) || \
((MODE) == TIM2_EncoderMode_TI12))
/**
* @brief Macro TIM2 event source
*/
#define IS_TIM2_EVENT_SOURCE(SOURCE) \
((((SOURCE) & (uint8_t)0x18) == 0x00) && \
((SOURCE) != 0x00))
/**
* @brief Macro TIM2 update source
*/
#define IS_TIM2_UPDATE_SOURCE(SOURCE) \
(((SOURCE) == TIM2_UpdateSource_Global) || \
((SOURCE) == TIM2_UpdateSource_Regular))
/**
* @brief Macro TIM2 TRGO source
*/
#define IS_TIM2_TRGO_SOURCE(SOURCE) \
(((SOURCE) == TIM2_TRGOSource_Reset) || \
((SOURCE) == TIM2_TRGOSource_Enable) || \
((SOURCE) == TIM2_TRGOSource_Update) || \
((SOURCE) == TIM2_TRGOSource_OC1) || \
((SOURCE) == TIM2_TRGOSource_OC1REF) || \
((SOURCE) == TIM2_TRGOSource_OC2REF))
/**
* @brief Macro TIM2 Slave mode
*/
#define IS_TIM2_SLAVE_MODE(MODE) \
(((MODE) == TIM2_SlaveMode_Reset) || \
((MODE) == TIM2_SlaveMode_Gated) || \
((MODE) == TIM2_SlaveMode_Trigger) || \
((MODE) == TIM2_SlaveMode_External1))
/**
* @brief Macro TIM2 Flags
*/
#define IS_TIM2_GET_FLAG(FLAG) \
(((FLAG) == TIM2_FLAG_Update) || \
((FLAG) == TIM2_FLAG_CC1) || \
((FLAG) == TIM2_FLAG_CC2) || \
((FLAG) == TIM2_FLAG_Trigger) || \
((FLAG) == TIM2_FLAG_Break) || \
((FLAG) == TIM2_FLAG_CC1OF) || \
((FLAG) == TIM2_FLAG_CC2OF))
#define IS_TIM2_CLEAR_FLAG(FLAG) \
((((FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
/**
* @brief Macro TIM2 DMA sources
*/
#define IS_TIM2_DMA_SOURCE(SOURCE) \
(((SOURCE) == TIM2_DMASource_Update) || \
((SOURCE) == TIM2_DMASource_CC1) || \
((SOURCE) == TIM2_DMASource_CC2))
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* TimeBase management ********************************************************/
void TIM2_DeInit(void);
void TIM2_TimeBaseInit(TIM2_Prescaler_TypeDef TIM2_Prescaler,
TIM2_CounterMode_TypeDef TIM2_CounterMode, uint16_t TIM2_Period);
void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler,
TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode);
void TIM2_CounterModeConfig(TIM2_CounterMode_TypeDef TIM2_CounterMode);
void TIM2_SetCounter(uint16_t Counter);
void TIM2_SetAutoreload(uint16_t Autoreload);
uint16_t TIM2_GetCounter(void);
TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void);
void TIM2_UpdateDisableConfig(FunctionalState NewState);
void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource);
void TIM2_ARRPreloadConfig(FunctionalState NewState);
void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode);
void TIM2_Cmd(FunctionalState NewState);
/* Output Compare management **************************************************/
void TIM2_OC1Init(TIM2_OCMode_TypeDef TIM2_OCMode,
TIM2_OutputState_TypeDef TIM2_OutputState,
uint16_t TIM2_Pulse,
TIM2_OCPolarity_TypeDef TIM2_OCPolarity,
TIM2_OCIdleState_TypeDef TIM2_OCIdleState);
void TIM2_OC2Init(TIM2_OCMode_TypeDef TIM2_OCMode,
TIM2_OutputState_TypeDef TIM2_OutputState,
uint16_t TIM2_Pulse,
TIM2_OCPolarity_TypeDef TIM2_OCPolarity,
TIM2_OCIdleState_TypeDef TIM2_OCIdleState);
void TIM2_BKRConfig(TIM2_OSSIState_TypeDef TIM2_OSSIState,
TIM2_LockLevel_TypeDef TIM2_LockLevel,
TIM2_BreakState_TypeDef TIM2_BreakState,
TIM2_BreakPolarity_TypeDef TIM2_BreakPolarity,
TIM2_AutomaticOutput_TypeDef TIM2_AutomaticOutput);
void TIM2_CtrlPWMOutputs(FunctionalState NewState);
void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode);
void TIM2_SetCompare1(uint16_t Compare);
void TIM2_SetCompare2(uint16_t Compare);
void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);
void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);
void TIM2_OC1PreloadConfig(FunctionalState NewState);
void TIM2_OC2PreloadConfig(FunctionalState NewState);
void TIM2_OC1FastConfig(FunctionalState NewState);
void TIM2_OC2FastConfig(FunctionalState NewState);
void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState);
/* Input Capture management ***************************************************/
void TIM2_ICInit(TIM2_Channel_TypeDef TIM2_Channel,
TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
TIM2_ICSelection_TypeDef TIM2_ICSelection,
TIM2_ICPSC_TypeDef TIM2_ICPrescaler,
uint8_t TIM2_ICFilter);
void TIM2_PWMIConfig(TIM2_Channel_TypeDef TIM2_Channel,
TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
TIM2_ICSelection_TypeDef TIM2_ICSelection,
TIM2_ICPSC_TypeDef TIM2_ICPrescaler,
uint8_t TIM2_ICFilter);
uint16_t TIM2_GetCapture1(void);
uint16_t TIM2_GetCapture2(void);
void TIM2_SetIC1Prescaler(TIM2_ICPSC_TypeDef TIM2_IC1Prescaler);
void TIM2_SetIC2Prescaler(TIM2_ICPSC_TypeDef TIM2_IC2Prescaler);
/* Interrupts, DMA and flags management ***************************************/
void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState);
void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource);
FlagStatus TIM2_GetFlagStatus(TIM2_FLAG_TypeDef TIM2_FLAG);
void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG);
ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT);
void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT);
void TIM2_DMACmd(TIM2_DMASource_TypeDef TIM2_DMASource, FunctionalState NewState);
void TIM2_SelectCCDMA(FunctionalState NewState);
/* Clocks management **********************************************************/
void TIM2_InternalClockConfig(void);
void TIM2_TIxExternalClockConfig(TIM2_TIxExternalCLK1Source_TypeDef TIM2_TIxExternalCLKSource,
TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
uint8_t ICFilter);
void TIM2_ETRClockMode1Config(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
uint8_t ExtTRGFilter);
void TIM2_ETRClockMode2Config(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
uint8_t ExtTRGFilter);
/* Synchronization management *************************************************/
void TIM2_SelectInputTrigger(TIM2_TRGSelection_TypeDef TIM2_InputTriggerSource);
void TIM2_SelectOutputTrigger(TIM2_TRGOSource_TypeDef TIM2_TRGOSource);
void TIM2_SelectSlaveMode(TIM2_SlaveMode_TypeDef TIM2_SlaveMode);
void TIM2_SelectMasterSlaveMode(FunctionalState NewState);
void TIM2_ETRConfig(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
uint8_t ExtTRGFilter);
/* Specific interface management **********************************************/
void TIM2_EncoderInterfaceConfig(TIM2_EncoderMode_TypeDef TIM2_EncoderMode,
TIM2_ICPolarity_TypeDef TIM2_IC1Polarity,
TIM2_ICPolarity_TypeDef TIM2_IC2Polarity);
void TIM2_SelectHallSensor(FunctionalState NewState);
#endif /* __STM8L15x_TIM2_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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firmware/inc/stm8l151x/inc/stm8l15x_tim3.h Normal file
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/**
******************************************************************************
* @file stm8l15x_tim3.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the TIM3 firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_TIM3_H
#define __STM8L15x_TIM3_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @defgroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup TIM3
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIM3_Exported_Types
* @{
*/
/** @defgroup TIM3_Forced_Action
* @{
*/
typedef enum
{
TIM3_ForcedAction_Active = ((uint8_t)0x50), /*!< Output Reference is forced low */
TIM3_ForcedAction_Inactive = ((uint8_t)0x40) /*!< Output Reference is forced high */
}
TIM3_ForcedAction_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Prescaler
* @{
*/
typedef enum
{
TIM3_Prescaler_1 = ((uint8_t)0x00), /*!< Time base Prescaler = 1 (No effect)*/
TIM3_Prescaler_2 = ((uint8_t)0x01), /*!< Time base Prescaler = 2 */
TIM3_Prescaler_4 = ((uint8_t)0x02), /*!< Time base Prescaler = 4 */
TIM3_Prescaler_8 = ((uint8_t)0x03), /*!< Time base Prescaler = 8 */
TIM3_Prescaler_16 = ((uint8_t)0x04), /*!< Time base Prescaler = 16 */
TIM3_Prescaler_32 = ((uint8_t)0x05), /*!< Time base Prescaler = 32 */
TIM3_Prescaler_64 = ((uint8_t)0x06), /*!< Time base Prescaler = 64 */
TIM3_Prescaler_128 = ((uint8_t)0x07) /*!< Time base Prescaler = 128 */
}TIM3_Prescaler_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_OCMode
* @{
*/
typedef enum
{
TIM3_OCMode_Timing = ((uint8_t)0x00), /*!< Timing (Frozen) Mode*/
TIM3_OCMode_Active = ((uint8_t)0x10), /*!< Active Mode*/
TIM3_OCMode_Inactive = ((uint8_t)0x20), /*!< Inactive Mode*/
TIM3_OCMode_Toggle = ((uint8_t)0x30), /*!< Toggle Mode*/
TIM3_OCMode_PWM1 = ((uint8_t)0x60), /*!< PWM Mode 1*/
TIM3_OCMode_PWM2 = ((uint8_t)0x70) /*!< PWM Mode 2*/
}TIM3_OCMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_OnePulseMode
* @{
*/
typedef enum
{
TIM3_OPMode_Single = ((uint8_t)0x01), /*!< Single one Pulse mode (OPM Active) */
TIM3_OPMode_Repetitive = ((uint8_t)0x00) /*!< Repetitive Pulse mode (OPM inactive) */
}TIM3_OPMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Channel
* @{
*/
typedef enum
{
TIM3_Channel_1 = ((uint8_t)0x00), /*!< Channel 1*/
TIM3_Channel_2 = ((uint8_t)0x01) /*!< Channel 2*/
}TIM3_Channel_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_CounterMode
* @{
*/
typedef enum
{
TIM3_CounterMode_Up = ((uint8_t)0x00), /*!< Counter Up Mode */
TIM3_CounterMode_Down = ((uint8_t)0x10), /*!< Counter Down Mode */
TIM3_CounterMode_CenterAligned1 = ((uint8_t)0x20), /*!< Counter Central aligned Mode 1 */
TIM3_CounterMode_CenterAligned2 = ((uint8_t)0x40), /*!< Counter Central aligned Mode 2 */
TIM3_CounterMode_CenterAligned3 = ((uint8_t)0x60) /*!< Counter Central aligned Mode 3 */
}TIM3_CounterMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Output_Compare_Polarity
* @{
*/
typedef enum
{
TIM3_OCPolarity_High = ((uint8_t)0x00), /*!< Output compare polarity = High */
TIM3_OCPolarity_Low = ((uint8_t)0x01) /*!< Output compare polarity = Low */
}TIM3_OCPolarity_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Output_State
* @{
*/
typedef enum
{
TIM3_OutputState_Disable = ((uint8_t)0x00), /*!< Output compare State disabled
(channel output disabled) */
TIM3_OutputState_Enable = ((uint8_t)0x01) /*!< Output compare State enabled
(channel output enabled) */
}TIM3_OutputState_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Break_State
* @{
*/
typedef enum
{
TIM3_BreakState_Disable = ((uint8_t)0x00), /*!< Break State disabled (break option disabled) */
TIM3_BreakState_Enable = ((uint8_t)0x10) /*!< Break State enabled (break option enabled) */
}TIM3_BreakState_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Break_Polarity
* @{
*/
typedef enum
{
TIM3_BreakPolarity_High = ((uint8_t)0x20), /*!< if Break, channel polarity = High */
TIM3_BreakPolarity_Low = ((uint8_t)0x00) /*!< if Break, channel polarity = Low */
}TIM3_BreakPolarity_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Automatic_Output
* @{
*/
typedef enum
{
TIM3_AutomaticOutput_Enable = ((uint8_t)0x40), /*!< Automatic Output option enabled */
TIM3_AutomaticOutput_Disable = ((uint8_t)0x00) /*!< Automatic Output option disabled */
}TIM3_AutomaticOutput_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Lock_Level
* @{
*/
typedef enum
{
TIM3_LockLevel_Off = ((uint8_t)0x00), /*!< Lock option disabled */
TIM3_LockLevel_1 = ((uint8_t)0x01), /*!< Select Lock Level 1 */
TIM3_LockLevel_2 = ((uint8_t)0x02), /*!< Select Lock Level 2 */
TIM3_LockLevel_3 = ((uint8_t)0x03) /*!< Select Lock Level 3 */
}TIM3_LockLevel_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_OSSI_State
* @{
*/
typedef enum
{
TIM3_OSSIState_Enable = ((uint8_t)0x04), /*!< Off-State Selection for Idle mode enabled */
TIM3_OSSIState_Disable = ((uint8_t)0x00) /*!< Off-State Selection for Idle mode disabled */
}TIM3_OSSIState_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Output_Compare_Idle_state
* @{
*/
typedef enum
{
TIM3_OCIdleState_Reset = ((uint8_t)0x00), /*!< Output Compare Idle state = Reset */
TIM3_OCIdleState_Set = ((uint8_t)0x01) /*!< Output Compare Idle state = Set */
}TIM3_OCIdleState_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Input_Capture_Polarity
* @{
*/
typedef enum
{
TIM3_ICPolarity_Rising = ((uint8_t)0x00), /*!< Input Capture on Rising Edge*/
TIM3_ICPolarity_Falling = ((uint8_t)0x01) /*!< Input Capture on Falling Edge*/
}TIM3_ICPolarity_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Input_Capture_Selection
* @{
*/
typedef enum
{
TIM3_ICSelection_DirectTI = ((uint8_t)0x01), /*!< Input Capture mapped on the direct input*/
TIM3_ICSelection_IndirectTI = ((uint8_t)0x02), /*!< Input Capture mapped on the indirect input*/
TIM3_ICSelection_TRGI = ((uint8_t)0x03) /*!< Input Capture mapped on the Trigger Input*/
}TIM3_ICSelection_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Input_Capture_Prescaler
* @{
*/
typedef enum
{
TIM3_ICPSC_DIV1 = ((uint8_t)0x00), /*!< Input Capture Prescaler = 1 (one capture every 1 event) */
TIM3_ICPSC_DIV2 = ((uint8_t)0x04), /*!< Input Capture Prescaler = 2 (one capture every 2 events) */
TIM3_ICPSC_DIV4 = ((uint8_t)0x08), /*!< Input Capture Prescaler = 4 (one capture every 4 events) */
TIM3_ICPSC_DIV8 = ((uint8_t)0x0C) /*!< Input Capture Prescaler = 8 (one capture every 8 events) */
}TIM3_ICPSC_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Interrupts
* @{
*/
typedef enum
{
TIM3_IT_Update = ((uint8_t)0x01), /*!< Update Interrupt*/
TIM3_IT_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Interrupt*/
TIM3_IT_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Interrupt*/
TIM3_IT_Trigger = ((uint8_t)0x40), /*!< Trigger Interrupt*/
TIM3_IT_Break = ((uint8_t)0x80) /*!< Break Interrupt*/
}TIM3_IT_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_External_Trigger_Prescaler
* @{
*/
typedef enum
{
TIM3_ExtTRGPSC_OFF = ((uint8_t)0x00), /*!< No External Trigger prescaler */
TIM3_ExtTRGPSC_DIV2 = ((uint8_t)0x10), /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */
TIM3_ExtTRGPSC_DIV4 = ((uint8_t)0x20), /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */
TIM3_ExtTRGPSC_DIV8 = ((uint8_t)0x30) /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */
}TIM3_ExtTRGPSC_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Internal_Trigger_Selection
* @{
*/
typedef enum
{
TIM3_TRGSelection_TIM4 = ((uint8_t)0x00), /*!< TRIG Input source = TIM TRIG Output */
TIM3_TRGSelection_TIM1 = ((uint8_t)0x10), /*!< TRIG Input source = TIM TRIG Output */
TIM3_TRGSelection_TIM5 = ((uint8_t)0x20), /*!< TRIG Input source = TIM TRIG Output */
TIM3_TRGSelection_TIM2 = ((uint8_t)0x30), /*!< TRIG Input source = TIM TRIG Output */
TIM3_TRGSelection_TI1F_ED = ((uint8_t)0x40), /*!< TRIG Input source = TI1F_ED (TI1 Edge Detector) */
TIM3_TRGSelection_TI1FP1 = ((uint8_t)0x50), /*!< TRIG Input source = TI1FP1 (Filtered Timer Input 1) */
TIM3_TRGSelection_TI2FP2 = ((uint8_t)0x60), /*!< TRIG Input source = TI2FP2 (Filtered Timer Input 2) */
TIM3_TRGSelection_ETRF = ((uint8_t)0x70) /*!< TRIG Input source = ETRF (External Trigger Input ) */
}TIM3_TRGSelection_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_TI_External_Clock_Source
* @{
*/
typedef enum
{
TIM3_TIxExternalCLK1Source_TI1ED = ((uint8_t)0x40), /*!< External Clock mode 1 source = TI1ED */
TIM3_TIxExternalCLK1Source_TI1 = ((uint8_t)0x50), /*!< External Clock mode 1 source = TI1 */
TIM3_TIxExternalCLK1Source_TI2 = ((uint8_t)0x60) /*!< External Clock mode 1 source = TI2 */
}TIM3_TIxExternalCLK1Source_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_External_Trigger_Polarity
* @{
*/
typedef enum
{
TIM3_ExtTRGPolarity_Inverted = ((uint8_t)0x80), /*!< External Trigger Polarity = inverted */
TIM3_ExtTRGPolarity_NonInverted = ((uint8_t)0x00) /*!< External Trigger Polarity = non inverted */
}TIM3_ExtTRGPolarity_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Prescaler_Reload_Mode
* @{
*/
typedef enum
{
TIM3_PSCReloadMode_Update = ((uint8_t)0x00), /*!< Prescaler value is reloaded at every update*/
TIM3_PSCReloadMode_Immediate = ((uint8_t)0x01) /*!< Prescaler value is reloaded immediatly*/
}TIM3_PSCReloadMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Encoder_Mode
* @{
*/
typedef enum
{
TIM3_EncoderMode_TI1 = ((uint8_t)0x01), /*!< Encoder mode 1*/
TIM3_EncoderMode_TI2 = ((uint8_t)0x02), /*!< Encoder mode 2*/
TIM3_EncoderMode_TI12 = ((uint8_t)0x03) /*!< Encoder mode 3*/
}TIM3_EncoderMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Event_Source
* @{
*/
typedef enum
{
TIM3_EventSource_Update = ((uint8_t)0x01), /*!< Update Event*/
TIM3_EventSource_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Event*/
TIM3_EventSource_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Event*/
TIM3_EventSource_Trigger = ((uint8_t)0x40), /*!< Trigger Event*/
TIM3_EventSource_Break = ((uint8_t)0x80) /*!< Break Event*/
}TIM3_EventSource_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Update_Source
* @{
*/
typedef enum
{
TIM3_UpdateSource_Global = ((uint8_t)0x00), /*!< Global Update request source */
TIM3_UpdateSource_Regular = ((uint8_t)0x01) /*!< Regular Update request source */
}TIM3_UpdateSource_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Trigger_Output_Source
* @{
*/
typedef enum
{
TIM3_TRGOSource_Reset = ((uint8_t)0x00), /*!< Trigger Output source = Reset*/
TIM3_TRGOSource_Enable = ((uint8_t)0x10), /*!< Trigger Output source = TIM3 is enabled*/
TIM3_TRGOSource_Update = ((uint8_t)0x20), /*!< Trigger Output source = Update event*/
TIM3_TRGOSource_OC1 = ((uint8_t)0x30), /*!< Trigger Output source = output compare channel1 */
TIM3_TRGOSource_OC1REF = ((uint8_t)0x40), /*!< Trigger Output source = output compare channel 1 reference */
TIM3_TRGOSource_OC2REF = ((uint8_t)0x50) /*!< Trigger Output source = output compare channel 2 reference */
}TIM3_TRGOSource_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Slave_Mode
* @{
*/
typedef enum
{
TIM3_SlaveMode_Reset = ((uint8_t)0x04), /*!< Slave Mode Selection = Reset*/
TIM3_SlaveMode_Gated = ((uint8_t)0x05), /*!< Slave Mode Selection = Gated*/
TIM3_SlaveMode_Trigger = ((uint8_t)0x06), /*!< Slave Mode Selection = Trigger*/
TIM3_SlaveMode_External1 = ((uint8_t)0x07) /*!< Slave Mode Selection = External 1*/
}TIM3_SlaveMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_Flags
* @{
*/
typedef enum
{
TIM3_FLAG_Update = ((uint16_t)0x0001), /*!< Update Flag */
TIM3_FLAG_CC1 = ((uint16_t)0x0002), /*!< Capture compare 1 Flag */
TIM3_FLAG_CC2 = ((uint16_t)0x0004), /*!< Capture compare 2 Flag */
TIM3_FLAG_Trigger = ((uint16_t)0x0040), /*!< Trigger Flag */
TIM3_FLAG_Break = ((uint16_t)0x0080), /*!< Break Flag */
TIM3_FLAG_CC1OF = ((uint16_t)0x0200), /*!< Capture compare 1 over capture Flag */
TIM3_FLAG_CC2OF = ((uint16_t)0x0400) /*!< Capture compare 2 over capture Flag */
}TIM3_FLAG_TypeDef;
/**
* @}
*/
/** @defgroup TIM3_DMA_Source_Requests
* @{
*/
typedef enum
{
TIM3_DMASource_Update = ((uint8_t)0x01), /*!< TIM3 DMA Update Request*/
TIM3_DMASource_CC1 = ((uint8_t)0x02),
TIM3_DMASource_CC2 = ((uint8_t)0x04)
}TIM3_DMASource_TypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup TIM3_Exported_Macros
* @{
*/
/**
* @brief Macro used by the assert function to check the different functions parameters.
*/
/**
* @brief Macro TIM3 Forced Action
*/
#define IS_TIM3_FORCED_ACTION(ACTION) \
(((ACTION) == TIM3_ForcedAction_Active) || \
((ACTION) == TIM3_ForcedAction_Inactive))
/**
* @brief Macro TIM3 Prescaler
*/
#define IS_TIM3_PRESCALER(PRESCALER) \
(((PRESCALER) == TIM3_Prescaler_1) || \
((PRESCALER) == TIM3_Prescaler_2) || \
((PRESCALER) == TIM3_Prescaler_4) || \
((PRESCALER) == TIM3_Prescaler_8) || \
((PRESCALER) == TIM3_Prescaler_16) || \
((PRESCALER) == TIM3_Prescaler_32) || \
((PRESCALER) == TIM3_Prescaler_64) || \
((PRESCALER) == TIM3_Prescaler_128))
/**
* @brief Macro TIM3 Output Compare and PWM modes
*/
#define IS_TIM3_OC_MODE(MODE) \
(((MODE) == TIM3_OCMode_Timing) || \
((MODE) == TIM3_OCMode_Active) || \
((MODE) == TIM3_OCMode_Inactive) || \
((MODE) == TIM3_OCMode_Toggle) || \
((MODE) == TIM3_OCMode_PWM1) || \
((MODE) == TIM3_OCMode_PWM2))
#define IS_TIM3_OCM(MODE) \
(((MODE) == TIM3_OCMode_Timing) || \
((MODE) == TIM3_OCMode_Active) || \
((MODE) == TIM3_OCMode_Inactive) || \
((MODE) == TIM3_OCMode_Toggle) || \
((MODE) == TIM3_OCMode_PWM1) || \
((MODE) == TIM3_OCMode_PWM2) || \
((MODE) == (uint8_t)TIM3_ForcedAction_Active) || \
((MODE) == (uint8_t)TIM3_ForcedAction_Inactive))
/**
* @brief Macro TIM3 One Pulse Mode
*/
#define IS_TIM3_OPM_MODE(MODE) \
(((MODE) == TIM3_OPMode_Single) || \
((MODE) == TIM3_OPMode_Repetitive))
/**
* @brief Macro TIM3 Channel
*/
#define IS_TIM3_CHANNEL(CHANNEL) \
(((CHANNEL) == TIM3_Channel_1) || \
((CHANNEL) == TIM3_Channel_2) )
/**
* @brief Macro TIM3 Counter Mode
*/
#define IS_TIM3_COUNTER_MODE(MODE) \
(((MODE) == TIM3_CounterMode_Up) || \
((MODE) == TIM3_CounterMode_Down) || \
((MODE) == TIM3_CounterMode_CenterAligned1) || \
((MODE) == TIM3_CounterMode_CenterAligned2) || \
((MODE) == TIM3_CounterMode_CenterAligned3))
/**
* @brief Macro TIM3 Output Compare Polarity
*/
#define IS_TIM3_OC_POLARITY(POLARITY) \
(((POLARITY) == TIM3_OCPolarity_High) || \
((POLARITY) == TIM3_OCPolarity_Low))
/**
* @brief Macro TIM3 Output Compare states
*/
#define IS_TIM3_OUTPUT_STATE(STATE) \
(((STATE) == TIM3_OutputState_Disable) || \
((STATE) == TIM3_OutputState_Enable))
/**
* @brief Macro Break Input enable/disable
*/
#define IS_TIM3_BREAK_STATE(STATE) \
(((STATE) == TIM3_BreakState_Enable) || \
((STATE) == TIM3_BreakState_Disable))
/**
* @brief Macro Break Polarity
*/
#define IS_TIM3_BREAK_POLARITY(POLARITY) \
(((POLARITY) == TIM3_BreakPolarity_Low) || \
((POLARITY) == TIM3_BreakPolarity_High))
/**
* @brief Macro TIM3 AOE Bit Set/Reset
*/
#define IS_TIM3_AUTOMATIC_OUTPUT_STATE(STATE) \
(((STATE) == TIM3_AutomaticOutput_Enable) || \
((STATE) == TIM3_AutomaticOutput_Disable))
/**
* @brief Macro Lock levels
*/
#define IS_TIM3_LOCK_LEVEL(LEVEL) \
(((LEVEL) == TIM3_LockLevel_Off) || \
((LEVEL) == TIM3_LockLevel_1) || \
((LEVEL) == TIM3_LockLevel_2) || \
((LEVEL) == TIM3_LockLevel_3))
/**
* @brief Macro OSSI: Off-State Selection for Idle mode states
*/
#define IS_TIM3_OSSI_STATE(STATE) \
(((STATE) == TIM3_OSSIState_Enable) || \
((STATE) == TIM3_OSSIState_Disable))
/**
* @brief Macro TIM3 OC IDLE STATE
*/
#define IS_TIM3_OCIDLE_STATE(STATE) \
(((STATE) == TIM3_OCIdleState_Set) || \
((STATE) == TIM3_OCIdleState_Reset))
/**
* @brief Macro TIM3 IC POLARITY
*/
#define IS_TIM3_IC_POLARITY(POLARITY) \
(((POLARITY) == TIM3_ICPolarity_Rising) || \
((POLARITY) == TIM3_ICPolarity_Falling))
/**
* @brief Macro TIM3 IC SELECTION
*/
#define IS_TIM3_IC_SELECTION(SELECTION) \
(((SELECTION) == TIM3_ICSelection_DirectTI) || \
((SELECTION) == TIM3_ICSelection_IndirectTI) || \
((SELECTION) == TIM3_ICSelection_TRGI))
/**
* @brief Macro TIM3 IC PRESCALER
*/
#define IS_TIM3_IC_PRESCALER(PRESCALER) \
(((PRESCALER) == TIM3_ICPSC_DIV1) || \
((PRESCALER) == TIM3_ICPSC_DIV2) || \
((PRESCALER) == TIM3_ICPSC_DIV4) || \
((PRESCALER) == TIM3_ICPSC_DIV8))
/**
* @brief Macro TIM3 Input Capture Filter Value
*/
#define IS_TIM3_IC_FILTER(ICFILTER) \
((ICFILTER) <= 0x0F)
/**
* @brief Macro TIM3 Interrupts
*/
#define IS_TIM3_IT(IT) \
((IT) != 0x00)
#define IS_TIM3_GET_IT(IT) \
(((IT) == TIM3_IT_Update) || \
((IT) == TIM3_IT_CC1) || \
((IT) == TIM3_IT_CC2) || \
((IT) == TIM3_IT_Trigger) || \
((IT) == TIM3_IT_Break))
/**
* @brief Macro TIM3 external trigger prescaler
*/
#define IS_TIM3_EXT_PRESCALER(PRESCALER) \
(((PRESCALER) == TIM3_ExtTRGPSC_OFF) || \
((PRESCALER) == TIM3_ExtTRGPSC_DIV2) || \
((PRESCALER) == TIM3_ExtTRGPSC_DIV4) || \
((PRESCALER) == TIM3_ExtTRGPSC_DIV8))
/**
* @brief Macro TIM3 Trigger Selection
*/
#define IS_TIM3_TRIGGER_SELECTION(SELECTION) \
(((SELECTION) == TIM3_TRGSelection_TI1F_ED) || \
((SELECTION) == TIM3_TRGSelection_TI1FP1) || \
((SELECTION) == TIM3_TRGSelection_TI2FP2) || \
((SELECTION) == TIM3_TRGSelection_TIM4) || \
((SELECTION) == TIM3_TRGSelection_TIM1) || \
((SELECTION) == TIM3_TRGSelection_TIM5) || \
((SELECTION) == TIM3_TRGSelection_TIM2) || \
((SELECTION) == TIM3_TRGSelection_ETRF))
#define IS_TIM3_TIX_TRIGGER_SELECTION(SELECTION) \
(((SELECTION) == TIM3_TRGSelection_TI1F_ED) || \
((SELECTION) == TIM3_TRGSelection_TI1FP1) || \
((SELECTION) == TIM3_TRGSelection_TI2FP2))
/**
* @brief Macro TIM3 TIx external Clock Selection
*/
#define IS_TIM3_TIXCLK_SOURCE(SOURCE) \
(((SOURCE) == TIM3_TIxExternalCLK1Source_TI1ED) || \
((SOURCE) == TIM3_TIxExternalCLK1Source_TI2) || \
((SOURCE) == TIM3_TIxExternalCLK1Source_TI1))
/**
* @brief Macro TIM3 Trigger Polarity
*/
#define IS_TIM3_EXT_POLARITY(POLARITY) \
(((POLARITY) == TIM3_ExtTRGPolarity_Inverted) || \
((POLARITY) == TIM3_ExtTRGPolarity_NonInverted))
/**
* @brief Macro TIM3 External Trigger Filter
*/
#define IS_TIM3_EXT_FILTER(EXTFILTER) \
((EXTFILTER) <= 0x0F)
/**
* @brief Macro TIM3 Prescaler Reload
*/
#define IS_TIM3_PRESCALER_RELOAD(RELOAD) \
(((RELOAD) == TIM3_PSCReloadMode_Update) || \
((RELOAD) == TIM3_PSCReloadMode_Immediate))
/**
* @brief Macro TIM3 encoder mode
*/
#define IS_TIM3_ENCODER_MODE(MODE) \
(((MODE) == TIM3_EncoderMode_TI1) || \
((MODE) == TIM3_EncoderMode_TI2) || \
((MODE) == TIM3_EncoderMode_TI12))
/**
* @brief Macro TIM3 event source
*/
#define IS_TIM3_EVENT_SOURCE(SOURCE) \
((((SOURCE) & (uint8_t)0x18) == 0x00) && ((SOURCE) != 0x00))
/**
* @brief Macro TIM3 update source
*/
#define IS_TIM3_UPDATE_SOURCE(SOURCE) \
(((SOURCE) == TIM3_UpdateSource_Global) || \
((SOURCE) == TIM3_UpdateSource_Regular))
/**
* @brief Macro TIM3 TRGO source
*/
#define IS_TIM3_TRGO_SOURCE(SOURCE) \
(((SOURCE) == TIM3_TRGOSource_Reset) || \
((SOURCE) == TIM3_TRGOSource_Enable) || \
((SOURCE) == TIM3_TRGOSource_Update) || \
((SOURCE) == TIM3_TRGOSource_OC1) || \
((SOURCE) == TIM3_TRGOSource_OC1REF) || \
((SOURCE) == TIM3_TRGOSource_OC2REF))
/**
* @brief Macro TIM3 Slave mode
*/
#define IS_TIM3_SLAVE_MODE(MODE) \
(((MODE) == TIM3_SlaveMode_Reset) || \
((MODE) == TIM3_SlaveMode_Gated) || \
((MODE) == TIM3_SlaveMode_Trigger) || \
((MODE) == TIM3_SlaveMode_External1))
/**
* @brief Macro TIM3 Flags
*/
#define IS_TIM3_GET_FLAG(FLAG) \
(((FLAG) == TIM3_FLAG_Update) || \
((FLAG) == TIM3_FLAG_CC1) || \
((FLAG) == TIM3_FLAG_CC2) || \
((FLAG) == TIM3_FLAG_Trigger) || \
((FLAG) == TIM3_FLAG_Break) || \
((FLAG) == TIM3_FLAG_CC1OF) || \
((FLAG) == TIM3_FLAG_CC2OF))
#define IS_TIM3_CLEAR_FLAG(FLAG) \
((((FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
/**
* @brief Macro TIM3 DMA sources
*/
#define IS_TIM3_DMA_SOURCE(SOURCE) \
(((SOURCE) == TIM3_DMASource_Update) || \
((SOURCE) == TIM3_DMASource_CC1) || \
((SOURCE) == TIM3_DMASource_CC2))
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* TimeBase management ********************************************************/
void TIM3_DeInit(void);
void TIM3_TimeBaseInit(TIM3_Prescaler_TypeDef TIM3_Prescaler,
TIM3_CounterMode_TypeDef TIM3_CounterMode,
uint16_t TIM3_Period);
void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler,
TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode);
void TIM3_CounterModeConfig(TIM3_CounterMode_TypeDef TIM3_CounterMode);
void TIM3_SetCounter(uint16_t Counter);
void TIM3_SetAutoreload(uint16_t Autoreload);
uint16_t TIM3_GetCounter(void);
TIM3_Prescaler_TypeDef TIM3_GetPrescaler(void);
void TIM3_UpdateDisableConfig(FunctionalState NewState);
void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource);
void TIM3_ARRPreloadConfig(FunctionalState NewState);
void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode);
void TIM3_Cmd(FunctionalState NewState);
/* Output Compare management **************************************************/
void TIM3_OC1Init(TIM3_OCMode_TypeDef TIM3_OCMode,
TIM3_OutputState_TypeDef TIM3_OutputState,
uint16_t TIM3_Pulse,
TIM3_OCPolarity_TypeDef TIM3_OCPolarity,
TIM3_OCIdleState_TypeDef TIM3_OCIdleState);
void TIM3_OC2Init(TIM3_OCMode_TypeDef TIM3_OCMode,
TIM3_OutputState_TypeDef TIM3_OutputState,
uint16_t TIM3_Pulse,
TIM3_OCPolarity_TypeDef TIM3_OCPolarity,
TIM3_OCIdleState_TypeDef TIM3_OCIdleState);
void TIM3_BKRConfig(TIM3_OSSIState_TypeDef TIM3_OSSIState,
TIM3_LockLevel_TypeDef TIM3_LockLevel,
TIM3_BreakState_TypeDef TIM3_BreakState,
TIM3_BreakPolarity_TypeDef TIM3_BreakPolarity,
TIM3_AutomaticOutput_TypeDef TIM3_AutomaticOutput);
void TIM3_CtrlPWMOutputs(FunctionalState NewState);
void TIM3_SelectOCxM(TIM3_Channel_TypeDef TIM3_Channel,
TIM3_OCMode_TypeDef TIM3_OCMode);
void TIM3_SetCompare1(uint16_t Compare);
void TIM3_SetCompare2(uint16_t Compare);
void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction);
void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction);
void TIM3_OC1PreloadConfig(FunctionalState NewState);
void TIM3_OC2PreloadConfig(FunctionalState NewState);
void TIM3_OC1FastConfig(FunctionalState NewState);
void TIM3_OC2FastConfig(FunctionalState NewState);
void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState);
/* Input Capture management ***************************************************/
void TIM3_ICInit(TIM3_Channel_TypeDef TIM3_Channel,
TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
TIM3_ICSelection_TypeDef TIM3_ICSelection,
TIM3_ICPSC_TypeDef TIM3_ICPrescaler,
uint8_t TIM3_ICFilter);
void TIM3_PWMIConfig(TIM3_Channel_TypeDef TIM3_Channel,
TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
TIM3_ICSelection_TypeDef TIM3_ICSelection,
TIM3_ICPSC_TypeDef TIM3_ICPrescaler,
uint8_t TIM3_ICFilter);
uint16_t TIM3_GetCapture1(void);
uint16_t TIM3_GetCapture2(void);
void TIM3_SetIC1Prescaler(TIM3_ICPSC_TypeDef TIM3_IC1Prescaler);
void TIM3_SetIC2Prescaler(TIM3_ICPSC_TypeDef TIM3_IC2Prescaler);
/* Interrupts, DMA and flags management ***************************************/
void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState);
void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource);
FlagStatus TIM3_GetFlagStatus(TIM3_FLAG_TypeDef TIM3_FLAG);
void TIM3_ClearFlag(TIM3_FLAG_TypeDef TIM3_FLAG);
ITStatus TIM3_GetITStatus(TIM3_IT_TypeDef TIM3_IT);
void TIM3_ClearITPendingBit(TIM3_IT_TypeDef TIM3_IT);
void TIM3_DMACmd(TIM3_DMASource_TypeDef TIM3_DMASource, FunctionalState NewState);
void TIM3_SelectCCDMA(FunctionalState NewState);
/* Clocks management **********************************************************/
void TIM3_InternalClockConfig(void);
void TIM3_TIxExternalClockConfig(TIM3_TIxExternalCLK1Source_TypeDef TIM3_TIxExternalCLKSource,
TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
uint8_t ICFilter);
void TIM3_ETRClockMode1Config(TIM3_ExtTRGPSC_TypeDef TIM3_ExtTRGPrescaler,
TIM3_ExtTRGPolarity_TypeDef TIM3_ExtTRGPolarity,
uint8_t ExtTRGFilter);
void TIM3_ETRClockMode2Config(TIM3_ExtTRGPSC_TypeDef TIM3_ExtTRGPrescaler,
TIM3_ExtTRGPolarity_TypeDef TIM3_ExtTRGPolarity,
uint8_t ExtTRGFilter);
/* Synchronization management *************************************************/
void TIM3_SelectInputTrigger(TIM3_TRGSelection_TypeDef TIM3_InputTriggerSource);
void TIM3_SelectOutputTrigger(TIM3_TRGOSource_TypeDef TIM3_TRGOSource);
void TIM3_SelectSlaveMode(TIM3_SlaveMode_TypeDef TIM3_SlaveMode);
void TIM3_SelectMasterSlaveMode(FunctionalState NewState);
void TIM3_ETRConfig(TIM3_ExtTRGPSC_TypeDef TIM3_ExtTRGPrescaler,
TIM3_ExtTRGPolarity_TypeDef TIM3_ExtTRGPolarity,
uint8_t ExtTRGFilter);
/* Specific interface management **********************************************/
void TIM3_EncoderInterfaceConfig(TIM3_EncoderMode_TypeDef TIM3_EncoderMode,
TIM3_ICPolarity_TypeDef TIM3_IC1Polarity,
TIM3_ICPolarity_TypeDef TIM3_IC2Polarity);
void TIM3_SelectHallSensor(FunctionalState NewState);
#endif /* __STM8L15x_TIM3_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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firmware/inc/stm8l151x/inc/stm8l15x_tim4.h Normal file
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/**
******************************************************************************
* @file stm8l15x_tim4.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the TIM4 firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_TIM4_H
#define __STM8L15x_TIM4_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup TIM4
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIM4_Exported_Types
* @{
*/
/** @defgroup TIM4_Prescaler
* @{
*/
typedef enum
{
TIM4_Prescaler_1 = ((uint8_t)0x00), /*!< Time base Prescaler = 1 (No effect)*/
TIM4_Prescaler_2 = ((uint8_t)0x01), /*!< Time base Prescaler = 2 */
TIM4_Prescaler_4 = ((uint8_t)0x02), /*!< Time base Prescaler = 4 */
TIM4_Prescaler_8 = ((uint8_t)0x03), /*!< Time base Prescaler = 8 */
TIM4_Prescaler_16 = ((uint8_t)0x04), /*!< Time base Prescaler = 16 */
TIM4_Prescaler_32 = ((uint8_t)0x05), /*!< Time base Prescaler = 32 */
TIM4_Prescaler_64 = ((uint8_t)0x06), /*!< Time base Prescaler = 64 */
TIM4_Prescaler_128 = ((uint8_t)0x07), /*!< Time base Prescaler = 128 */
TIM4_Prescaler_256 = ((uint8_t)0x08), /*!< Time base Prescaler = 256 */
TIM4_Prescaler_512 = ((uint8_t)0x09), /*!< Time base Prescaler = 512 */
TIM4_Prescaler_1024 = ((uint8_t)0x0A), /*!< Time base Prescaler = 1024 */
TIM4_Prescaler_2048 = ((uint8_t)0x0B), /*!< Time base Prescaler = 2048 */
TIM4_Prescaler_4096 = ((uint8_t)0x0C), /*!< Time base Prescaler = 4096 */
TIM4_Prescaler_8192 = ((uint8_t)0x0D), /*!< Time base Prescaler = 8196 */
TIM4_Prescaler_16384 = ((uint8_t)0x0E), /*!< Time base Prescaler = 16384 */
TIM4_Prescaler_32768 = ((uint8_t)0x0F) /*!< Time base Prescaler = 32768 */
}TIM4_Prescaler_TypeDef;
/**
* @}
*/
/** @defgroup TIM4_One_Pulse_Mode
* @{
*/
typedef enum
{
TIM4_OPMode_Single = ((uint8_t) 0x01), /*!< Single one Pulse mode (OPM Active) */
TIM4_OPMode_Repetitive = ((uint8_t) 0x00) /*!< Repetitive Pulse mode (OPM inactive) */
}TIM4_OPMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM4_Reload_Mode_Prescaler
* @{
*/
typedef enum
{
TIM4_PSCReloadMode_Update = ((uint8_t)0x00), /*!< Prescaler value is reloaded at every update */
TIM4_PSCReloadMode_Immediate = ((uint8_t)0x01) /*!< Prescaler value is reloaded immediatly */
}TIM4_PSCReloadMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM4_Update_Source
* @{
*/
typedef enum
{
TIM4_UpdateSource_Global = ((uint8_t)0x00), /*!< Global Update request source */
TIM4_UpdateSource_Regular = ((uint8_t)0x01) /*!< Regular Update request source */
}TIM4_UpdateSource_TypeDef;
/**
* @}
*/
/** @defgroup TIM4_Event_Source
* @{
*/
typedef enum
{
TIM4_EventSource_Update = ((uint8_t)0x01), /*!< Update Event */
TIM4_EventSource_Trigger = ((uint8_t)0x40) /*!< Trigger Event */
}TIM4_EventSource_TypeDef;
/**
* @}
*/
/** @defgroup TIM4_Trigger_Output_Source
* @{
*/
typedef enum
{
TIM4_TRGOSource_Reset = ((uint8_t)0x00), /*!< Trigger Output source = Reset */
TIM4_TRGOSource_Enable = ((uint8_t)0x10), /*!< Trigger Output source = TIM4 is enabled */
TIM4_TRGOSource_Update = ((uint8_t)0x20) /*!< Trigger Output source = Update event */
}TIM4_TRGOSource_TypeDef;
/**
* @}
*/
/** @defgroup TIM4_Salve_Mode
* @{
*/
typedef enum
{
TIM4_SlaveMode_Disable = ((uint8_t)0x00), /*!< Disable slave mode to clock the prescaler
directly with the internal clock */
TIM4_SlaveMode_Reset = ((uint8_t)0x04), /*!< Slave Mode Selection = Reset*/
TIM4_SlaveMode_Gated = ((uint8_t)0x05), /*!< Slave Mode Selection = Gated*/
TIM4_SlaveMode_Trigger = ((uint8_t)0x06), /*!< Slave Mode Selection = Trigger*/
TIM4_SlaveMode_External1 = ((uint8_t)0x07) /*!< Slave Mode Selection = External 1*/
}TIM4_SlaveMode_TypeDef;
/**
* @}
*/
/** @defgroup TIM4_Flags
* @{
*/
typedef enum
{
TIM4_FLAG_Update = ((uint8_t)0x01), /*!< Update Flag */
TIM4_FLAG_Trigger = ((uint8_t)0x40) /*!< Trigger Flag */
}TIM4_FLAG_TypeDef;
/**
* @}
*/
/** @defgroup TIM4_Interrupts
* @{
*/
typedef enum
{
TIM4_IT_Update = ((uint8_t)0x01), /*!< Update Interrupt*/
TIM4_IT_Trigger = ((uint8_t)0x40) /*!< Trigger Interrupt*/
}TIM4_IT_TypeDef;
/**
* @}
*/
/** @defgroup TIM4_Internal_Trigger_Selection
* @{
*/
typedef enum
{
TIM4_TRGSelection_TIM5 = ((uint8_t)0x00), /*!< TRIG Input source = TIM5 TRIG Output */
TIM4_TRGSelection_TIM1 = ((uint8_t)0x10), /*!< TRIG Input source = TIM1 TRIG Output */
TIM4_TRGSelection_TIM3 = ((uint8_t)0x20), /*!< TRIG Input source = TIM3 TRIG Output */
TIM4_TRGSelection_TIM2 = ((uint8_t)0x30) /*!< TRIG Input source = TIM2 TRIG Output */
}TIM4_TRGSelection_TypeDef;
/**
* @}
*/
/** @defgroup TIM4_DMA_source_requests
* @{
*/
typedef enum
{
TIM4_DMASource_Update = ((uint8_t)0x01) /*!< TIM4 DMA Update Request*/
}TIM4_DMASource_TypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup TIM4_Exported_Macros
* @{
*/
/**
* @brief Macro used by the assert function to check the different functions parameters.
*/
/**
* @brief Macro TIM4 Prescaler
*/
#define IS_TIM4_Prescaler(PRESCALER) \
(((PRESCALER) == TIM4_Prescaler_1) || \
((PRESCALER) == TIM4_Prescaler_2) || \
((PRESCALER) == TIM4_Prescaler_4) || \
((PRESCALER) == TIM4_Prescaler_8) || \
((PRESCALER) == TIM4_Prescaler_16) || \
((PRESCALER) == TIM4_Prescaler_32) || \
((PRESCALER) == TIM4_Prescaler_64) || \
((PRESCALER) == TIM4_Prescaler_128) || \
((PRESCALER) == TIM4_Prescaler_256) || \
((PRESCALER) == TIM4_Prescaler_512) || \
((PRESCALER) == TIM4_Prescaler_1024) || \
((PRESCALER) == TIM4_Prescaler_2048) || \
((PRESCALER) == TIM4_Prescaler_4096) || \
((PRESCALER) == TIM4_Prescaler_8192) || \
((PRESCALER) == TIM4_Prescaler_16384)|| \
((PRESCALER) == TIM4_Prescaler_32768))
/**
* @brief Macro TIM4 One Pulse Mode
*/
#define IS_TIM4_OPM_MODE(MODE) \
(((MODE) == TIM4_OPMode_Single) || \
((MODE) == TIM4_OPMode_Repetitive))
/**
* @brief Macro TIM4 Prescaler reload
*/
#define IS_TIM4_Prescaler_RELOAD(RELOAD) \
(((RELOAD) == TIM4_PSCReloadMode_Update) || \
((RELOAD) == TIM4_PSCReloadMode_Immediate))
/**
* @brief Macro TIM4 Update source
*/
#define IS_TIM4_UPDATE_SOURCE(SOURCE) \
(((SOURCE) == TIM4_UpdateSource_Global) || \
((SOURCE) == TIM4_UpdateSource_Regular))
/**
* @brief Macro TIM4 Event source
*/
#define IS_TIM4_EVENT_SOURCE(SOURCE) \
((((SOURCE) & (uint8_t)0xBE) == 0x00) && \
((SOURCE) != 0x00))
/**
* @brief Macro TIM4 TRGO source
*/
#define IS_TIM4_TRGO_SOURCE(SOURCE) \
(((SOURCE) == TIM4_TRGOSource_Reset) || \
((SOURCE) == TIM4_TRGOSource_Enable)|| \
((SOURCE) == TIM4_TRGOSource_Update))
/**
* @brief Macro TIM4 Slave mode
*/
#define IS_TIM4_SLAVE_MODE(MODE) \
(((MODE) == TIM4_SlaveMode_Disable) || \
((MODE) == TIM4_SlaveMode_Reset) || \
((MODE) == TIM4_SlaveMode_Gated) || \
((MODE) == TIM4_SlaveMode_Trigger) || \
((MODE) == TIM4_SlaveMode_External1))
/**
* @brief Macro TIM4 Flags
*/
#define IS_TIM4_GET_FLAG(FLAG) \
(((FLAG) == TIM4_FLAG_Update) || \
((FLAG) == TIM4_FLAG_Trigger))
#define IS_TIM4_CLEAR_FLAG(FLAG) \
((((FLAG) & (uint8_t)0xBE) == 0x00) && ((FLAG) != 0x00))
/**
* @brief Macro TIM4 interrupts
*/
#define IS_TIM4_IT(IT) \
(((IT) != 0x00) && \
(((uint8_t)(IT) & (uint8_t)(~(uint8_t)(0x41)))== 0x00))
#define IS_TIM4_GET_IT(IT) \
(((IT) == TIM4_IT_Update) || \
((IT) == TIM4_IT_Trigger))
/**
* @brief Macro TIM4 Trigger selection
*/
#define IS_TIM4_TRIGGER_SELECTION(SELECTION) \
(((SELECTION) == TIM4_TRGSelection_TIM5) || \
((SELECTION) == TIM4_TRGSelection_TIM1) || \
((SELECTION) == TIM4_TRGSelection_TIM3) || \
((SELECTION) == TIM4_TRGSelection_TIM2))
/**
* @brief Macro TIM4 DMA sources
*/
#define IS_TIM4_DMA_SOURCE(SOURCE) (((SOURCE) == TIM4_DMASource_Update))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* TimeBase management ********************************************************/
void TIM4_DeInit(void);
void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler,
uint8_t TIM4_Period);
void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler,
TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode);
void TIM4_SetCounter(uint8_t Counter);
void TIM4_SetAutoreload(uint8_t Autoreload);
uint8_t TIM4_GetCounter(void);
TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void);
void TIM4_UpdateDisableConfig(FunctionalState NewState);
void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource);
void TIM4_ARRPreloadConfig(FunctionalState NewState);
void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode);
void TIM4_Cmd(FunctionalState NewState);
/* Interrupts, DMA and flags management ***************************************/
void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState);
void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource);
FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG);
void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG);
ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT);
void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT);
void TIM4_DMACmd(TIM4_DMASource_TypeDef TIM4_DMASource, FunctionalState NewState);
/* Clocks management **********************************************************/
void TIM4_InternalClockConfig(void);
/* Synchronization management *************************************************/
void TIM4_SelectInputTrigger(TIM4_TRGSelection_TypeDef TIM4_InputTriggerSource);
void TIM4_SelectOutputTrigger(TIM4_TRGOSource_TypeDef TIM4_TRGOSource);
void TIM4_SelectSlaveMode(TIM4_SlaveMode_TypeDef TIM4_SlaveMode);
void TIM4_SelectMasterSlaveMode(FunctionalState NewState);
#endif /* __STM8L15x_TIM4_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_tim5.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the TIM5 firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_TIM5_H
#define __STM8L15x_TIM5_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup TIM5
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIM5_Exported_Types
* @{
*/
/** @defgroup TIM5_Forced_Action
* @{
*/
typedef enum
{
TIM5_ForcedAction_Active = ((uint8_t)0x50), /*!< Output Reference is forced low */
TIM5_ForcedAction_Inactive = ((uint8_t)0x40) /*!< Output Reference is forced high */
}
TIM5_ForcedAction_TypeDef;
#define IS_TIM5_FORCED_ACTION(ACTION) (((ACTION) == TIM5_ForcedAction_Active) || \
((ACTION) == TIM5_ForcedAction_Inactive))
/**
* @}
*/
/** @defgroup TIM5_Prescaler
* @{
*/
typedef enum
{
TIM5_Prescaler_1 = ((uint8_t)0x00), /*!< Time base Prescaler = 1 (No effect)*/
TIM5_Prescaler_2 = ((uint8_t)0x01), /*!< Time base Prescaler = 2 */
TIM5_Prescaler_4 = ((uint8_t)0x02), /*!< Time base Prescaler = 4 */
TIM5_Prescaler_8 = ((uint8_t)0x03), /*!< Time base Prescaler = 8 */
TIM5_Prescaler_16 = ((uint8_t)0x04), /*!< Time base Prescaler = 16 */
TIM5_Prescaler_32 = ((uint8_t)0x05), /*!< Time base Prescaler = 32 */
TIM5_Prescaler_64 = ((uint8_t)0x06), /*!< Time base Prescaler = 64 */
TIM5_Prescaler_128 = ((uint8_t)0x07) /*!< Time base Prescaler = 128 */
}TIM5_Prescaler_TypeDef;
#define IS_TIM5_PRESCALER(PRESCALER) (((PRESCALER) == TIM5_Prescaler_1) || \
((PRESCALER) == TIM5_Prescaler_2) || \
((PRESCALER) == TIM5_Prescaler_4) || \
((PRESCALER) == TIM5_Prescaler_8) || \
((PRESCALER) == TIM5_Prescaler_16) || \
((PRESCALER) == TIM5_Prescaler_32) || \
((PRESCALER) == TIM5_Prescaler_64) || \
((PRESCALER) == TIM5_Prescaler_128))
/**
* @}
*/
/** @defgroup TIM5_OCMode
* @{
*/
typedef enum
{
TIM5_OCMode_Timing = ((uint8_t)0x00), /*!< Timing (Frozen) Mode*/
TIM5_OCMode_Active = ((uint8_t)0x10), /*!< Active Mode*/
TIM5_OCMode_Inactive = ((uint8_t)0x20), /*!< Inactive Mode*/
TIM5_OCMode_Toggle = ((uint8_t)0x30), /*!< Toggle Mode*/
TIM5_OCMode_PWM1 = ((uint8_t)0x60), /*!< PWM Mode 1*/
TIM5_OCMode_PWM2 = ((uint8_t)0x70) /*!< PWM Mode 2*/
}TIM5_OCMode_TypeDef;
#define IS_TIM5_OC_MODE(MODE) (((MODE) == TIM5_OCMode_Timing) || \
((MODE) == TIM5_OCMode_Active) || \
((MODE) == TIM5_OCMode_Inactive) || \
((MODE) == TIM5_OCMode_Toggle) || \
((MODE) == TIM5_OCMode_PWM1) || \
((MODE) == TIM5_OCMode_PWM2))
#define IS_TIM5_OCM(MODE) (((MODE) == TIM5_OCMode_Timing) || \
((MODE) == TIM5_OCMode_Active) || \
((MODE) == TIM5_OCMode_Inactive) || \
((MODE) == TIM5_OCMode_Toggle) || \
((MODE) == TIM5_OCMode_PWM1) || \
((MODE) == TIM5_OCMode_PWM2) || \
((MODE) == (uint8_t)TIM5_ForcedAction_Active) || \
((MODE) == (uint8_t)TIM5_ForcedAction_Inactive))
/**
* @}
*/
/** @defgroup TIM5_OnePulseMode
* @{
*/
typedef enum
{
TIM5_OPMode_Single = ((uint8_t)0x01), /*!< Single one Pulse mode (OPM Active) */
TIM5_OPMode_Repetitive = ((uint8_t)0x00) /*!< Repetitive Pulse mode (OPM inactive) */
}TIM5_OPMode_TypeDef;
#define IS_TIM5_OPM_MODE(MODE) (((MODE) == TIM5_OPMode_Single) || \
((MODE) == TIM5_OPMode_Repetitive))
/**
* @}
*/
/** @defgroup TIM5_Channel
* @{
*/
typedef enum
{
TIM5_Channel_1 = ((uint8_t)0x00), /*!< Channel 1*/
TIM5_Channel_2 = ((uint8_t)0x01) /*!< Channel 2*/
}TIM5_Channel_TypeDef;
#define IS_TIM5_CHANNEL(CHANNEL) (((CHANNEL) == TIM5_Channel_1) || \
((CHANNEL) == TIM5_Channel_2) )
/**
* @}
*/
/** @defgroup TIM5_CounterMode
* @{
*/
typedef enum
{
TIM5_CounterMode_Up = ((uint8_t)0x00), /*!< Counter Up Mode */
TIM5_CounterMode_Down = ((uint8_t)0x10), /*!< Counter Down Mode */
TIM5_CounterMode_CenterAligned1 = ((uint8_t)0x20), /*!< Counter Central aligned Mode 1 */
TIM5_CounterMode_CenterAligned2 = ((uint8_t)0x40), /*!< Counter Central aligned Mode 2 */
TIM5_CounterMode_CenterAligned3 = ((uint8_t)0x60) /*!< Counter Central aligned Mode 3 */
}TIM5_CounterMode_TypeDef;
#define IS_TIM5_COUNTER_MODE(MODE) (((MODE) == TIM5_CounterMode_Up) || \
((MODE) == TIM5_CounterMode_Down) || \
((MODE) == TIM5_CounterMode_CenterAligned1) || \
((MODE) == TIM5_CounterMode_CenterAligned2) || \
((MODE) == TIM5_CounterMode_CenterAligned3))
/**
* @}
*/
/** @defgroup TIM5_Output_Compare_Polarity
* @{
*/
typedef enum
{
TIM5_OCPolarity_High = ((uint8_t)0x00), /*!< Output compare polarity = High */
TIM5_OCPolarity_Low = ((uint8_t)0x01) /*!< Output compare polarity = Low */
}TIM5_OCPolarity_TypeDef;
#define IS_TIM5_OC_POLARITY(POLARITY) (((POLARITY) == TIM5_OCPolarity_High) || \
((POLARITY) == TIM5_OCPolarity_Low))
/**
* @}
*/
/** @defgroup TIM5_Output_State
* @{
*/
typedef enum
{
TIM5_OutputState_Disable = ((uint8_t)0x00), /*!< Output compare State disabled (channel output disabled) */
TIM5_OutputState_Enable = ((uint8_t)0x01) /*!< Output compare State enabled (channel output enabled) */
}TIM5_OutputState_TypeDef;
#define IS_TIM5_OUTPUT_STATE(STATE) (((STATE) == TIM5_OutputState_Disable) || \
((STATE) == TIM5_OutputState_Enable))
/**
* @}
*/
/** @defgroup TIM5_Break_State
* @{
*/
typedef enum
{
TIM5_BreakState_Disable = ((uint8_t)0x00), /*!< Break State disabled (break option disabled) */
TIM5_BreakState_Enable = ((uint8_t)0x10) /*!< Break State enabled (break option enabled) */
}TIM5_BreakState_TypeDef;
#define IS_TIM5_BREAK_STATE(STATE) (((STATE) == TIM5_BreakState_Enable) || \
((STATE) == TIM5_BreakState_Disable))
/**
* @}
*/
/** @defgroup TIM5_Break_Polarity
* @{
*/
typedef enum
{
TIM5_BreakPolarity_High = ((uint8_t)0x20), /*!< if Break, channel polarity = High */
TIM5_BreakPolarity_Low = ((uint8_t)0x00) /*!< if Break, channel polarity = Low */
}TIM5_BreakPolarity_TypeDef;
#define IS_TIM5_BREAK_POLARITY(POLARITY) \
(((POLARITY) == TIM5_BreakPolarity_Low) || \
((POLARITY) == TIM5_BreakPolarity_High))
/**
* @}
*/
/** @defgroup TIM5_Automatic_Output
* @{
*/
typedef enum
{
TIM5_AutomaticOutput_Enable = ((uint8_t)0x40), /*!< Automatic Output option enabled */
TIM5_AutomaticOutput_Disable = ((uint8_t)0x00) /*!< Automatic Output option disabled */
}TIM5_AutomaticOutput_TypeDef;
#define IS_TIM5_AUTOMATIC_OUTPUT_STATE(STATE) \
(((STATE) == TIM5_AutomaticOutput_Enable) || \
((STATE) == TIM5_AutomaticOutput_Disable))
/**
* @}
*/
/** @defgroup TIM5_Lock_Level
* @{
*/
typedef enum
{
TIM5_LockLevel_Off = ((uint8_t)0x00), /*!< Lock option disabled */
TIM5_LockLevel_1 = ((uint8_t)0x01), /*!< Select Lock Level 1 */
TIM5_LockLevel_2 = ((uint8_t)0x02), /*!< Select Lock Level 2 */
TIM5_LockLevel_3 = ((uint8_t)0x03) /*!< Select Lock Level 3 */
}TIM5_LockLevel_TypeDef;
#define IS_TIM5_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM5_LockLevel_Off) || \
((LEVEL) == TIM5_LockLevel_1) || \
((LEVEL) == TIM5_LockLevel_2) || \
((LEVEL) == TIM5_LockLevel_3))
/**
* @}
*/
/** @defgroup TIM5_OSSI_State
* @{
*/
typedef enum
{
TIM5_OSSIState_Enable = ((uint8_t)0x04), /*!< Off-State Selection for Idle mode enabled */
TIM5_OSSIState_Disable = ((uint8_t)0x00) /*!< Off-State Selection for Idle mode disabled */
}TIM5_OSSIState_TypeDef;
#define IS_TIM5_OSSI_STATE(STATE) \
(((STATE) == TIM5_OSSIState_Enable) || \
((STATE) == TIM5_OSSIState_Disable))
/**
* @}
*/
/** @defgroup TIM5_Output_Compare_Idle_state
* @{
*/
typedef enum
{
TIM5_OCIdleState_Reset = ((uint8_t)0x00), /*!< Output Compare Idle state = Reset */
TIM5_OCIdleState_Set = ((uint8_t)0x01) /*!< Output Compare Idle state = Set */
}TIM5_OCIdleState_TypeDef;
#define IS_TIM5_OCIDLE_STATE(STATE) \
(((STATE) == TIM5_OCIdleState_Set) || \
((STATE) == TIM5_OCIdleState_Reset))
/**
* @}
*/
/** @defgroup TIM5_Input_Capture_Polarity
* @{
*/
typedef enum
{
TIM5_ICPolarity_Rising = ((uint8_t)0x00), /*!< Input Capture on Rising Edge*/
TIM5_ICPolarity_Falling = ((uint8_t)0x01) /*!< Input Capture on Falling Edge*/
}TIM5_ICPolarity_TypeDef;
#define IS_TIM5_IC_POLARITY(POLARITY) \
(((POLARITY) == TIM5_ICPolarity_Rising) || \
((POLARITY) == TIM5_ICPolarity_Falling))
/**
* @}
*/
/** @defgroup TIM5_Input_Capture_Selection
* @{
*/
typedef enum
{
TIM5_ICSelection_DirectTI = ((uint8_t)0x01), /*!< Input Capture mapped on the direct input*/
TIM5_ICSelection_IndirectTI = ((uint8_t)0x02), /*!< Input Capture mapped on the indirect input*/
TIM5_ICSelection_TRGI = ((uint8_t)0x03) /*!< Input Capture mapped on the Trigger Input*/
}TIM5_ICSelection_TypeDef;
#define IS_TIM5_IC_SELECTION(SELECTION) \
(((SELECTION) == TIM5_ICSelection_DirectTI) || \
((SELECTION) == TIM5_ICSelection_IndirectTI) || \
((SELECTION) == TIM5_ICSelection_TRGI))
/**
* @}
*/
/** @defgroup TIM5_Input_Capture_Prescaler
* @{
*/
typedef enum
{
TIM5_ICPSC_DIV1 = ((uint8_t)0x00), /*!< Input Capture Prescaler = 1 (one capture every 1 event) */
TIM5_ICPSC_DIV2 = ((uint8_t)0x04), /*!< Input Capture Prescaler = 2 (one capture every 2 events) */
TIM5_ICPSC_DIV4 = ((uint8_t)0x08), /*!< Input Capture Prescaler = 4 (one capture every 4 events) */
TIM5_ICPSC_DIV8 = ((uint8_t)0x0C) /*!< Input Capture Prescaler = 8 (one capture every 8 events) */
}TIM5_ICPSC_TypeDef;
#define IS_TIM5_IC_PRESCALER(PRESCALER) \
(((PRESCALER) == TIM5_ICPSC_DIV1) || \
((PRESCALER) == TIM5_ICPSC_DIV2) || \
((PRESCALER) == TIM5_ICPSC_DIV4) || \
((PRESCALER) == TIM5_ICPSC_DIV8))
/**
* @}
*/
/** @defgroup TIM5_Interrupts
* @{
*/
typedef enum
{
TIM5_IT_Update = ((uint8_t)0x01), /*!< Update Interrupt*/
TIM5_IT_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Interrupt*/
TIM5_IT_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Interrupt*/
TIM5_IT_Trigger = ((uint8_t)0x40), /*!< Trigger Interrupt*/
TIM5_IT_Break = ((uint8_t)0x80) /*!< Break Interrupt*/
}TIM5_IT_TypeDef;
#define IS_TIM5_IT(IT) \
((IT) != 0x00)
#define IS_TIM5_GET_IT(IT) \
(((IT) == TIM5_IT_Update) || \
((IT) == TIM5_IT_CC1) || \
((IT) == TIM5_IT_CC2) || \
((IT) == TIM5_IT_Trigger) || \
((IT) == TIM5_IT_Break))
/**
* @}
*/
/** @defgroup TIM5_External_Trigger_Prescaler
* @{
*/
typedef enum
{
TIM5_ExtTRGPSC_OFF = ((uint8_t)0x00), /*!< No External Trigger prescaler */
TIM5_ExtTRGPSC_DIV2 = ((uint8_t)0x10), /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */
TIM5_ExtTRGPSC_DIV4 = ((uint8_t)0x20), /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */
TIM5_ExtTRGPSC_DIV8 = ((uint8_t)0x30) /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */
}TIM5_ExtTRGPSC_TypeDef;
#define IS_TIM5_EXT_PRESCALER(PRESCALER) \
(((PRESCALER) == TIM5_ExtTRGPSC_OFF) || \
((PRESCALER) == TIM5_ExtTRGPSC_DIV2) || \
((PRESCALER) == TIM5_ExtTRGPSC_DIV4) || \
((PRESCALER) == TIM5_ExtTRGPSC_DIV8))
/**
* @}
*/
/** @defgroup TIM5_Internal_Trigger_Selection
* @{
*/
typedef enum
{
TIM5_TRGSelection_TIM4 = ((uint8_t)0x00), /*!< TRIG Input source = TIM TRIG Output */
TIM5_TRGSelection_TIM1 = ((uint8_t)0x10), /*!< TRIG Input source = TIM TRIG Output */
TIM5_TRGSelection_TIM3 = ((uint8_t)0x20), /*!< TRIG Input source = TIM TRIG Output */
TIM5_TRGSelection_TIM2 = ((uint8_t)0x30), /*!< TRIG Input source = TIM TRIG Output */
TIM5_TRGSelection_TI1F_ED = ((uint8_t)0x40), /*!< TRIG Input source = TI1F_ED (TI1 Edge Detector) */
TIM5_TRGSelection_TI1FP1 = ((uint8_t)0x50), /*!< TRIG Input source = TI1FP1 (Filtered Timer Input 1) */
TIM5_TRGSelection_TI2FP2 = ((uint8_t)0x60), /*!< TRIG Input source = TI2FP2 (Filtered Timer Input 2) */
TIM5_TRGSelection_ETRF = ((uint8_t)0x70) /*!< TRIG Input source = ETRF (External Trigger Input ) */
}TIM5_TRGSelection_TypeDef;
#define IS_TIM5_TRIGGER_SELECTION(SELECTION) \
(((SELECTION) == TIM5_TRGSelection_TIM4) || \
((SELECTION) == TIM5_TRGSelection_TIM1) || \
((SELECTION) == TIM5_TRGSelection_TIM3) || \
((SELECTION) == TIM5_TRGSelection_TIM2) || \
((SELECTION) == TIM5_TRGSelection_TI1F_ED) || \
((SELECTION) == TIM5_TRGSelection_TI1FP1) || \
((SELECTION) == TIM5_TRGSelection_TI2FP2) || \
((SELECTION) == TIM5_TRGSelection_ETRF))
#define IS_TIM5_TIX_TRIGGER_SELECTION(SELECTION) \
(((SELECTION) == TIM5_TRGSelection_TI1F_ED) || \
((SELECTION) == TIM5_TRGSelection_TI1FP1) || \
((SELECTION) == TIM5_TRGSelection_TI2FP2))
/**
* @}
*/
/** @defgroup TIM5_TI_External_Clock_Source
* @{
*/
typedef enum
{
TIM5_TIxExternalCLK1Source_TI1ED = ((uint8_t)0x40), /*!< External Clock mode 1 source = TI1ED */
TIM5_TIxExternalCLK1Source_TI1 = ((uint8_t)0x50), /*!< External Clock mode 1 source = TI1 */
TIM5_TIxExternalCLK1Source_TI2 = ((uint8_t)0x60) /*!< External Clock mode 1 source = TI2 */
}TIM5_TIxExternalCLK1Source_TypeDef;
#define IS_TIM5_TIXCLK_SOURCE(SOURCE) \
(((SOURCE) == TIM5_TIxExternalCLK1Source_TI1ED) || \
((SOURCE) == TIM5_TIxExternalCLK1Source_TI2) || \
((SOURCE) == TIM5_TIxExternalCLK1Source_TI1))
/**
* @}
*/
/** @defgroup TIM5_External_Trigger_Polarity
* @{
*/
typedef enum
{
TIM5_ExtTRGPolarity_Inverted = ((uint8_t)0x80), /*!< External Trigger Polarity = inverted */
TIM5_ExtTRGPolarity_NonInverted = ((uint8_t)0x00) /*!< External Trigger Polarity = non inverted */
}TIM5_ExtTRGPolarity_TypeDef;
#define IS_TIM5_EXT_POLARITY(POLARITY) \
(((POLARITY) == TIM5_ExtTRGPolarity_Inverted) || \
((POLARITY) == TIM5_ExtTRGPolarity_NonInverted))
/**
* @}
*/
/** @defgroup TIM5_Prescaler_Reload_Mode
* @{
*/
typedef enum
{
TIM5_PSCReloadMode_Update = ((uint8_t)0x00), /*!< Prescaler value is reloaded at every update*/
TIM5_PSCReloadMode_Immediate = ((uint8_t)0x01) /*!< Prescaler value is reloaded immediatly*/
}TIM5_PSCReloadMode_TypeDef;
#define IS_TIM5_PRESCALER_RELOAD(RELOAD) \
(((RELOAD) == TIM5_PSCReloadMode_Update) || \
((RELOAD) == TIM5_PSCReloadMode_Immediate))
/**
* @}
*/
/** @defgroup TIM5_Encoder_Mode
* @{
*/
typedef enum
{
TIM5_EncoderMode_TI1 = ((uint8_t)0x01), /*!< Encoder mode 1*/
TIM5_EncoderMode_TI2 = ((uint8_t)0x02), /*!< Encoder mode 2*/
TIM5_EncoderMode_TI12 = ((uint8_t)0x03) /*!< Encoder mode 3*/
}TIM5_EncoderMode_TypeDef;
#define IS_TIM5_ENCODER_MODE(MODE) \
(((MODE) == TIM5_EncoderMode_TI1) || \
((MODE) == TIM5_EncoderMode_TI2) || \
((MODE) == TIM5_EncoderMode_TI12))
/**
* @}
*/
/** @defgroup TIM5_Event_Source
* @{
*/
typedef enum
{
TIM5_EventSource_Update = ((uint8_t)0x01), /*!< Update Event*/
TIM5_EventSource_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Event*/
TIM5_EventSource_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Event*/
TIM5_EventSource_Trigger = ((uint8_t)0x40), /*!< Trigger Event*/
TIM5_EventSource_Break = ((uint8_t)0x80) /*!< Break Event*/
}TIM5_EventSource_TypeDef;
#define IS_TIM5_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint8_t)0x18) == 0x00) && \
((SOURCE) != 0x00))
/**
* @}
*/
/** @defgroup TIM5_Update_Source
* @{
*/
typedef enum
{
TIM5_UpdateSource_Global = ((uint8_t)0x00), /*!< Global Update request source */
TIM5_UpdateSource_Regular = ((uint8_t)0x01) /*!< Regular Update request source */
}TIM5_UpdateSource_TypeDef;
#define IS_TIM5_UPDATE_SOURCE(SOURCE) \
(((SOURCE) == TIM5_UpdateSource_Global) || \
((SOURCE) == TIM5_UpdateSource_Regular))
/**
* @}
*/
/** @defgroup TIM5_Trigger_Output_Source
* @{
*/
typedef enum
{
TIM5_TRGOSource_Reset = ((uint8_t)0x00), /*!< Trigger Output source = Reset*/
TIM5_TRGOSource_Enable = ((uint8_t)0x10), /*!< Trigger Output source = TIM5 is enabled*/
TIM5_TRGOSource_Update = ((uint8_t)0x20), /*!< Trigger Output source = Update event*/
TIM5_TRGOSource_OC1 = ((uint8_t)0x30), /*!< Trigger Output source = output compare channel1 */
TIM5_TRGOSource_OC1REF = ((uint8_t)0x40), /*!< Trigger Output source = output compare channel 1 reference */
TIM5_TRGOSource_OC2REF = ((uint8_t)0x50) /*!< Trigger Output source = output compare channel 2 reference */
}TIM5_TRGOSource_TypeDef;
#define IS_TIM5_TRGO_SOURCE(SOURCE) \
(((SOURCE) == TIM5_TRGOSource_Reset) || \
((SOURCE) == TIM5_TRGOSource_Enable) || \
((SOURCE) == TIM5_TRGOSource_Update) || \
((SOURCE) == TIM5_TRGOSource_OC1) || \
((SOURCE) == TIM5_TRGOSource_OC1REF) || \
((SOURCE) == TIM5_TRGOSource_OC2REF))
/**
* @}
*/
/** @defgroup TIM5_Slave_Mode
* @{
*/
typedef enum
{
TIM5_SlaveMode_Reset = ((uint8_t)0x04), /*!< Slave Mode Selection = Reset*/
TIM5_SlaveMode_Gated = ((uint8_t)0x05), /*!< Slave Mode Selection = Gated*/
TIM5_SlaveMode_Trigger = ((uint8_t)0x06), /*!< Slave Mode Selection = Trigger*/
TIM5_SlaveMode_External1 = ((uint8_t)0x07) /*!< Slave Mode Selection = External 1*/
}TIM5_SlaveMode_TypeDef;
#define IS_TIM5_SLAVE_MODE(MODE) \
(((MODE) == TIM5_SlaveMode_Reset) || \
((MODE) == TIM5_SlaveMode_Gated) || \
((MODE) == TIM5_SlaveMode_Trigger) || \
((MODE) == TIM5_SlaveMode_External1))
/**
* @}
*/
/** @defgroup TIM5_Flags
* @{
*/
typedef enum
{
TIM5_FLAG_Update = ((uint16_t)0x0001), /*!< Update Flag */
TIM5_FLAG_CC1 = ((uint16_t)0x0002), /*!< Capture compare 1 Flag */
TIM5_FLAG_CC2 = ((uint16_t)0x0004), /*!< Capture compare 2 Flag */
TIM5_FLAG_Trigger = ((uint16_t)0x0040), /*!< Trigger Flag */
TIM5_FLAG_Break = ((uint16_t)0x0080), /*!< Break Flag */
TIM5_FLAG_CC1OF = ((uint16_t)0x0200), /*!< Capture compare 1 over capture Flag */
TIM5_FLAG_CC2OF = ((uint16_t)0x0400) /*!< Capture compare 2 over capture Flag */
}TIM5_FLAG_TypeDef;
#define IS_TIM5_GET_FLAG(FLAG) \
(((FLAG) == TIM5_FLAG_Update) || \
((FLAG) == TIM5_FLAG_CC1) || \
((FLAG) == TIM5_FLAG_CC2) || \
((FLAG) == TIM5_FLAG_Trigger) || \
((FLAG) == TIM5_FLAG_Break) || \
((FLAG) == TIM5_FLAG_CC1OF) || \
((FLAG) == TIM5_FLAG_CC2OF))
#define IS_TIM5_CLEAR_FLAG(FLAG) \
((((FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
/**
* @}
*/
/** @defgroup TIM5_DMA_Source_Requests
* @{
*/
typedef enum
{
TIM5_DMASource_Update = ((uint8_t)0x01), /*!< TIM5 DMA Update Request*/
TIM5_DMASource_CC1 = ((uint8_t)0x02), /*!< TIM5 DMA CC1 Request*/
TIM5_DMASource_CC2 = ((uint8_t)0x04) /*!< TIM5 DMA CC2 Request*/
}TIM5_DMASource_TypeDef;
#define IS_TIM5_DMA_SOURCE(SOURCE) \
(((SOURCE) == TIM5_DMASource_Update) || \
((SOURCE) == TIM5_DMASource_CC1) || \
((SOURCE) == TIM5_DMASource_CC2))
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup TIM5_Exported_Macros
* @{
*/
/**
* @brief Macro TIM5 Input Capture Filter Value
*/
#define IS_TIM5_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F)
/**
* @brief Macro TIM5 External Trigger Filter
*/
#define IS_TIM5_EXT_FILTER(EXTFILTER) \
((EXTFILTER) <= 0x0F)
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* TimeBase management ********************************************************/
void TIM5_DeInit(void);
void TIM5_TimeBaseInit(TIM5_Prescaler_TypeDef TIM5_Prescaler,
TIM5_CounterMode_TypeDef TIM5_CounterMode, uint16_t TIM5_Period);
void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler,
TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode);
void TIM5_CounterModeConfig(TIM5_CounterMode_TypeDef TIM5_CounterMode);
void TIM5_SetCounter(uint16_t Counter);
void TIM5_SetAutoreload(uint16_t Autoreload);
uint16_t TIM5_GetCounter(void);
TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void);
void TIM5_UpdateDisableConfig(FunctionalState NewState);
void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource);
void TIM5_ARRPreloadConfig(FunctionalState NewState);
void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode);
void TIM5_Cmd(FunctionalState NewState);
/* Output Compare management **************************************************/
void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode,
TIM5_OutputState_TypeDef TIM5_OutputState,
uint16_t TIM5_Pulse,
TIM5_OCPolarity_TypeDef TIM5_OCPolarity,
TIM5_OCIdleState_TypeDef TIM5_OCIdleState);
void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode,
TIM5_OutputState_TypeDef TIM5_OutputState,
uint16_t TIM5_Pulse,
TIM5_OCPolarity_TypeDef TIM5_OCPolarity,
TIM5_OCIdleState_TypeDef TIM5_OCIdleState);
void TIM5_BKRConfig(TIM5_OSSIState_TypeDef TIM5_OSSIState,
TIM5_LockLevel_TypeDef TIM5_LockLevel,
TIM5_BreakState_TypeDef TIM5_BreakState,
TIM5_BreakPolarity_TypeDef TIM5_BreakPolarity,
TIM5_AutomaticOutput_TypeDef TIM5_AutomaticOutput);
void TIM5_CtrlPWMOutputs(FunctionalState NewState);
void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode);
void TIM5_SetCompare1(uint16_t Compare);
void TIM5_SetCompare2(uint16_t Compare);
void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);
void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);
void TIM5_OC1PreloadConfig(FunctionalState NewState);
void TIM5_OC2PreloadConfig(FunctionalState NewState);
void TIM5_OC1FastConfig(FunctionalState NewState);
void TIM5_OC2FastConfig(FunctionalState NewState);
void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState);
/* Input Capture management ***************************************************/
void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel,
TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
TIM5_ICSelection_TypeDef TIM5_ICSelection,
TIM5_ICPSC_TypeDef TIM5_ICPrescaler,
uint8_t TIM5_ICFilter);
void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel,
TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
TIM5_ICSelection_TypeDef TIM5_ICSelection,
TIM5_ICPSC_TypeDef TIM5_ICPrescaler,
uint8_t TIM5_ICFilter);
uint16_t TIM5_GetCapture1(void);
uint16_t TIM5_GetCapture2(void);
void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler);
void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler);
/* Interrupts, DMA and flags management ***************************************/
void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState);
void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource);
FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG);
void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG);
ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT);
void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT);
void TIM5_DMACmd(TIM5_DMASource_TypeDef TIM5_DMASource, FunctionalState NewState);
void TIM5_SelectCCDMA(FunctionalState NewState);
/* Clocks management **********************************************************/
void TIM5_InternalClockConfig(void);
void TIM5_TIxExternalClockConfig(TIM5_TIxExternalCLK1Source_TypeDef TIM5_TIxExternalCLKSource,
TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
uint8_t ICFilter);
void TIM5_ETRClockMode1Config(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler,
TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity,
uint8_t ExtTRGFilter);
void TIM5_ETRClockMode2Config(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler,
TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity,
uint8_t ExtTRGFilter);
/* Synchronization management *************************************************/
void TIM5_SelectInputTrigger(TIM5_TRGSelection_TypeDef TIM5_InputTriggerSource);
void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource);
void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode);
void TIM5_SelectMasterSlaveMode(FunctionalState NewState);
void TIM5_ETRConfig(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler,
TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity,
uint8_t ExtTRGFilter);
/* Specific interface management **********************************************/
void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode,
TIM5_ICPolarity_TypeDef TIM5_IC1Polarity,
TIM5_ICPolarity_TypeDef TIM5_IC2Polarity);
void TIM5_SelectHallSensor(FunctionalState NewState);
#endif /* __STM8L15x_TIM5_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
********************************************************************************
* @file stm8l15x_usart.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the USART firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_USART_H
#define __STM8L15x_USART_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
#include "stm8l15x_clk.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup USART
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup USART_Exported_Types
* @{
*/
/** @defgroup USART_Flags
* @{
*/
typedef enum
{
USART_FLAG_TXE = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */
USART_FLAG_TC = (uint16_t)0x0040, /*!< Transmission Complete flag */
USART_FLAG_RXNE = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */
USART_FLAG_IDLE = (uint16_t)0x0010, /*!< Idle line detected flag */
USART_FLAG_OR = (uint16_t)0x0008, /*!< OverRun error flag */
USART_FLAG_NF = (uint16_t)0x0004, /*!< Noise error flag */
USART_FLAG_FE = (uint16_t)0x0002, /*!< Framing Error flag */
USART_FLAG_PE = (uint16_t)0x0001, /*!< Parity Error flag */
USART_FLAG_SBK = (uint16_t)0x0101 /*!< Send Break characters Flag */
} USART_FLAG_TypeDef;
#define IS_USART_FLAG(Flag) \
(((Flag) == USART_FLAG_TXE) || \
((Flag) == USART_FLAG_TC) || \
((Flag) == USART_FLAG_RXNE) || \
((Flag) == USART_FLAG_IDLE) || \
((Flag) == USART_FLAG_OR) || \
((Flag) == USART_FLAG_NF) || \
((Flag) == USART_FLAG_FE) || \
((Flag) == USART_FLAG_PE) || \
((Flag) == USART_FLAG_SBK))
#define IS_USART_CLEAR_FLAG(Flag) (((Flag) == USART_FLAG_TC))
/**
* @}
*/
/** @defgroup USART_Interrupts
* @{
*/
/**
* @brief USART Interrupt definition
* USART_IT possible values
* Elements values convention: 0x0ZYX
* X: Position of the corresponding Interrupt
* Y: Flag position
* Z: Register index
*/
typedef enum
{
USART_IT_TXE = (uint16_t)0x0277, /*!< Transmit interrupt */
USART_IT_TC = (uint16_t)0x0266, /*!< Transmission Complete interrupt */
USART_IT_RXNE = (uint16_t)0x0255, /*!< Receive interrupt */
USART_IT_IDLE = (uint16_t)0x0244, /*!< IDLE line interrupt */
USART_IT_OR = (uint16_t)0x0235, /*!< Overrun Error interrupt */
USART_IT_PE = (uint16_t)0x0100, /*!< Parity Error interrupt */
USART_IT_ERR = (uint16_t)0x0500, /*!< Error interrupt */
USART_IT_NF = (uint16_t)0x0102, /*!< Noise Error interrupt */
USART_IT_FE = (uint16_t)0x0101 /*!< Frame Error interrupt */
} USART_IT_TypeDef;
#define IS_USART_CONFIG_IT(Interrupt) \
(((Interrupt) == USART_IT_PE) || \
((Interrupt) == USART_IT_TXE) || \
((Interrupt) == USART_IT_TC) || \
((Interrupt) == USART_IT_RXNE) || \
((Interrupt) == USART_IT_OR) || \
((Interrupt) == USART_IT_ERR) || \
((Interrupt) == USART_IT_IDLE))
#define IS_USART_GET_IT(ITPendingBit) \
(((ITPendingBit) == USART_IT_TXE) || \
((ITPendingBit) == USART_IT_TC) || \
((ITPendingBit) == USART_IT_RXNE) || \
((ITPendingBit) == USART_IT_IDLE) || \
((ITPendingBit) == USART_IT_OR) || \
((ITPendingBit) == USART_IT_PE))
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE))
/**
* @}
*/
/** @defgroup USART_Wakeup_Modes
* @{
*/
typedef enum
{
USART_WakeUp_IdleLine = (uint8_t)0x00, /*!< 0x01 Idle Line wake up */
USART_WakeUp_AddressMark = (uint8_t)0x08 /*!< 0x02 Address Mark wake up */
} USART_WakeUp_TypeDef;
#define IS_USART_WAKEUP(WakeUpMode)(((WakeUpMode) == USART_WakeUp_IdleLine) || \
((WakeUpMode) == USART_WakeUp_AddressMark))
/**
* @}
*/
/** @defgroup USART_Stop_Bits
* @{
*/
typedef enum
{
USART_StopBits_1 = (uint8_t)0x00, /*!< One stop bit is transmitted at the end of frame*/
USART_StopBits_2 = (uint8_t)0x20, /*!< Two stop bits are transmitted at the end of frame*/
USART_StopBits_1_5 = (uint8_t)0x30 /*!< One and half stop bits*/
} USART_StopBits_TypeDef;
#define IS_USART_STOPBITS(StopBit)(((StopBit) == USART_StopBits_1) || \
((StopBit) == USART_StopBits_1_5) || \
((StopBit) == USART_StopBits_2))
/**
* @}
*/
/** @defgroup USART_Parity
* @{
*/
typedef enum
{
USART_Parity_No = (uint8_t)0x00, /*!< No Parity*/
USART_Parity_Even = (uint8_t)0x04, /*!< Even Parity*/
USART_Parity_Odd = (uint8_t)0x06 /*!< Odd Parity*/
} USART_Parity_TypeDef;
#define IS_USART_PARITY(Parity)(((Parity) == USART_Parity_No) || \
((Parity) == USART_Parity_Even) || \
((Parity) == USART_Parity_Odd ))
/**
* @}
*/
/** @defgroup USART_Lin_Break_Detection_Length
* @{
*/
typedef enum
{
USART_LINBreakDetectionLength_10BITS = (uint8_t)0x00, /*!< 10 bits Lin Break detection */
USART_LINBreakDetectionLength_11BITS = (uint8_t)0x01 /*!< 11 bits Lin Break detection */
} USART_LINBreakDetectionLength_TypeDef;
/**
* @}
*/
/** @defgroup USART_Word_Length
* @{
*/
typedef enum
{
USART_WordLength_8b = (uint8_t)0x00, /*!< 8 bits Data */
USART_WordLength_9b = (uint8_t)0x10 /*!< 9 bits Data */
} USART_WordLength_TypeDef;
#define IS_USART_WORDLENGTH(WordLength) (((WordLength) == USART_WordLength_8b) || \
((WordLength) == USART_WordLength_9b))
/**
* @}
*/
/** @defgroup USART_Mode
* @{
*/
typedef enum
{
USART_Mode_Rx = (uint8_t)0x04, /*!< Receive Enable */
USART_Mode_Tx = (uint8_t)0x08 /*!< Transmit Enable */
} USART_Mode_TypeDef;
#define IS_USART_MODE(MODE) ((((MODE) & (uint8_t)0xF3) == 0x00) && ((MODE) != (uint16_t)0x00))
/**
* @}
*/
/** @defgroup USART_DMA_Requests
* @{
*/
typedef enum
{
USART_DMAReq_TX = (uint8_t)0x80, /*!< Receive DMA request Enable */
USART_DMAReq_RX = (uint8_t)0x40 /*!< Transmit DMA request Enable */
} USART_DMAReq_TypeDef;
#define IS_USART_DMAREQ(DMAReq) ((((DMAReq) & (uint8_t)0x3F) == 0x00) && ((DMAReq) != (uint8_t)0x00))
/**
* @}
*/
/** @defgroup USART_IrDA_Mode
* @{
*/
typedef enum
{
USART_IrDAMode_Normal = (uint8_t)0x00, /*!< IrDA Normal Mode */
USART_IrDAMode_LowPower = (uint8_t)0x01 /*!< IrDA Low Power Mode */
} USART_IrDAMode_TypeDef;
#define IS_USART_IRDAMODE(IrDAMode) (((IrDAMode) == USART_IrDAMode_LowPower) || \
((IrDAMode) == USART_IrDAMode_Normal))
/**
* @}
*/
/** @defgroup USART_Clock
* @{
*/
typedef enum
{
USART_Clock_Disable = (uint8_t)0x00, /*!< CK pin disabled */
USART_Clock_Enable = (uint8_t)0x08 /*!< CK pin enabled */
} USART_Clock_TypeDef;
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) ||((CLOCK) == USART_Clock_Enable))
/**
* @}
*/
/** @defgroup USART_Clock_Polarity
* @{
*/
typedef enum
{
USART_CPOL_Low = (uint8_t)0x00, /*!< CK to 0 when idle */
USART_CPOL_High = (uint8_t)0x04 /*!< CK to 1 when idle.*/
} USART_CPOL_TypeDef;
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
/**
* @}
*/
/** @defgroup USART_Clock_Phase
* @{
*/
typedef enum
{
USART_CPHA_1Edge = (uint8_t)0x00, /*!< The first clock transition is the first data capture edge*/
USART_CPHA_2Edge = (uint8_t)0x02 /*!< The second clock transition is the first data capture edge*/
} USART_CPHA_TypeDef;
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
/**
* @}
*/
/** @defgroup USART_LastBit
* @{
*/
typedef enum
{
USART_LastBit_Disable = (uint8_t)0x00, /*!< The clock pulse of the last data bit is not output to the SCLK pin.*/
USART_LastBit_Enable = (uint8_t)0x01 /*!< The clock pulse of the last data bit is output to the SCLK pin.*/
} USART_LastBit_TypeDef;
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
((LASTBIT) == USART_LastBit_Enable))
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroupUSART_Exported_Macros
* @{
*/
/* BaudRate value should be < 625000 bps */
#define IS_USART_BAUDRATE(NUM) ((NUM) <= (uint32_t)625000)
#define USART_ADDRESS_MAX ((uint8_t)16)
#define IS_USART_ADDRESS(address) ((address) < USART_ADDRESS_MAX)
#define USART_DATA_9BITS_MAX ((uint16_t)0x1FF)
#define IS_USART_DATA_9BITS(DATA) ((DATA) < USART_DATA_9BITS_MAX)
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the USART configuration to the default reset state ***/
void USART_DeInit(USART_TypeDef* USARTx);
/* Initialization and Configuration functions *********************************/
void USART_Init(USART_TypeDef* USARTx, uint32_t BaudRate, USART_WordLength_TypeDef
USART_WordLength, USART_StopBits_TypeDef USART_StopBits,
USART_Parity_TypeDef USART_Parity, USART_Mode_TypeDef USART_Mode);
void USART_ClockInit(USART_TypeDef* USARTx, USART_Clock_TypeDef USART_Clock,
USART_CPOL_TypeDef USART_CPOL, USART_CPHA_TypeDef USART_CPHA,
USART_LastBit_TypeDef USART_LastBit);
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
void USART_SendBreak(USART_TypeDef* USARTx);
/* Data transfers functions ***************************************************/
void USART_SendData8(USART_TypeDef* USARTx, uint8_t Data);
void USART_SendData9(USART_TypeDef* USARTx, uint16_t Data);
uint8_t USART_ReceiveData8(USART_TypeDef* USARTx);
uint16_t USART_ReceiveData9(USART_TypeDef* USARTx);
/* Multi-Processor Communication functions ************************************/
void USART_WakeUpConfig(USART_TypeDef* USARTx, USART_WakeUp_TypeDef USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
/* Half-duplex mode function **************************************************/
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
/* Smartcard mode functions ***************************************************/
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
/* IrDA mode functions ********************************************************/
void USART_IrDAConfig(USART_TypeDef* USARTx, USART_IrDAMode_TypeDef USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
/* DMA transfers management functions *****************************************/
void USART_DMACmd(USART_TypeDef* USARTx, USART_DMAReq_TypeDef USART_DMAReq,
FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void USART_ITConfig(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT,
FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG);
void USART_ClearFlag(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT);
void USART_ClearITPendingBit(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT);
#endif /* __STM8L15x_USART_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_wfe.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the WFE firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_WFE_H
#define __STM8L15x_WFE_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup WFE
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup WFE_Exported_Types
* @{
*/
/** @defgroup WFE_Sources
* @brief Signal Sources to generate wake_up events
@verbatim
Elements values convention: 0xXXYY
X = SRx registers index
XX = 01 : CR1
XX = 02 : CR2
XX = 03 : CR3
XX = 04 : CR4
YY = flag mask in the dedicated register(XX register)
@endverbatim
* @{
*/
typedef enum {
WFE_Source_TIM2_EV0 = (uint16_t)0x0101, /*!< TIM2 Update/Trigger and Break interrupt */
WFE_Source_TIM2_EV1 = (uint16_t)0x0102, /*!< TIM2 Capture/Compare interrupt */
WFE_Source_TIM1_EV0 = (uint16_t)0x0104, /*!< TIM1 Update/Trigger and Break interrupt */
WFE_Source_TIM1_EV1 = (uint16_t)0x0108, /*!< TIM1 Capture/Compare interrupt */
WFE_Source_EXTI_EV0 = (uint16_t)0x0110, /*!< I/O port interrupt from Pins 0 */
WFE_Source_EXTI_EV1 = (uint16_t)0x0120, /*!< I/O port interrupt from Pins 1 */
WFE_Source_EXTI_EV2 = (uint16_t)0x0140, /*!< I/O port interrupt from Pins 2 */
WFE_Source_EXTI_EV3 = (uint16_t)0x0180, /*!< I/O port interrupt from Pins 3 */
WFE_Source_EXTI_EV4 = (uint16_t)0x0201, /*!< I/O port interrupt from Pins 4 */
WFE_Source_EXTI_EV5 = (uint16_t)0x0202, /*!< I/O port interrupt from Pins 5 */
WFE_Source_EXTI_EV6 = (uint16_t)0x0204, /*!< I/O port interrupt from Pins 6 */
WFE_Source_EXTI_EV7 = (uint16_t)0x0208, /*!< I/O port interrupt from Pins 7 */
WFE_Source_EXTI_EVB_G = (uint16_t)0x0210, /*!< I/O port interrupt from port B and G */
WFE_Source_EXTI_EVD_H = (uint16_t)0x0220, /*!< I/O port interrupt from Port D and H */
WFE_Source_EXTI_EVE_F = (uint16_t)0x0240, /*!< I/O port interrupt from Port E and F */
WFE_Source_ADC1_COMP_EV = (uint16_t)0x0280, /*!< ADC1, COMP1 and COMP2 interrupts */
WFE_Source_TIM3_EV0 = (uint16_t)0x0301, /*!< TIM3 Update/Trigger and Break interrupt */
WFE_Source_TIM3_EV1 = (uint16_t)0x0302, /*!< TIM3 Capture/Compare interrupt */
WFE_Source_TIM4_EV = (uint16_t)0x0304, /*!< TIM4 Update and Trigger interrupt */
WFE_Source_SPI1_EV = (uint16_t)0x0308, /*!< SPI1 Rx and Tx interrupt */
WFE_Source_I2C1_EV = (uint16_t)0x0310, /*!< I2C1 Rx and Tx interrupt */
WFE_Source_USART1_EV = (uint16_t)0x0320, /*!< USART1 Rx and Tx interrupt */
WFE_Source_DMA1CH01_EV = (uint16_t)0x0340, /*!< DMA1 channel 0 and 1 interrupt */
WFE_Source_DMA1CH23_EV = (uint16_t)0x0380, /*!< DMA1 channel 2 and 3 interrupt */
WFE_Source_RTC_CSS_EV = (uint16_t)0x0401, /*!< RTC or CSS on LSE event */
WFE_Source_SPI2_EV = (uint16_t)0x0402, /*!< SPI2 Rx and Tx interrupt */
WFE_Source_USART2_EV = (uint16_t)0x0404, /*!< USART2 Rx and Tx interrupt */
WFE_Source_USART3_EV = (uint16_t)0x0408, /*!< USART3 Rx and Tx interrupt */
WFE_Source_TIM5_EV0 = (uint16_t)0x0410, /*!< TIM5 Update/Trigger and Break interrupt */
WFE_Source_TIM5_EV1 = (uint16_t)0x0420, /*!< TIM5 Capture/Compare interrupt */
WFE_Source_AES_EV = (uint16_t)0x0440 /*!< AES interrupt */
} WFE_Source_TypeDef;
#define IS_WFE_SOURCE(Source) (((Source) == WFE_Source_TIM2_EV0) || \
((Source) == WFE_Source_TIM2_EV1) || \
((Source) == WFE_Source_TIM1_EV0) || \
((Source) == WFE_Source_TIM1_EV1) || \
((Source) == WFE_Source_EXTI_EV0) || \
((Source) == WFE_Source_EXTI_EV1) || \
((Source) == WFE_Source_EXTI_EV2) || \
((Source) == WFE_Source_EXTI_EV3) || \
((Source) == WFE_Source_EXTI_EV4) || \
((Source) == WFE_Source_EXTI_EV5) || \
((Source) == WFE_Source_EXTI_EV6) || \
((Source) == WFE_Source_EXTI_EV7) || \
((Source) == WFE_Source_EXTI_EVB_G) || \
((Source) == WFE_Source_EXTI_EVD_H) || \
((Source) == WFE_Source_EXTI_EVE_F) || \
((Source) == WFE_Source_ADC1_COMP_EV) || \
((Source) == WFE_Source_TIM3_EV0) || \
((Source) == WFE_Source_TIM3_EV1) || \
((Source) == WFE_Source_TIM4_EV) || \
((Source) == WFE_Source_SPI1_EV) || \
((Source) == WFE_Source_I2C1_EV) || \
((Source) == WFE_Source_USART1_EV) || \
((Source) == WFE_Source_DMA1CH01_EV) || \
((Source) == WFE_Source_AES_EV) || \
((Source) == WFE_Source_TIM5_EV1) || \
((Source) == WFE_Source_TIM5_EV0) || \
((Source) == WFE_Source_USART3_EV) || \
((Source) == WFE_Source_USART2_EV) || \
((Source) == WFE_Source_SPI2_EV) || \
((Source) == WFE_Source_RTC_CSS_EV) || \
((Source) == WFE_Source_DMA1CH23_EV))
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the WFE configuration to the default reset state ******/
void WFE_DeInit(void);
/* WFE Source configuration and management functions **************************/
void WFE_WakeUpSourceEventCmd(WFE_Source_TypeDef WFE_Source, FunctionalState NewState);
FunctionalState WFE_GetWakeUpSourceEventStatus(WFE_Source_TypeDef WFE_Source);
#endif /* __STM8L15x_WFE_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_wwdg.h
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file contains all the functions prototypes for the WWDG firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8L15x_WWDG_H
#define __STM8L15x_WWDG_H
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Macros
* @{
*/
/** @defgroup WWDG_WindowLimitValue
* @{
*/
#define IS_WWDG_WINDOW_LIMIT_VALUE(WindowLimitValue) ((WindowLimitValue) <= 0x7F)
/**
* @}
*/
/** @defgroup WWDG_CounterValue
* @{
*/
#define IS_WWDG_COUNTER_VALUE(CounterValue) ((CounterValue) <= 0x7F)
/**
* @}
*/
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/* Refresh window and Counter configuration functions *************************/
void WWDG_Init(uint8_t Counter, uint8_t WindowValue);
void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_SetCounter(uint8_t Counter);
/* WWDG activation function ***************************************************/
void WWDG_Enable(uint8_t Counter);
/* WWDG counter and software reset management **********************************/
uint8_t WWDG_GetCounter(void);
void WWDG_SWReset(void);
#endif /* __STM8L15x_WWDG_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_adc.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* - Initialization and Configuration
* - Power saving
* - Analog Watchdog configuration
* - Temperature Sensor & Vrefint (Voltage Reference internal) management
* - Regular Channels Configuration
* - Regular Channels DMA Configuration
* - Injected channels Configuration
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable The ADC controller clock using CLK_PeripheralClockConfig()
* function : CLK_PeripheralClockConfig(CLK_Peripheral_ADC1, ENABLE).
*
* 2. Configure the ADC Prescaler, conversion resolution and data
* alignment using the ADC_Init() function.
*
* 3. Activate the ADC peripheral using ADC_Cmd() function.
*
* Regular channels group configuration
* ====================================
* - To configure the ADC regular channels group features, use
* ADC_Init() and ADC_RegularChannelConfig() functions.
* - To activate the continuous mode, use the ADC_continuousModeCmd()
* function.
* - To configure and activate the Discontinuous mode, use the
* ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
* - To read the ADC converted values, use the ADC_GetConversionValue()
* function.
*
* DMA for Regular channels group features configuration
* ======================================================
* - To enable the DMA mode for regular channels group, use the
* ADC_DMACmd() function.
* - To enable the generation of DMA requests continuously at the end
* of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
* function.
* Injected channels group configuration
* =====================================
* - To configure the ADC Injected channels group features, use
* ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()
* functions.
* - To activate the continuous mode, use the ADC_continuousModeCmd()
* function.
* - To activate the Injected Discontinuous mode, use the
* ADC_InjectedDiscModeCmd() function.
* - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
* function.
* - To read the ADC converted values, use the ADC_GetInjectedConversionValue()
* function.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_adc.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup ADC
* @brief ADC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup ADC_Private_Functions
* @{
*/
/** @defgroup ADC_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
Initialization and Configuration functions
===============================================================================
This section provides functions allowing to:
- Enable or disable the ADC peripheral,
- Initialize and configure the ADC Prescaler, ADC Conversion Resolution
(12bit..6bit), ADC Continuous Conversion Mode (Continuous or Single
conversion),
- Configure External trigger Sensitivity and source,
- Start ADC conversion, by software trigger.
@endverbatim
* @{
*/
/**
* @brief Deinitializes the ADC peripheral registers to their default reset
* values.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @retval None
*/
void ADC_DeInit(ADC_TypeDef* ADCx)
{
/* Set the Configuration registers to their reset values */
ADCx->CR1 = ADC_CR1_RESET_VALUE;
ADCx->CR2 = ADC_CR2_RESET_VALUE;
ADCx->CR3 = ADC_CR3_RESET_VALUE;
/* Set the status registers to their reset values */
ADCx->SR = (uint8_t)~ADC_SR_RESET_VALUE;
/* Set the High threshold registers to their reset values */
ADCx->HTRH = ADC_HTRH_RESET_VALUE;
ADCx->HTRL = ADC_HTRL_RESET_VALUE;
/* Set the low threshold registers to their reset values */
ADCx->LTRH = ADC_LTRH_RESET_VALUE;
ADCx->LTRL = ADC_LTRL_RESET_VALUE;
/* Set the channels sequence registers to their reset values */
ADCx->SQR[0] = ADC_SQR1_RESET_VALUE;
ADCx->SQR[1] = ADC_SQR2_RESET_VALUE;
ADCx->SQR[2] = ADC_SQR3_RESET_VALUE;
ADCx->SQR[3] = ADC_SQR4_RESET_VALUE;
/* Set the channels Trigger registers to their reset values */
ADCx->TRIGR[0] = ADC_TRIGR1_RESET_VALUE;
ADCx->TRIGR[1] = ADC_TRIGR2_RESET_VALUE;
ADCx->TRIGR[2] = ADC_TRIGR3_RESET_VALUE;
ADCx->TRIGR[3] = ADC_TRIGR4_RESET_VALUE;
}
/**
* @brief Initializes the specified ADC peripheral according to the specified
* parameters.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param ADC_ConversionMode : specifies the ADC conversion mode,
* This parameter can be one of the following values:
* @arg ADC_ConversionMode_Single: Single Conversion Mode
* @arg ADC_ConversionMode_Continuous: Continuous Conversion Mode
* @param ADC_Resolution : specifies the ADC Data resolution,
* This parameter can be one of the following values:
* @arg ADC_Resolution_12Bit: 12 bit resolution
* @arg ADC_Resolution_10Bit: 10 bit resolution
* @arg ADC_Resolution_8Bit: 8 bit resolution
* @arg ADC_Resolution_6Bit: 6 bit resolution
* @param ADC_Prescaler : specifies the ADC Prescaler,
* This parameter can be one of the following values:
* @arg ADC_Prescaler_1: ADC Clock frequency is divided by 1
* @arg ADC_Prescaler_2: ADC Clock frequency is divided by 2
* @retval None
*/
void ADC_Init(ADC_TypeDef* ADCx,
ADC_ConversionMode_TypeDef ADC_ConversionMode,
ADC_Resolution_TypeDef ADC_Resolution,
ADC_Prescaler_TypeDef ADC_Prescaler)
{
/* Check the parameters */
assert_param(IS_ADC_CONVERSION_MODE(ADC_ConversionMode));
assert_param(IS_ADC_RESOLUTION(ADC_Resolution));
assert_param(IS_ADC_PRESCALER(ADC_Prescaler));
/*clear CR1 register */
ADCx->CR1 &= (uint8_t)~(ADC_CR1_CONT | ADC_CR1_RES);
/* set the resolution and the conversion mode */
ADCx->CR1 |= (uint8_t)((uint8_t)ADC_ConversionMode | (uint8_t)ADC_Resolution);
/*clear CR2 register */
ADCx->CR2 &= (uint8_t)~(ADC_CR2_PRESC);
/* set the Prescaler */
ADCx->CR2 |= (uint8_t) ADC_Prescaler;
}
/**
* @brief Enables or disables the selected ADC peripheral.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param NewState : new state of the specified ADC peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void ADC_Cmd(ADC_TypeDef* ADCx,
FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Set the ADON bit to wake up the specified ADC from power down mode */
ADCx->CR1 |= ADC_CR1_ADON;
}
else
{
/* Disable the selected ADC peripheral */
ADCx->CR1 &= (uint8_t)~ADC_CR1_ADON;
}
}
/**
* @brief Starts ADC conversion, by software trigger.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @retval None
*/
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
{
/* Start the ADC software conversion */
ADCx->CR1 |= ADC_CR1_START;
}
/**
* @brief Configures the ADC conversion through external trigger.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param ADC_ExtEventSelection : Specifies the external trigger.
* This parameter can be one of the following values:
* @arg ADC_ExtEventSelection_None: Conversion starts only by software start
* @arg ADC_ExtEventSelection_Trigger1: Trigger 1 Enables conversion
* @arg ADC_ExtEventSelection_Trigger2: Trigger 2 Enables conversion
* @arg ADC_ExtEventSelection_Trigger3: Trigger 3 Enables conversion
* @param ADC_ExtTRGSensitivity : Specifies the external trigger sensitivity.
* This parameter can be one of the following values:
* @arg ADC_ExtTRGSensitivity_Rising: External Trigger Sensitivity is Rising Edge
* @arg ADC_ExtTRGSensitivity_Falling: External Trigger Sensitivity is Falling Edge
* @arg ADC_ExtTRGSensitivity_All: External Trigger Sensitivity is Falling and Rising Edge
* @retval None
*/
void ADC_ExternalTrigConfig(ADC_TypeDef* ADCx,
ADC_ExtEventSelection_TypeDef ADC_ExtEventSelection,
ADC_ExtTRGSensitivity_TypeDef ADC_ExtTRGSensitivity)
{
/* Check the parameters */
assert_param(IS_ADC_EXT_EVENT_SELECTION(ADC_ExtEventSelection));
assert_param(IS_ADC_EXT_TRG_SENSITIVITY(ADC_ExtTRGSensitivity));
/*clear old configuration of CR2 register */
ADCx->CR2 &= (uint8_t)~(ADC_CR2_TRIGEDGE | ADC_CR2_EXTSEL);
/* set the External Trigger Edge Sensitivity and the external event
selection */
ADCx->CR2 |= (uint8_t)( (uint8_t)ADC_ExtTRGSensitivity | \
(uint8_t)ADC_ExtEventSelection);
}
/**
* @}
*/
/** @defgroup ADC_Group2 Analog Watchdog configuration functions
* @brief Analog Watchdog configuration functions
*
@verbatim
===============================================================================
Analog Watchdog configuration functions
===============================================================================
This section provides functions allowing to configure the Analog Watchdog
(AWD) feature in the ADC.
A typical configuration Analog Watchdog is done following these steps :
1. the ADC guarded channel is selected using the
ADC_AnalogWatchdogChannelSelect() function.
2. The Analog watchdog lower and higher threshold are configured using the
ADC_AnalogWatchdogThresholdsConfig() function.
Note : Both AWD selection and thresholds can be configured with one unique
function ADC_AnalogWatchdogConfig(), which is kept for firmware
compatibility reason.
@endverbatim
* @{
*/
/**
* @brief Configures the channel to be checked by the Analog watchdog.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param ADC_AnalogWatchdogSelection : Specifies the channel to be checked
* by the Analog watchdog.
* This parameter can be one of the following values:
* @arg ADC_AnalogWatchdogSelection_Channel0: AWD affected to Channel 0
* @arg ADC_AnalogWatchdogSelection_Channel1: AWD affected to Channel 1
* @arg ADC_AnalogWatchdogSelection_Channel2: AWD affected to Channel 2
* @arg ADC_AnalogWatchdogSelection_Channel3: AWD affected to Channel 3
* @arg ADC_AnalogWatchdogSelection_Channel4: AWD affected to Channel 4
* @arg ADC_AnalogWatchdogSelection_Channel5: AWD affected to Channel 5
* @arg ADC_AnalogWatchdogSelection_Channel6: AWD affected to Channel 6
* @arg ADC_AnalogWatchdogSelection_Channel7: AWD affected to Channel 7
* @arg ADC_AnalogWatchdogSelection_Channel8: AWD affected to Channel 8
* @arg ADC_AnalogWatchdogSelection_Channel9: AWD affected to Channel 9
* @arg ADC_AnalogWatchdogSelection_Channel10: AWD affected to Channel 10
* @arg ADC_AnalogWatchdogSelection_Channel11: AWD affected to Channel 11
* @arg ADC_AnalogWatchdogSelection_Channel12: AWD affected to Channel 12
* @arg ADC_AnalogWatchdogSelection_Channel13: AWD affected to Channel 13
* @arg ADC_AnalogWatchdogSelection_Channel14: AWD affected to Channel 14
* @arg ADC_AnalogWatchdogSelection_Channel15: AWD affected to Channel 15
* @arg ADC_AnalogWatchdogSelection_Channel16: AWD affected to Channel 16
* @arg ADC_AnalogWatchdogSelection_Channel17: AWD affected to Channel 17
* @arg ADC_AnalogWatchdogSelection_Channel18: AWD affected to Channel 18
* @arg ADC_AnalogWatchdogSelection_Channel19: AWD affected to Channel 19
* @arg ADC_AnalogWatchdogSelection_Channel20: AWD affected to Channel 20
* @arg ADC_AnalogWatchdogSelection_Channel21: AWD affected to Channel 21
* @arg ADC_AnalogWatchdogSelection_Channel22: AWD affected to Channel 22
* @arg ADC_AnalogWatchdogSelection_Channel23: AWD affected to Channel 23
* @ref ADC_AnalogWatchdogSelection_TypeDef enumeration.
* @retval None
*/
void ADC_AnalogWatchdogChannelSelect(ADC_TypeDef* ADCx,
ADC_AnalogWatchdogSelection_TypeDef ADC_AnalogWatchdogSelection)
{
/* Check the parameters */
assert_param(IS_ADC_ANALOGWATCHDOG_SELECTION(ADC_AnalogWatchdogSelection));
/* Reset the CHSEL bits */
ADCx->CR3 &= ((uint8_t)~ADC_CR3_CHSEL);
/* Select the channel to be checked by the Analog watchdog */
ADCx->CR3 |= (uint8_t)ADC_AnalogWatchdogSelection;
}
/**
* @brief Configures the high and low thresholds of the Analog watchdog.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param HighThreshold: Analog watchdog High threshold value.
* This parameter must be a 12bit value.
* @param LowThreshold: Analog watchdog Low threshold value.
* This parameter must be a 12bit value.
* @retval None
*/
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
{
/* Check the parameters */
assert_param(IS_ADC_THRESHOLD(HighThreshold));
assert_param(IS_ADC_THRESHOLD(LowThreshold));
/* Set the ADC high threshold */
ADCx->HTRH = (uint8_t)(HighThreshold >> 8);
ADCx->HTRL = (uint8_t)(HighThreshold);
/* Set the ADC low threshold */
ADCx->LTRH = (uint8_t)(LowThreshold >> 8);
ADCx->LTRL = (uint8_t)(LowThreshold);
}
/**
* @brief Configures the Analog watchdog.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param ADC_AnalogWatchdogSelection : Specifies the channel to be checked
* by the Analog watchdog.
* This parameter can be one of the following values:
* @arg ADC_AnalogWatchdogSelection_Channel0: AWD affected to Channel 0
* @arg ADC_AnalogWatchdogSelection_Channel1: AWD affected to Channel 1
* @arg ADC_AnalogWatchdogSelection_Channel2: AWD affected to Channel 2
* @arg ADC_AnalogWatchdogSelection_Channel3: AWD affected to Channel 3
* @arg ADC_AnalogWatchdogSelection_Channel4: AWD affected to Channel 4
* @arg ADC_AnalogWatchdogSelection_Channel5: AWD affected to Channel 5
* @arg ADC_AnalogWatchdogSelection_Channel6: AWD affected to Channel 6
* @arg ADC_AnalogWatchdogSelection_Channel7: AWD affected to Channel 7
* @arg ADC_AnalogWatchdogSelection_Channel8: AWD affected to Channel 8
* @arg ADC_AnalogWatchdogSelection_Channel9: AWD affected to Channel 9
* @arg ADC_AnalogWatchdogSelection_Channel10: AWD affected to Channel 10
* @arg ADC_AnalogWatchdogSelection_Channel11: AWD affected to Channel 11
* @arg ADC_AnalogWatchdogSelection_Channel12: AWD affected to Channel 12
* @arg ADC_AnalogWatchdogSelection_Channel13: AWD affected to Channel 13
* @arg ADC_AnalogWatchdogSelection_Channel14: AWD affected to Channel 14
* @arg ADC_AnalogWatchdogSelection_Channel15: AWD affected to Channel 15
* @arg ADC_AnalogWatchdogSelection_Channel16: AWD affected to Channel 16
* @arg ADC_AnalogWatchdogSelection_Channel17: AWD affected to Channel 17
* @arg ADC_AnalogWatchdogSelection_Channel18: AWD affected to Channel 18
* @arg ADC_AnalogWatchdogSelection_Channel19: AWD affected to Channel 19
* @arg ADC_AnalogWatchdogSelection_Channel20: AWD affected to Channel 20
* @arg ADC_AnalogWatchdogSelection_Channel21: AWD affected to Channel 21
* @arg ADC_AnalogWatchdogSelection_Channel22: AWD affected to Channel 22
* @arg ADC_AnalogWatchdogSelection_Channel23: AWD affected to Channel 23
* @param HighThreshold: Analog watchdog High threshold value.
* This parameter must be a 12bit value.
* @param LowThreshold: Analog watchdog Low threshold value.
* This parameter must be a 12bit value.
* @retval None
*/
void ADC_AnalogWatchdogConfig(ADC_TypeDef* ADCx,
ADC_AnalogWatchdogSelection_TypeDef ADC_AnalogWatchdogSelection,
uint16_t HighThreshold,
uint16_t LowThreshold)
{
/* Check the parameters */
assert_param(IS_ADC_ANALOGWATCHDOG_SELECTION(ADC_AnalogWatchdogSelection));
assert_param(IS_ADC_THRESHOLD(HighThreshold));
assert_param(IS_ADC_THRESHOLD(LowThreshold));
/*Reset the CHSEL bits */
ADCx->CR3 &= ((uint8_t)~ADC_CR3_CHSEL);
/* Select the channel to be checked by the Analog watchdog.*/
ADCx->CR3 |= (uint8_t)ADC_AnalogWatchdogSelection;
/* Set the ADC high threshold */
ADCx->HTRH = (uint8_t)(HighThreshold >> 8);
ADCx->HTRL = (uint8_t)(HighThreshold);
/* Set the ADC low threshold */
ADCx->LTRH = (uint8_t)(LowThreshold >> 8);
ADCx->LTRL = (uint8_t)LowThreshold;
}
/**
* @}
*/
/** @defgroup ADC_Group3 Temperature Sensor & Vrefint (Voltage Reference
* internal) management functions
* @brief Temperature Sensor & Vrefint (Voltage Reference internal)
* management functions
*
@verbatim
===============================================================================
Temperature Sensor & Vrefint (Voltage Reference internal) management functions
===============================================================================
This section provides functions allowing to enable/ disable the internal
connections between the ADC and the Temperature Sensor and the Vrefint source.
A typical configuration to get the Temperature sensor or/and Vrefint channels
voltages is done following these steps :
1. Enable the internal connection of Temperature sensor or/and Vrefint sources
with the ADC channels:
- for the Temperature sensor using ADC_TempSensorCmd() function.
- for the Internal Voltage reference using ADC_VrefintCmd() function.
2. Enable the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint channels
using ADC_ChannelCmd()function.
3. Get the voltage values, using ADC_GetConversionValue().
@endverbatim
* @{
*/
/**
* @brief Enables or disables the Temperature sensor internal reference.
* @param NewState : new state of the Temperature sensor internal reference.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void ADC_TempSensorCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/*Enable the Temperature sensor internal reference.*/
ADC1->TRIGR[0] |= (uint8_t)(ADC_TRIGR1_TSON);
}
else
{
/*Disable the Temperature sensor internal reference.*/
ADC1->TRIGR[0] &= (uint8_t)(~ADC_TRIGR1_TSON);
}
}
/**
* @brief Enables or disables the Internal Voltage reference.
* @param NewState : new state of the Internal Voltage reference.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void ADC_VrefintCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the Internal Voltage reference.*/
ADC1->TRIGR[0] |= (uint8_t)(ADC_TRIGR1_VREFINTON);
}
else
{
/* Disable the Internal Voltage reference.*/
ADC1->TRIGR[0] &= (uint8_t)(~ADC_TRIGR1_VREFINTON);
}
}
/**
* @}
*/
/** @defgroup ADC_Group4 Channels Configuration functions
* @brief Channels Configuration functions
*
@verbatim
===============================================================================
Channels Configuration functions
===============================================================================
This section provides functions allowing to:
- Enable or disable the ADC channel using ADC_ChannelCmd() function,
- Configure the channels sampling times using ADC_SamplingTimeConfig()
function.
Note: there are 2 sampling times configuration values :
- 1st Group value : for channels 0..23
- 2nd Group value : for channels 24..27 (depending on the MCU
package density) and Temperature Sensor and Vrefint channels.
- Configure the channels Schmitt Trigger for each channel using
ADC_SchmittTriggerConfig() function.
- Get the current ADC conversion value.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the selected ADC channel(s).
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param ADC_Channels: specifies the ADC channels to be initialized
* This parameter can be one of the following values:
* @arg ADC_Channel_0: Channel 0
* @arg ADC_Channel_1: Channel 1
* @arg ADC_Channel_2: Channel 2
* @arg ADC_Channel_3: Channel 3
* @arg ADC_Channel_4: Channel 4
* @arg ADC_Channel_5: Channel 5
* @arg ADC_Channel_6: Channel 6
* @arg ADC_Channel_7: Channel 7
* @arg ADC_Channel_8: Channel 8
* @arg ADC_Channel_9: Channel 9
* @arg ADC_Channel_10: Channel 10
* @arg ADC_Channel_11: Channel 11
* @arg ADC_Channel_12: Channel 12
* @arg ADC_Channel_13: Channel 13
* @arg ADC_Channel_14: Channel 14
* @arg ADC_Channel_15: Channel 15
* @arg ADC_Channel_16: Channel 16
* @arg ADC_Channel_17: Channel 17
* @arg ADC_Channel_18: Channel 18
* @arg ADC_Channel_19: Channel 19
* @arg ADC_Channel_20: Channel 20
* @arg ADC_Channel_21: Channel 21
* @arg ADC_Channel_22: Channel 22
* @arg ADC_Channel_23: Channel 23
* @arg ADC_Channel_24: Channel 24
* @arg ADC_Channel_25: Channel 25
* @arg ADC_Channel_26: Channel 26
* @arg ADC_Channel_27: Channel 27
* @arg ADC_Channel_Vrefint: Vrefint Channel
* @arg ADC_Channel_TempSensor: Temperature sensor Channel
* @arg ADC_Channel_00To07: select from channel00 to channel07
* @arg ADC_Channel_08To15: select from channel08 to channel15
* @arg ADC_Channel_16To23: select from channel16 to channel23
* @arg ADC_Channel_24To27: select from channel24 to channel27
* @param NewState : new state of the specified ADC channel(s).
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void ADC_ChannelCmd(ADC_TypeDef* ADCx, ADC_Channel_TypeDef ADC_Channels, FunctionalState NewState)
{
uint8_t regindex = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
regindex = (uint8_t)((uint16_t)ADC_Channels >> 8);
if (NewState != DISABLE)
{
/* Enable the selected ADC channel(s). */
ADCx->SQR[regindex] |= (uint8_t)(ADC_Channels);
}
else
{
/* Disable the selected ADC channel(s). */
ADCx->SQR[regindex] &= (uint8_t)(~(uint8_t)(ADC_Channels));
}
}
/**
* @brief Configures the sampling time for the selected ADC channel group.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param ADC_GroupChannels : ADC channel group to configure.
* This parameter can be one of the following values:
* @arg ADC_Group_SlowChannels: Slow Channels group
* @arg ADC_Group_FastChannels: Fast Channels group
* @note The channels of 1st ADC Group can be channels 0..23
* @note The channels of 2nd ADC Group can be channels 24..27 (depending on the MCU
* package density) and Temperature Sensor and Vrefint channels.
* @param ADC_SamplingTime : Specifies the sample time value
* This parameter can be one of the following values:
* @arg ADC_SamplingTime_4Cycles: Sampling Time Cycles is 4
* @arg ADC_SamplingTime_9Cycles: Sampling Time Cycles is 9
* @arg ADC_SamplingTime_16Cycles: Sampling Time Cycles is 16
* @arg ADC_SamplingTime_24Cycles: Sampling Time Cycles is 24
* @arg ADC_SamplingTime_48Cycles: Sampling Time Cycles is 48
* @arg ADC_SamplingTime_96Cycles: Sampling Time Cycles is 96
* @arg ADC_SamplingTime_192Cycles: Sampling Time Cycles is 192
* @arg ADC_SamplingTime_384Cycles: Sampling Time Cycles is 384
* @retval None
*/
void ADC_SamplingTimeConfig(ADC_TypeDef* ADCx,
ADC_Group_TypeDef ADC_GroupChannels,
ADC_SamplingTime_TypeDef ADC_SamplingTime)
{
/* Check the parameters */
assert_param(IS_ADC_GROUP(ADC_GroupChannels));
assert_param(IS_ADC_SAMPLING_TIME_CYCLES(ADC_SamplingTime));
if ( ADC_GroupChannels != ADC_Group_SlowChannels)
{
/* Configures the sampling time for the Fast ADC channel group. */
ADCx->CR3 &= (uint8_t)~ADC_CR3_SMPT2;
ADCx->CR3 |= (uint8_t)(ADC_SamplingTime << 5);
}
else
{
/* Configures the sampling time for the Slow ADC channel group. */
ADCx->CR2 &= (uint8_t)~ADC_CR2_SMPT1;
ADCx->CR2 |= (uint8_t)ADC_SamplingTime;
}
}
/**
* @brief Configures the status of the Schmitt Trigger for the selected ADC
* channel(s).
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param ADC_Channels: specifies the ADC channels to be initialized,
* This parameter can be one of the following values:
* @arg ADC_Channel_0: Channel 0
* @arg ADC_Channel_1: Channel 1
* @arg ADC_Channel_2: Channel 2
* @arg ADC_Channel_3: Channel 3
* @arg ADC_Channel_4: Channel 4
* @arg ADC_Channel_5: Channel 5
* @arg ADC_Channel_6: Channel 6
* @arg ADC_Channel_7: Channel 7
* @arg ADC_Channel_8: Channel 8
* @arg ADC_Channel_9: Channel 9
* @arg ADC_Channel_10: Channel 10
* @arg ADC_Channel_11: Channel 11
* @arg ADC_Channel_12: Channel 12
* @arg ADC_Channel_13: Channel 13
* @arg ADC_Channel_14: Channel 14
* @arg ADC_Channel_15: Channel 15
* @arg ADC_Channel_16: Channel 16
* @arg ADC_Channel_17: Channel 17
* @arg ADC_Channel_18: Channel 18
* @arg ADC_Channel_19: Channel 19
* @arg ADC_Channel_20: Channel 20
* @arg ADC_Channel_21: Channel 21
* @arg ADC_Channel_22: Channel 22
* @arg ADC_Channel_23: Channel 23
* @arg ADC_Channel_24: Channel 24
* @arg ADC_Channel_25: Channel 25
* @arg ADC_Channel_26: Channel 26
* @arg ADC_Channel_27: Channel 27
* @arg ADC_Channel_Vrefint: Vrefint Channel
* @arg ADC_Channel_TempSensor: Temperature sensor Channel
* @arg ADC_Channel_00To07: select from channel00 to channel07
* @arg ADC_Channel_08To15: select from channel08 to channel15
* @arg ADC_Channel_16To23: select from channel16 to channel23
* @arg ADC_Channel_24To27: select from channel24 to channel27
* @param NewState : new state of the Schmitt Trigger
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void ADC_SchmittTriggerConfig(ADC_TypeDef* ADCx, ADC_Channel_TypeDef ADC_Channels,
FunctionalState NewState)
{
uint8_t regindex = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
regindex = (uint8_t)((uint16_t)ADC_Channels >> 8);
if (NewState != DISABLE)
{
/* Enable the Schmitt Trigger for the selected ADC channel(s).*/
ADCx->TRIGR[regindex] &= (uint8_t)(~(uint8_t)ADC_Channels);
}
else
{
/* Disable the Schmitt Trigger for the selected ADC channel(s).*/
ADCx->TRIGR[regindex] |= (uint8_t)(ADC_Channels);
}
}
/**
* @brief Returns the last ADC converted data.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @retval The Data conversion value.
*/
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
{
uint16_t tmpreg = 0;
/* Get last ADC converted data.*/
tmpreg = (uint16_t)(ADCx->DRH);
tmpreg = (uint16_t)((uint16_t)((uint16_t)tmpreg << 8) | ADCx->DRL);
/* Return the selected ADC conversion value */
return (uint16_t)(tmpreg) ;
}
/**
* @}
*/
/** @defgroup ADC_Group5 ADC Channels DMA Configuration function
* @brief ADC Channels DMA Configuration function
*
@verbatim
===============================================================================
ADC Channels DMA Configuration function
===============================================================================
This section provides a function allowing to configure the DMA for ADC
channel.
Since converted channel values are stored into a unique data register,
it is useful to use DMA for conversion of more than one channel. This
avoids the loss of the data already stored in the ADC Data register.
When the DMA mode is enabled (using the ADC_DMACmd() function), after each
conversion of a channel, a DMA request is generated.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified ADC DMA request.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param NewState : new state of the specified ADC DMA transfer.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the specified ADC DMA request */
ADCx->SQR[0] &= (uint8_t)~ADC_SQR1_DMAOFF;
}
else
{
/* Disable the specified ADC DMA request */
ADCx->SQR[0] |= ADC_SQR1_DMAOFF;
}
}
/**
* @}
*/
/** @defgroup ADC_Group6 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
This section provides functions allowing to configure the ADC Interrupts and
get the status and clear flags and Interrupts pending bits.
The ADC provides 3 Interrupt sources and 3 Flags:
Flags :
----------
1. ADC_FLAG_OVR : Overrun detection when ADC channel converted data is lost
2. ADC_FLAG_EOC : End of conversion<6F>- to indicate the end of a regular
CHANNEL conversion or a GROUP conversions, depending of the
ADC Continuous Conversion Mode (Continuous or Single
conversion) and of the DMA usage.
Note : if DMA is used, EOC occurs at the end of the sequence
conversion, else it occurs after each conversion
3. ADC_FLAG_AWD: to indicate if the converted voltage crosses the
programmed Analog watchdog thresholds values.
Interrupts :
------------
1. ADC_IT_OVR : specifies the interrupt source for the Overrun detection event.
2. ADC_IT_EOC : specifies the interrupt source for the End of conversion event.
3. ADC_IT_AWD : specifies the interrupt source for the Analog watchdog event.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified ADC interrupts.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param ADC_IT : specifies the ADC interrupt sources to be enabled or
* disabled.
* This parameter can be one of the following values:
* @arg ADC_IT_EOC: End of Conversion Interrupt
* @arg ADC_IT_AWD: Analog Watchdog Interrupt
* @arg ADC_IT_OVER: Over Run Interrupt
* @param NewState : new state of the specified ADC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void ADC_ITConfig(ADC_TypeDef* ADCx, ADC_IT_TypeDef ADC_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_ADC_IT(ADC_IT));
if (NewState != DISABLE)
{
/* Enable the selected ADC interrupts */
ADCx->CR1 |= (uint8_t) ADC_IT;
}
else
{
/* Disable the selected ADC interrupts */
ADCx->CR1 &= (uint8_t)(~ADC_IT);
}
}
/**
* @brief Checks whether the specified ADC flag is set or not.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param ADC_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg ADC_FLAG_EOC: End of Conversion flag
* @arg ADC_FLAG_AWD: Analog Watchdog flag
* @arg ADC_FLAG_OVER: Over Run flag
* @retval The new state of ADC_FLAG (SET or RESET).
*/
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, ADC_FLAG_TypeDef ADC_FLAG)
{
FlagStatus flagstatus = RESET;
/* Check the parameters */
assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
/* Check the status of the specified ADC flag */
if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
{
/* ADC_FLAG is set */
flagstatus = SET;
}
else
{
/* ADC_FLAG is reset */
flagstatus = RESET;
}
/* Return the ADC_FLAG status */
return flagstatus;
}
/**
* @brief Clears the ADC's pending flags.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param ADC_FLAG: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg ADC_FLAG_EOC: End of Conversion flag
* @arg ADC_FLAG_AWD: Analog Watchdog flag
* @arg ADC_FLAG_OVER: Over Run flag
* @retval None
*/
void ADC_ClearFlag(ADC_TypeDef* ADCx,
ADC_FLAG_TypeDef ADC_FLAG)
{
/* Check the parameters */
assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
/* Clear the selected ADC flags */
ADCx->SR = (uint8_t)~ADC_FLAG;
}
/**
* @brief Checks whether the specified ADC interrupt has occurred or not.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param ADC_IT: specifies the ADC interrupt source to check.
* This parameter can be one of the following values:
* @arg ADC_IT_EOC: End of Conversion Interrupt
* @arg ADC_IT_AWD: Analog Watchdog Interrupt
* @arg ADC_IT_OVER: Over Run Interrupt
* @retval Status of ADC_IT (SET or RESET).
*/
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx,
ADC_IT_TypeDef ADC_IT)
{
ITStatus itstatus = RESET;
uint8_t itmask = 0, enablestatus = 0;
/* Check the parameters */
assert_param(IS_ADC_GET_IT(ADC_IT));
/* Get the ADC IT index */
itmask = (uint8_t)(ADC_IT >> 3);
itmask = (uint8_t)((uint8_t)((uint8_t)(itmask & (uint8_t)0x10) >> 2) | \
(uint8_t)(itmask & (uint8_t)0x03));
/* Get the ADC_IT enable bit status */
enablestatus = (uint8_t)(ADCx->CR1 & (uint8_t)ADC_IT) ;
/* Check the status of the specified ADC interrupt */
if (((ADCx->SR & itmask) != (uint8_t)RESET) && enablestatus)
{
/* ADC_IT is set */
itstatus = SET;
}
else
{
/* ADC_IT is reset */
itstatus = RESET;
}
/* Return the ADC_IT status */
return itstatus;
}
/**
* @brief Clears the ADC<44>s interrupt pending bits.
* @param ADCx where x can be 1 to select the specified ADC peripheral.
* @param ADC_IT: specifies the ADC interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg ADC_IT_EOC: End of Conversion Interrupt
* @arg ADC_IT_AWD: Analog Watchdog Interrupt
* @arg ADC_IT_OVER: Over Run Interrupt
* @retval None
*/
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx,
ADC_IT_TypeDef ADC_IT)
{
uint8_t itmask = 0;
/* Check the parameters */
assert_param(IS_ADC_IT(ADC_IT));
/* Get the ADC IT index */
itmask = (uint8_t)(ADC_IT >> 3);
itmask = (uint8_t)((uint8_t)(((uint8_t)(itmask & (uint8_t)0x10)) >> 2) | \
(uint8_t)(itmask & (uint8_t)0x03));
/* Clear the selected ADC interrupt pending bits */
ADCx->SR = (uint8_t)~itmask;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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firmware/inc/stm8l151x/src/stm8l15x_aes.c Normal file
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@@ -0,0 +1,488 @@
/**
******************************************************************************
* @file stm8l15x_aes.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Advanced Encryption Standard (AES) peripheral:
* - Configuration
* - Read/Write operations
* - DMA transfers management
* - Interrupts and flags management
*
* @verbatim
* ===================================================================
* How to use this driver
* ===================================================================
* 1- Enable AES clock to get write access to AES registers
* using CLK_PeripheralClockConfig(CLK_Peripheral_AES, ENABLE);
*
* 2- Configure the AES operation mode using AES_OperationModeConfig()
*
* 3- If required, enable interrupt source using AES_ITConfig()
*
* 4- If required, when using the DMA mode
* - Configure the DMA using DMA_Init()
* - Enable DMA requests using AES_DMAConfig()
*
* 5- Enable the AES peripheral using AES_Cmd()
*
* 6- Write data/key using AES_WriteSubData() / AES_WriteSubKey()
*
* @endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_aes.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup AES
* @brief AES driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup AES_Private_Functions
* @{
*/
/** @defgroup AES_Group1 Configuration
* @brief Configuration
*
@verbatim
===============================================================================
Configuration
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the AES peripheral.
* @param None.
* @retval None
*/
void AES_DeInit(void)
{
/* Set AES_CR to reset value 0x00, AES_SR is reset by setting ERRC and CCFC bits in CR */
AES->CR = AES_CR_ERRC | AES_CR_CCFC;
AES->DINR = AES_DINR_RESET_VALUE; /* Set AES_DINR to reset value 0x00 */
AES->DOUTR = AES_DOUTR_RESET_VALUE; /* Set AES_DOUTR to reset value 0x00 */
}
/**
* @brief Configures the AES operation mode.
* @param AES_Operation : the selected AES operation mode.
* This parameter can be one of the following values:
* @arg AES_Operation_Encryp: AES in Encryption mode
* @arg AES_Operation_KeyDeriv: AES in Key Derivation mode
* @arg AES_Operation_Decryp: AES in Decryption mode
* @arg AES_Operation_KeyDerivAndDecryp: AES in Key Derivation and Decryption mode
* @note The operation mode must be configured when AES peripheral is disabled.
* @retval None
*/
void AES_OperationModeConfig(AES_Operation_TypeDef AES_Operation)
{
/* Check the parameter */
assert_param(IS_AES_MODE(AES_Operation));
/* Reset the operation mode bits in CR register */
AES->CR &= (uint8_t) (~AES_CR_MODE);
/* Set the new operation mode bits in CR register */
AES->CR |= (uint8_t) (AES_Operation);
}
/**
* @brief Enable the AES peripheral.
* @param NewState : The new state of the AES peripheral.
* This parameter can be: ENABLE or DISABLE.
* @note AES peripheral can be enabled once operation mode is configured using
* AES_OperationModeConfig()
* @retval None
*/
void AES_Cmd(FunctionalState NewState)
{
/* Check the parameter */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
AES->CR |= (uint8_t) AES_CR_EN; /**< AES Enable */
}
else
{
AES->CR &= (uint8_t)(~AES_CR_EN); /**< AES Disable */
}
}
/**
* @}
*/
/** @defgroup AES_Group2 AES Read and Write
* @brief AES Read and Write
*
@verbatim
===============================================================================
AES Read and Write operations
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Write data in DINR register to be processed by AES peripheral.
* @param Data: The data to be processed.
* @note When an unexpected write to DINR register is detected, WRERR flag is
* set.
* @retval None
*/
void AES_WriteSubData(uint8_t Data)
{
/* Write Data */
AES->DINR = Data;
}
/**
* @brief Write key in DINR register.
* @param Key: The key to be used for encryption/decryption.
* @note When an unexpected write to DINR register is detected, WRERR flag is
* set.
* @retval None
*/
void AES_WriteSubKey(uint8_t Key)
{
/* Write key */
AES->DINR = Key;
}
/**
* @brief Returns the data in DOUTR register processed by AES peripheral.
* @note When an unexpected read of DOUTR register is detected, RDERR flag is
* set
* @retval The processed data.
*/
uint8_t AES_ReadSubData(void)
{
return AES->DOUTR;
}
/**
* @brief Returns the DOUTR register content.
* @retval The derivation key.
* @note When an unexpected read of DOUTR register is detected, RDERR flag is
* set.
*/
uint8_t AES_ReadSubKey(void)
{
return AES->DOUTR;
}
/**
* @}
*/
/** @defgroup AES_Group3 DMA transfers management functions
* @brief DMA transfers management function
*
@verbatim
===============================================================================
DMA transfers management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Configures the AES DMA interface.
* @param AES_DMATransfer: Specifies the AES DMA transfer.
* This parameter can be one of the following values:
* @arg AES_DMATransfer_InOut: DMA requests enabled for input/Output transfer phase
* @param NewState Indicates the new state of the AES DMA interface.
* This parameter can be: ENABLE or DISABLE.
* @retval None
* @note CCF bit has no meaning when DMA requests are enabled (DMAEN = 1).
*/
void AES_DMAConfig(AES_DMATransfer_TypeDef AES_DMATransfer, FunctionalState NewState)
{
/* Check the parameter */
assert_param(IS_AES_DMATRANSFER(AES_DMATransfer));
if (NewState != DISABLE)
{
/* Enable the DMA transfer */
AES->CR |= (uint8_t) AES_DMATransfer;
}
else
{
/* Disable the DMA transfer */
AES->CR &= (uint8_t)(~AES_DMATransfer);
}
}
/**
* @}
*/
/** @defgroup AES_Group4 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified AES interrupt.
* @param AES_IT: Specifies the AES interrupt source to enable/disable.
* This parameter can be one of the following values:
* @arg AES_IT_CCIE: Computation Complete interrupt enable
* @arg AES_IT_ERRIE: Error interrupt enable
* @param NewState : The new state of the AES peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void AES_ITConfig(AES_IT_TypeDef AES_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_AES_IT(AES_IT));
if (NewState != DISABLE)
{
AES->CR |= (uint8_t) AES_IT; /**< AES_IT Enable */
}
else
{
AES->CR &= (uint8_t)(~AES_IT); /**< AES_IT Disable */
}
}
/**
* @brief Checks whether the specified AES flag is set or not.
* @param AES_FLAG specifies the flag to check.
* This parameter can be one of the following values:
* @arg AES_FLAG_CCF: Computation Complete Flag
* @arg AES_FLAG_RDERR: Read Error Flag
* @arg AES_FLAG_WRERR: Write Error Flag
* @retval FlagStatus (SET or RESET)
* @note CCF bit has a meaning only when DMA requests are disabled (DMAEN bit = 0).
*/
FlagStatus AES_GetFlagStatus(AES_FLAG_TypeDef AES_FLAG)
{
FlagStatus status = RESET;
/* Check parameters */
assert_param(IS_AES_FLAG(AES_FLAG));
if (AES_FLAG == AES_FLAG_CCF)
{
if ((AES->SR & (uint8_t)AES_FLAG_CCF) != (uint8_t)0x00)
{
/* Computation Complete Flag CCF is set */
status = (FlagStatus) SET;
}
else
{
/* Computation Complete Flag CCF is reset */
status = (FlagStatus) RESET;
}
}
else if (AES_FLAG == AES_FLAG_RDERR)
{
if ((AES->SR & (uint8_t)AES_FLAG_RDERR) != (uint8_t)0x00)
{
/* Read Error Flag RDERR is set */
status = (FlagStatus) SET;
}
else
{
/* Read Error Flag RDERR is reset */
status = (FlagStatus) RESET;
}
}
else
{
if ((AES->SR & (uint8_t)AES_FLAG_WRERR) != (uint8_t)0x00)
{
/* Write Error Flag WRERR is set */
status = (FlagStatus) SET;
}
else
{
/* Write Error Flag WRERR is reset */
status = (FlagStatus) RESET;
}
}
/* Return the AES_FLAG status */
return ((FlagStatus) status);
}
/**
* @brief Clears the AES flags.
* @param AES_FLAG: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg AES_FLAG_CCF: Computation Complete Flag
* @arg AES_FLAG_RDERR: Read Error Flag
* @arg AES_FLAG_WRERR: Write Error Flag
* @retval None
*/
void AES_ClearFlag(AES_FLAG_TypeDef AES_FLAG)
{
/* Check the parameters */
assert_param(IS_AES_FLAG(AES_FLAG));
/* Check if AES_FLAG is AES_FLAG_CCF */
if (AES_FLAG == AES_FLAG_CCF)
{
/* Clear CCF flag by setting CCFC bit */
AES->CR |= (uint8_t) AES_CR_CCFC;
}
else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */
{
/* Clear RDERR and WRERR flags by setting ERRC bit */
AES->CR |= (uint8_t) AES_CR_ERRC;
}
}
/**
* @brief Checks whether the specified AES interrupt has occurred or not.
* @param AES_IT: Specifies the AES interrupt pending bit to check.
* This parameter can be one of the following values:
* @arg AES_IT_CCIE: Computation Complete interrupt enable
* @arg AES_IT_ERRIE: Error interrupt enable
* @retval ITStatus The new state of AES_IT (SET or RESET).
*/
ITStatus AES_GetITStatus(AES_IT_TypeDef AES_IT)
{
ITStatus itstatus = RESET;
BitStatus cciebitstatus, ccfbitstatus = RESET;
/* Check parameters */
assert_param(IS_AES_IT(AES_IT));
cciebitstatus = (BitStatus) (AES->CR & AES_CR_CCIE);
ccfbitstatus = (BitStatus) (AES->SR & AES_SR_CCF);
/* Check if AES_IT is AES_IT_CCIE */
if (AES_IT == AES_IT_CCIE)
{
/* Check the status of the specified AES interrupt */
if (((cciebitstatus) != RESET) && ((ccfbitstatus) != RESET))
{
/* Interrupt occurred */
itstatus = (ITStatus) SET;
}
else
{
/* Interrupt not occurred */
itstatus = (ITStatus) RESET;
}
}
else /* AES_IT is AES_IT_ERRIE */
{
/* Check the status of the specified AES interrupt */
if ((AES->CR & AES_CR_ERRIE) != RESET)
{
/* Check if WRERR or RDERR flags are set */
if ((AES->SR & (uint8_t)(AES_SR_WRERR | AES_SR_RDERR)) != RESET)
{
/* Interrupt occurred */
itstatus = (ITStatus) SET;
}
else
{
/* Interrupt not occurred */
itstatus = (ITStatus) RESET;
}
}
else
{
/* Interrupt not occurred */
itstatus = (ITStatus) RESET;
}
}
/* Return the AES_IT status */
return ((ITStatus)itstatus);
}
/**
* @brief Clears the AES's interrupt pending bits.
* @param AES_IT: specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg AES_IT_CCIE: Computation Complete interrupt enable
* @arg AES_IT_ERRIE: Error interrupt enable
* @retval None
*/
void AES_ClearITPendingBit(AES_IT_TypeDef AES_IT)
{
/* Check the parameters */
assert_param(IS_AES_IT(AES_IT));
/* Check if AES_IT is AES_IT_CCIE */
if (AES_IT == AES_IT_CCIE)
{
/* Clear CCF flag by setting CCFC bit */
AES->CR |= (uint8_t) AES_CR_CCFC;
}
else /* AES_IT is AES_IT_ERRIE */
{
/* Clear RDERR and WRERR flags by setting ERRC bit */
AES->CR |= (uint8_t) AES_CR_ERRC;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_beep.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the BEEPER (BEEP) peripheral:
* - Initialization and Configuration
* - Low Speed Internal Clock(LSI) Calibration
*
* @verbatim
* ===================================================================
* How to use this driver
* ===================================================================
* 1- Make sure that the LS RC clock calibration is performed by the following
* steps:
* - Connect internally the LS clock source to TIM2 channel 1 input
* capture for measurement using BEEP_LSClockToTIMConnectCmd() function
* - Update the BEEP_CSR register by the measured LSI frequency
* --> During this phase the BEEPER must be disabled to avoid
* unwanted interrupts
*
* 2- Configure the output beeper frequency using the BEEP_Init() function
*
* 3- Enable the beeper using the BEEP_Cmd() function
*
* @endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_beep.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup BEEP
* @brief BEEP driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup BEEP_Private_Functions
* @{
*/
/** @defgroup BEEP_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
Initialization and Configuration functions
===============================================================================
This section provides functions allowing to:
- Initialize and configure the Beeper frequency
- Enable and Disable the Beeper output
@endverbatim
* @{
*/
/**
* @brief Deinitializes the BEEP peripheral registers to their default
* reset values.
* @param None
* @retval None
*/
void BEEP_DeInit(void)
{
BEEP->CSR1 = BEEP_CSR1_RESET_VALUE;
BEEP->CSR2 = BEEP_CSR2_RESET_VALUE;
}
/**
* @brief Initializes the BEEP function according to the specified parameters.
* @note The LS RC calibration must be performed before calling this function.
* @param BEEP_Frequency Frequency selection.
* This parameter can be one of the values of @ref BEEP_Frequency_TypeDef.
* @retval None
*/
void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency)
{
/* Check parameter */
assert_param(IS_BEEP_FREQUENCY(BEEP_Frequency));
/* Set a default calibration value if no calibration is done */
if ((BEEP->CSR2 & BEEP_CSR2_BEEPDIV) == BEEP_CSR2_BEEPDIV)
{
BEEP->CSR2 &= (uint8_t)(~BEEP_CSR2_BEEPDIV); /* Clear bits */
BEEP->CSR2 |= BEEP_CALIBRATION_DEFAULT;
}
/* Select the output frequency */
BEEP->CSR2 &= (uint8_t)(~BEEP_CSR2_BEEPSEL);
BEEP->CSR2 |= (uint8_t)(BEEP_Frequency);
}
/**
* @brief Enable or disable the BEEP function.
* @note Initialisation of BEEP and LS RC calibration must be done before.
* @param NewState Indicates the new state of the BEEP function.
* @retval None
*/
void BEEP_Cmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the BEEP peripheral */
BEEP->CSR2 |= BEEP_CSR2_BEEPEN;
}
else
{
/* Disable the BEEP peripheral */
BEEP->CSR2 &= (uint8_t)(~BEEP_CSR2_BEEPEN);
}
}
/**
* @}
*/
/** @defgroup BEEP_Group2 Low Speed Internal Clock(LSI) Calibration functions
* @brief Low Speed Internal Clock(LSI) Calibration functions
*
@verbatim
===============================================================================
Low Speed Internal Clock(LSI) Calibration functions
===============================================================================
This section provides functions allowing to measure and calibrate the internal
low speed clock source to ensure better BEEPER output frequency .
A typical configuration for LSI calibration is done following these steps :
1. Disable the Beeper to avoid any unwanted interrupt using BEEP_Cmd() function
2. Measure the LSI clock frequency by connecting it internally to TIM2 input capture
using BEEP_LSClockToTIMConnectCmd() function.
3. Calibrate the beeper frequency with the measured LSI clock frequency using
BEEP_LSICalibrationConfig() function.
@endverbatim
* @{
*/
/**
* @brief Enable or disable the LS clock source connection to TIM for measurement.
* @param NewState Indicates the new state of the LS clock to TIM connection
* @retval None
*/
void BEEP_LSClockToTIMConnectCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Connect LS clock to TIM for measurement */
BEEP->CSR1 |= BEEP_CSR1_MSR;
}
else
{
/* Disconnect LS clock to TIM */
BEEP->CSR1 &= (uint8_t)(~BEEP_CSR1_MSR);
}
}
/**
* @brief Update CSR register with the measured LSI frequency.
* @note BEEP must be disabled to avoid unwanted interrupts.
* @note Prescaler calculation:
* A is the integer part of LSIFreqkHz/4 and x the decimal part.
* x <= A/(1+2A) is equivalent to A >= x(1+2A)
* and also to 4A >= 4x(1+2A) [F1]
* but we know that A + x = LSIFreqkHz/4 ==> 4x = LSIFreqkHz-4A
* so [F1] can be written :
* 4A >= (LSIFreqkHz-4A)(1+2A)
* @param LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
* @retval None
*/
void BEEP_LSICalibrationConfig(uint32_t LSIFreqHz)
{
uint16_t lsifreqkhz;
uint16_t A;
/* Check parameter */
assert_param(IS_LSI_FREQUENCY(LSIFreqHz));
lsifreqkhz = (uint16_t)(LSIFreqHz / 1000); /* Converts value in kHz */
/* Calculation of BEEPER calibration value */
BEEP->CSR2 &= (uint8_t)(~BEEP_CSR2_BEEPDIV); /* Clear bits */
A = (uint16_t)(lsifreqkhz >> 3U); /* Division by 8, keep integer part only */
if ((8U * A) >= ((lsifreqkhz - (8U * A)) * (1U + (2U * A))))
{
BEEP->CSR2 |= (uint8_t)(A - 2U);
}
else
{
BEEP->CSR2 |= (uint8_t)(A - 1U);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_comp.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the comparators (COMP1 and COMP2) peripheral:
* - Comparators configuration
* - Window mode control
* - Internal Reference Voltage (VREFINT) output
* - Comparator channels trigger configuration
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1- Enable comparators clock using CLK_PeripheralClockConfig(CLK_Peripheral_COMP, ENABLE);
*
* When using COMP1:
* 2- Connect internal reference voltage to COMP1 inverting input
* using COMP_VrefintToCOMP1Connect()
* 3- Close the analog switch number 14 using SYSCFG_RIAnalogSwitchConfig()
* 4- Close the analog switch that corresponds to the pin to be used as
* non inverting input using SYSCFG_RIAnalogSwitchConfig()
* 5- Close the I/O switch of the pin to be used as non inverting input
* using SYSCFG_RIIOSwitchConfig()
* 6- Configure the event detection using COMP_EdgeConfig()
*
* When using COMP2:
* 2- Select the COMP2 inverting input, configure the speed and COMP2
* output redirection using COMP_Init()
* If the inverting input is an external pin, close the I/O channel
* switch using SYSCFG_RIIOSwitchConfig()
* 3- Close I/O Switch that corresponds to the selected pin as
* comparator 2 non inverting input using SYSCFG_RIIOSwitchConfig()
* 4- Configure the event detection using COMP_EdgeConfig()
*
* @note
* 1- COMP1 comparator and ADC can't be used at the same time since
* they share the same ADC switch matrix (analog switches).
*
* 2- When an I/O is used as comparator input, the corresponding GPIO
* registers should be configured in input floating.
*
* 3- Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on
* GPIO pin. They are only internal.
* To get the comparator output level, use COMP_GetOutputLevel() function
* @endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_comp.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup COMP
* @brief COMP driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup COMP_Private_Functions
* @{
*/
/** @defgroup COMP_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
Initialization and Configuration functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the COMPx peripheral registers to their default reset values.
* @param None.
* @retval None.
*/
void COMP_DeInit(void)
{
/* Set COMP->CSR1 to reset value 0x00 */
COMP->CSR1 = (uint8_t) COMP_CSR1_RESET_VALUE;
/* Set COMP->CSR2 to reset value 0x00 */
COMP->CSR2 = (uint8_t) COMP_CSR2_RESET_VALUE;
/* Set COMP->CSR3 to reset value 0xC0 */
COMP->CSR3 = (uint8_t) COMP_CSR3_RESET_VALUE;
/* Set COMP->CSR4 to reset value 0x00 */
COMP->CSR4 = (uint8_t) COMP_CSR4_RESET_VALUE;
/* Set COMP->CSR5 to reset value 0x00 */
COMP->CSR5 = (uint8_t) COMP_CSR5_RESET_VALUE;
}
/**
* @brief Initializes the comparator inverting input, output and speed.
* @note This function configures only COMP2.
* @param COMP_InvertingInput : selects the comparator inverting input.
* This parameter can be one of the following values:
* @arg COMP_InvertingInput_IO: Input/Output on comparator inverting input enable
* @arg COMP_InvertingInput_VREFINT: VREFINT on comparator inverting input enable
* @arg COMP_InvertingInput_3_4VREFINT: 3/4 VREFINT on comparator inverting input enable
* @arg COMP_InvertingInput_1_2VREFINT: 1/2 VREFINT on comparator inverting input enable
* @arg COMP_InvertingInput_1_4VREFINT: 1/4 VREFINT on comparator inverting input enable
* @arg COMP_InvertingInput_DAC1: DAC1 output on comparator inverting input enable
* @arg COMP_InvertingInput_DAC2: DAC2 output on comparator inverting input enable
* @param COMP_OutputSelect : selects the comparator output
* This parameter can be one of the following values:
* @arg COMP_OutputSelect_TIM2IC2: COMP2 output connected to TIM2 Input Capture 2
* @arg COMP_OutputSelect_TIM3IC2: COMP2 output connected to TIM3 Input Capture 2
* @arg COMP_OutputSelect_TIM1BRK: COMP2 output connected to TIM1 Break Input
* @arg COMP_OutputSelect_TIM1OCREFCLR: COMP2 output connected to TIM1 OCREF Clear
* @param COMP_Speed selects the comparator speed
* This parameter can be one of the following values:
* @arg COMP_Speed_Slow: Comparator speed: slow
* @arg COMP_Speed_Fast: Comparator speed: fast
* @retval None.
*/
void COMP_Init(COMP_InvertingInput_Typedef COMP_InvertingInput,
COMP_OutputSelect_Typedef COMP_OutputSelect, COMP_Speed_TypeDef COMP_Speed)
{
/* Check the parameters */
assert_param(IS_COMP_INVERTING_INPUT(COMP_InvertingInput));
assert_param(IS_COMP_OUTPUT(COMP_OutputSelect));
assert_param(IS_COMP_SPEED(COMP_Speed));
/* Reset the INSEL[2:0] bits in CSR3 register */
COMP->CSR3 &= (uint8_t) (~COMP_CSR3_INSEL);
/* Select the comparator inverting input */
COMP->CSR3 |= (uint8_t) COMP_InvertingInput;
/* Reset the OUTSEL[1:0] bits in CSR3 register */
COMP->CSR3 &= (uint8_t) (~COMP_CSR3_OUTSEL);
/* Redirect the comparator output */
COMP->CSR3 |= (uint8_t) COMP_OutputSelect;
/* Reset the comparator speed bit */
COMP->CSR2 &= (uint8_t) (~COMP_CSR2_SPEED);
/* Select the comparator speed */
COMP->CSR2 |= (uint8_t) COMP_Speed;
}
/**
* @brief Enables or disables connection between VREFINT and COMP1 inverting input.
* @param NewState new state of the VREFINT connection to COMP1 inverting input.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void COMP_VrefintToCOMP1Connect(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the comparator */
COMP->CSR3 |= COMP_CSR3_VREFEN;
}
else
{
/* Disable the comparator */
COMP->CSR3 &= (uint8_t)(~COMP_CSR3_VREFEN);
}
}
/**
* @brief Configures the COMP edge detection.
* @param COMP_Selection: selects the comparator.
* This parameter can be one of the following values:
* @arg COMP_Selection_COMP1: Selection of Comparator 1
* @arg COMP_Selection_COMP2: Selection of Comparator 2
* @param COMP_Edge: This parameter can be one of the following values:
* @arg COMP_Edge_Falling: Falling edge selection
* @arg COMP_Edge_Rising: Rising edge selection
* @arg COMP_Edge_Rising_Falling: Rising and Falling edge selection
* @retval None.
*/
void COMP_EdgeConfig(COMP_Selection_TypeDef COMP_Selection, COMP_Edge_TypeDef COMP_Edge)
{
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
assert_param(IS_COMP_EDGE(COMP_Edge));
/* Check if comparator 1 is selected */
if (COMP_Selection == COMP_Selection_COMP1)
{
/* Reset the comparator 1 edge control bits */
COMP->CSR1 &= (uint8_t) (~COMP_CSR1_CMP1);
/* Select the edge detection of comparator 1 output */
COMP->CSR1 |= (uint8_t) COMP_Edge;
}
/* The comparator 2 is selected */
else
{
/* Reset the comparator 2 edge control bits */
COMP->CSR2 &= (uint8_t) (~COMP_CSR2_CMP2);
/* Select the edge detection of comparator 2 output */
COMP->CSR2 |= (uint8_t) COMP_Edge;
}
}
/**
* @brief Returns the output level of the comparator.
* @note Comparators outputs aren't available on GPIO (outputs levels are
* only internal).
* @param COMP_Selection: selects the comparator.
* This parameter can be one of the following values:
* @arg COMP_Selection_COMP1: Selection of Comparator 1
* @arg COMP_Selection_COMP2: Selection of Comparator 2
* @retval Returns the comparator output level
* This value can be one of the following:
* - COMP_OutputLevel_Low: Comparator output level is low
* - COMP_OutputLevel_High: Comparator output level is high
*/
COMP_OutputLevel_TypeDef COMP_GetOutputLevel(COMP_Selection_TypeDef COMP_Selection)
{
uint8_t compout;
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
/* Check if Comparator 1 is selected */
if (COMP_Selection == COMP_Selection_COMP1)
{
/* Check if comparator 1 output level is high */
if ((COMP->CSR1 & COMP_CSR1_CMP1OUT) != (uint8_t) RESET)
{
/* Get Comparator 1 output level */
compout = (COMP_OutputLevel_TypeDef) COMP_OutputLevel_High;
}
/* comparator 1 output level is low */
else
{
/* Get Comparator 1 output level */
compout = (COMP_OutputLevel_TypeDef) COMP_OutputLevel_Low;
}
}
/* Comparator 2 is selected */
else
{
/* Check if comparator 2 output level is high */
if ((COMP->CSR2 & COMP_CSR2_CMP2OUT) != (uint8_t) RESET)
{
/* Get Comparator output level */
compout = (COMP_OutputLevel_TypeDef) COMP_OutputLevel_High;
}
/* comparator 2 output level is low */
else
{
/* Get Comparator 2 output level */
compout = (COMP_OutputLevel_TypeDef) COMP_OutputLevel_Low;
}
}
/* Return the comparator output level */
return (COMP_OutputLevel_TypeDef)(compout);
}
/**
* @}
*/
/** @defgroup COMP_Group2 Window mode control function
* @brief Window mode control function
*
@verbatim
===============================================================================
Window mode control function
===============================================================================
In window mode:
- COMP1 inverting input is fixed to VREFINT defining the first
threshold
- COMP2 inverting input is configurable (DAC_OUT1, VREFINT sub-multiples, ...)
defining the second threshold
- COMP1 and COMP2 non inverting inputs are connected together.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the window mode.
* @param NewState new state of the window mode.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void COMP_WindowCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the window mode */
COMP->CSR3 |= (uint8_t) COMP_CSR3_WNDWE;
}
else
{
/* Disable the window mode */
COMP->CSR3 &= (uint8_t)(~COMP_CSR3_WNDWE);
}
}
/**
* @}
*/
/** @defgroup COMP_Group3 Internal Reference Voltage output function
* @brief Internal Reference Voltage (VREFINT) output function
*
@verbatim
===============================================================================
Internal Reference Voltage (VREFINT) output function
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the output of the internal reference voltage.
* @param NewState : new state of the Vrefint output.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void COMP_VrefintOutputCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the output of internal reference voltage */
COMP->CSR3 |= (uint8_t) COMP_CSR3_VREFOUTEN;
}
else
{
/* Disable the output of internal reference voltage */
COMP->CSR3 &= (uint8_t) (~COMP_CSR3_VREFOUTEN);
}
}
/**
* @}
*/
/** @defgroup COMP_Group4 Comparator channels trigger configuration
* @brief Comparator channels trigger configuration
*
@verbatim
===============================================================================
Comparator channels trigger configuration
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the schmitt trigger.
* @param NewState : new state of the schmitt trigger.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void COMP_SchmittTriggerCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable Schmitt trigger on Input Output switches Channels */
COMP->CSR1 |= (uint8_t) COMP_CSR1_STE;
}
else
{
/* Enable Schmitt trigger on Input Output switches Channels */
COMP->CSR1 &= (uint8_t) (~COMP_CSR1_STE);
}
}
/**
* @brief Enables or disables trigger on the specified input/output group.
* @param COMP_TriggerGroup : specifies the input/output group
* This parameter can be one of the following values:
* @arg COMP_TriggerGroup_InvertingInput: Trigger on comparator 2 inverting input
* @arg COMP_TriggerGroup_NonInvertingInput: Trigger on comparator 2 non inverting input
* @arg COMP_TriggerGroup_VREFINTOutput: Trigger on VREFINT output
* @arg COMP_TriggerGroup_DACOutput: Trigger on DAC output
* @param COMP_TriggerPin : specifies the pin(s) within the input/output group
* This parameter can be one of the following values:
* @arg COMP_TriggerPin_0: Trigger Pin 0
* @arg COMP_TriggerPin_0: Trigger Pin 1
* @arg COMP_TriggerPin_0: Trigger Pin 2
* @param NewState : enable or disable the trigger on the selected pin(s)
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void COMP_TriggerConfig(COMP_TriggerGroup_TypeDef COMP_TriggerGroup,
COMP_TriggerPin_TypeDef COMP_TriggerPin,
FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_COMP_TRIGGERGROUP(COMP_TriggerGroup));
assert_param(IS_COMP_TRIGGERPIN(COMP_TriggerPin));
switch (COMP_TriggerGroup)
{
case COMP_TriggerGroup_InvertingInput:
if (NewState != DISABLE)
{
COMP->CSR4 &= (uint8_t) ~COMP_TriggerPin;
}
else
{
COMP->CSR4 |= (uint8_t) COMP_TriggerPin;
}
break;
case COMP_TriggerGroup_NonInvertingInput:
if (NewState != DISABLE)
{
COMP->CSR4 &= (uint8_t) ~((uint8_t)(COMP_TriggerPin << 3));
}
else
{
COMP->CSR4 |= (uint8_t) (COMP_TriggerPin << 3);
}
break;
case COMP_TriggerGroup_VREFINTOutput:
if (NewState != DISABLE)
{
COMP->CSR5 &= (uint8_t) ~COMP_TriggerPin;
}
else
{
COMP->CSR5 |= (uint8_t) COMP_TriggerPin;
}
break;
case COMP_TriggerGroup_DACOutput:
if (NewState != DISABLE)
{
COMP->CSR5 &= (uint8_t) ~((uint8_t)(COMP_TriggerPin << 3));
}
else
{
COMP->CSR5 |= (uint8_t) (COMP_TriggerPin << 3);
}
break;
default:
break;
}
}
/**
* @}
*/
/** @defgroup COMP_Group5 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the interrupt generation when an event is detected.
* @param COMP_Selection : selects the comparator
* This parameter can be one of the following values:
* @arg COMP_Selection_COMP1: Selection of Comparator 1
* @arg COMP_Selection_COMP2: Selection of Comparator 2
* @param NewState : new state of the COMPx interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void COMP_ITConfig(COMP_Selection_TypeDef COMP_Selection, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Check if Comparator 1 is selected */
if (COMP_Selection == COMP_Selection_COMP1)
{
if (NewState != DISABLE)
{
/* Enable the COMP1 Interrupt source */
COMP->CSR1 |= (uint8_t) COMP_CSR1_IE1;
}
else
{
/* Disable the COMP1 Interrupt source */
COMP->CSR1 &= (uint8_t)(~COMP_CSR1_IE1);
}
}
else /* Comparator 2 is selected */
{
if (NewState != DISABLE)
{
/* Enable the COMP2 Interrupt source */
COMP->CSR2 |= (uint8_t) COMP_CSR2_IE2;
}
else
{
/* Disable the COMP2 Interrupt source */
COMP->CSR2 &= (uint8_t)(~COMP_CSR2_IE2);
}
}
}
/**
* @brief Checks whether the comparator flag is set or not.
* @param COMP_Selection : selects the comparator
* This parameter can be one of the following values:
* @arg COMP_Selection_COMP1: Selection of Comparator 1
* @arg COMP_Selection_COMP2: Selection of Comparator 2
* @retval The new state of COMPx event flag (SET or RESET).
*/
FlagStatus COMP_GetFlagStatus(COMP_Selection_TypeDef COMP_Selection)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
/* Check if COMP1 is selected */
if (COMP_Selection == COMP_Selection_COMP1)
{
if ((COMP->CSR1 & COMP_CSR1_EF1) != (uint8_t) RESET)
{
/* The comparator 1 event flag is set */
bitstatus = SET;
}
else
{
/* The comparator 1 event flag is reset */
bitstatus = RESET;
}
}
else /* COMP2 is selected */
{
if ((COMP->CSR2 & COMP_CSR2_EF2) != (uint8_t) RESET)
{
/* The comparator 2 event flag is set */
bitstatus = SET;
}
else
{
/* The comparator 2 event flag is reset */
bitstatus = RESET;
}
}
/* return the comparator event flag status */
return (FlagStatus)(bitstatus);
}
/**
* @brief Clears the comparator<6F>s pending flag.
* @param COMP_Selection : selects the comparator
* This parameter can be one of the following values:
* @arg COMP_Selection_COMP1: Selection of Comparator 1
* @arg COMP_Selection_COMP2: Selection of Comparator 2
* @retval None.
*/
void COMP_ClearFlag(COMP_Selection_TypeDef COMP_Selection)
{
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
if (COMP_Selection == COMP_Selection_COMP1)
{
/* Clear the flag EF1 (rc_w0) clear this bit by writing 0. */
COMP->CSR1 &= (uint8_t) (~COMP_CSR1_EF1);
}
else
{
/* Clear the flag EF2 (rc_w0) clear this bit by writing 0. */
COMP->CSR2 &= (uint8_t) (~COMP_CSR2_EF2);
}
}
/**
* @brief Checks whether the comparator interrupt has occurred or not.
* @param COMP_Selection : selects the comparator
* This parameter can be one of the following values:
* @arg COMP_Selection_COMP1: Selection of Comparator 1
* @arg COMP_Selection_COMP2: Selection of Comparator 2
* @retval ITStatus : The state of the COMPx event flag (SET or RESET).
*/
ITStatus COMP_GetITStatus(COMP_Selection_TypeDef COMP_Selection)
{
ITStatus bitstatus = RESET;
uint8_t itstatus = 0x00, itenable = 0x00;
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
if (COMP_Selection == COMP_Selection_COMP1)
{
/* Get the EF1 comparator event flag status */
itstatus = (uint8_t) (COMP->CSR1 & COMP_CSR1_EF1);
/* Get the IE1 interrupt enable bit status */
itenable = (uint8_t) (COMP->CSR1 & COMP_CSR1_IE1);
if ((itstatus != (uint8_t) RESET) && (itenable != (uint8_t) RESET))
{
/* the EF1 and IE1 are set */
bitstatus = SET;
}
else
{
/* the EF1 or IE1 is reset */
bitstatus = RESET;
}
}
else
{
/* Get the EF2 comparator event flag value */
itstatus = (uint8_t) (COMP->CSR2 & COMP_CSR2_EF2);
/* Get the IE2 interrupt enable bit value */
itenable = (uint8_t) (COMP->CSR2 & COMP_CSR2_IE2);
if ((itstatus != (uint8_t)RESET) && (itenable != (uint8_t)RESET))
{
/* The EF2 and IE2 are set */
bitstatus = SET;
}
else
{
/* The EF2 or IE2 is reset */
bitstatus = RESET;
}
}
/* Return the COMP interrupt status */
return (ITStatus) bitstatus;
}
/**
* @brief Clears the interrupt pending bits of the comparator.
* @param COMP_Selection : selects the comparator
* This parameter can be one of the following values:
* @arg COMP_Selection_COMP1: Selection of Comparator 1
* @arg COMP_Selection_COMP2: Selection of Comparator 2
* @retval None
*/
void COMP_ClearITPendingBit(COMP_Selection_TypeDef COMP_Selection)
{
/* Check the parameters */
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
if (COMP_Selection == COMP_Selection_COMP1)
{
/* Clear the flag EF1 (rc_w0) clear this bit by writing 0. */
COMP->CSR1 &= (uint8_t) (~COMP_CSR1_EF1);
}
else
{
/* Clear the flag EF2 (rc_w0) clear this bit by writing 0. */
COMP->CSR2 &= (uint8_t) (~COMP_CSR2_EF2);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_dac.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
* - DAC channels configuration: trigger, output buffer, data format
* - DMA management
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* DAC Peripheral features
* ===================================================================
* The device integrates two 12-bit Digital Analog Converters that can
* be used independently or simultaneously (dual mode):
* 1- DAC channel1 with DAC_OUT1 (PF0) as output
* 1- DAC channel2 with DAC_OUT2 (PF1) as output
*
* Digital to Analog conversion can be non-triggered using DAC_Trigger_None
* and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
* DAC_SetChannel1Data()/DAC_SetChannel2Data.
*
* Digital to Analog conversion can be triggered by:
* 1- External event: PE4 using DAC_Trigger_Ext.
* This pin (PE4) must be configured in input mode.
*
* 2- Timers TRGO: TIM4, TIM5
* (DAC_Trigger_T4_TRGO, DAC_Trigger_T5_TRGO)
* The timer TRGO event should be selected using TIMx_SelectOutputTrigger()
*
* 3- Software using DAC_Trigger_Software
*
* Each DAC channel integrates an output buffer that can be used to
* reduce the output impedance, and to drive external loads directly
* without having to add an external operational amplifier.
*
* Refer to the device datasheet for more details about output impedance
* value with and without output buffer.
*
* Both DAC channels can be used to generate
* 1- Noise wave using DAC_Wave_Noise
* 2- Triangle wave using DAC_Wave_Triangle
*
*
* The DAC data format can be:
* 1- 8-bit right alignment using DAC_Align_8b_R
* 2- 12-bit left alignment using DAC_Align_12b_L
* 3- 12-bit right alignment using DAC_Align_12b_R
*
* The analog output voltage on each DAC channel pin is determined
* by the following equation: DAC_OUTx = VREF+ * DOR / 4095
* with DOR is the Data Output Register
* VEF+ is the input voltage reference (refer to the device datasheet)
* e.g. To set DAC_OUT1 to 0.7V, use
* DAC_SetChannel1Data(DAC_Align_12b_R, 868);
* Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
*
* A DMA1 request can be generated when an external trigger (but not
* a software trigger) occurs if DMA1 requests are enabled using
* DAC_DMACmd()
* DMA1 requests are mapped as following:
* 1- DAC channel1 is mapped on DMA1 channel3 which must be already
* configured
* 2- DAC channel2 is mapped on DMA1 channel1 which must be already
* configured
*
* ===================================================================
* How to use this driver
* ===================================================================
* - DAC clock must be enabled to get write access to DAC registers using
* CLK_PeripheralClockConfig(CLK_Peripheral_DAC, ENABLE)
* - Configure DAC_OUTx (DAC_OUT1: PF0, DAC_OUT2: PF1) in analog mode.
* - Configure the DAC channel using DAC_Init()
* - Enable the DAC channel using DAC_Cmd()
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_dac.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup DAC
* @brief DAC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DAC_Private_Functions
* @{
*/
/** @defgroup DAC_Group1 DAC channels configuration
* @brief DAC channels configuration: trigger, output buffer, data format
*
@verbatim
===============================================================================
DAC channels configuration: trigger, output buffer, data format
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the DAC peripheral registers to their default reset values.
* @param None
* @retval None
*/
void DAC_DeInit(void)
{
/* Set Channel1 the Configuration registers to their reset values */
DAC->CH1CR1 = DAC_CR1_RESET_VALUE;
DAC->CH1CR2 = DAC_CR2_RESET_VALUE;
/* Set Channel2 the Configuration registers to their reset values */
DAC->CH2CR1 = DAC_CR1_RESET_VALUE;
DAC->CH2CR2 = DAC_CR2_RESET_VALUE;
/* Set the Software Trigger configuration registers to their reset values */
DAC->SWTRIGR = DAC_SWTRIGR_RESET_VALUE;
/* Set the Status registers to their reset values */
DAC->SR = (uint8_t)~DAC_SR_RESET_VALUE;
/* Set the Channel1 Data holding registers to their reset values */
DAC->CH1RDHRH = DAC_RDHRH_RESET_VALUE;
DAC->CH1RDHRL = DAC_RDHRL_RESET_VALUE;
DAC->CH1LDHRH = DAC_LDHRH_RESET_VALUE;
DAC->CH1LDHRL = DAC_LDHRL_RESET_VALUE;
DAC->CH1DHR8 = DAC_DHR8_RESET_VALUE;
/* Set the Channel2 Data holding registers to their reset values */
DAC->CH2RDHRH = DAC_RDHRH_RESET_VALUE;
DAC->CH2RDHRL = DAC_RDHRL_RESET_VALUE;
DAC->CH2LDHRH = DAC_LDHRH_RESET_VALUE;
DAC->CH2LDHRL = DAC_LDHRL_RESET_VALUE;
DAC->CH2DHR8 = DAC_DHR8_RESET_VALUE;
/* Set the Dual mode 12bit Right Data holding registers to their reset values */
DAC->DCH1RDHRH = DAC_RDHRH_RESET_VALUE;
DAC->DCH1RDHRL = DAC_RDHRL_RESET_VALUE;
DAC->DCH2RDHRH = DAC_RDHRH_RESET_VALUE;
DAC->DCH2RDHRL = DAC_RDHRL_RESET_VALUE;
/* Set the Dual mode 12bit Left Data holding registers to their reset values */
DAC->DCH1LDHRH = DAC_LDHRH_RESET_VALUE;
DAC->DCH1LDHRL = DAC_LDHRL_RESET_VALUE;
DAC->DCH2LDHRH = DAC_LDHRH_RESET_VALUE;
DAC->DCH2LDHRL = DAC_LDHRL_RESET_VALUE;
/* Set the Dual mode 8bit Data holding registers to their reset values */
DAC->DCH1DHR8 = DAC_DHR8_RESET_VALUE;
DAC->DCH2DHR8 = DAC_DHR8_RESET_VALUE;
}
/**
* @brief Initializes the DAC according to the specified parameters.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_Trigger : the selected DAC trigger.
* This parameter can be one of the following values:
* @arg DAC_Trigger_None: DAC trigger None
* @arg DAC_Trigger_T4_TRGO: DAC trigger TIM4 TRGO
* @arg DAC_Trigger_T5_TRGO: DAC trigger TIM5 TRGO
* @arg DAC_Trigger_Ext: DAC trigger External Trigger (PE4)
* @arg DAC_Trigger_Software: DAC trigger software
* @param DAC_OutputBuffer : the status of DAC load Buffer
* This parameter can be one of the following values:
* @arg DAC_OutputBuffer_Enable: DAC output buffer Enabled
* @arg DAC_OutputBuffer_Disable: DAC output buffer Disabled
* @retval None
*/
void DAC_Init(DAC_Channel_TypeDef DAC_Channel,
DAC_Trigger_TypeDef DAC_Trigger,
DAC_OutputBuffer_TypeDef DAC_OutputBuffer)
{
uint8_t tmpreg = 0;
uint16_t tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_TRIGGER(DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_OutputBuffer));
/* Get the DAC CHxCR1 value */
tmpreg2 = (uint16_t)((uint8_t)((uint8_t)DAC_Channel << 1));
tmpreg = *(uint8_t*)((uint16_t)(DAC_BASE + CR1_Offset + tmpreg2));
/* Clear BOFFx, TENx, TSELx bits */
tmpreg &= (uint8_t)~(DAC_CR1_BOFF | DAC_CR1_TEN | DAC_CR1_TSEL );
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg |= (uint8_t)(DAC_OutputBuffer);
/* Configure for the selected DAC channel trigger*/
if (DAC_Trigger != DAC_Trigger_None)
{
/* Set TSELx and TEN bits according to DAC_Trigger value */
tmpreg |= (uint8_t)(DAC_CR1_TEN | DAC_Trigger) ;
}
/* Write to DAC CHxCR1 */
*(uint8_t*)((uint16_t)(DAC_BASE + CR1_Offset + tmpreg2)) = (uint8_t)tmpreg;
}
/**
* @brief Enables or disables the specified DAC channel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the DAC channel.
* This parameter can be: ENABLE or DISABLE.
* @note When the DAC channel is enabled the trigger source can no more
* be modified.
* @retval None
*/
void DAC_Cmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState)
{
uint16_t cr1addr = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Find CHxCR1 register Address */
cr1addr = DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1);
if (NewState != DISABLE)
{
/* Enable the selected DAC channel */
(*(uint8_t*)(cr1addr)) |= DAC_CR1_EN;
}
else
{
/* Disable the selected DAC channel */
(*(uint8_t*)(cr1addr)) &= (uint8_t) ~(DAC_CR1_EN);
}
}
/**
* @brief Enables or disables the selected DAC channel software trigger.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel software trigger.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void DAC_SoftwareTriggerCmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for the selected DAC channel */
DAC->SWTRIGR |= (uint8_t)(DAC_SWTRIGR_SWTRIG1 << DAC_Channel);
}
else
{
/* Disable software trigger for the selected DAC channel */
DAC->SWTRIGR &= (uint8_t)~((uint8_t)(DAC_SWTRIGR_SWTRIG1 << DAC_Channel));
}
}
/**
* @brief Enables or disables simultaneously the two DAC channels software
* triggers.
* @param NewState: new state of the DAC channels software triggers.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable software trigger for both DAC channels */
DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2) ;
}
else
{
/* Disable software trigger for both DAC channels */
DAC->SWTRIGR &= (uint8_t)~(DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2);
}
}
/**
* @brief Enables or disables the selected DAC channel wave generation.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_Wave: Specifies the wave type to enable or disable.
* This parameter can be one of the following values:
* @arg DAC_Wave_Noise: noise wave generation
* @arg DAC_Wave_Triangle: triangle wave generation
* @param NewState: new state of the selected DAC channel wave generation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_WaveGenerationCmd(DAC_Channel_TypeDef DAC_Channel,
DAC_Wave_TypeDef DAC_Wave,
FunctionalState NewState)
{
uint8_t tmpreg = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_WAVE(DAC_Wave));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Get the DAC CHxCR1 value & Clear WAVEN bits */
tmpreg = (uint8_t)((*(uint8_t*)(uint16_t)(DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1))) & (uint8_t)~(DAC_CR1_WAVEN));
if (NewState != DISABLE)
{
tmpreg |= (uint8_t)(DAC_Wave);
}
/* Write to DAC CHxCR1 */
(*(uint8_t*) (uint16_t)(DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1))) = tmpreg;
}
/**
* @brief Select DAC Noise Wave Generation LFSR according to the specified parameters.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_LFSRUnmask : the selected unmasked bit.
* This parameter can be one of the following values:
* @arg DAC_LFSRUnmask_Bit0: Noise LFSR Unmask 1 LSB
* @arg DAC_LFSRUnmask_Bits1_0: Noise LFSR Unmask 2 LSB
* @arg DAC_LFSRUnmask_Bit2_0: Noise LFSR Unmask 3 LSB
* @arg DAC_LFSRUnmask_Bit3_0: Noise LFSR Unmask 4 LSB
* @arg DAC_LFSRUnmask_Bit4_0: Noise LFSR Unmask 5 LSB
* @arg DAC_LFSRUnmask_Bit5_0: Noise LFSR Unmask 6 LSB
* @arg DAC_LFSRUnmask_Bit6_0: Noise LFSR Unmask 7 LSB
* @arg DAC_LFSRUnmask_Bit7_0: Noise LFSR Unmask 8 LSB
* @arg DAC_LFSRUnmask_Bit8_0: Noise LFSR Unmask 9 LSB
* @arg DAC_LFSRUnmask_Bit9_0: Noise LFSR Unmask 10 LSB
* @arg DAC_LFSRUnmask_Bit10_0: Noise LFSR Unmask 11 LSB
* @arg DAC_LFSRUnmask_Bit11_0: Noise LFSR Unmask 12 LSB
* @retval None
*/
void DAC_SetNoiseWaveLFSR(DAC_Channel_TypeDef DAC_Channel, DAC_LFSRUnmask_TypeDef DAC_LFSRUnmask)
{
uint8_t tmpreg = 0;
uint16_t cr2addr = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_LFSRUnmask));
/* Get the DAC CHxCR2 value & Clear MAMPx bits */
cr2addr = (uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1));
tmpreg = (uint8_t)((*(uint8_t*)(cr2addr)) & (uint8_t)~(DAC_CR2_MAMPx));
/* Write to DAC CHxCR2 */
(*(uint8_t*)(cr2addr)) = (uint8_t)( tmpreg | DAC_LFSRUnmask);
}
/**
* @brief Select DAC Triangle Wave Generation Amplitude according to the specified parameters.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_TriangleAmplitude : the selected Amplitude
* This parameter can be one of the following values:
* @arg DAC_TriangleAmplitude_1: Triangle Amplitude = Vref.(1/4096)
* @arg DAC_TriangleAmplitude_3: Triangle Amplitude = Vref.(3/4096)
* @arg DAC_TriangleAmplitude_7: Triangle Amplitude = Vref.(7/4096)
* @arg DAC_TriangleAmplitude_15: Triangle Amplitude = Vref.(15/4096)
* @arg DAC_TriangleAmplitude_31: Triangle Amplitude = Vref.(31/4096)
* @arg DAC_TriangleAmplitude_63: Triangle Amplitude = Vref.(63/4096)
* @arg DAC_TriangleAmplitude_127: Triangle Amplitude = Vref.(127/4096)
* @arg DAC_TriangleAmplitude_255: Triangle Amplitude = Vref.(255/4096)
* @arg DAC_TriangleAmplitude_511: Triangle Amplitude = Vref.(511/4096)
* @arg DAC_TriangleAmplitude_1023: Triangle Amplitude = Vref.(1023/4096)
* @arg DAC_TriangleAmplitude_2047: Triangle Amplitude = Vref.(2047/4096)
* @arg DAC_TriangleAmplitude_4095: Triangle Amplitude = Vref.(4095/4096)
* @retval None
*/
void DAC_SetTriangleWaveAmplitude(DAC_Channel_TypeDef DAC_Channel, DAC_TriangleAmplitude_TypeDef DAC_TriangleAmplitude)
{
uint8_t tmpreg = 0;
uint16_t cr2addr = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_TriangleAmplitude));
/* Get the DAC CHxCR2 value & Clear MAMPx bits */
cr2addr = (uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1));
tmpreg = (uint8_t)((*(uint8_t*)(cr2addr)) & (uint8_t)~(DAC_CR2_MAMPx));
/* Write to DAC CHxCR2 */
(*(uint8_t*)(cr2addr)) = (uint8_t)( tmpreg | DAC_TriangleAmplitude);
}
/**
* @brief Set the specified data holding register value for DAC channel1.
* @param DAC_Align: Specifies the data alignment for DAC channel1.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None.
*/
void DAC_SetChannel1Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data)
{
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
if (DAC_Align != DAC_Align_8b_R)
{
/* Set the DAC channel1 selected data holding register */
*(uint8_t*)((uint16_t)(DAC_BASE + CH1RDHRH_Offset + DAC_Align )) = (uint8_t)(((uint16_t)DAC_Data) >> 8);
*(uint8_t*)((uint16_t)(DAC_BASE + CH1RDHRH_Offset + 1 + DAC_Align )) = (uint8_t)DAC_Data;
}
else
{
/* Check the parameter */
assert_param(IS_DAC_DATA_08R(DAC_Data));
/* Set the DAC channel1 selected data holding register */
DAC->CH1DHR8 = (uint8_t)(DAC_Data);
}
}
/**
* @brief Set the specified data holding register value for DAC channel2.
* @param DAC_Align: Specifies the data alignment for DAC channel2.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data : Data to be loaded in the selected data holding register.
* @retval None.
*/
void DAC_SetChannel2Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data)
{
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
if (DAC_Align != DAC_Align_8b_R)
{
/* Set the DAC channel2 selected data holding register */
*(uint8_t*)((uint16_t)(DAC_BASE + CH2RDHRH_Offset + DAC_Align )) = (uint8_t)(((uint16_t)DAC_Data) >> 8);
*(uint8_t*)((uint16_t)(DAC_BASE + CH2RDHRH_Offset + 1 + DAC_Align )) = (uint8_t)DAC_Data;
}
else
{
/* Check the parameter */
assert_param(IS_DAC_DATA_08R(DAC_Data));
/* Set the DAC channel2 selected data holding register */
DAC->CH2DHR8 = (uint8_t)(DAC_Data);
}
}
/**
* @brief Set the specified data holding register value for dual channel DAC.
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* @arg DAC_Align_8b_R: 8bit right data alignment selected
* @arg DAC_Align_12b_L: 12bit left data alignment selected
* @arg DAC_Align_12b_R: 12bit right data alignment selected
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
* holding register.
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
* holding register.
* @note In dual mode, a unique register access is required to write in both
* DAC channels at the same time.
* @retval None.
*/
void DAC_SetDualChannelData(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data2, uint16_t DAC_Data1)
{
uint16_t dchxrdhrhaddr = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(DAC_Align));
if (DAC_Align != DAC_Align_8b_R)
{
/* Identify the DCHxRDHRH address*/
dchxrdhrhaddr = (uint16_t)(DAC_BASE + DCH1RDHRH_Offset + DAC_Align);
/* Set the DAC channels Dual data holding registers */
*(uint8_t*)(uint16_t)dchxrdhrhaddr = (uint8_t)(((uint16_t)DAC_Data1) >> 8);
*(uint8_t*)(uint16_t)(dchxrdhrhaddr + 1) = (uint8_t)DAC_Data1;
*(uint8_t*)(uint16_t)(dchxrdhrhaddr + 2) = (uint8_t)(((uint16_t)DAC_Data2) >> 8);
*(uint8_t*)(uint16_t)(dchxrdhrhaddr + 3) = (uint8_t)DAC_Data2;
}
else
{
/* Check the parameter */
assert_param(IS_DAC_DATA_08R(DAC_Data1 | DAC_Data2));
/* Set the DAC channels Dual data holding registers */
DAC->DCH1DHR8 = (uint8_t)(DAC_Data1);
DAC->DCH2DHR8 = (uint8_t)(DAC_Data2);
}
}
/**
* @brief Returns the last data output value of the selected DAC channel.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
uint16_t DAC_GetDataOutputValue(DAC_Channel_TypeDef DAC_Channel)
{
uint16_t outputdata = 0;
uint16_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
if ( DAC_Channel == DAC_Channel_1)
{
/* Returns the DAC channel data output register value */
tmp = (uint16_t)((uint16_t)DAC->CH1DORH << 8);
outputdata = (uint16_t)(tmp | (DAC->CH1DORL));
}
else
{
/* Returns the DAC channel data output register value */
tmp = (uint16_t)((uint16_t)DAC->CH2DORH << 8);
outputdata = (uint16_t)(tmp | (DAC->CH2DORL));
}
/* return the selected DAC channel data output value.*/
return (uint16_t)outputdata;
}
/**
* @}
*/
/** @defgroup DAC_Group2 DMA management functions
* @brief DMA management functions
*
@verbatim
===============================================================================
DMA management function
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified DAC channel DMA request.
* When enabled DMA1 is generated when an external trigger occurs
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param NewState: new state of the selected DAC channel DMA request.
* This parameter can be: ENABLE or DISABLE.
* The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel1) which
* must be already configured.
* @retval None
*/
void DAC_DMACmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState)
{
uint16_t cr2addr = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Find CHxCR2 register Address */
cr2addr = DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1);
if (NewState != DISABLE)
{
/* Enable the selected DAC channel DMA request */
(*(uint8_t*)(cr2addr)) |= DAC_CR2_DMAEN;
}
else
{
/* Disable the selected DAC channel DMA request */
(*(uint8_t*)(cr2addr)) &= (uint8_t)~(DAC_CR2_DMAEN);
}
}
/**
* @}
*/
/** @defgroup DAC_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified DAC interrupts.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @note The DMA underrun occurs when a second external trigger arrives before
* the acknowledgement for the first external trigger is received (first request).
* @param NewState: new state of the specified DAC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DAC_ITConfig(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT, FunctionalState NewState)
{
uint16_t cr2addr = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_DAC_IT(DAC_IT));
/* Find CHxCR2 register Address */
cr2addr = DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1);
if (NewState != DISABLE)
{
/* Enable the selected DAC interrupts */
(*(uint8_t*)(cr2addr)) |= (uint8_t)(DAC_IT);
}
else
{
/* Disable the selected DAC interrupts */
(*(uint8_t*)(cr2addr)) &= (uint8_t)(~(DAC_IT));
}
}
/**
* @brief Checks whether the specified DAC flag is set or not.
* @param DAC_Channel: thee selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_FLAG: specifies the flag to check.
* This parameter can be only of the following value:
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
* @note The DMA underrun occurs when a second external trigger arrives before
* the acknowledgement for the first external trigger is received (first request).
* @retval The new state of DAC_FLAG (SET or RESET).
*/
FlagStatus DAC_GetFlagStatus(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG)
{
FlagStatus flagstatus = RESET;
uint8_t flag = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_FLAG(DAC_FLAG));
flag = (uint8_t)(DAC_FLAG << DAC_Channel);
/* Check the status of the specified DAC flag */
if ((DAC->SR & flag ) != (uint8_t)RESET)
{
/* DAC FLAG is set */
flagstatus = SET;
}
else
{
/* DAC FLAG is reset */
flagstatus = RESET;
}
/* Return the DAC FLAG status */
return flagstatus;
}
/**
* @brief Clears the DAC channel's pending flags.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_FLAG: specifies the flag to clear.
* This parameter can be of the following value:
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
* @retval None
*/
void DAC_ClearFlag(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG)
{
uint8_t flag = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_FLAG(DAC_FLAG));
/* identify the selected flag*/
flag = (uint8_t)(DAC_FLAG << DAC_Channel);
/* Clear the selected DAC flag */
DAC->SR = (uint8_t)(~flag);
}
/**
* @brief Checks whether the specified DAC interrupt has occurred or not.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt source to check.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @note The DMA underrun occurs when a second external trigger arrives before
* the acknowledgement for the first external trigger is received (first request).
* @retval The new state of DAC_IT (SET or RESET).
*/
ITStatus DAC_GetITStatus(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT)
{
ITStatus itstatus = RESET;
uint8_t enablestatus = 0;
uint8_t flagstatus = 0;
uint8_t tempreg = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_IT(DAC_IT));
/* identify the status of the IT and its correspondent flag*/
tempreg = *(uint8_t*)(uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 2));
enablestatus = (uint8_t)( tempreg & (uint8_t)((uint8_t)DAC_IT << DAC_Channel));
flagstatus = (uint8_t)(DAC->SR & (uint8_t)(DAC_IT >> ((uint8_t)0x05 - DAC_Channel)));
/* Check the status of the specified DAC interrupt */
if (((flagstatus) != (uint8_t)RESET) && enablestatus)
{
/* DAC IT is set */
itstatus = SET;
}
else
{
/* DAC IT is reset */
itstatus = RESET;
}
/* Return the DAC IT status */
return itstatus;
}
/**
* @brief Clears the DAC channel's interrupt pending bits.
* @param DAC_Channel: the selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_Channel_1: DAC Channel1 selected
* @arg DAC_Channel_2: DAC Channel2 selected
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
* This parameter can be the following values:
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
* @retval None
*/
void DAC_ClearITPendingBit(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(DAC_Channel));
assert_param(IS_DAC_IT(DAC_IT));
/* Clear the selected DAC interrupt pending bits */
DAC->SR = (uint8_t)~(uint8_t)((uint8_t)DAC_IT >> (0x05 - DAC_Channel));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_dma.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides all the DMA firmware functions.
* @brief This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access controller (DMA):
* - Initialization and Configuration
* - Data Counter
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable The DMA controller clock using CLK_PeripheralClockConfig()
* function: CLK_PeripheralClockConfig(CLK_Peripheral_DMA1, ENABLE).
*
* 2. Enable and configure the peripheral to be connected to the DMA
* channel (except for internal SRAM / FLASH memories: no
* initialization is necessary).
*
* 3. For a given Channel, program the Source and Destination
* addresses, the transfer Direction, the Buffer Size, the
* Peripheral and Memory Incrementation mode and Data Size,
* the Circular or Normal mode, the channel transfer Priority
* and the Memory-to-Memory transfer mode (for channel 3 only,
* if needed) using the DMA_Init() function.
*
* 4. Enable the corresponding interrupt(s) using the function
* DMA_ITConfig() if you need to use DMA interrupts.
*
* 5. Enable the DMA channel using the DMA_Cmd() function.
*
* 6. Activate the needed channel Request using PPP_DMACmd() function
* for any PPP peripheral except internal SRAM and FLASH (ie. TIM4,
* USART ...). The function allowing this operation is provided in
* each PPP peripheral driver (ie. TIM4_DMACmd for TIM4 peripheral).
*
* 7. Optionally, you can configure the number of data to be
* transferred when the channel is disabled (ie. after each
* Transfer Complete event or when a Transfer Error occurs) using
* the function DMA_SetCurrDataCounter().
* And you can get the number of remaining data to be transferred
* using the function DMA_GetCurrDataCounter() at run time (when
* the DMA channel is enabled and running).
*
* 8. To control DMA events you can use one of the following
* two methods:
* a- Check on DMA channel flags using the function
* DMA_GetFlagStatus().
* b- Use DMA interrupts through the function DMA_ITConfig()
* at initialization phase and DMA_GetITStatus() function
* into interrupt routines in communication phase.
* After checking on a flag you should clear it using
* DMA_ClearFlag() function. And after checking on an interrupt
* event you should clear it using DMA_ClearITPendingBit()
* function.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_dma.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup DMA
* @brief DMA driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DMA_Private_Functions
* @{
*/
/** @defgroup DMA_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
Initialization and Configuration functions
===============================================================================
This subsection provides functions allowing to initialize the DMA channel
source and destination addresses, incrementation and data sizes, transfer
direction, buffer size, circular/normal mode selection, memory-to-memory mode
selection and channel priority value.
- The DMA_Init() function follows the DMA configuration procedures.
- All DMA channels can be enabled and disabled in the same time using
DMA_GlobalCmd() function.
- The DMA has 4 channels, User can enable or disable channels using
DMA_Cmd() function.
- The timeout duration (number of wait cycles starting from the latest
request) is configured using DMA_SetTimeOut() function. The DMA then waits
until this timeout has elapsed before requesting from the core a high
priority access to the bus.
@endverbatim
* @{
*/
/**
* @brief Deinitializes the DMA Global Status register to its default reset
* values.
* @param None
* @retval None
*/
void DMA_GlobalDeInit(void)
{
/* Disable the DMA */
DMA1->GCSR &= (uint8_t)~(DMA_GCSR_GE);
/* Reset DMA Channelx control register */
DMA1->GCSR = (uint8_t)DMA_GCSR_RESET_VALUE;
}
/**
* @brief Deinitializes the DMA Channelx registers to their default reset
* values.
* @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
* @retval None
*/
void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_CHANNEL(DMA_Channelx));
/* Disable the selected DMA Channelx */
DMA_Channelx->CCR &= (uint8_t)~(DMA_CCR_CE);
/* Reset DMA Channelx control register */
DMA_Channelx->CCR = DMA_CCR_RESET_VALUE;
/* Reset DMA Channelx remaining bytes register */
DMA_Channelx->CNBTR = DMA_CNBTR_RESET_VALUE;
/* Reset DMA Channelx peripheral address register */
if (DMA_Channelx == DMA1_Channel3)
{
DMA_Channelx->CPARH = DMA_C3PARH_RESET_VALUE;
DMA_Channelx->CM0EAR = DMA_C3M0EAR_RESET_VALUE;
}
else
{
DMA_Channelx->CPARH = DMA_CPARH_RESET_VALUE;
}
DMA_Channelx->CPARL = DMA_CPARL_RESET_VALUE;
/* Reset DMA Channelx memory address register */
DMA_Channelx->CM0ARH = DMA_CM0ARH_RESET_VALUE;
DMA_Channelx->CM0ARL = DMA_CM0ARL_RESET_VALUE;
/* Reset interrupt pending bits for DMA Channel */
DMA_Channelx->CSPR = DMA_CSPR_RESET_VALUE;
}
/**
* @brief Initializes the DMA Channelx according to the specified parameters.
* @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
* @param DMA_Memory0BaseAddr: Specifies Memory 0 Base Address
* @param DMA_PeripheralMemory1BaseAddr: Specifies DMA channelx Peripheral
* Base Address (if data is from/to peripheral) or DMA channelx
* Memory1 Base Address (if data is from Memory0 to Memory1).
* @param DMA_BufferSize: Specifies the size of the DMA channelx Buffer.
* This parameter must be a value greater than 0.
* @param DMA_DIR: Specifies the DMA Channelx transfer direction.
* This parameter can be one of the following values:
* @arg DMA_DIR_PeripheralToMemory: Data transfer direction is Peripheral To Memory
* @arg DMA_DIR_MemoryToPeripheral: Data transfer direction is Memory To Peripheral
* @arg DMA_DIR_Memory0ToMemory1: Data transfer direction is Memory0 To Memory 1
* @param DMA_Mode: Specifies the DMA channelx mode.
* This parameter can be one of the following values:
* @arg DMA_Mode_Normal: DMA normal buffer mode
* @arg DMA_Mode_Circular: DMA circular buffer mode
* @param DMA_MemoryIncMode: Specifies the DMA channelx memory Incremental/Decremental mode
* This parameter can be one of the following values:
* @arg DMA_MemoryIncMode_Dec: DMA memory incremented mode is decremental
* @arg DMA_MemoryIncMode_Inc: DMA memory incremented mode is incremental
* @param DMA_Priority: Specifies the DMA channelx priority.
* This parameter can be one of the following values:
* @arg DMA_Priority_Low: Software Priority is Low
* @arg DMA_Priority_Medium: Software Priority is Medium
* @arg DMA_Priority_High: Software Priority is High
* @arg DMA_Priority_VeryHigh: Software Priority is Very High
* @param DMA_MemoryDataSize: Specifies the DMA channelx transfer Data size
* This parameter can be one of the following values:
* @arg DMA_MemoryDataSize_Byte: Memory Data Size is 1 Byte
* @arg DMA_MemoryDataSize_HalfWord: Memory Data Size is 2 Bytes
* @retval None
*/
void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx,
uint32_t DMA_Memory0BaseAddr,
uint16_t DMA_PeripheralMemory1BaseAddr,
uint8_t DMA_BufferSize,
DMA_DIR_TypeDef DMA_DIR,
DMA_Mode_TypeDef DMA_Mode,
DMA_MemoryIncMode_TypeDef DMA_MemoryIncMode,
DMA_Priority_TypeDef DMA_Priority,
DMA_MemoryDataSize_TypeDef DMA_MemoryDataSize )
{
/* Check the parameters */
assert_param(IS_DMA_CHANNEL(DMA_Channelx));
assert_param(IS_DMA_DIR(DMA_DIR));
assert_param(IS_DMA_BUFFER_SIZE(DMA_BufferSize));
assert_param(IS_DMA_MODE(DMA_Mode));
assert_param(IS_DMA_MEMORY_INC_MODE(DMA_MemoryIncMode));
assert_param(IS_DMA_PRIORITY(DMA_Priority));
/*--------------------------- DMA Channelx CCR Configuration ---------------*/
/* Disable the selected DMA Channelx */
DMA_Channelx->CCR &= (uint8_t)~(DMA_CCR_CE);
/* Reset DMA Channelx control register */
DMA_Channelx->CCR = DMA_CCR_RESET_VALUE;
/* Set DMA direction & Mode & Incremental Memory mode */
DMA_Channelx->CCR |= (uint8_t)((uint8_t)((uint8_t)DMA_DIR | \
(uint8_t)DMA_Mode) | \
(uint8_t)DMA_MemoryIncMode);
/*Clear old priority and memory data size option */
DMA_Channelx->CSPR &= (uint8_t)(~(uint8_t)(DMA_CSPR_PL | DMA_CSPR_16BM));
/* Set old priority and memory data size option */
DMA_Channelx->CSPR |= (uint8_t)((uint8_t)DMA_Priority | \
(uint8_t)DMA_MemoryDataSize);
/*--------------------------- DMA Channelx CNDTR Configuration -------------*/
/* Write to DMA Channelx CNDTR */
DMA_Channelx->CNBTR = (uint8_t)DMA_BufferSize;
/*--------------------------- DMA Channelx CPAR Configuration --------------*/
/* Write to DMA Channelx (0, 1 or 2) Peripheral address or Write to
DMA Channel 3 Memory 1 address */
DMA_Channelx->CPARH = (uint8_t)(DMA_PeripheralMemory1BaseAddr >> (uint8_t)8);
DMA_Channelx->CPARL = (uint8_t)(DMA_PeripheralMemory1BaseAddr);
/*--------------------------- DMA Channelx CMAR Configuration --------------*/
/* Write to DMA Channelx Memory address */
if (DMA_Channelx == DMA1_Channel3)
{
DMA_Channelx->CM0EAR = (uint8_t)(DMA_Memory0BaseAddr >> (uint8_t)16);
}
DMA_Channelx->CM0ARH = (uint8_t)(DMA_Memory0BaseAddr >> (uint8_t)8);
DMA_Channelx->CM0ARL = (uint8_t)(DMA_Memory0BaseAddr);
}
/**
* @brief Enables or disables All the DMA.
* @param NewState: new state of the DMA. This parameter can be: ENABLE
* or DISABLE.
* @retval None
*/
void DMA_GlobalCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the DMA */
DMA1->GCSR |= (uint8_t)DMA_GCSR_GE;
}
else
{
/* Disable the DMA */
DMA1->GCSR &= (uint8_t)(~DMA_GCSR_GE);
}
}
/**
* @brief Enables or disables the specified DMA Channelx.
* @note DMA_GlobalCmd function must be called first to enable or disable
* the global DMA.
* @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
* @param NewState: new state of the DMA Channelx.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_CHANNEL(DMA_Channelx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA Channelx */
DMA_Channelx->CCR |= DMA_CCR_CE;
}
else
{
/* Disable the selected DMA Channelx */
DMA_Channelx->CCR &= (uint8_t)(~DMA_CCR_CE);
}
}
/**
* @brief Sets the Time out Value.
* @param DMA_TimeOut: an integer from 0 to 63
* @note If timeout duration >0 (number of wait cycles starting from the
* latest request), the DMA waits until this timeout has elapsed before
* requesting from the core a high priority access to the bus.
* @note If timeout duration =0, there is no timeout and once a request is served,
* the DMA immediately asks to the CPU a high priority access to the bus.
* @retval None
*/
void DMA_SetTimeOut(uint8_t DMA_TimeOut)
{
/* Check the parameters */
assert_param(IS_DMA_TIMEOUT(DMA_TimeOut));
/* set the time out, GB and GE must be = 0 */
DMA1->GCSR = 0;
DMA1->GCSR = (uint8_t)(DMA_TimeOut << (uint8_t)2);
}
/**
* @}
*/
/** @defgroup DMA_Group2 Data Counter functions
* @brief Data Counter functions
*
@verbatim
===============================================================================
Data Counter functions
===============================================================================
This subsection provides functions allowing to configure and read the buffer
size (number of data to be transferred).
The DMA data counter can be written only when the DMA channel is disabled
(ie. after transfer complete event).
The DMA_SetCurrDataCounter() function can be used to write the Channel data
counter value.
Note: It is advised to use this function rather than DMA_Init() (DMA_BufferSize
parameter) in situations where only the Data buffer needs to be reloaded.
The DMA data counter can be read to indicate the number of remaining transfers
for the relative DMA channel. This counter is decremented at the end of each
data transfer and when the transfer is complete:
- If Normal mode is selected: the counter is set to 0.
- If Circular mode is selected: the counter is reloaded with the initial value
(configured before enabling the DMA channel)
The DMA_GetCurrDataCounter() function can be used to read the Channel current
data counter value.
@endverbatim
* @{
*/
/**
* @brief Set the number of data units to transfer for DMA Channelx.
* @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
* @param DataNumber: The number of data units to transfer, it can be any value
* from 0 to 255
* @note It is advised to use this function rather than DMA_Init() in situations
* where only the Data buffer needs to be reloaded.
* @retval None
*/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx, uint8_t DataNumber)
{
/* Check the parameters */
assert_param(IS_DMA_CHANNEL(DMA_Channelx));
/*Set the number of data units for DMA Channelx */
DMA_Channelx->CNBTR = DataNumber;
}
/**
* @brief Returns the number of remaining data units in the current DMA Channelx transfer.
* @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
* @retval The number of remaining data units in the current DMA Channelx
*/
uint8_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_CHANNEL(DMA_Channelx));
/* Return the number of remaining data units for DMA Channelx */
return ((uint8_t)(DMA_Channelx->CNBTR));
}
/**
* @}
*/
/** @defgroup DMA_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
This subsection provides functions allowing to configure the DMA Interrupts
sources and check or clear the flags or pending bits status.
The user should identify which mode will be used in his application to manage
the DMA controller events: Polling mode or Interrupt mode.
Polling Mode
=============
Each DMA channel can be managed through 2 event Flags:
(x: DMA channel number )
1. DMA1_FLAG_TCx: to indicate that a Transfer Complete event occurred
2. DMA1_FLAG_HTx: to indicate that a Half-Transfer Complete event
occurred
In this Mode it is advised to use DMA_GetFlagStatus() and DMA_ClearFlag()
functions.
Interrupt Mode
===============
Each DMA channel can be managed through 2 Interrupts:
Interrupt Source
----------------
1. DMA_IT_TC: specifies the interrupt source for the Transfer Complete
event.
2. DMA_IT_HT: specifies the interrupt source for the Half-transfer
Complete event.
In this Mode it is advised to use DMA_ITConfig(), DMA_GetITStatus() and
DMA_ClearITPendingBit() functions.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified DMA Channelx interrupts.
* @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
* @param DMA_ITx: specifies the DMA interrupts sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg DMA_ITx_TC: Transaction Complete Interrupt
* @arg DMA_ITx_HT: Half Transaction Interrupt
* @param NewState: new state of the specified DMA interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx,
DMA_ITx_TypeDef DMA_ITx,
FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_CHANNEL(DMA_Channelx));
assert_param(IS_DMA_CONFIG_ITX(DMA_ITx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA interrupts */
DMA_Channelx->CCR |= (uint8_t)(DMA_ITx);
}
else
{
/* Disable the selected DMA interrupts */
DMA_Channelx->CCR &= (uint8_t)~(DMA_ITx);
}
}
/**
* @brief Checks whether the specified DMA Channelx flag is set or not.
* @param DMA_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg DMA1_FLAG_GB: Global Busy Flag
* @arg DMA1_FLAG_IFC0: Global Interrupt Flag Channel 0
* @arg DMA1_FLAG_IFC1: Global Interrupt Flag Channel 1
* @arg DMA1_FLAG_IFC2: Global Interrupt Flag Channel 2
* @arg DMA1_FLAG_IFC3: Global Interrupt Flag Channel 3
* @arg DMA1_FLAG_TC0: Transaction Complete Interrupt Flag Channel 0
* @arg DMA1_FLAG_TC1: Transaction Complete Interrupt Flag Channel 1
* @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 2
* @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 3
* @arg DMA1_FLAG_HT0: Half Transaction Interrupt Flag Channel 0
* @arg DMA1_FLAG_HT1: Half Transaction Interrupt Flag Channel 1
* @arg DMA1_FLAG_HT2: Half Transaction Interrupt Flag Channel 2
* @arg DMA1_FLAG_HT3: Half Transaction Interrupt Flag Channel 3
* @arg DMA1_FLAG_PEND0: DMA Request pending on Channel 0
* @arg DMA1_FLAG_PEND1: DMA Request pending on Channel 1
* @arg DMA1_FLAG_PEND2: DMA Request pending on Channel 2
* @arg DMA1_FLAG_PEND3: DMA Request pending on Channel 3
* @arg DMA1_FLAG_BUSY0: No DMA transfer on going in Channel 0
* @arg DMA1_FLAG_BUSY1: No DMA transfer on going in Channel 1
* @arg DMA1_FLAG_BUSY2: No DMA transfer on going in Channel 2
* @arg DMA1_FLAG_BUSY3: No DMA transfer on going in Channel 3
* @retval The status of DMA_FLAG (SET or RESET).
*/
FlagStatus DMA_GetFlagStatus(DMA_FLAG_TypeDef DMA_FLAG)
{
FlagStatus flagstatus = RESET;
DMA_Channel_TypeDef* DMA_Channelx = DMA1_Channel0;
uint8_t tmpgir1 = 0;
uint8_t tmpgcsr = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
/* Get flags registers values*/
tmpgcsr = DMA1->GCSR;
tmpgir1 = DMA1->GIR1;
if (((uint16_t)DMA_FLAG & (uint16_t)0x0F00) != (uint16_t)RESET)
{
/* find the used DMA channel */
if (((uint16_t)DMA_FLAG & 0x0100) != (uint16_t)RESET)
{
DMA_Channelx = DMA1_Channel0;
}
else if (((uint16_t)DMA_FLAG & 0x0200) != (uint16_t)RESET)
{
DMA_Channelx = DMA1_Channel1;
}
else if (((uint16_t)DMA_FLAG & 0x0400) != (uint16_t)RESET)
{
DMA_Channelx = DMA1_Channel2;
}
else
{
DMA_Channelx = DMA1_Channel3;
}
/* Get the specified DMA Channelx flag status. */
flagstatus = (FlagStatus)((uint8_t)(DMA_Channelx->CSPR) & (uint8_t)DMA_FLAG);
}
else if (((uint16_t)DMA_FLAG & 0x1000) != (uint16_t)RESET)
{
/* Get the specified DMA Channelx flag status. */
flagstatus = (FlagStatus)(tmpgir1 & (uint8_t)DMA_FLAG);
}
else /*if ((DMA_FLAG & DMA_FLAG_GB) != (uint16_t)RESET)*/
{
/* Get the specified DMA Channelx flag status. */
flagstatus = (FlagStatus)(tmpgcsr & DMA_GCSR_GB);
}
/* Return the specified DMA Channelx flag status. */
return (flagstatus);
}
/**
* @brief Clears the DMA Channels selected flags.
* @param DMA_FLAG: specifies the flag to clear.
* This parameter can be one or a combination (for the same channel)of
* the following values:
* @arg DMA1_FLAG_TC0: Transaction Complete Interrupt Flag Channel 0
* @arg DMA1_FLAG_TC1: Transaction Complete Interrupt Flag Channel 1
* @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 2
* @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 3
* @arg DMA1_FLAG_HT0: Half Transaction Interrupt Flag Channel 0
* @arg DMA1_FLAG_HT1: Half Transaction Interrupt Flag Channel 1
* @arg DMA1_FLAG_HT2: Half Transaction Interrupt Flag Channel 2
* @arg DMA1_FLAG_HT3: Half Transaction Interrupt Flag Channel 3
* @retval None
*/
void DMA_ClearFlag(DMA_FLAG_TypeDef DMA_FLAG)
{
DMA_Channel_TypeDef* DMA_Channelx = DMA1_Channel0;
/* Check the parameters */
assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
/* Identify the used DMA channel */
if (((uint16_t)DMA_FLAG & (uint16_t)0x0100) != (uint16_t)RESET)
{
DMA_Channelx = DMA1_Channel0;
}
else
{
if (((uint16_t)DMA_FLAG & (uint16_t)0x0200) != (uint16_t)RESET)
{
DMA_Channelx = DMA1_Channel1;
}
else
{
if (((uint16_t)DMA_FLAG & (uint16_t)0x0400) != (uint16_t)RESET)
{
DMA_Channelx = DMA1_Channel2;
}
else
{
DMA_Channelx = DMA1_Channel3;
}
}
}
/*Clears the DMA flags.*/
DMA_Channelx->CSPR &= (uint8_t)~(uint8_t)((uint8_t)DMA_FLAG & (uint8_t)0x06);
}
/**
* @brief Checks whether the specified DMA Channelx interrupt has occurred or not.
* @param DMA_IT: specifies the DMA interrupt source to check.
* This parameter can be one or a combination of the following values:
* @arg DMA1_IT_TC0: Transaction Complete Interrupt Channel 0
* @arg DMA1_IT_TC1: Transaction Complete Interrupt Channel 1
* @arg DMA1_IT_TC2: Transaction Complete Interrupt Channel 2
* @arg DMA1_IT_TC3: Transaction Complete Interrupt Channel 3
* @arg DMA1_IT_HT0: Half Transaction Interrupt Channel 0
* @arg DMA1_IT_HT1: Half Transaction Interrupt Channel 1
* @arg DMA1_IT_HT2: Half Transaction Interrupt Channel 2
* @arg DMA1_IT_HT3: Half Transaction Interrupt Channel 3
* @retval ITStatus: The status of DMA_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(DMA_IT_TypeDef DMA_IT)
{
ITStatus itstatus = RESET;
uint8_t tmpreg = 0;
uint8_t tmp2 = 0;
DMA_Channel_TypeDef* DMA_Channelx = DMA1_Channel0;
/* Check the parameters */
assert_param(IS_DMA_GET_IT(DMA_IT));
/* Identify the used DMA channel */
if ((DMA_IT & 0x10) != (uint8_t)RESET)
{
DMA_Channelx = DMA1_Channel0;
}
else
{
if ((DMA_IT & 0x20) != (uint8_t)RESET)
{
DMA_Channelx = DMA1_Channel1;
}
else
{
if ((DMA_IT & 0x40) != (uint8_t)RESET)
{
DMA_Channelx = DMA1_Channel2;
}
else
{
DMA_Channelx = DMA1_Channel3;
}
}
}
/* Get the specified DMA Channelx interrupt status. */
tmpreg = DMA_Channelx->CSPR ;
tmpreg &= DMA_Channelx->CCR ;
tmp2 = (uint8_t)(DMA_IT & (uint8_t)(DMA_CCR_TCIE | DMA_CCR_HTIE));
itstatus = (ITStatus)((uint8_t)tmpreg & (uint8_t)tmp2);
/* Return the specified DMA Channelx interrupt status. */
return (itstatus);
}
/**
* @brief Clears the DMA Channelx<6C>s interrupt pending bits.
* @param DMA_IT: specifies the DMA interrupt pending bit to clear.
* This parameter can be one or a combination(for the same channel)of
* the following values:
* @arg DMA1_IT_TC0: Transaction Complete Interrupt Channel 0
* @arg DMA1_IT_TC1: Transaction Complete Interrupt Channel 1
* @arg DMA1_IT_TC2: Transaction Complete Interrupt Channel 2
* @arg DMA1_IT_TC3: Transaction Complete Interrupt Channel 3
* @arg DMA1_IT_HT0: Half Transaction Interrupt Channel 0
* @arg DMA1_IT_HT1: Half Transaction Interrupt Channel 1
* @arg DMA1_IT_HT2: Half Transaction Interrupt Channel 2
* @arg DMA1_IT_HT3: Half Transaction Interrupt Channel 3
* @retval None
*/
void DMA_ClearITPendingBit(DMA_IT_TypeDef DMA_IT)
{
DMA_Channel_TypeDef* DMA_Channelx = DMA1_Channel0;
/* Check the parameters */
assert_param(IS_DMA_CLEAR_IT(DMA_IT));
/* Identify the used DMA channel */
if ((DMA_IT & 0x10) != (uint8_t)RESET)
{
DMA_Channelx = DMA1_Channel0;
}
else
{
if ((DMA_IT & 0x20) != (uint8_t)RESET)
{
DMA_Channelx = DMA1_Channel1;
}
else
{
if ((DMA_IT & 0x40) != (uint8_t)RESET)
{
DMA_Channelx = DMA1_Channel2;
}
else
{
DMA_Channelx = DMA1_Channel3;
}
}
}
/*Clears the DMA Channelx<6C>s interrupt pending bits*/
DMA_Channelx->CSPR &= (uint8_t)~(uint8_t)(DMA_IT & (uint8_t)0x06);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

559
firmware/inc/stm8l151x/src/stm8l15x_exti.c Normal file
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@@ -0,0 +1,559 @@
/**
******************************************************************************
* @file stm8l15x_exti.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the EXTI peripheral:
* - Interrupt sensitivity of GPIO ports/pins configuration
* - Interrupt status management
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* This driver provides functions to configure and initialize the EXTI
* peripheral
* These functions are split in 2 groups:
*
* 1. EXTI configuration: this group includes all needed functions
* to configure the EXTI GPIO ports and pins:
* - Set GPIO pins sensitivity
* - Select GPIO port, GPIO half port and set the GPIO port sensitivity
*
* 2. EXTI interrupt status management
* - Get the interrupt status: set/reset
* - Clear interrupt pending bits
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_exti.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup EXTI
* @brief EXTI driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup EXTI_Private_Functions
* @{
*/
/** @defgroup EXTI_Group1 Interrupt sensitivity of GPIO ports/pins configuration
* @brief Interrupt sensitivity of GPIO ports/pins configuration
*
@verbatim
===============================================================================
EXTI configuration functions
===============================================================================
===================================================================
EXTI Driver: how to configure EXTI
===================================================================
To use a GPIO pin as an interrupt source, follow theses steps:
1. Configure the GPIO pin in input mode with interrupt enabled using
GPIO_Init()
2. Configure the GPIO pin sensitivity (falling, rising...) using
EXTI_SetPinSensitivity()
3. Enable global interrupts using enableInterrupts()
4. In the IRQ handler corresponding to the GPIO pin, clear the interrupt
pending bit using EXTI_ClearITPendingBit()
To use a GPIO port as an interrupt source, follows theses steps:
1. Configure the GPIO pins of the same port in input mode with interrupt
enabled using GPIO_Init()
2. Configure the GPIO port sensitivity (falling, rising...) using
EXTI_SetPortSensitivity()
3. Select the GPIO port and the corresponding half port using
EXTI_SelectPort() then EXTI_SetHalfPortSelection()
4. Enable global interrupts using enableInterrupts()
5. In the IRQ handler corresponding to the GPIO port, clear the interrupt
pending bit using EXTI_ClearITPendingBit()
@endverbatim
* @{
*/
/**
* @brief Deinitializes the EXTI registers to their default reset value.
* @param None
* @retval None
*/
void EXTI_DeInit(void)
{
EXTI->CR1 = EXTI_CR1_RESET_VALUE;
EXTI->CR2 = EXTI_CR2_RESET_VALUE;
EXTI->CR3 = EXTI_CR3_RESET_VALUE;
EXTI->CR4 = EXTI_CR4_RESET_VALUE;
EXTI->SR1 = 0xFF; /* Setting SR1 bits in order to clear flags */
EXTI->SR2 = 0xFF; /* Setting SR2 bits in order to clear flags */
EXTI->CONF1 = EXTI_CONF1_RESET_VALUE;
EXTI->CONF2 = EXTI_CONF2_RESET_VALUE;
}
/**
* @brief Sets the external interrupt sensitivity of the selected pin.
* @note Global interrupts must be disabled before calling this function.
* @note The modification of external interrupt sensitivity is only possible
* when he interrupts are disabled.
* @note The normal behavior is to disable the interrupts before calling this
* function, and re-enable them after.
* @param EXTI_Pin : The pin to configure.
* This parameter can be one of the following values:
* @arg EXTI_Pin_0: GPIO Pin 0
* @arg EXTI_Pin_1: GPIO Pin 1
* @arg EXTI_Pin_2: GPIO Pin 2
* @arg EXTI_Pin_3: GPIO Pin 3
* @arg EXTI_Pin_4: GPIO Pin 4
* @arg EXTI_Pin_5: GPIO Pin 5
* @arg EXTI_Pin_6: GPIO Pin 6
* @arg EXTI_Pin_7: GPIO Pin 7
* @param EXTI_Trigger : The external interrupt sensitivity value to set.
* This parameter can be one of the following values:
* @arg EXTI_Trigger_Falling_Low: Interrupt on Falling edge and Low level
* @arg EXTI_Trigger_Rising: Interrupt on Rising edge only
* @arg EXTI_Trigger_Falling: Interrupt on Falling edge only
* @arg EXTI_Trigger_Rising_Falling: Interrupt on Rising and Falling edges
* @retval None
*/
void EXTI_SetPinSensitivity(EXTI_Pin_TypeDef EXTI_Pin, EXTI_Trigger_TypeDef EXTI_Trigger)
{
/* Check function parameters */
assert_param(IS_EXTI_PINNUM(EXTI_Pin));
assert_param(IS_EXTI_TRIGGER(EXTI_Trigger));
/* Clear port sensitivity bits */
switch (EXTI_Pin)
{
case EXTI_Pin_0:
EXTI->CR1 &= (uint8_t)(~EXTI_CR1_P0IS);
EXTI->CR1 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Pin);
break;
case EXTI_Pin_1:
EXTI->CR1 &= (uint8_t)(~EXTI_CR1_P1IS);
EXTI->CR1 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Pin);
break;
case EXTI_Pin_2:
EXTI->CR1 &= (uint8_t)(~EXTI_CR1_P2IS);
EXTI->CR1 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Pin);
break;
case EXTI_Pin_3:
EXTI->CR1 &= (uint8_t)(~EXTI_CR1_P3IS);
EXTI->CR1 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Pin);
break;
case EXTI_Pin_4:
EXTI->CR2 &= (uint8_t)(~EXTI_CR2_P4IS);
EXTI->CR2 |= (uint8_t)((uint8_t)(EXTI_Trigger) << ((uint8_t)EXTI_Pin & (uint8_t)0xEF));
break;
case EXTI_Pin_5:
EXTI->CR2 &= (uint8_t)(~EXTI_CR2_P5IS);
EXTI->CR2 |= (uint8_t)((uint8_t)(EXTI_Trigger) << ((uint8_t)EXTI_Pin & (uint8_t)0xEF));
break;
case EXTI_Pin_6:
EXTI->CR2 &= (uint8_t)(~EXTI_CR2_P6IS);
EXTI->CR2 |= (uint8_t)((uint8_t)(EXTI_Trigger) << ((uint8_t)EXTI_Pin & (uint8_t)0xEF));
break;
case EXTI_Pin_7:
EXTI->CR2 &= (uint8_t)(~EXTI_CR2_P7IS);
EXTI->CR2 |= (uint8_t)((uint8_t)(EXTI_Trigger) << ((uint8_t)EXTI_Pin & (uint8_t)0xEF));
break;
default:
break;
}
}
/**
* @brief Selects the port interrupt selection.
* @param EXTI_Port : The port number to access.
* This parameter can be one of the following values:
* @arg EXTI_Port_B: GPIO Port B
* @arg EXTI_Port_D: GPIO Port D
* @arg EXTI_Port_E: GPIO Port E
* @arg EXTI_Port_F: GPIO Port F
* @arg EXTI_Port_G: GPIO Port G
* @arg EXTI_Port_H: GPIO Port H
* @retval None
*/
void EXTI_SelectPort(EXTI_Port_TypeDef EXTI_Port)
{
/* Check function parameter */
assert_param(IS_EXTI_PORT(EXTI_Port));
if (EXTI_Port == EXTI_Port_B)
{
/* Select Port B by resetting PGBS bit in CONF2 register */
EXTI->CONF2 &= (uint8_t) (~EXTI_CONF2_PGBS);
}
else if (EXTI_Port == EXTI_Port_D)
{
/* Select Port D by resetting PHDS bit in CONF2 register */
EXTI->CONF2 &= (uint8_t) (~EXTI_CONF2_PHDS);
}
else if (EXTI_Port == EXTI_Port_E)
{
/* Select Port E by resetting PFES bit in CONF1 register */
EXTI->CONF1 &= (uint8_t) (~EXTI_CONF1_PFES);
}
else if (EXTI_Port == EXTI_Port_F)
{
/* Select Port F by setting PFES bit in CONF1 register */
EXTI->CONF1 |= (uint8_t) (EXTI_CONF1_PFES);
}
else if (EXTI_Port == EXTI_Port_G)
{
/* Select Port G by setting PGBS bit in CONF2 register */
EXTI->CONF2 |= (uint8_t) (EXTI_CONF2_PGBS);
}
else /* EXTI_Port is EXTI_Port_H */
{
/* Select Port H by setting PHDS bit in CONF2 register */
EXTI->CONF2 |= (uint8_t) (EXTI_CONF2_PHDS);
}
}
/**
* @brief Configures the half port interrupt selection.
* @note This function should be called once the port sensitivity configured,
* otherwise it will not have any effect on the port external interrupt.
* @note This function should be called after EXTI_SelectPort() function which
* selects the port to be used otherwise ports are selected by default
* @param EXTI_HalfPort : The port part to access (MSB or LSB).
* This parameter can be one of the following values:
* @arg EXTI_HalfPort_B_LSB: Interrupt selector PB(3:0)
* @arg EXTI_HalfPort_B_MSB: Interrupt selector PB(7:4)
* @arg EXTI_HalfPort_D_LSB: Interrupt selector PD(3:0)
* @arg EXTI_HalfPort_D_MSB: Interrupt selector PD(7:4)
* @arg EXTI_HalfPort_E_LSB: Interrupt selector PE(3:0)
* @arg EXTI_HalfPort_E_MSB: Interrupt selector PE(7:4)
* @arg EXTI_HalfPort_F_LSB: Interrupt selector PF(3:0)
* @arg EXTI_HalfPort_F_MSB: Interrupt selector PF(7:4)
* @arg EXTI_HalfPort_G_LSB: Interrupt selector PG(3:0)
* @arg EXTI_HalfPort_G_MSB: Interrupt selector PG(7:4)
* @arg EXTI_HalfPort_H_LSB: Interrupt selector PH(3:0)
* @arg EXTI_HalfPort_H_MSB: Interrupt selector PH(7:4)
* @param NewState : The external interrupt new state.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void EXTI_SetHalfPortSelection(EXTI_HalfPort_TypeDef EXTI_HalfPort,
FunctionalState NewState)
{
/* Check function parameters */
assert_param(IS_EXTI_HALFPORT(EXTI_HalfPort));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if ((EXTI_HalfPort & 0x80) == 0x00)
{
if (NewState != DISABLE)
{
/* Enable port interrupt selector */
EXTI->CONF1 |= (uint8_t)EXTI_HalfPort;
}
else /*NewState == DISABLE */
{
/* Disable port interrupt selector */
EXTI->CONF1 &= (uint8_t)(~(uint8_t)EXTI_HalfPort);
}
}
else
{
if (NewState != DISABLE)
{
/* Enable port interrupt selector */
EXTI->CONF2 |= (uint8_t)(EXTI_HalfPort & (uint8_t)0x7F);
}
else /*NewState == DISABLE */
{
/* Disable port interrupt selector */
EXTI->CONF2 &= (uint8_t)(~(uint8_t) (EXTI_HalfPort & (uint8_t)0x7F));
}
}
}
/**
* @brief Sets the external interrupt sensitivity of the selected port.
* @note Global interrupts must be disabled before calling this function.
* @note The modification of external interrupt sensitivity is only possible
* when the interrupts are disabled.
* @note The normal behavior is to disable the interrupts before calling this
* function, and re-enable them after.
* @param EXTI_Port : The port number to access.
* This parameter can be one of the following values:
* @arg EXTI_Port_B: GPIO Port B
* @arg EXTI_Port_D: GPIO Port D
* @arg EXTI_Port_E: GPIO Port E
* @arg EXTI_Port_F: GPIO Port F
* @arg EXTI_Port_G: GPIO Port G
* @arg EXTI_Port_H: GPIO Port H
* @param EXTI_Trigger : The external interrupt sensitivity value to set.
* This parameter can be one of the following values:
* @arg EXTI_Trigger_Falling_Low: Interrupt on Falling edge and Low level
* @arg EXTI_Trigger_Rising: Interrupt on Rising edge only
* @arg EXTI_Trigger_Falling: Interrupt on Falling edge only
* @arg EXTI_Trigger_Rising_Falling: Interrupt on Rising and Falling edges
* @retval None
*/
void EXTI_SetPortSensitivity(EXTI_Port_TypeDef EXTI_Port,
EXTI_Trigger_TypeDef EXTI_Trigger)
{
/* Check function parameters */
assert_param(IS_EXTI_PORT(EXTI_Port));
assert_param(IS_EXTI_TRIGGER(EXTI_Trigger));
/* Ceck if selected port is in EXTI_CR3 register */
if ((EXTI_Port & 0xF0) == 0x00)
{
/* Reset the trigger bits corresponding to EXTI_Port */
EXTI->CR3 &= (uint8_t) (~(uint8_t)((uint8_t)0x03 << EXTI_Port));
/* Write EXTI port trigger */
EXTI->CR3 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Port);
}
else /* selected port is in EXTI_CR4 register */
{
/* Reset the trigger bits corresponding to EXTI_Port */
EXTI->CR4 &= (uint8_t) (~(uint8_t)((uint8_t)0x03 << (EXTI_Port & 0x0F)));
/* Write EXTI port trigger */
EXTI->CR4 |= (uint8_t)(EXTI_Trigger << (EXTI_Port & 0x0F));
}
}
/**
* @brief Gets the external interrupt sensitivity of the selected pin.
* @param EXTI_Pin : The pin number to access.
* This parameter can be one of the following values:
* @arg EXTI_Pin_0: GPIO Pin 0
* @arg EXTI_Pin_1: GPIO Pin 1
* @arg EXTI_Pin_2: GPIO Pin 2
* @arg EXTI_Pin_3: GPIO Pin 3
* @arg EXTI_Pin_4: GPIO Pin 4
* @arg EXTI_Pin_5: GPIO Pin 5
* @arg EXTI_Pin_6: GPIO Pin 6
* @arg EXTI_Pin_7: GPIO Pin 7
* @retval The external interrupt sensitivity of the selected port.
*/
EXTI_Trigger_TypeDef EXTI_GetPinSensitivity(EXTI_Pin_TypeDef EXTI_Pin)
{
uint8_t value = 0;
/* Check function parameters */
assert_param(IS_EXTI_PINNUM(EXTI_Pin));
switch (EXTI_Pin)
{
case EXTI_Pin_0:
value = (uint8_t)(EXTI->CR1 & EXTI_CR1_P0IS);
break;
case EXTI_Pin_1:
value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_P1IS) >> EXTI_Pin_1);
break;
case EXTI_Pin_2:
value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_P2IS) >> EXTI_Pin_2);
break;
case EXTI_Pin_3:
value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_P3IS) >> EXTI_Pin_3);
break;
case EXTI_Pin_4:
value = (uint8_t)(EXTI->CR2 & EXTI_CR2_P4IS);
break;
case EXTI_Pin_5:
value = (uint8_t)((uint8_t)(EXTI->CR2 & EXTI_CR2_P5IS) >> ((uint8_t)EXTI_Pin_5 & (uint8_t)0x0F));
break;
case EXTI_Pin_6:
value = (uint8_t)((uint8_t)(EXTI->CR2 & EXTI_CR2_P6IS) >> ((uint8_t)EXTI_Pin_6 & (uint8_t)0x0F));
break;
case EXTI_Pin_7:
value = (uint8_t)((uint8_t)(EXTI->CR2 & EXTI_CR2_P7IS) >> ((uint8_t)EXTI_Pin_7 & (uint8_t)0x0F));
break;
default:
break;
}
return((EXTI_Trigger_TypeDef)value);
}
/**
* @brief Gets the external interrupt sensitivity of the selected port.
* @param EXTI_Port : The port number to access.
* This parameter can be one of the following values:
* @arg EXTI_Port_B: GPIO Port B
* @arg EXTI_Port_D: GPIO Port D
* @arg EXTI_Port_E: GPIO Port E
* @arg EXTI_Port_F: GPIO Port F
* @arg EXTI_Port_G: GPIO Port G
* @arg EXTI_Port_H: GPIO Port H
* @retval The external interrupt sensitivity of the selected port.
*/
EXTI_Trigger_TypeDef EXTI_GetPortSensitivity(EXTI_Port_TypeDef EXTI_Port)
{
uint8_t portsensitivity = 0;
/* Check function parameters */
assert_param(IS_EXTI_PORT(EXTI_Port));
/* Check if selected port is in EXTI_CR3 */
if ((EXTI_Port & 0xF0) == 0x00)
{
/* Get port sensitivity */
portsensitivity = (uint8_t)((uint8_t)0x03 & (uint8_t)(EXTI->CR3 >> EXTI_Port));
}
/* selected port is in EXTI_CR4 */
else
{
/* Get port sensitivity */
portsensitivity = (uint8_t)((uint8_t)0x03 & (uint8_t)(EXTI->CR4 >> (EXTI_Port & 0x0F)));
}
return((EXTI_Trigger_TypeDef)portsensitivity);
}
/**
* @}
*/
/** @defgroup EXTI_Group2 EXTI Interrupt status management functions
* @brief EXTI Interrupt status management functions
*
@verbatim
===============================================================================
EXTI Interrupt status management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Gets the external interrupt status.
* @param EXTI_IT : Specifies the interrupt to read.
* This parameter can be one of the following values:
* @arg EXTI_IT_Pin0: GPIO Pin 0
* @arg EXTI_IT_Pin1: GPIO Pin 1
* @arg EXTI_IT_Pin2: GPIO Pin 2
* @arg EXTI_IT_Pin3: GPIO Pin 3
* @arg EXTI_IT_Pin4: GPIO Pin 4
* @arg EXTI_IT_Pin5: GPIO Pin 5
* @arg EXTI_IT_Pin6: GPIO Pin 6
* @arg EXTI_IT_Pin7: GPIO Pin 7
* @arg EXTI_IT_PortB: GPIO Port B
* @arg EXTI_IT_PortD: GPIO Port D
* @arg EXTI_IT_PortE: GPIO Port E
* @arg EXTI_IT_PortF: GPIO Port F
* @arg EXTI_IT_PortG: GPIO Port G
* @arg EXTI_IT_PortH: GPIO Port H
* @retval The status of the specified interrupt.
* This parameter can be a SET or RESET
*/
ITStatus EXTI_GetITStatus(EXTI_IT_TypeDef EXTI_IT)
{
ITStatus status = RESET;
/* Check function parameters */
assert_param(IS_EXTI_ITPENDINGBIT(EXTI_IT));
if (((uint16_t)EXTI_IT & (uint16_t)0xFF00) == 0x0100)
{
status = (ITStatus)(EXTI->SR2 & (uint8_t)((uint16_t)EXTI_IT & (uint16_t)0x00FF));
}
else
{
status = (ITStatus)(EXTI->SR1 & ((uint8_t)((uint16_t)EXTI_IT & (uint16_t)0x00FF)));
}
return((ITStatus)status);
}
/**
* @brief Clears the specified interrupt pending bit
* @param EXTI_IT : Specifies the interrupt to clear
* This parameter can be one of the following values:
* @arg EXTI_IT_Pin0: GPIO Pin 0
* @arg EXTI_IT_Pin1: GPIO Pin 1
* @arg EXTI_IT_Pin2: GPIO Pin 2
* @arg EXTI_IT_Pin3: GPIO Pin 3
* @arg EXTI_IT_Pin4: GPIO Pin 4
* @arg EXTI_IT_Pin5: GPIO Pin 5
* @arg EXTI_IT_Pin6: GPIO Pin 6
* @arg EXTI_IT_Pin7: GPIO Pin 7
* @arg EXTI_IT_PortB: GPIO Port B
* @arg EXTI_IT_PortD: GPIO Port D
* @arg EXTI_IT_PortE: GPIO Port E
* @arg EXTI_IT_PortF: GPIO Port F
* @arg EXTI_IT_PortG: GPIO Port G
* @arg EXTI_IT_PortH: GPIO Port H
* @retval None
*/
void EXTI_ClearITPendingBit(EXTI_IT_TypeDef EXTI_IT)
{
uint16_t tempvalue = 0;
/* Check function parameters */
assert_param(IS_EXTI_ITPENDINGBIT(EXTI_IT));
tempvalue = ((uint16_t)EXTI_IT & (uint16_t)0xFF00);
if ( tempvalue == 0x0100)
{
EXTI->SR2 = (uint8_t)((uint16_t)EXTI_IT & (uint16_t)0x00FF);
}
else
{
EXTI->SR1 = (uint8_t) (EXTI_IT);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_gpio.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral:
* - Initialization and Configuration
* - GPIO Read and Write
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Configure the GPIO pin(s) using GPIO_Init()
* Two main configuration are available for each pin:
* - Input: Floating
* Pull-up.
* In Input mode, external interrupt can be enabled or disabled
* - Output: Push-Pull
* Open Drain.
* In output mode, the GPIO pin speed is configurable:
* Slow (2 MHz) or Fast (10MHz).
*
* 2. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
*
* 3. To set/reset GPIO pins sharing the same GPIO port use
* GPIO_SetBits() / GPIO_ResetBits()
*
* 4. To enable external interrupt, the GPIO pin must be configured
* in input mode with interrupt enabled. Interrupt sensitivity
* (rising, falling...) is configurable using
* EXTI_SetPinSensitivity() in the EXTI peripheral driver "stm8l15x_exti.c"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_gpio.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup CLK
* @brief CLK driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Functions
* @{
*/
/** @defgroup GPIO_Group1 Initialization and Configuration
* @brief Initialization and Configuration
*
@verbatim
===============================================================================
Initialization and Configuration
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the GPIOx peripheral registers to their default reset values.
* @param GPIOx: Select the GPIO peripheral number (x = A to I).
* @retval None
*/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
GPIOx->CR2 = GPIO_CR2_RESET_VALUE; /* Reset Control Register 2 */
GPIOx->ODR = GPIO_ODR_RESET_VALUE; /* Reset Output Data Register */
GPIOx->DDR = GPIO_DDR_RESET_VALUE; /* Reset Data Direction Register */
GPIOx->CR1 = GPIO_CR1_RESET_VALUE; /* Reset Control Register 1 */
}
/**
* @brief Initializes the GPIOx according to the specified parameters.
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
* @param GPIO_Pin : This parameter contains the pin number
* This parameter can be one of the following values:
* @arg GPIO_Pin_0: Pin 0
* @arg GPIO_Pin_1: Pin 1
* @arg GPIO_Pin_2: Pin 2
* @arg GPIO_Pin_3: Pin 3
* @arg GPIO_Pin_4: Pin 4
* @arg GPIO_Pin_5: Pin 5
* @arg GPIO_Pin_6: Pin 6
* @arg GPIO_Pin_7: Pin 7
* @param GPIO_Mode : This parameter can be a value of the
* This parameter can be one of the following values:
* @arg GPIO_Mode_In_FL_No_IT: Input floating, no external interrupt
* @arg GPIO_Mode_In_PU_No_IT: Input pull-up, no external interrupt
* @arg GPIO_Mode_In_FL_IT: Input pull-up, external interrupt
* @arg GPIO_Mode_Out_OD_Low_Fast: Output open-drain, low level, 10MHz
* @arg GPIO_Mode_Out_PP_Low_Fast: Output push-pull, low level, 10MHz
* @arg GPIO_Mode_Out_OD_Low_Slow: Output open-drain, low level, 2MHz
* @arg GPIO_Mode_Out_PP_Low_Slow: Output push-pull, low level, 2MHz
* @arg GPIO_Mode_Out_OD_HiZ_Fast: Output open-drain, high-impedance level, 10MHz
* @arg GPIO_Mode_Out_PP_High_Fast: Output push-pull, high level, 10MHz
* @arg GPIO_Mode_Out_OD_HiZ_Slow: Output open-drain, high-impedance level, 2MHz
* @arg GPIO_Mode_Out_PP_High_Slow: Output push-pull, high level, 2MHz
* @retval None
*/
void GPIO_Init(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
{
/*----------------------*/
/* Check the parameters */
/*----------------------*/
assert_param(IS_GPIO_MODE(GPIO_Mode));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Reset corresponding bit to GPIO_Pin in CR2 register */
GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
/*-----------------------------*/
/* Input/Output mode selection */
/*-----------------------------*/
if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x80) != (uint8_t)0x00) /* Output mode */
{
if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x10) != (uint8_t)0x00) /* High level */
{
GPIOx->ODR |= GPIO_Pin;
} else /* Low level */
{
GPIOx->ODR &= (uint8_t)(~(GPIO_Pin));
}
/* Set Output mode */
GPIOx->DDR |= GPIO_Pin;
} else /* Input mode */
{
/* Set Input mode */
GPIOx->DDR &= (uint8_t)(~(GPIO_Pin));
}
/*------------------------------------------------------------------------*/
/* Pull-Up/Float (Input) or Push-Pull/Open-Drain (Output) modes selection */
/*------------------------------------------------------------------------*/
if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x40) != (uint8_t)0x00) /* Pull-Up or Push-Pull */
{
GPIOx->CR1 |= GPIO_Pin;
} else /* Float or Open-Drain */
{
GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
}
/*-----------------------------------------------------*/
/* Interrupt (Input) or Slope (Output) modes selection */
/*-----------------------------------------------------*/
if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x20) != (uint8_t)0x00) /* Interrupt or Slow slope */
{
GPIOx->CR2 |= GPIO_Pin;
} else /* No external interrupt or No slope control */
{
GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
}
}
/**
* @brief Configures the external pull-up on GPIOx pins.
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
* @param GPIO_Pin : Specifies the pin number
* This parameter can be one of the following values:
* @arg GPIO_Pin_0: Pin 0
* @arg GPIO_Pin_1: Pin 1
* @arg GPIO_Pin_2: Pin 2
* @arg GPIO_Pin_3: Pin 3
* @arg GPIO_Pin_4: Pin 4
* @arg GPIO_Pin_5: Pin 5
* @arg GPIO_Pin_6: Pin 6
* @arg GPIO_Pin_7: Pin 7
* @param NewState : The new state of the pull up pin.
* Can be ENABLE or DISABLE
* @retval None
*/
void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE) /* External Pull-Up Set*/
{
GPIOx->CR1 |= GPIO_Pin;
} else /* External Pull-Up Reset*/
{
GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
}
}
/**
* @}
*/
/** @defgroup GPIO_Group2 GPIO Read and Write
* @brief GPIO Read and Write
*
@verbatim
===============================================================================
GPIO Read and Write
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Writes data to the specified GPIO data port.
* @note The port must be configured in output mode.
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
* @param GPIO_PortVal : Specifies the value to be written to the port output
* data register.
* @retval None
*/
void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t GPIO_PortVal)
{
GPIOx->ODR = GPIO_PortVal;
}
/**
* @brief Sets or clears the selected data port bit.
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
* @param GPIO_Pin: Specifies the port bit to be written.
* This parameter can be one of the following values:
* @arg GPIO_Pin_0: Pin 0
* @arg GPIO_Pin_1: Pin 1
* @arg GPIO_Pin_2: Pin 2
* @arg GPIO_Pin_3: Pin 3
* @arg GPIO_Pin_4: Pin 4
* @arg GPIO_Pin_5: Pin 5
* @arg GPIO_Pin_6: Pin 6
* @arg GPIO_Pin_7: Pin 7
* @param GPIO_BitVal: specifies the desired status to be written.
* This parameter can be SET or RESET
* @retval None
*/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction GPIO_BitVal)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_STATE_VALUE(GPIO_BitVal));
if (GPIO_BitVal != RESET)
{
GPIOx->ODR |= GPIO_Pin;
}
else
{
GPIOx->ODR &= (uint8_t)(~GPIO_Pin);
}
}
/**
* @brief Writes high level to the specified GPIO pins.
* @note The port must be configured in output mode.
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
* @param GPIO_Pin : Specifies the pins to be turned high.
* This parameter can be one of the following values:
* @arg GPIO_Pin_0: Pin 0
* @arg GPIO_Pin_1: Pin 1
* @arg GPIO_Pin_2: Pin 2
* @arg GPIO_Pin_3: Pin 3
* @arg GPIO_Pin_4: Pin 4
* @arg GPIO_Pin_5: Pin 5
* @arg GPIO_Pin_6: Pin 6
* @arg GPIO_Pin_7: Pin 7
* @retval None
*/
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
{
GPIOx->ODR |= GPIO_Pin;
}
/**
* @brief Writes low level to the specified GPIO pins.
* @note The port must be configured in output mode.
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
* @param GPIO_Pin : Specifies the pins to be turned low
* This parameter can be one of the following values:
* @arg GPIO_Pin_0: Pin 0
* @arg GPIO_Pin_1: Pin 1
* @arg GPIO_Pin_2: Pin 2
* @arg GPIO_Pin_3: Pin 3
* @arg GPIO_Pin_4: Pin 4
* @arg GPIO_Pin_5: Pin 5
* @arg GPIO_Pin_6: Pin 6
* @arg GPIO_Pin_7: Pin 7
* @retval None
*/
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
{
GPIOx->ODR &= (uint8_t)(~GPIO_Pin);
}
/**
* @brief Toggles the specified GPIO pins.
* @note The port must be configured in output mode.
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
* @param GPIO_Pin : Specifies the pins to be toggled.
* @retval None
*/
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
{
GPIOx->ODR ^= GPIO_Pin;
}
/**
* @brief Reads the specified GPIO input data port.
* @note The port must be configured in input mode.
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
* @retval The GPIOx input data port value.
*/
uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
{
return ((uint8_t)GPIOx->IDR);
}
/**
* @brief Reads the specified GPIO output data port.
* @note The port must be configured in input mode.
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
* @retval The GPIOx output data port value.
*/
uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
return ((uint8_t)GPIOx->ODR);
}
/**
* @brief Reads the specified GPIO input data pin.
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
* @param GPIO_Pin : Specifies the pin number.
* This parameter can be one of the following values:
* @arg GPIO_Pin_0: Pin 0
* @arg GPIO_Pin_1: Pin 1
* @arg GPIO_Pin_2: Pin 2
* @arg GPIO_Pin_3: Pin 3
* @arg GPIO_Pin_4: Pin 4
* @arg GPIO_Pin_5: Pin 5
* @arg GPIO_Pin_6: Pin 6
* @arg GPIO_Pin_7: Pin 7
* @retval BitStatus : GPIO input pin status.
*/
BitStatus GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
{
return ((BitStatus)(GPIOx->IDR & (uint8_t)GPIO_Pin));
}
/**
* @brief Reads the specified GPIO Output data pin.
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
* @param GPIO_Pin : Specifies the pin number
* @retval BitStatus : GPIO output pin status.
*/
BitStatus GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
{
return ((BitStatus)(GPIOx->ODR & (uint8_t)GPIO_Pin));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_irtim.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to configure the IRTIM peripheral.
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* This driver provides functions to:
* 1. Enable the IRTIM peripheral
* 2. Enable the high sink mode on the IRTIM pin
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_irtim.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup IRTIM
* @brief IRTIM driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup IRTIM_Private_Functions
* @{
*/
/** @defgroup IRTIM_Group1 IRTIM configuration functions
* @brief IRTIM configuration functions
*
@verbatim
===============================================================================
IRTIM configuration functions
===============================================================================
===================================================================
IRTIM Driver: how to use it
===================================================================
To generate the infrared remote control signal, perform the following steps:
1. Use TIM2 channel 1 to generate the high frequency carrier signal
by calling TIM2_OC1Init()
2. Use TIM3 channel 1 to generate the modulation envelope by
calling TIM3_OC1Init()
3. Enable the IRTIM peripheral using IRTIM_Cmd()
Note1: When IRTIM peripheral is enabled, TIM2 channel 1 and TIM3 channel 1
become inactive (no signal on output) and can be used as GPIO.
Note2: The high sink LED driver capability (only available on the IRTIM pin)
can be activated using IRTIM_HighSinkODCmd() to sink the high
current needed to directly control an infrared LED
@endverbatim
* @{
*/
/**
* @brief Deinitializes the IRTIM peripheral registers to their default reset values.
* @param None
* @retval None
*/
void IRTIM_DeInit(void)
{
IRTIM->CR = IRTIM_CR_RESET_VALUE;
}
/**
* @brief Enables or disables the IRTIM peripheral.
* @param NewState : The new state of the IRTIM peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void IRTIM_Cmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* set or Reset the EN Bit */
if (NewState == DISABLE)
{
IRTIM->CR &= (uint8_t)(~IRTIM_CR_EN) ;
}
else
{
IRTIM->CR |= IRTIM_CR_EN ;
}
}
/**
* @brief Enables or disables the High sink open drain buffer of the IRTIM peripheral.
* @param NewState : The new state of the High sink open drain buffer.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void IRTIM_HighSinkODCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* set or Reset the EN Bit */
if (NewState == DISABLE)
{
IRTIM->CR &= (uint8_t)(~IRTIM_CR_HSEN) ;
}
else
{
IRTIM->CR |= IRTIM_CR_HSEN ;
}
}
/**
* @}
*/
/** @defgroup IRTIM_Group2 IRITM status management functions
* @brief IRITM status management functions
*
@verbatim
===============================================================================
IRITM status management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the IRTIM device is enabled or not.
* @param None
* @retval state of the IRTIM device.
*/
FunctionalState IRTIM_GetStatus(void)
{
return ((FunctionalState) (IRTIM->CR & IRTIM_CR_EN));
}
/**
* @brief Checks whether the IRTIM High Sink Open Drain buffer is Enabled or not.
* @param None
* @retval state of High Sink Open Drain buffer.
*/
FunctionalState IRTIM_GetHighSinkODStatus(void)
{
return ((FunctionalState)(IRTIM->CR & IRTIM_CR_HSEN));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_itc.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionality of the Interrupt controller (ITC) peripheral:
* - Configuration and management
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_itc.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup ITC
* @brief ITC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup ITC_Private_Functions
* @{
*/
/**
* @brief Utility function used to read CC register.
* @param None
* @retval CPU CC register value
*/
uint8_t ITC_GetCPUCC(void)
{
#ifdef _COSMIC_
_asm("push cc");
_asm("pop a");
return; /* Ignore compiler warning, the returned value is in A register */
#elif defined _RAISONANCE_ /* _RAISONANCE_ */
return _getCC_();
#elif defined(_SDCC_) /* SDCC patch: do same as IAR */
__asm__("push cc");
__asm__("pop a");
#else /* _IAR_ */
asm("push cc");
asm("pop a"); /* Ignore compiler warning, the returned value is in A register */
#endif /* _COSMIC_*/
}
/** @defgroup ITC_Group1 ITC configuration and management functions
* @brief ITC configuration and management functions
*
@verbatim
===============================================================================
ITC configuration and management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the ITC registers to their default reset value.
* @param None
* @retval None
*/
void ITC_DeInit(void)
{
ITC->ISPR1 = ITC_SPRX_RESET_VALUE;
ITC->ISPR2 = ITC_SPRX_RESET_VALUE;
ITC->ISPR3 = ITC_SPRX_RESET_VALUE;
ITC->ISPR4 = ITC_SPRX_RESET_VALUE;
ITC->ISPR5 = ITC_SPRX_RESET_VALUE;
ITC->ISPR6 = ITC_SPRX_RESET_VALUE;
ITC->ISPR7 = ITC_SPRX_RESET_VALUE;
ITC->ISPR8 = ITC_SPRX_RESET_VALUE;
}
/**
* @brief Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
* @param None
* @retval The interrupt software priority bits value.
*/
uint8_t ITC_GetSoftIntStatus(void)
{
return ((uint8_t)(ITC_GetCPUCC() & CPU_SOFT_INT_DISABLED));
}
/**
* @brief Gets the software priority of the specified interrupt source.
* @param IRQn : Specifies the peripheral interrupt source.
* @retval Specifies the software priority of the interrupt source.
*/
ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(IRQn_TypeDef IRQn)
{
uint8_t Value = 0;
uint8_t Mask = 0;
/* Check function parameters */
assert_param(IS_ITC_IRQ(IRQn));
/* Define the mask corresponding to the bits position in the SPR register */
Mask = (uint8_t)(0x03U << ((IRQn % 4U) * 2U));
switch (IRQn)
{
case FLASH_IRQn:
case DMA1_CHANNEL0_1_IRQn:
case DMA1_CHANNEL2_3_IRQn:
Value = (uint8_t)(ITC->ISPR1 & Mask); /* Read software priority */
break;
case EXTIE_F_PVD_IRQn:
#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
case RTC_IRQn:
case EXTIB_IRQn:
case EXTID_IRQn:
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
case RTC_CSSLSE_IRQn:
case EXTIB_IRQn:
case EXTID_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
case RTC_CSSLSE_IRQn:
case EXTIB_G_IRQn:
case EXTID_H_IRQn:
#endif /* STM8L15X_MD */
Value = (uint8_t)(ITC->ISPR2 & Mask); /* Read software priority */
break;
case EXTI0_IRQn:
case EXTI1_IRQn:
case EXTI2_IRQn:
case EXTI3_IRQn:
Value = (uint8_t)(ITC->ISPR3 & Mask); /* Read software priority */
break;
case EXTI4_IRQn:
case EXTI5_IRQn:
case EXTI6_IRQn:
case EXTI7_IRQn:
Value = (uint8_t)(ITC->ISPR4 & Mask); /* Read software priority */
break;
#if defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
case SWITCH_CSS_IRQn:
#else
case SWITCH_CSS_BREAK_DAC_IRQn:
#endif /* STM8L15X_LD */
case ADC1_COMP_IRQn:
#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
case LCD_IRQn:
case TIM2_UPD_OVF_TRG_BRK_IRQn:
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
case TIM2_UPD_OVF_TRG_BRK_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
case LCD_AES_IRQn:
case TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn:
#endif /* STM8L15X_MD */
Value = (uint8_t)(ITC->ISPR5 & Mask); /* Read software priority */
break;
#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
case TIM1_UPD_OVF_TRG_IRQn:
#endif /* STM8L15X_LD */
#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
case TIM2_CC_IRQn:
case TIM3_UPD_OVF_TRG_BRK_IRQn :
case TIM3_CC_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
case TIM2_CC_USART2_RX_IRQn:
case TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn :
case TIM3_CC_USART3_RX_IRQn:
#endif /* STM8L15X_MD */
Value = (uint8_t)(ITC->ISPR6 & Mask); /* Read software priority */
break;
#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
case TIM1_CC_IRQn:
#endif /* STM8L15X_LD */
case TIM4_UPD_OVF_TRG_IRQn:
case SPI1_IRQn:
#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
case USART1_TX_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
case USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn:
#endif /* STM8L15X_MD || STM8L15X_LD */
Value = (uint8_t)(ITC->ISPR7 & Mask); /* Read software priority */
break;
#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
case USART1_RX_IRQn:
case I2C1_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
case USART1_RX_TIM5_CC_IRQn:
case I2C1_SPI2_IRQn:
#endif /* STM8L15X_MD || STM8L15X_LD*/
Value = (uint8_t)(ITC->ISPR8 & Mask); /* Read software priority */
break;
default:
break;
}
Value >>= (uint8_t)((IRQn % 4u) * 2u);
return((ITC_PriorityLevel_TypeDef)Value);
}
/**
* @brief Sets the software priority of the specified interrupt source.
* @note The modification of the software priority is only possible when
* the interrupts are disabled.
* @note The normal behavior is to disable the interrupt before calling
* this function, and re-enable it after.
* @note The priority level 0 cannot be set (see product specification
* for more details).
* @param IRQn : Specifies the peripheral interrupt source.
* @param ITC_PriorityLevel : Specifies the software priority value to set
* This parameter can be one of the following values:
* @arg ITC_PriorityLevel_0: Software priority level 0 (cannot be written)
* @arg ITC_PriorityLevel_1: Software priority level 1
* @arg ITC_PriorityLevel_2: Software priority level 2
* @arg ITC_PriorityLevel_3: Software priority level 3
* @retval None
*/
void ITC_SetSoftwarePriority(IRQn_TypeDef IRQn, ITC_PriorityLevel_TypeDef ITC_PriorityLevel)
{
uint8_t Mask = 0;
uint8_t NewPriority = 0;
/* Check function parameters */
assert_param(IS_ITC_IRQ(IRQn));
assert_param(IS_ITC_PRIORITY(ITC_PriorityLevel));
/* Check if interrupts are disabled */
assert_param(IS_ITC_INTERRUPTS_DISABLED);
/* Define the mask corresponding to the bits position in the SPR register */
/* The mask is reversed in order to clear the 2 bits after more easily */
Mask = (uint8_t)(~(uint8_t)(0x03U << ((IRQn % 4U) * 2U)));
/* Define the new priority to write */
NewPriority = (uint8_t)((uint8_t)(ITC_PriorityLevel) << ((IRQn % 4U) * 2U));
switch (IRQn)
{
case FLASH_IRQn:
case DMA1_CHANNEL0_1_IRQn:
case DMA1_CHANNEL2_3_IRQn:
ITC->ISPR1 &= Mask;
ITC->ISPR1 |= NewPriority;
break;
case EXTIE_F_PVD_IRQn:
#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
case RTC_IRQn:
case EXTIB_IRQn:
case EXTID_IRQn:
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
case RTC_CSSLSE_IRQn:
case EXTIB_IRQn:
case EXTID_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
case RTC_CSSLSE_IRQn:
case EXTIB_G_IRQn:
case EXTID_H_IRQn:
#endif /* STM8L15X_MD */
ITC->ISPR2 &= Mask;
ITC->ISPR2 |= NewPriority;
break;
case EXTI0_IRQn:
case EXTI1_IRQn:
case EXTI2_IRQn:
case EXTI3_IRQn:
ITC->ISPR3 &= Mask;
ITC->ISPR3 |= NewPriority;
break;
case EXTI4_IRQn:
case EXTI5_IRQn:
case EXTI6_IRQn:
case EXTI7_IRQn:
ITC->ISPR4 &= Mask;
ITC->ISPR4 |= NewPriority;
break;
#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
case SWITCH_CSS_BREAK_DAC_IRQn:
#else
case SWITCH_CSS_IRQn:
#endif /* STM8L15X_LD */
case ADC1_COMP_IRQn:
#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
case LCD_IRQn:
case TIM2_UPD_OVF_TRG_BRK_IRQn:
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
case TIM2_UPD_OVF_TRG_BRK_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
case LCD_AES_IRQn:
case TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn:
#endif /* STM8L15X_MD */
ITC->ISPR5 &= Mask;
ITC->ISPR5 |= NewPriority;
break;
#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
case TIM1_UPD_OVF_TRG_IRQn:
#endif /* STM8L15X_LD */
#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
case TIM2_CC_IRQn:
case TIM3_UPD_OVF_TRG_BRK_IRQn :
case TIM3_CC_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
case TIM2_CC_USART2_RX_IRQn:
case TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn :
case TIM3_CC_USART3_RX_IRQn:
#endif /* STM8L15X_MD */
ITC->ISPR6 &= Mask;
ITC->ISPR6 |= NewPriority;
break;
#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
case TIM1_CC_IRQn:
#endif /* STM8L15X_LD */
case TIM4_UPD_OVF_TRG_IRQn:
case SPI1_IRQn:
#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
case USART1_TX_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
case USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn:
#endif /* STM8L15X_MD */
ITC->ISPR7 &= Mask;
ITC->ISPR7 |= NewPriority;
break;
#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
case USART1_RX_IRQn:
case I2C1_IRQn:
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
case USART1_RX_TIM5_CC_IRQn:
case I2C1_SPI2_IRQn:
#endif /* STM8L15X_MD */
ITC->ISPR8 &= Mask;
ITC->ISPR8 |= NewPriority;
break;
default:
break;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
********************************************************************************
* @file stm8l15x_iwdg.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Independent watchdog (IWDG) peripheral:
* - Prescaler and Counter configuration
* - IWDG activation
*
* @verbatim
*
* ===================================================================
* IWDG features
* ===================================================================
*
* The IWDG can be started by either software or hardware (configurable
* through option byte).
*
* The IWDG is clocked by its own dedicated low-speed clock (LSI) and
* thus stays active even if the main clock fails.
* Once the IWDG is started, the LSI is forced ON and cannot be disabled
* (LSI cannot be disabled too), and the counter starts counting down from
* the reset value of 0xFF. When it reaches the end of count value (0x00)
* a system reset is generated.
* The IWDG counter should be reloaded at regular intervals to prevent
* an MCU reset.
*
* The IWDG is implemented in the VDD voltage domain that is still functional
* in Halt and Active Halt mode depending on the configuration of the IWDG_HALT
* option byte. (IWDG reset can wake-up from Halt).
*
* IWDGF flag in RST_SR register can be used to inform when a IWDG
* reset occurs.
*
* Min-max timeout value @38KHz (LSI): 0.10 ms / ~1.724s
* The IWDG timeout may vary due to LSI frequency dispersion. STM8L15x
* devices provide the capability to measure the LSI frequency (LSI clock
* connected internally to TIM2 CH1 input capture). The measured value
* can be used to have an IWDG timeout with an acceptable accuracy.
* For more information, please refer to the STM8L15x Reference manual
*
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable write access to IWDG_PR and IWDG_RLR registers using
* IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
*
* 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function
*
* 3. Configure the IWDG counter value using IWDG_SetReload() function.
* This value will be loaded in the IWDG counter each time the counter
* is reloaded, then the IWDG will start counting down from this value.
*
* 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used
* in software mode (no need to enable the LSI, it will be enabled
* by hardware)
*
* 5. Then the application program must reload the IWDG counter at regular
* intervals during normal operation to prevent an MCU reset, using
* IWDG_ReloadCounter() function.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_iwdg.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup IWDG
* @brief IWDG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup IWDG_Private_Functions
* @{
*/
/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
* @brief Prescaler and Counter configuration functions
*
@verbatim
===============================================================================
Prescaler and Counter configuration functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
* This parameter can be one of the following values:
* @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
* @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
* @retval None
*/
void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
{
/* Check the parameters */
assert_param(IS_IWDG_WRITE_ACCESS_MODE(IWDG_WriteAccess));
IWDG->KR = IWDG_WriteAccess; /* Write Access */
}
/**
* @brief Sets IWDG Prescaler value.
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
* This parameter can be one of the following values:
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
* @retval None
*/
void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler)
{
/* Check the parameters */
assert_param(IS_IWDG_PRESCALER_VALUE(IWDG_Prescaler));
IWDG->PR = IWDG_Prescaler;
}
/**
* @brief Sets IWDG Reload value.
* @note Write access should be enabled
* @param IWDG_Reload : Reload register value.
* This parameter must be a number between 0 and 0xFF.
* @retval None
*/
void IWDG_SetReload(uint8_t IWDG_Reload)
{
IWDG->RLR = IWDG_Reload;
}
/**
* @brief Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param None
* @retval None
*/
void IWDG_ReloadCounter(void)
{
IWDG->KR = IWDG_KEY_REFRESH;
}
/**
* @}
*/
/** @defgroup IWDG_Group2 IWDG activation function
* @brief IWDG activation function
*
@verbatim
===============================================================================
IWDG activation function
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param None
* @retval None
*/
void IWDG_Enable(void)
{
IWDG->KR = IWDG_KEY_ENABLE;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_lcd.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the LCD controller (LCD) peripheral:
* - Initialization and configuration
* - LCD RAM memory write
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* LCD Clock
* ===================================================================
* LCD has tow clock sources:
* - RTCCLK divided by 2 used to generate LCD frame rate
* - LCDCLK to used for LCD registers read/write access
*
* To configure the RTCCLK/LCDCLK, proceed as follows:
* - Enable RTC clock using CLK_PeripheralClockConfig(CLK_Peripheral_RTC, ENABLE)
* function
* - Enable LCD clock using CLK_PeripheralClockConfig(CLK_Peripheral_LCD, ENABLE)
* function
* - Select the RTC clock source using the CLK_RTCClockConfig() function.
*
* ===================================================================
* LCD and low power modes
* ===================================================================
* The LCD remains active during Active-halt, Wait, Low power run and
* Low power wait modes unless disabled
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable RTC clock using CLK_PeripheralClockConfig(CLK_Peripheral_RTC, ENABLE) function
*
* 2. Enable LCD clock using CLK_PeripheralClockConfig(CLK_Peripheral_LCD, ENABLE) function
*
* 3. Select the RTC clock source using the CLK_RTCClockConfig() function.
*
* 4. Configure the LCD prescaler, divider, duty, bias and voltage source
* using LCD_Init() function
*
* 5. Call the LCD_PortMaskConfig() function to assign the unused SEGx
* (segment) and COMx (common) pins as standard general purpose IOs
*
* 6. Optionally you can enable/configure:
* - LCD High Drive using the LCD_HighDriveCmd() function
* - LCD Pulse ON Duration using the LCD_PulseOnDurationConfig() function
* - LCD Dead Time using the LCD_DeadTimeConfig() function
* - The LCD Blink mode and frequency using the LCD_BlinkConfig() function
* - The LCD Contrast using the LCD_ContrastConfig() function
*
* 7. Call the LCD_Cmd() to enable the LCD controller
*
* 8. Write to the LCD RAM memory using the LCD_WriteRAM() function.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_lcd.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup LCD
* @brief LCD driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup LCD_Private_Functions
* @{
*/
/** @defgroup LCD_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
Initialization and Configuration functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the LCD Controller registers to their default reset values.
* @param None
* @retval None
*/
void LCD_DeInit(void)
{
uint8_t counter = 0;
LCD->CR1 = LCD_CR1_RESET_VALUE;
LCD->CR2 = LCD_CR2_RESET_VALUE;
LCD->CR3 = LCD_CR3_RESET_VALUE;
LCD->FRQ = LCD_FRQ_RESET_VALUE;
for (counter = 0;counter < 0x05; counter++)
{
LCD->PM[counter] = LCD_PM_RESET_VALUE;
}
for (counter = 0;counter < 0x16; counter++)
{
LCD->RAM[counter] = LCD_RAM_RESET_VALUE;
}
LCD->CR4 = LCD_CR4_RESET_VALUE;
}
/**
* @brief Initializes the LCD according to the specified parameters.
* @param LCD_CLKPrescalerDiv : LCD clock prescaler
* This parameter can be one of the following values:
* @arg LCD_Prescaler_1: CLKprescaler = ClKinput
* @arg LCD_Prescaler_2: CLKprescaler = ClKinput/2
* @arg LCD_Prescaler_4: CLKprescaler = ClKinput/4
* @arg LCD_Prescaler_8: CLKprescaler = ClKinput/8
* @arg LCD_Prescaler_16: CLKprescaler = ClKinput/16
* @arg LCD_Prescaler_32: CLKprescaler = ClKinput/32
* @arg LCD_Prescaler_64: CLKprescaler = ClKinput/64
* @arg LCD_Prescaler_128: CLKprescaler = ClKinput/128
* @arg LCD_Prescaler_256: CLKprescaler = ClKinput/256
* @arg LCD_Prescaler_512: CLKprescaler = ClKinput/512
* @arg LCD_Prescaler_1024: CLKprescaler = ClKinput/1024
* @arg LCD_Prescaler_2048: CLKprescaler = ClKinput/2048
* @arg LCD_Prescaler_4096: CLKprescaler = ClKinput/4096
* @arg LCD_Prescaler_8192: CLKprescaler = ClKinput/8192
* @arg LCD_Prescaler_16384: CLKprescaler = ClKinput/16384
* @arg LCD_Prescaler_32768: CLKprescaler = ClKinput/32768
* @param LCD_Divider : LCD clock divider
* This parameter can be one of the following values:
* @arg LCD_Divider_16: LCD frequency = CLKprescaler/16
* @arg LCD_Divider_17: LCD frequency = CLKprescaler/17
* @arg LCD_Divider_18: LCD frequency = CLKprescaler/18
* @arg LCD_Divider_19: LCD frequency = CLKprescaler/19
* @arg LCD_Divider_20: LCD frequency = CLKprescaler/20
* @arg LCD_Divider_21: LCD frequency = CLKprescaler/21
* @arg LCD_Divider_22: LCD frequency = CLKprescaler/22
* @arg LCD_Divider_23: LCD frequency = CLKprescaler/23
* @arg LCD_Divider_24: LCD frequency = CLKprescaler/24
* @arg LCD_Divider_25: LCD frequency = CLKprescaler/25
* @arg LCD_Divider_26: LCD frequency = CLKprescaler/26
* @arg LCD_Divider_27: LCD frequency = CLKprescaler/27
* @arg LCD_Divider_28: LCD frequency = CLKprescaler/28
* @arg LCD_Divider_29: LCD frequency = CLKprescaler/29
* @arg LCD_Divider_30: LCD frequency = CLKprescaler/30
* @arg LCD_Divider_31: LCD frequency = CLKprescaler/31
* @param LCD_Duty : LCD duty
* This parameter can be one of the following values:
* @arg LCD_Duty_Static: Static duty
* @arg LCD_Duty_1_2: 1/2 duty
* @arg LCD_Duty_1_3: 1/3 duty
* @arg LCD_Duty_1_4: 1/4 duty
* @arg LCD_Duty_1_8: 1/8 duty
* @param LCD_Bias : LCD bias
* This parameter can be one of the following values:
* @arg LCD_Bias_1_4: 1/4 bias
* @arg LCD_Bias_1_3: 1/3 bias
* @arg LCD_Bias_1_2: 1/2 bias
* @param LCD_VoltageSource : LCD voltage source
* This parameter can be one of the following values:
* @arg LCD_VoltageSource_Internal: Internal voltage source
* @arg LCD_VoltageSource_External: External voltage source
* @retval None
*/
void LCD_Init(LCD_Prescaler_TypeDef LCD_Prescaler, LCD_Divider_TypeDef LCD_Divider,
LCD_Duty_TypeDef LCD_Duty, LCD_Bias_TypeDef LCD_Bias,
LCD_VoltageSource_TypeDef LCD_VoltageSource)
{
/* Check function parameters */
assert_param(IS_LCD_CLOCK_PRESCALER(LCD_Prescaler));
assert_param(IS_LCD_CLOCK_DIVIDER(LCD_Divider));
assert_param(IS_LCD_DUTY(LCD_Duty));
assert_param(IS_LCD_BIAS(LCD_Bias));
assert_param(IS_LCD_VOLTAGE_SOURCE(LCD_VoltageSource));
LCD->FRQ &= (uint8_t)(~LCD_FRQ_PS); /* Clear the prescaler bits */
LCD->FRQ |= LCD_Prescaler;
LCD->FRQ &= (uint8_t)(~LCD_FRQ_DIV); /* Clear the divider bits */
LCD->FRQ |= LCD_Divider;
/* Configure the Duty cycle */
LCD->CR1 &= (uint8_t)(~LCD_CR1_DUTY); /* Clear the duty bits */
LCD->CR4 &= (uint8_t)(~LCD_CR4_DUTY8); /* Clear the DUTY8 bit */
if (LCD_Duty == LCD_Duty_1_8)
{
LCD->CR4 |= (uint8_t)((uint8_t)((uint8_t)LCD_Duty & (uint8_t)0xF0) >> 4);
}
else
{
LCD->CR1 |= (uint8_t)((uint8_t)LCD_Duty & (uint8_t)0x0F);
}
/* Configure the Bias */
LCD->CR1 &= (uint8_t)(~LCD_CR1_B2); /* Clear the B2 bit */
LCD->CR4 &= (uint8_t)(~LCD_CR4_B4); /* Clear the B4 bit */
if (LCD_Bias == LCD_Bias_1_4)
{
LCD->CR1 |= (uint8_t)((uint8_t)LCD_Bias & (uint8_t)0x0F);
LCD->CR4 |= (uint8_t)((uint8_t)((uint8_t)LCD_Bias & (uint8_t)0xF0) >> 4);
}
else
{
LCD->CR1 |= (uint8_t)((uint8_t)LCD_Bias & (uint8_t)0x0F);
}
LCD->CR2 &= (uint8_t)(~LCD_CR2_VSEL); /* Clear the voltage source bit */
LCD->CR2 |= LCD_VoltageSource;
}
/**
* @brief Configures the LCD Port Mask.
* @param LCD_PortMaskRegister: The LCD register index in the port mask matrix.
* This parameter can be one of the following values:
* @arg LCD_PortMaskRegister_0: PortMask Register 0
* @arg LCD_PortMaskRegister_1: PortMask Register 1
* @arg LCD_PortMaskRegister_2: PortMask Register 2
* @arg LCD_PortMaskRegister_3: PortMask Register 3
* @arg LCD_PortMaskRegister_4: PortMask Register 4
* @arg LCD_PortMaskRegister_5: PortMask Register 5
* @param LCD_Mask : Value to be written
* @retval None
*/
void LCD_PortMaskConfig(LCD_PortMaskRegister_TypeDef LCD_PortMaskRegister, uint8_t LCD_Mask)
{
/* Check function parameters */
assert_param(IS_LCD_PORT_MASK(LCD_PortMaskRegister));
/* Copy data bytes to Port mask register */
LCD->PM[LCD_PortMaskRegister] = LCD_Mask;
}
/**
* @brief Enables or disables the LCD Controller.
* @param NewState: new state of the LCD peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval None
* @retval None
*/
void LCD_Cmd(FunctionalState NewState)
{
/* Check function parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
LCD->CR3 |= LCD_CR3_LCDEN; /* Enable the LCD peripheral*/
}
else
{
LCD->CR3 &= (uint8_t)(~LCD_CR3_LCDEN); /* Disable the LCD peripheral*/
}
}
/**
* @brief Enables or disables the low resistance divider. Displays with high
* internal resistance may need a longer drive time to achieve
* satisfactory contrast. This function is useful in this case if some
* additional power consumption can be tolerated.
* @note When this mode is enabled, the PulseOn Duration (PON) have to be
* programmed to 1/CK_PS (LCD_PulseOnDuration_1).
* @param NewState: new state of the low resistance divider.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void LCD_HighDriveCmd(FunctionalState NewState)
{
/* Check function parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
LCD->CR2 |= LCD_CR2_HD; /* Permanently enable low resistance divider */
}
else
{
LCD->CR2 &= (uint8_t)(~LCD_CR2_HD); /* Permanently disable low resistance divider */
}
}
/**
* @brief Configures the LCD pulses on duration.
* @param LCD_PulseOnDuration: specifies the LCD pulse on duration in terms of
* CLKprescaler (prescaled LCD clock period) pulses.
* This parameter can be one of the following values:
* @arg LCD_PulseOnDuration_0: 0 pulse
* @arg LCD_PulseOnDuration_1: Pulse ON duration = 1/CLKprescaler
* @arg LCD_PulseOnDuration_2: Pulse ON duration = 2/CLKprescaler
* @arg LCD_PulseOnDuration_3: Pulse ON duration = 3/CLKprescaler
* @arg LCD_PulseOnDuration_4: Pulse ON duration = 4/CLKprescaler
* @arg LCD_PulseOnDuration_5: Pulse ON duration = 5/CLKprescaler
* @arg LCD_PulseOnDuration_6: Pulse ON duration = 6/CLKprescaler
* @arg LCD_PulseOnDuration_7: Pulse ON duration = 7/CLKprescaler
* @retval None
*/
void LCD_PulseOnDurationConfig(LCD_PulseOnDuration_TypeDef LCD_PulseOnDuration)
{
/* Check function parameters */
assert_param(IS_LCD_PULSE_DURATION(LCD_PulseOnDuration));
LCD->CR2 &= (uint8_t)(~LCD_CR2_PON); /* Clear the pulses on duration bits */
LCD->CR2 |= LCD_PulseOnDuration;
}
/**
* @brief Configures the LCD dead time.
* @param LCD_DeadTime: specifies the LCD dead time.
* This parameter can be one of the following values:
* @arg LCD_DeadTime_0: No dead Time
* @arg LCD_DeadTime_1: One Phase between different couple of Frame
* @arg LCD_DeadTime_2: Two Phase between different couple of Frame
* @arg LCD_DeadTime_3: Three Phase between different couple of Frame
* @arg LCD_DeadTime_4: Four Phase between different couple of Frame
* @arg LCD_DeadTime_5: Five Phase between different couple of Frame
* @arg LCD_DeadTime_6: Six Phase between different couple of Frame
* @arg LCD_DeadTime_7: Seven Phase between different couple of Frame
* @retval None
*/
void LCD_DeadTimeConfig(LCD_DeadTime_TypeDef LCD_DeadTime)
{
/* Check function parameters */
assert_param(IS_LCD_DEAD_TIME(LCD_DeadTime));
LCD->CR3 &= (uint8_t)(~LCD_CR3_DEAD); /* Clear the dead time bits */
LCD->CR3 |= LCD_DeadTime;
}
/**
* @brief Configures the LCD Blink mode and Blink frequency.
* @param LCD_BlinkMode: specifies the LCD blink mode.
* This parameter can be one of the following values:
* @arg LCD_BlinkMode_Off: Blink disabled
* @arg LCD_BlinkMode_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
* @arg LCD_BlinkMode_SEG0_AllCOM: Blink enabled on SEG[0], all COM (up to 8
* pixels according to the programmed duty)
* @arg LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM
* (all pixels)
* @param LCD_BlinkFrequency: specifies the LCD blink frequency.
* This parameter can be one of the following values:
* @arg LCD_BlinkFrequency_Div8: The Blink frequency = fLcd/8
* @arg LCD_BlinkFrequency_Div16: The Blink frequency = fLcd/16
* @arg LCD_BlinkFrequency_Div32: The Blink frequency = fLcd/32
* @arg LCD_BlinkFrequency_Div64: The Blink frequency = fLcd/64
* @arg LCD_BlinkFrequency_Div128: The Blink frequency = fLcd/128
* @arg LCD_BlinkFrequency_Div256: The Blink frequency = fLcd/256
* @arg LCD_BlinkFrequency_Div512: The Blink frequency = fLcd/512
* @arg LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024
* @retval None
*/
void LCD_BlinkConfig(LCD_BlinkMode_TypeDef LCD_BlinkMode, LCD_BlinkFrequency_TypeDef LCD_BlinkFrequency)
{
/* Check function parameters */
assert_param(IS_LCD_BLINK_MODE(LCD_BlinkMode));
assert_param(IS_LCD_BLINK_FREQUENCY(LCD_BlinkFrequency));
LCD->CR1 &= (uint8_t)(~LCD_CR1_BLINK); /* Clear the blink mode bits */
LCD->CR1 |= LCD_BlinkMode; /* Config the LCD Blink Mode */
LCD->CR1 &= (uint8_t)(~LCD_CR1_BLINKF); /* Clear the blink frequency bits */
LCD->CR1 |= LCD_BlinkFrequency; /* Config the LCD Blink Frequency */
}
/**
* @brief Configures the LCD Contrast.
* @param LCD_Contrast: specifies the LCD Contrast.
* This parameter can be one of the following values:
* @arg LCD_Contrast_Level_0: Medium Density / High Density Maximum Voltage = 2.60V / 2.60V
* @arg LCD_Contrast_Level_1: Medium Density / High Density Maximum Voltage = 2.70V / 2.73V
* @arg LCD_Contrast_Level_2: Medium Density / High Density Maximum Voltage = 2.80V / 2.86V
* @arg LCD_Contrast_Level_3: Medium Density / High Density Maximum Voltage = 2.90V / 2.99V
* @arg LCD_Contrast_Level_4: Medium Density / High Density Maximum Voltage = 3.00V / 3.12V
* @arg LCD_Contrast_Level_5: Medium Density / High Density Maximum Voltage = 3.10V / 3.25V
* @arg LCD_Contrast_Level_6: Medium Density / High Density Maximum Voltage = 3.20V / 3.38V
* @arg LCD_Contrast_Level_7: Medium Density / High Density Maximum Voltage = 3.30V / 3.51V
* @retval None
*/
void LCD_ContrastConfig(LCD_Contrast_TypeDef LCD_Contrast)
{
/* Check function parameters */
assert_param(IS_LCD_CONTRAST(LCD_Contrast));
LCD->CR2 &= (uint8_t)(~LCD_CR2_CC); /* Clear the contrast bits */
LCD->CR2 |= LCD_Contrast; /* Select the maximum voltage value Vlcd */
}
/**
* @}
*/
/** @defgroup LCD_Group2 LCD RAM memory write functions
* @brief LCD RAM memory write functions
*
@verbatim
===============================================================================
LCD RAM memory write functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Writes a word in the specific LCD RAM.
* @param LCD_RAMRegister: specifies the LCD Contrast.
* This parameter can be one of the following values:
* @arg LCD_RAMRegister_0: LCD RAM Register 0
* @arg LCD_RAMRegister_1: LCD RAM Register 1
* @arg LCD_RAMRegister_2: LCD RAM Register 2
* @arg LCD_RAMRegister_3: LCD RAM Register 3
* @arg LCD_RAMRegister_4: LCD RAM Register 4
* @arg LCD_RAMRegister_5: LCD RAM Register 5
* @arg LCD_RAMRegister_6: LCD RAM Register 6
* @arg LCD_RAMRegister_7: LCD RAM Register 7
* @arg LCD_RAMRegister_8: LCD RAM Register 8
* @arg LCD_RAMRegister_9: LCD RAM Register 9
* @arg LCD_RAMRegister_10: LCD RAM Register 10
* @arg LCD_RAMRegister_11: LCD RAM Register 11
* @arg LCD_RAMRegister_12: LCD RAM Register 12
* @arg LCD_RAMRegister_13: LCD RAM Register 13
* @arg LCD_RAMRegister_14: LCD RAM Register 14
* @arg LCD_RAMRegister_15: LCD RAM Register 15
* @arg LCD_RAMRegister_15: LCD RAM Register 16
* @arg LCD_RAMRegister_15: LCD RAM Register 17
* @arg LCD_RAMRegister_15: LCD RAM Register 18
* @arg LCD_RAMRegister_15: LCD RAM Register 19
* @arg LCD_RAMRegister_15: LCD RAM Register 20
* @arg LCD_RAMRegister_15: LCD RAM Register 21
* @param LCD_Data: specifies LCD Data Value to be written.
* @retval None
*/
void LCD_WriteRAM(LCD_RAMRegister_TypeDef LCD_RAMRegister, uint8_t LCD_Data)
{
/* Check function parameters */
assert_param(IS_LCD_RAM_REGISTER(LCD_RAMRegister));
/* Copy data bytes to RAM register */
LCD->RAM[LCD_RAMRegister] = LCD_Data;
}
/**
* @brief Select the LCD page where the data will be written.
* @param LCD_Page: The accessed LCD page.
* This parameter can be one of the following values:
* @arg LCD_PageSelection_FirstPage: The LCD RAM is selected as the first page
* @arg LCD_PageSelection_SecondPage: The LCD RAM is selected as the second page
* @retval None
*/
void LCD_PageSelect(LCD_PageSelection_TypeDef LCD_PageSelection)
{
/* Check function parameters */
assert_param(IS_LCD_PAGE_SELECT(LCD_PageSelection));
LCD->CR4 &= (uint8_t)(~LCD_CR4_PAGECOM); /* Clear the PAGE COM bit */
LCD->CR4 |= LCD_PageSelection; /* Select the LCD page */
}
/**
* @}
*/
/** @defgroup LCD_Group3 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the start of frame interrupt.
* @param NewState: new state of the specified LCD interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void LCD_ITConfig(FunctionalState NewState)
{
/* Check function parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
LCD->CR3 |= LCD_CR3_SOFIE; /* Enable interrupt*/
}
else
{
LCD->CR3 &= (uint8_t)(~LCD_CR3_SOFIE); /* Disable interrupt*/
}
}
/**
* @brief Checks whether the LCD start of new frame flag is set or not.
* @retval The new state of the start of new frame flag.
* This returned value can be: SET or RESET.
*/
FlagStatus LCD_GetFlagStatus(void)
{
FlagStatus status = RESET;
/* Check the status of the start of new frame LCD flag */
if ((LCD->CR3 & (uint8_t)LCD_CR3_SOF) != (uint8_t)RESET)
{
status = SET; /* Flag is set */
}
else
{
status = RESET; /* Flag is reset*/
}
/* Return the FLAG status */
return status;
}
/**
* @brief Clears the start of frame LCD flag.
* @param None
* @retval None
*/
void LCD_ClearFlag(void)
{
/* Clear the flag bit */
LCD->CR3 |= (uint8_t)(LCD_CR3_SOFC);
}
/**
* @brief Checks whether the start of frame interrupt has occurred or not.
* @param None
* @retval The new state of the start of new frame interrupt.
* This returned value can be: SET or RESET.
*/
ITStatus LCD_GetITStatus(void)
{
ITStatus pendingbitstatus = RESET;
uint8_t enablestatus = 0;
enablestatus = (uint8_t)((uint8_t)LCD->CR3 & LCD_CR3_SOFIE);
/* Check the status of the start of frame interrupt */
if (((LCD->CR3 & LCD_CR3_SOF) != RESET) && enablestatus)
{
/* ITPENDINGBIT is set */
pendingbitstatus = SET;
}
else
{
/* ITPENDINGBIT is reset */
pendingbitstatus = RESET;
}
/* Return the ITPENDINGBIT status */
return pendingbitstatus;
}
/**
* @brief Clears the start of frame interrupt pending bits.
* @param None
* @retval None
*/
void LCD_ClearITPendingBit(void)
{
/* Clear the flag bit */
LCD->CR3 |= (uint8_t)(LCD_CR3_SOFC);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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firmware/inc/stm8l151x/src/stm8l15x_pwr.c Normal file
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/**
******************************************************************************
* @file stm8l15x_pwr.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* - PVD configuration
* - Ultra Low Power mode configuration
* - Interrupts and flags management
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_pwr.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup PWR
* @brief PWR driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PWR_Private_Functions
* @{
*/
/** @defgroup PWR_Group1 PVD configuration functions
* @brief PVD configuration functions
*
@verbatim
===============================================================================
PVD configuration functions
===============================================================================
- The PVD is used to monitor the VDD power supply by comparing it to a threshold
selected by the PVD Level (PLS[2:0] bits in the PWR_CSR1).
- The PVD can use an external input analog voltage (PVD_IN) which is compared
internally to VREFINT. The PVD_IN (PE6) has to be configured in Analog mode
when PWR_PVDLevel_PVDIn is selected (PLS[2:0] = 111).
- A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
PVD threshold. An interrupt is generated in case enabled for PVD.
- The PVD interrup event has the capability to wake up the CPU from Halt/Active Halt modes.
@endverbatim
* @{
*/
/**
* @brief Deinitializes the PWR peripheral registers to their default reset values.
* @param None
* @retval None
*/
void PWR_DeInit(void)
{
PWR->CSR1 = PWR_CSR1_PVDIF;
PWR->CSR2 = PWR_CSR2_RESET_VALUE;
}
/**
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
* @param PWR_PVDLevel: specifies the PVD detection level
* This parameter can be one of the following values:
* @arg PWR_PVDLevel_1V85: PVD detection level set to 1.85V
* @arg PWR_PVDLevel_2V05: PVD detection level set to 2.05V
* @arg PWR_PVDLevel_2V26: PVD detection level set to 2.26V
* @arg PWR_PVDLevel_2V45: PVD detection level set to 2.45V
* @arg PWR_PVDLevel_2V65: PVD detection level set to 2.65V
* @arg PWR_PVDLevel_2V85: PVD detection level set to 2.85V
* @arg PWR_PVDLevel_3V05: PVD detection level set to 3.05V
* @arg PWR_PVDLevel_PVDIn: External input analog voltage (Compare internally to VREFINT)
* @retval None
*/
void PWR_PVDLevelConfig(PWR_PVDLevel_TypeDef PWR_PVDLevel)
{
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
/* Clear the PVD level */
PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PLS);
/* Configure the PVD level */
PWR->CSR1 |= PWR_PVDLevel;
}
/**
* @brief Enables or disables the Power Voltage Detector(PVD).
* @param NewState: new state of the PVD.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_PVDCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the PWR PVD */
PWR->CSR1 |= PWR_CSR1_PVDE;
}
else
{
/* Disable the PWR PVD */
PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PVDE);
}
}
/**
* @}
*/
/** @defgroup PWR_Group2 Ultra Low Power mode configuration functions
* @brief Ultra Low Power mode configuration functions
*
@verbatim
===============================================================================
Ultra Low Power mode configuration functions
===============================================================================
- The internal voltage reference consumption is not negligible, in particular
in Halt and Active Halt modes. To reduce power consumption, use the PWR_UltraLowPowerCmd()
function (ULP bit (Ultra low power) in the PWR_CSR2 register) to disable the
internal voltage reference. However, in this case, when exiting from the
Halt/Active Halt modes, the functions managed through the internal voltage reference
are not reliable during the internal voltage reference startup time (up to 3 ms).
To reduce the wakeup time, the device can exit from Halt/Active Halt modes without
waiting for the internal voltage reference startup time. This is performed
by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast
wakeup) in the PWR_CSR2 register) before entering Halt/Active Halt mode.
@endverbatim
* @{
*/
/**
* @brief Enables or disables the Fast WakeUp from Ultra Low Power mode.
* @param NewState: new state of the Fast WakeUp functionality.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_FastWakeUpCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the PWR FWU */
PWR->CSR2 |= PWR_CSR2_FWU;
}
else
{
/* Disable the PWR FWU */
PWR->CSR2 &= (uint8_t)(~PWR_CSR2_FWU);
}
}
/**
* @brief Enables or disables the Ultra Low Power mode.
* @param NewState: new state of the Ultra Low Power mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_UltraLowPowerCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the PWR ULP */
PWR->CSR2 |= PWR_CSR2_ULP;
}
else
{
/* Disable the PWR ULP */
PWR->CSR2 &= (uint8_t)(~PWR_CSR2_ULP);
}
}
/**
* @}
*/
/** @defgroup PWR_Group3 Interrupts and Flags management functions
* @brief Interrupts and Flags management functions
*
@verbatim
===============================================================================
Interrupts and Flags management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Configures the Programmable Voltage Detector (PVD) Interrupt .
* @param NewState : Indicates the new state of the PVD interrupt.
* @retval None
*/
void PWR_PVDITConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the PVD interrupt */
PWR->CSR1 |= PWR_CSR1_PVDIEN;
}
else
{
/* Disable the PVD interrupt */
PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PVDIEN);
}
}
/**
* @brief Checks whether the specified PWR flag is set or not.
* @param PWR_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_PVDOF: PVD Output. This flag is valid only if PVD is enabled
* by the PWR_PVDCmd() function.
* @arg PWR_FLAG_VREFINTF: Internal Voltage Reference Ready flag. This
* flag indicates the state of the internal voltage reference, VREFINT.
* @arg PWR_FLAG_PVDIF: PVD Interrupt Flag, it's set by hardware when a PVD
* event occurs
* @retval The new state of PWR_FLAG (SET or RESET).
*/
FlagStatus PWR_GetFlagStatus(PWR_FLAG_TypeDef PWR_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_PWR_FLAG(PWR_FLAG));
if ((PWR_FLAG & PWR_FLAG_VREFINTF) != 0)
{
if ((PWR->CSR2 & PWR_CR2_VREFINTF) != (uint8_t)RESET )
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
else
{
if ((PWR->CSR1 & PWR_FLAG) != (uint8_t)RESET )
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
/* Return the flag status */
return((FlagStatus)bitstatus);
}
/**
* @brief Clears the PWR PVDIF Flag.
* @param None
* @retval None
*/
void PWR_PVDClearFlag(void)
{
/* Set the PVDIF to clear it */
PWR->CSR1 |= PWR_CSR1_PVDIF;
}
/**
* @brief Checks whether the PVD interrupt has occurred or not.
* @param None
* @retval The new state of the PVD Interrupt (SET or RESET).
*/
ITStatus PWR_PVDGetITStatus(void)
{
ITStatus bitstatus = RESET;
uint8_t PVD_itStatus = 0x0, PVD_itEnable = 0x0;
PVD_itStatus = (uint8_t)(PWR->CSR1 & (uint8_t)PWR_CSR1_PVDIF);
PVD_itEnable = (uint8_t)(PWR->CSR1 & (uint8_t)PWR_CSR1_PVDIEN);
if ((PVD_itStatus != (uint8_t)RESET ) && (PVD_itEnable != (uint8_t)RESET))
{
bitstatus = (ITStatus)SET;
}
else
{
bitstatus = (ITStatus)RESET;
}
return ((ITStatus)bitstatus);
}
/**
* @brief Clears the PWR interrupt pending bit.
* @param None
* @retval None
*/
void PWR_PVDClearITPendingBit(void)
{
/* Set the PVDIF to clear it */
PWR->CSR1 |= PWR_CSR1_PVDIF;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_rst.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the RST peripheral:
* - Flag management
* - NRST Pin configuration
*
* @verbatim
*
* ===================================================================
* RST specific features
* ===================================================================
*
* When a reset occurs, there is a reset phase from the external pin
* pull-down to the internal reset signal release. During this phase,
* the microcontroller sets some hardware configurations before going
* to the reset vector.
* At the end of this phase, most of the registers are configured with
* their <20>reset state<74> values.
* During the reset phase, some pin configurations may be different from
* their <20>reset state<74> configuration.
*
* The NRST pin is an input and can be configured as open-drain output
* using the RST_GPOutputEnable() function
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_rst.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup RST
* @brief RST driver modules
* @{
*/
/* Private define ------------------------------------------------------------*/
#define RST_CR_MASK 0xD0 /*!< Enable the GPIO */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RST_Private_Functions
* @{
*/
/** @defgroup RST_Group1 Flag management functions
* @brief Flag management functions
*
@verbatim
===============================================================================
Flag management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Checks whether the specified RST flag is set or not.
* @param RST_Flag : specify the reset flag to check.
* This parameter can be one of the following values:
* @arg RST_FLAG_PORF: POR reset flag
* @arg RST_FLAG_SWIMF: SWIM reset flag
* @arg RST_FLAG_ILLOPF: Illegal opcode reset flag
* @arg RST_FLAG_IWDGF: Independent watchdog reset flag
* @arg RST_FLAG_WWDGF: Window watchdog reset flag
* @arg RST_FLAG_BORF: BOR reset flag
* @retval The new state of RST_Flag (SET or RESET).
*/
FlagStatus RST_GetFlagStatus(RST_FLAG_TypeDef RST_Flag)
{
/* Check the parameters */
assert_param(IS_RST_FLAG(RST_Flag));
/* Get flag status */
return((FlagStatus)(((uint8_t)(RST->SR & RST_Flag) == (uint8_t)0x00) ? RESET : SET));
}
/**
* @brief Clears the specified RST flag.
* @param RST_Flag : specify the reset flag to check.
* This parameter can be one of the following values:
* @arg RST_FLAG_PORF: POR reset flag
* @arg RST_FLAG_SWIMF: SWIM reset flag
* @arg RST_FLAG_ILLOPF: Illegal opcode reset flag
* @arg RST_FLAG_IWDGF: Independent watchdog reset flag
* @arg RST_FLAG_WWDGF: Window watchdog reset flag
* @arg RST_FLAG_BORF: BOR reset flag
* @retval None
*/
void RST_ClearFlag(RST_FLAG_TypeDef RST_Flag)
{
/* Check the parameters */
assert_param(IS_RST_FLAG(RST_Flag));
RST->SR = (uint8_t)RST_Flag;
}
/**
* @}
*/
/** @defgroup RST_Group2 NRST Pin configuration function
* @brief NRST Pin configuration function
*
@verbatim
===============================================================================
NRST Pin configuration function
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Configures the reset pad as GP output.
* @param None
* @retval None
*/
void RST_GPOutputEnable(void)
{
RST->CR = RST_CR_MASK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_spi.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Serial peripheral interface (SPI):
* - Initialization and Configuration
* - Data transfers functions
* - Hardware CRC Calculation
* - DMA transfers management
* - Interrupts and flags management
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Enable peripheral clock using CLK_PeripheralClockConfig(CLK_Peripheral_SPIx,
* ENABLE) function (Refer to the product datasheet for the available SPI
* peripherals)
*
* 2. Enable the external Pull-up on the used SPI Pins using the
* GPIO_ExternalPullUpConfig() function or an eternal pull-up equivalent resistor
* (RPU = 45 KOhm typical value).
*
*
* 3. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
* Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
* function.
*
* 4. Enable the corresponding interrupt using the function SPI_ITConfig() if you
* need to use interrupt mode.
*
* 5. When using the DMA mode
* - Configure the DMA using DMA_Init() function
* - Active the needed channel Request using SPI_DMACmd() function
*
* 6. Enable the SPI using the SPI_Cmd() function.
*
* 7. Enable the DMA using the DMA_Cmd() function when using DMA mode.
*
* 8. Optionally you can enable/configure the following parameters without
* re-initialization (i.e there is no need to call again SPI_Init() function):
* - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
* is programmed as Data direction parameter using the SPI_Init() function
* it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
* using the SPI_BiDirectionalLineConfig() function.
* - When SPI_NSS_Soft is selected as Slave Select Management parameter
* using the SPI_Init() function it can be possible to manage the
* NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
*
* 9. To use the CRC Hardware calculation feature refer to the Peripheral
* CRC hardware Calculation subsection.
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_spi.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup SPI
* @brief SPI driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SPI_Private_Functions
* @{
*/
/** @defgroup SPI_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
Initialization and Configuration functions
===============================================================================
This section provides a set of functions allowing to initialize the SPI Direction,
SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
The SPI_Init() function follows the SPI configuration procedures for Master mode
and Slave mode (details for these procedures are available in reference manual
(RM0031)).
@endverbatim
* @{
*/
/**
* @brief Deinitializes the SPI peripheral registers to their default reset values.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param None
* @retval None
*/
void SPI_DeInit(SPI_TypeDef* SPIx)
{
SPIx->CR1 = SPI_CR1_RESET_VALUE;
SPIx->CR2 = SPI_CR2_RESET_VALUE;
SPIx->CR3 = SPI_CR3_RESET_VALUE;
SPIx->SR = SPI_SR_RESET_VALUE;
SPIx->CRCPR = SPI_CRCPR_RESET_VALUE;
}
/**
* @brief Initializes the SPI according to the specified parameters.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param SPI_FirstBit: This parameter can be any of the
* This parameter can be one of the following values:
* @arg SPI_FirstBit_MSB: MSB bit will be transmitted first
* @arg SPI_FirstBit_LSB: LSB bit will be transmitted first
* @param SPI_BaudRatePrescaler: This parameter can be any of the
* This parameter can be one of the following values:
* @arg SPI_BaudRatePrescaler_2: SPI frequency = frequency(CPU)/2
* @arg SPI_BaudRatePrescaler_4: SPI frequency = frequency(CPU)/4
* @arg SPI_BaudRatePrescaler_8: SPI frequency = frequency(CPU)/8
* @arg SPI_BaudRatePrescaler_16: SPI frequency = frequency(CPU)/16
* @arg SPI_BaudRatePrescaler_32: SPI frequency = frequency(CPU)/32
* @arg SPI_BaudRatePrescaler_64: SPI frequency = frequency(CPU)/64
* @arg SPI_BaudRatePrescaler_128: SPI frequency = frequency(CPU)/128
* @arg SPI_BaudRatePrescaler_256: SPI frequency = frequency(CPU)/256
* @param SPI_Mode: Mode
* This parameter can be one of the following values:
* @arg SPI_Mode_Master: SPI Master configuration
* @arg SPI_Mode_Slave: SPI Slave configuration
* @param SPI_CPOL: Clock Polarity
* This parameter can be one of the following values:
* @arg SPI_CPOL_Low: Clock to 0 when idle
* @arg SPI_CPOL_High: Clock to 1 when idle
* @param SPI_CPHA: Clock Phase
* This parameter can be one of the following values:
* @arg SPI_CPHA_1Edge: The first clock transition is the first data capture edge
* @arg SPI_CPHA_2Edge: The second clock transition is the first data capture edge
* @param SPI_Data_Direction: Data direction
* This parameter can be one of the following values:
* @arg SPI_Direction_Rx: Select Rx receive direction in bi-directional mode
* @arg SPI_Direction_Tx: Select Tx transmission direction in bi-directional mode
* @param SPI_Slave_Management: Slave management
* This parameter can be one of the following values:
* @arg SPI_NSS_Soft: Software slave management disabled
* @arg SPI_NSS_Hard: Software slave management enabled
* @param CRCPolynomial: Configures the CRC polynomial.
* @retval None
*/
void SPI_Init(SPI_TypeDef* SPIx, SPI_FirstBit_TypeDef SPI_FirstBit,
SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler,
SPI_Mode_TypeDef SPI_Mode, SPI_CPOL_TypeDef SPI_CPOL,
SPI_CPHA_TypeDef SPI_CPHA, SPI_DirectionMode_TypeDef SPI_Data_Direction,
SPI_NSS_TypeDef SPI_Slave_Management, uint8_t CRCPolynomial)
{
/* Check structure elements */
assert_param(IS_SPI_FIRSTBIT(SPI_FirstBit));
assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_BaudRatePrescaler));
assert_param(IS_SPI_MODE(SPI_Mode));
assert_param(IS_SPI_POLARITY(SPI_CPOL));
assert_param(IS_SPI_PHASE(SPI_CPHA));
assert_param(IS_SPI_DATA_DIRECTION(SPI_Data_Direction));
assert_param(IS_SPI_SLAVEMANAGEMENT(SPI_Slave_Management));
assert_param(IS_SPI_CRC_POLYNOMIAL(CRCPolynomial));
/* Frame Format, BaudRate, Clock Polarity and Phase configuration */
SPIx->CR1 = (uint8_t)((uint8_t)((uint8_t)SPI_FirstBit |
(uint8_t)SPI_BaudRatePrescaler) |
(uint8_t)((uint8_t)SPI_CPOL |
SPI_CPHA));
/* Data direction configuration: BDM, BDOE and RXONLY bits */
SPIx->CR2 = (uint8_t)((uint8_t)(SPI_Data_Direction) | (uint8_t)(SPI_Slave_Management));
if (SPI_Mode == SPI_Mode_Master)
{
SPIx->CR2 |= (uint8_t)SPI_CR2_SSI;
}
else
{
SPIx->CR2 &= (uint8_t)~(SPI_CR2_SSI);
}
/* Master/Slave mode configuration */
SPIx->CR1 |= (uint8_t)(SPI_Mode);
/* CRC configuration */
SPIx->CRCPR = (uint8_t)CRCPolynomial;
}
/**
* @brief Enables or disables the SPI peripheral.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param NewState New state of the SPI peripheral.
* This parameter can be: ENABLE or DISABLE
* @retval None
*/
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
/* Check function parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SPIx->CR1 |= SPI_CR1_SPE; /* Enable the SPI peripheral*/
}
else
{
SPIx->CR1 &= (uint8_t)(~SPI_CR1_SPE); /* Disable the SPI peripheral*/
}
}
/**
* @brief Configures internally by software the NSS pin.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param NewState Indicates the new state of the SPI Software slave management.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SPI_NSSInternalSoftwareCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
/* Check function parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
SPIx->CR2 |= SPI_CR2_SSI; /* Set NSS pin internally by software*/
}
else
{
SPIx->CR2 &= (uint8_t)(~SPI_CR2_SSI); /* Reset NSS pin internally by software*/
}
}
/**
* @brief Selects the data transfer direction in Bi-directional mode.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param SPI_Direction Specifies the data transfer direction in Bi-directional mode.
* This parameter can be one of the following values:
* @arg SPI_Direction_Rx: Select Rx receive direction in bi-directional mode
* @arg SPI_Direction_Tx: Select Tx transmission direction in bi-directional mode
* @retval None
*/
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, SPI_Direction_TypeDef SPI_Direction)
{
/* Check function parameters */
assert_param(IS_SPI_DIRECTION(SPI_Direction));
if (SPI_Direction != SPI_Direction_Rx)
{
SPIx->CR2 |= SPI_CR2_BDOE; /* Set the Tx only mode*/
}
else
{
SPIx->CR2 &= (uint8_t)(~SPI_CR2_BDOE); /* Set the Rx only mode*/
}
}
/**
* @}
*/
/** @defgroup SPI_Group2 Data transfers functions
* @brief Data transfers functions
*
@verbatim
===============================================================================
Data transfers functions
===============================================================================
This section provides a set of functions allowing to manage the SPI data transfers
In reception, data are received and then stored into an internal Rx buffer while
In transmission, data are first stored into an internal Tx buffer before being
transmitted.
The read access of the SPI_DR register can be done using the SPI_ReceiveData()
function and returns the Rx buffered value. Whereas a write access to the SPI_DR
can be done using SPI_SendData() function and stores the written data into
Tx buffer.
@endverbatim
* @{
*/
/**
* @brief Transmits a Data through the SPI peripheral.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param Data: Byte to be transmitted.
* @retval None
*/
void SPI_SendData(SPI_TypeDef* SPIx, uint8_t Data)
{
SPIx->DR = Data; /* Write in the DR register the data to be sent*/
}
/**
* @brief Returns the most recent received data by the SPI peripheral.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @retval The value of the received data.
*/
uint8_t SPI_ReceiveData(SPI_TypeDef* SPIx)
{
return ((uint8_t)SPIx->DR); /* Return the data in the DR register*/
}
/**
* @}
*/
/** @defgroup SPI_Group3 Hardware CRC Calculation functions
* @brief Hardware CRC Calculation functions
*
@verbatim
===============================================================================
Hardware CRC Calculation functions
===============================================================================
This section provides a set of functions allowing to manage the SPI CRC hardware
calculation
SPI communication using CRC is possible through the following procedure:
1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
function.
2. Enable the CRC calculation using the SPI_CalculateCRC() function.
3. Enable the SPI using the SPI_Cmd() function
4. Before writing the last data to the TX buffer, set the CRCNext bit using the
SPI_TransmitCRC() function to indicate that after transmission of the last
data, the CRC should be transmitted.
5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR2_CRCNEXT
bit is reset. The CRC is also received and compared against the SPI_RXCRCR
value.
If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
can be generated when the SPI_IT_ERR interrupt is enabled.
Note:
-----
- It is advised to don't read the calculate CRC values during the communication.
- When the SPI is in slave mode, be careful to enable CRC calculation only
when the clock is stable, that is, when the clock is in the steady state.
If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
to the SCK slave input clock as soon as CRCEN is set, and this, whatever
the value of the SPE bit.
- With high bitrate frequencies, be careful when transmitting the CRC.
As the number of used CPU cycles has to be as low as possible in the CRC
transfer phase, it is forbidden to call software functions in the CRC
transmission sequence to avoid errors in the last data and CRC reception.
In fact, CRCNEXT bit has to be written before the end of the transmission/reception
of the last data.
- For high bit rate frequencies, it is advised to use the DMA mode to avoid the
degradation of the SPI speed performance due to CPU accesses impacting the
SPI bandwidth.
- When the STM8L15x are configured as slaves and the NSS hardware mode is
used, the NSS pin needs to be kept low between the data phase and the CRC
phase.
- When the SPI is configured in slave mode with the CRC feature enabled, CRC
calculation takes place even if a high level is applied on the NSS pin.
This may happen for example in case of a multislave environment where the
communication master addresses slaves alternately.
- Between a slave de-selection (high level on NSS) and a new slave selection
(low level on NSS), the CRC value should be cleared on both master and slave
sides in order to resynchronize the master and slave for their respective
CRC calculation.
To clear the CRC, follow the procedure below:
1. Disable SPI using the SPI_Cmd() function
2. Disable the CRC calculation using the SPI_CalculateCRC() function.
3. Enable the CRC calculation using the SPI_CalculateCRC() function.
4. Enable SPI using the SPI_Cmd() function.
@endverbatim
* @{
*/
/**
* @brief Enables the transmit of the CRC value.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @retval None
*/
void SPI_TransmitCRC(SPI_TypeDef* SPIx)
{
SPIx->CR2 |= SPI_CR2_CRCNEXT; /* Enable the CRC transmission*/
}
/**
* @brief Enables or disables the CRC value calculation of the transferred bytes.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param NewState Indicates the new state of the SPI CRC value calculation.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SPI_CalculateCRCCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
/* Check function parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* SPI must be disabled for correct operation od Hardware CRC calculation */
SPI_Cmd(SPI1, DISABLE);
if (NewState != DISABLE)
{
SPIx->CR2 |= SPI_CR2_CRCEN; /* Enable the CRC calculation*/
}
else
{
SPIx->CR2 &= (uint8_t)(~SPI_CR2_CRCEN); /* Disable the CRC calculation*/
}
}
/**
* @brief Returns the transmit or the receive CRC register value.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param SPI_CRC: Specifies the CRC register to be read.
* This parameter can be one of the following values:
* @arg SPI_CRC_RX: Select Tx CRC register
* @arg SPI_CRC_TX: Select Rx CRC register
* @retval The selected CRC register value.
*/
uint8_t SPI_GetCRC(SPI_TypeDef* SPIx, SPI_CRC_TypeDef SPI_CRC)
{
uint8_t crcreg = 0;
/* Check function parameters */
assert_param(IS_SPI_CRC(SPI_CRC));
if (SPI_CRC != SPI_CRC_RX)
{
crcreg = SPIx->TXCRCR; /* Get the Tx CRC register*/
}
else
{
crcreg = SPIx->RXCRCR; /* Get the Rx CRC register*/
}
/* Return the selected CRC register status*/
return crcreg;
}
/**
* @brief Reset the Rx CRCR and Tx CRCR registers.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @retval None
*/
void SPI_ResetCRC(SPI_TypeDef* SPIx)
{
/* Rx CRCR & Tx CRCR registers are reset when CRCEN (hardware calculation)
bit in SPI_CR2 is written to 1 (enable) */
SPI_CalculateCRCCmd(SPIx, ENABLE);
/* Previous function disable the SPI */
SPI_Cmd(SPIx, ENABLE);
}
/**
* @brief Returns the CRC Polynomial register value.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @retval uint8_t The CRC Polynomial register value.
*/
uint8_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
{
return SPIx->CRCPR; /* Return the CRC polynomial register */
}
/**
* @}
*/
/** @defgroup SPI_Group4 DMA transfers management functions
* @brief DMA transfers management functions
*
@verbatim
===============================================================================
DMA transfers management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the SPI DMA interface.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param SPI_DMAReq Specifies the SPI DMA transfer request to be enabled or disabled.
* This parameter can be one of the following values:
* @arg SPI_DMAReq_RX: SPI DMA Rx transfer requests
* @arg SPI_DMAReq_TX: SPI DMA Tx transfer requests
* @param NewState Indicates the new state of the SPI DMA request.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SPI_DMACmd(SPI_TypeDef* SPIx, SPI_DMAReq_TypeDef SPI_DMAReq, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_SPI_DMAREQ(SPI_DMAReq));
if (NewState != DISABLE)
{
/* Enable the selected SPI DMA requests */
SPIx->CR3 |= (uint8_t) SPI_DMAReq;
}
else
{
/* Disable the selected SPI DMA requests */
SPIx->CR3 &= (uint8_t)~SPI_DMAReq;
}
}
/**
* @}
*/
/** @defgroup SPI_Group5 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@verbatim
===============================================================================
Interrupts and flags management functions
===============================================================================
This section provides a set of functions allowing to configure the SPI Interrupts
sources and check or clear the flags or pending bits status.
The user should identify which mode will be used in his application to manage
the communication: Polling mode, Interrupt mode or DMA mode.
Polling Mode
=============
In Polling Mode, the SPI communication can be managed by 6 flags:
1. SPI_FLAG_TXE: to indicate the status of the transmit buffer register
2. SPI_FLAG_RXNE: to indicate the status of the receive buffer register
3. SPI_FLAG_WKUP: to indicate the state of the Wakeup event.
4. SPI_FLAG_CRCERR: to indicate if a CRC Calculation error occurs
5. SPI_FLAG_MODF: to indicate if a Mode Fault error occurs
6. SPI_FLAG_OVR: to indicate if an Overrun error occurs
In this Mode it is advised to use the following functions:
- FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG);
- void SPI_ClearFlag(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG);
Interrupt Mode
===============
In Interrupt Mode, the SPI communication can be managed by 4 interrupt sources
and 6 pending bits:
Pending Bits:
-------------
1. SPI_IT_TXE: to indicate the status of the transmit buffer register
2. SPI_IT_RXNE: to indicate the status of the receive buffer register
3. SPI_IT_CRCERR: to indicate if a CRC Calculation error occurs
4. SPI_IT_MODF: to indicate if a Mode Fault error occurs
5. SPI_IT_OVR: to indicate if an Overrun error occurs
6. SPI_IT_WKUP: to indicate if an Wake_up event occurs
Interrupt Source:
-----------------
1. SPI_IT_TXE: specifies the interrupt source for the Tx buffer empty
interrupt.
2. SPI_IT_RXNE: specifies the interrupt source for the Rx buffer not
empty interrupt.
3. SPI_IT_ERR: specifies the interrupt source for the errors interrupt.
4. SPI_IT_WKUP: specifies the interrupt source for the Wake-up interrupt.
In this Mode it is advised to use the following functions:
- void SPI_ITConfig(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT, FunctionalState NewState);
- ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT);
- void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT);
DMA Mode
========
In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
1. SPI_DMAReq_Tx: specifies the Tx buffer DMA transfer request
2. SPI_DMAReq_Rx: specifies the Rx buffer DMA transfer request
In this Mode it is advised to use the following function:
- void SPI_DMACmd(SPI_TypeDef* SPIx, SPI_DMAReq_TypeDef SPI_DMAReq, FunctionalState NewState);
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified interrupts.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param SPI_IT Specifies the SPI interrupts sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Transmit buffer empty
* @arg SPI_IT_RXNE: Receive buffer not empty
* @arg SPI_IT_ERR: Error
* @arg SPI_IT_WKUP: Wake-up
* @param NewState: The new state of the specified SPI interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void SPI_ITConfig(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
{
uint8_t itpos = 0;
/* Check function parameters */
assert_param(IS_SPI_CONFIG_IT(SPI_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Get the SPI IT index */
itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)SPI_IT & (uint8_t)0x0F));
if (NewState != DISABLE)
{
SPIx->CR3 |= itpos; /* Enable interrupt*/
}
else
{
SPIx->CR3 &= (uint8_t)(~itpos); /* Disable interrupt*/
}
}
/**
* @brief Checks whether the specified SPI flag is set or not.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param SPI_FLAG: Specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_BSY: Busy
* @arg SPI_FLAG_OVR: Overrun
* @arg SPI_FLAG_MODF: Mode fault
* @arg SPI_FLAG_CRCERR: CRC error
* @arg SPI_FLAG_WKUP: Wake-up
* @arg SPI_FLAG_TXE: Transmit buffer empty
* @arg SPI_FLAG_RXNE: Receive buffer empty
* @retval Indicates the state of SPI_FLAG.
* This parameter can be SET or RESET.
*/
FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG)
{
FlagStatus status = RESET;
/* Check parameters */
assert_param(IS_SPI_FLAG(SPI_FLAG));
/* Check the status of the specified SPI flag */
if ((SPIx->SR & (uint8_t)SPI_FLAG) != (uint8_t)RESET)
{
status = SET; /* SPI_FLAG is set */
}
else
{
status = RESET; /* SPI_FLAG is reset*/
}
/* Return the SPI_FLAG status */
return status;
}
/**
* @brief Clears the SPI flags.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param SPI_FLAG: Specifies the flag to clear.
* This parameter can be one of the following values:
* @arg SPI_FLAG_CRCERR
* @arg SPI_FLAG_WKUP
* @note OVR (OverRun Error) interrupt pending bit is cleared by software
* sequence: a read operation to SPI_DR register (SPI_ReceiveData()) followed by
* a read operation to SPI_SR register (SPI_GetFlagStatus()).
* @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
* a read/write operation to SPI_SR register (SPI_GetFlagStatus()) followed by
* a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
* @retval None
*/
void SPI_ClearFlag(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG)
{
assert_param(IS_SPI_CLEAR_FLAG(SPI_FLAG));
/* Clear the flag bit */
SPIx->SR = (uint8_t)(~SPI_FLAG);
}
/**
* @brief Checks whether the specified interrupt has occurred or not.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param SPI_IT: Specifies the SPI interrupt pending bit to check.
* This parameter can be one of the following values:
* @arg SPI_IT_CRCERR
* @arg SPI_IT_WKUP
* @arg SPI_IT_OVR
* @arg SPI_IT_MODF
* @arg SPI_IT_RXNE
* @arg SPI_IT_TXE
* @retval Indicates the state of the SPI_IT.
*/
ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT)
{
ITStatus pendingbitstatus = RESET;
uint8_t itpos = 0;
uint8_t itmask1 = 0;
uint8_t itmask2 = 0;
__IO uint8_t enablestatus = 0;
assert_param(IS_SPI_GET_IT(SPI_IT));
/* Get the SPI IT index */
itpos = (uint8_t)((uint8_t)1 << ((uint8_t)SPI_IT & (uint8_t)0x0F));
/* Get the SPI IT mask */
itmask1 = (uint8_t)((uint8_t)SPI_IT >> (uint8_t)4);
/* Set the IT mask */
itmask2 = (uint8_t)((uint8_t)1 << itmask1);
/* Get the SPI_IT enable bit status */
enablestatus = (uint8_t)((uint8_t)SPIx->SR & itmask2);
/* Check the status of the specified SPI interrupt */
if (((SPIx->CR3 & itpos) != RESET) && enablestatus)
{
/* SPI_IT is set */
pendingbitstatus = SET;
}
else
{
/* SPI_IT is reset */
pendingbitstatus = RESET;
}
/* Return the SPI_IT status */
return pendingbitstatus;
}
/**
* @brief Clears the interrupt pending bits.
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
* @param SPI_IT: Specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg SPI_IT_CRCERR
* @arg SPI_IT_WKUP
* @note OVR (OverRun Error) interrupt pending bit is cleared by software sequence:
* a read operation to SPI_DR register (SPI_ReceiveData()) followed by
* a read operation to SPI_SR register (SPI_GetITStatus()).
* @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
* a read/write operation to SPI_SR register (SPI_GetITStatus()) followed by
* a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
* @retval None
*/
void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT)
{
uint8_t itpos = 0;
assert_param(IS_SPI_CLEAR_IT(SPI_IT));
/* Clear SPI_IT_CRCERR or SPI_IT_WKUP interrupt pending bits */
/* Get the SPI pending bit index */
itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)(SPI_IT & (uint8_t)0xF0) >> 4));
/* Clear the pending bit */
SPIx->SR = (uint8_t)(~itpos);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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firmware/inc/stm8l151x/src/stm8l15x_syscfg.c Normal file
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/**
******************************************************************************
* @file stm8l15x_syscfg.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the RI and SYSCFG:
* - RI configuration
* - SYSCFG configuration
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* This driver provides functions to configure the RI and SYSCFG
* These functions are split in 2 groups:
*
* 1. RI configuration: this group includes all needed functions
* to configure the RI:
* - Routing the TIM1 Input capture channels
* - Close and Open the I/O switches
* - Close and Open the analog switches
* - Configure the internal Pull-up and Pull-down resistors
*
* 2. SYSCFG configuration: this group includes all needed functions
* to configure the SYSCFG:
* - Configure the alternate function remapping of some peripherals
* such as: USART, SPI, TIMs...
* Remapping possibilities depends on the device (low-density,
* medium-density or high density) so it is recommended to
* refer to the product reference manual.
* - Configure the DMA channels remapping of ADC1 and TIM4
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_syscfg.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup SYSCFG
* @brief SYSCFG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SYSCFG_Private_Functions
* @{
*/
/** @defgroup SYSCFG_Group1 RI configuration
* @brief RI configuration
*
@verbatim
===============================================================================
RI configuration functions
===============================================================================
===================================================================
SYSCFG Driver: how to configure RI
===================================================================
1. By default, TIM1 Input Capture channels 2 and 3 are connected to the
I/O port assigned in the datasheet pinout (default routing).
TIM1 Input Capture channels 2 and 3 can be routed by calling
SYSCFG_RITIMInputCaptureConfig()
Refer to the device reference manual for more details about
TIM1 input capture routing
2. For more details about using SYSCFG_RIIOSwitchConfig()
and SYSCFG_RIAnalogSwitchConfig() with COMP1 and COMP2, refer to
comparators driver
3. To output the Internal reference voltage VREFINT, configure corresponding
GPIO pin in input mode using GPIO_Init() then use SYSCFG_RIIOSwitchConfig()
4. To use the internal Pull-up and Pull-down resistors call
SYSCFG_RIResistorConfig()
@endverbatim
* @{
*/
/**
* @brief Deinitializes the RI registers to their default reset values.
* @param None
* @retval None
*/
void SYSCFG_RIDeInit(void)
{
RI->ICR1 = RI_ICR1_RESET_VALUE; /*!< Set RI->ICR1 to reset value */
RI->ICR2 = RI_ICR2_RESET_VALUE; /*!< Set RI->ICR2 to reset value */
RI->IOSR1 = RI_IOSR1_RESET_VALUE; /*!< Set RI->IOSR1 to reset value */
RI->IOSR2 = RI_IOSR2_RESET_VALUE; /*!< Set RI->IOSR2 to reset value */
RI->IOSR3 = RI_IOSR3_RESET_VALUE; /*!< Set RI->IOSR3 to reset value */
RI->IOSR4 = RI_IOSR4_RESET_VALUE; /*!< Set RI->IOSR3 to reset value */
RI->ASCR1 = RI_ASCR1_RESET_VALUE; /*!< Set RI->ASCR1 to reset value */
RI->ASCR2 = RI_ASCR2_RESET_VALUE; /*!< Set RI->ASCR2 to reset value */
RI->RCR = RI_RCR_RESET_VALUE; /*!< Set RI->RCR to reset value */
}
/**
* @brief Configures the routing interface to select which Input Output pin
* to be routed to TIM1 Input Capture.
* @param RI_InputCapture: selects the TIM1 input capture2 RI_InputCapture_IC2
* or the TIM1 input capture3 RI_InputCapture_IC3
* @param RI_InputCaptureRouting: selects the value to set in TIM1 Input Capture
* routing register ICRx and can be from RI_InputCaptureRouting_0 to
* RI_InputCaptureRouting_22.
* @retval None.
*/
void SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_TypeDef RI_InputCapture,
RI_InputCaptureRouting_TypeDef RI_InputCaptureRouting)
{
/* Check the parameters */
assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));
assert_param(IS_RI_INPUTCAPTUREROUTING(RI_InputCaptureRouting));
/* Check whether Input Capture 2 is selected */
if (RI_InputCapture == RI_InputCapture_IC2)
{
/* Set the value in ICR1 register to route TIM input Capture 2 */
RI->ICR1 = (uint8_t) RI_InputCaptureRouting;
}
else /* The Input Capture 3 is selected */
{
/* Set the value in ICR2 register to route TIM input capture 3 */
RI->ICR2 = (uint8_t) RI_InputCaptureRouting;
}
}
/**
* @brief Enables or disables the Routing Interface Analog switch.
* @param RI_AnalogSwitch: Analog Switch
* This parameter can be one of the following values:
* @arg RI_AnalogSwitch_0: Analog switch 0
* @arg RI_AnalogSwitch_1: Analog switch 1
* @arg RI_AnalogSwitch_2: Analog switch 2
* @arg RI_AnalogSwitch_3: Analog switch 3
* @arg RI_AnalogSwitch_4: Analog switch 4
* @arg RI_AnalogSwitch_5: Analog switch 5
* @arg RI_AnalogSwitch_6: Analog switch 6
* @arg RI_AnalogSwitch_7: Analog switch 7
* @arg RI_AnalogSwitch_8: Analog switch 8
* @arg RI_AnalogSwitch_9: Analog switch 9
* @arg RI_AnalogSwitch_10: Analog switch 10
* @arg RI_AnalogSwitch_11: Analog switch 11
* @arg RI_AnalogSwitch_12: Analog switch 14
* @param NewState: new state of the analog switch.
* This parameter can be ENABLE or DISABLE.
* @retval None
*/
void SYSCFG_RIAnalogSwitchConfig(RI_AnalogSwitch_TypeDef RI_AnalogSwitch,
FunctionalState NewState)
{
uint8_t AnalogSwitchRegister, AnalogSwitchIndex = 0;
/* Check the parameters */
assert_param(IS_RI_ANALOGSWITCH(RI_AnalogSwitch));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Get the analog switch register ASCR1 or ASCR2 */
AnalogSwitchRegister = (uint8_t) (RI_AnalogSwitch & (uint8_t) 0xF0);
/* Get the analog switch bit index in ASCRx register */
AnalogSwitchIndex = (uint8_t) (RI_AnalogSwitch & (uint8_t) 0x0F);
if (NewState != DISABLE)
{
if (AnalogSwitchRegister == (uint8_t) 0x10)
{
/* Enable the analog switch */
RI->ASCR1 |= (uint8_t) ((uint8_t)1 << (uint8_t) AnalogSwitchIndex);
}
else
{
/* Enable the analog switch */
RI->ASCR2 |= (uint8_t) ((uint8_t)1 << (uint8_t) AnalogSwitchIndex);
}
}
else
{
if (AnalogSwitchRegister == (uint8_t) 0x10)
{
/* Disable the analog switch */
RI->ASCR1 &= (uint8_t) (~(uint8_t)((uint8_t)1 << AnalogSwitchIndex));
}
else
{
/* Disable the analog switch */
RI->ASCR2 &= (uint8_t) (~ (uint8_t)((uint8_t)1 << AnalogSwitchIndex));
}
}
}
/**
* @brief Closes or Opens the routing interface Input Output switches.
* @param RI_IOSwitch: can be one of RI_IOSwitch_1..RI_IOSwitch_24
* @param NewState: new state of the Input Output Switch.
* This parameter can be ENABLE or DISABLE.
* @retval None.
*/
void SYSCFG_RIIOSwitchConfig(RI_IOSwitch_TypeDef RI_IOSwitch,
FunctionalState NewState)
{
uint8_t IOSwitchRegister, IOSwitchIndex = 0;
/* Check the parameters */
assert_param(IS_RI_IOSWITCH(RI_IOSwitch));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Get the Input Output switch bit index in IOSRx register */
IOSwitchIndex = (uint8_t) (RI_IOSwitch & (uint8_t) 0x0F);
/* Get the Input Output switch register IOSR1, IOSR2 or IOSR3 */
IOSwitchRegister = (uint8_t) (RI_IOSwitch & (uint8_t) 0xF0);
/* Check whether the Input Output switch control bit is in the IOSR1 register */
if (IOSwitchRegister == (uint8_t) 0x10)
{
if (NewState != DISABLE)
{
/* Close the Input Output switch */
RI->IOSR1 |= (uint8_t) ((uint8_t)1 << IOSwitchIndex);
}
else
{
/* Open the Input Output switch */
RI->IOSR1 &= (uint8_t) (~ (uint8_t)((uint8_t)1 << IOSwitchIndex));
}
}
/* Check whether the Input Output switch control bit is in the IOSR2 register */
else if (IOSwitchRegister == (uint8_t) 0x20)
{
if (NewState != DISABLE)
{
/* Close the Input Output switch */
RI->IOSR2 |= (uint8_t) ((uint8_t)1 << IOSwitchIndex);
}
else
{
/* Open the Input Output switch */
RI->IOSR2 &= (uint8_t) (~(uint8_t)((uint8_t)1 << IOSwitchIndex));
}
}
/* The Input Output switch control bit is in the IOSR3 register */
else if (IOSwitchRegister == (uint8_t) 0x30)
{
if (NewState != DISABLE)
{
/* Close the Input Output switch */
RI->IOSR3 |= (uint8_t) ((uint8_t)1 << IOSwitchIndex);
}
else
{
/* Open the Input Output switch */
RI->IOSR3 &= (uint8_t) (~ (uint8_t) ((uint8_t) 1 << IOSwitchIndex));
}
}
/* The Input Output switch control bit is in the IOSR4 register */
else
{
if (NewState != DISABLE)
{
/* Close the Input Output switch */
RI->IOSR4 |= (uint8_t) ((uint8_t)1 << IOSwitchIndex);
}
else
{
/* Open the Input Output switch */
RI->IOSR4 &= (uint8_t) (~ (uint8_t) ((uint8_t) 1 << IOSwitchIndex));
}
}
}
/**
* @brief Configures the Pull-up and Pull-down Resistors
* @param RI_Resistor: selects the resistor to connect,
* This parameter can be one of the following values:
* @arg RI_Resistor_10KPU: 10K pull up
* @arg RI_Resistor_400KPU: 400K pull up
* @arg RI_Resistor_10KPD: 10K pull down
* @arg RI_Resistor_400KPD: 400K pull down
* @retval None
*/
void SYSCFG_RIResistorConfig(RI_Resistor_TypeDef RI_Resistor, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_RI_RESISTOR(RI_Resistor));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the resistor */
RI->RCR |= (uint8_t) RI_Resistor;
}
else
{
/* Disable the Resistor */
RI->RCR &= (uint8_t) (~RI_Resistor);
}
}
/**
* @}
*/
/** @defgroup SYSCFG_Group2 SYSCFG configuration
* @brief SYSCFG configuration
*
@verbatim
===============================================================================
SYSCFG configuration functions
===============================================================================
===================================================================
SYSCFG Driver: how to use it for remapping
===================================================================
1. To remap the alternate function of some peripherals (such as: USART,
SPI, TIMs...), use SYSCFG_REMAPPinConfig()
2. To remap the DMA channels of ADC1 and TIM4, use SYSCFG_REMAPDMAChannelConfig()
@endverbatim
* @{
*/
/**
* @brief Deinitializes the Remapping registers to their default reset values.
* @param None
* @retval None
*/
void SYSCFG_REMAPDeInit(void)
{
/*!< Set RMPCR1 to reset value */
SYSCFG->RMPCR1 = SYSCFG_RMPCR1_RESET_VALUE;
/*!< Set RMPCR2 to reset value */
SYSCFG->RMPCR2 = SYSCFG_RMPCR2_RESET_VALUE;
/*!< Set RMPCR3 to reset value */
SYSCFG->RMPCR3 = SYSCFG_RMPCR3_RESET_VALUE;
}
/**
* @brief Changes the mapping of the specified pins.
* @param REMAP_Pin: selects the pin to remap.
* This parameter can be one of the following values:
* @arg REMAP_Pin_USART1TxRxPortA: USART1 Tx- Rx (PC3- PC2) remapping to PA2- PA3
* @arg REMAP_Pin_USART1TxRxPortC: USART1 Tx- Rx (PC3- PC2) remapping to PC5- PC6
* @arg REMAP_Pin_USART1Clk: USART1 CK (PC4) remapping to PA0
* @arg REMAP_Pin_SPI1Full: SPI1 MISO- MOSI- SCK- NSS(PB7- PB6- PB5- PB4)
* remapping to PA2- PA3- PC6- PC5
* @arg REMAP_Pin_ADC1ExtTRIG1: ADC1 External Trigger 1 (PA6) remapping to PD0
* @arg REMAP_Pin_TIM2TRIGPortA: TIM2 Trigger (PB3) remapping to PA4
* @arg REMAP_Pin_TIM3TRIGPortA: TIM3 Trigger (PD1) remapping to PA5
* @arg REMAP_Pin_TIM2TRIGLSE: TIM2 Trigger remapping to LSE
* @arg REMAP_Pin_TIM3TRIGLSE: TIM3 Trigger remapping to LSE
* @arg REMAP_Pin_SPI2Full: SPI2 MISO- MOSI- SCK- NSS(PG7- PG6- PG5- PG4)
* remapping to PI3- PI2- PI1- PI0
* @arg REMAP_Pin_TIM3TRIGPortG: TIM3 Trigger (PD1) remapping to PG3
* @arg REMAP_Pin_TIM23BKIN: TIM2 Break Input (PA4) remapping to PG0
* and TIM3 Break Input (PA5) remapping to PG1
* @arg REMAP_Pin_SPI1PortF: SPI1 MISO- MOSI- SCK- NSS(PB7- PB6- PB5- PB4)
* remapping to PF0- PF1- PF2- PF3
* @arg REMAP_Pin_USART3TxRxPortF: USART3 Tx- Rx (PG1- PG0) remapping to PF0- PF1
* @arg REMAP_Pin_USART3Clk: USART3 CK (PG2) remapping to PF2
* @arg REMAP_Pin_TIM3Channel1: TIM3 Channel 1 (PB1) remapping to PI0
* @arg REMAP_Pin_TIM3Channel2: TIM3 Channel 2 (PD0) remapping to PI3
* @arg REMAP_Pin_CCO: CCO (PC4) remapping to PE2
* @arg REMAP_Pin_TIM2Channel1: TIM2 Channel 1 (PB0) remapping to PC5
* @arg REMAP_Pin_TIM2Channel2: TIM2 Channel 2 (PB2) remapping to PC6
* @param NewState: This parameter can be ENABLE or DISABLE.
* @retval None
*/
void SYSCFG_REMAPPinConfig(REMAP_Pin_TypeDef REMAP_Pin, FunctionalState NewState)
{
uint8_t regindex = 0;
/* Check the parameters */
assert_param(IS_REMAP_PIN(REMAP_Pin));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Read register index */
regindex = (uint8_t) ((uint16_t) REMAP_Pin >> 8);
/* Check if REMAP_Pin is in RMPCR1 register */
if (regindex == 0x01)
{
SYSCFG->RMPCR1 &= (uint8_t)((uint8_t)((uint8_t)REMAP_Pin << 4) | (uint8_t)0x0F);
if (NewState != DISABLE)
{
SYSCFG->RMPCR1 |= (uint8_t)((uint16_t)REMAP_Pin & (uint16_t)0x00F0);
}
}
/* Check if REMAP_Pin is in RMPCR2 register */
else if (regindex == 0x02)
{
if (NewState != DISABLE)
{
SYSCFG->RMPCR2 |= (uint8_t) REMAP_Pin;
}
else
{
SYSCFG->RMPCR2 &= (uint8_t)((uint16_t)(~(uint16_t)REMAP_Pin));
}
}
/* REMAP_Pin is in RMPCR3 register */
else
{
if (NewState != DISABLE)
{
SYSCFG->RMPCR3 |= (uint8_t) REMAP_Pin;
}
else
{
SYSCFG->RMPCR3 &= (uint8_t)((uint16_t)(~(uint16_t)REMAP_Pin));
}
}
}
/**
* @brief Remaps the DMA Channel to the specific peripheral (ADC or TIM4)
* @param REMAP_DMAChannel: specifies the DMA Channel to remap.
* This parameter can be one of the following values:
* @arg REMAP_DMA1Channel_ADC1ToChannel0: ADC1 DMA1 req/ack mapped on DMA1 channel 0
* @arg REMAP_DMA1Channel_ADC1ToChannel1: ADC1 DMA1 req/ack mapped on DMA1 channel 1
* @arg REMAP_DMA1Channel_ADC1ToChannel2: ADC1 DMA1 req/ack mapped on DMA1 channel 2
* @arg REMAP_DMA1Channel_ADC1ToChannel3: ADC1 DMA1 req/ack mapped on DMA1 channel 3
* @arg REMAP_DMA1Channel_TIM4ToChannel0: TIM4 DMA1 req/ack mapped on DMA1 channel 0
* @arg REMAP_DMA1Channel_TIM4ToChannel1: TIM4 DMA1 req/ack mapped on DMA1 channel 1
* @arg REMAP_DMA1Channel_TIM4ToChannel2: TIM4 DMA1 req/ack mapped on DMA1 channel 2
* @arg REMAP_DMA1Channel_TIM4ToChannel3: TIM4 DMA1 req/ack mapped on DMA1 channel 3
* @retval None
*/
void SYSCFG_REMAPDMAChannelConfig(REMAP_DMAChannel_TypeDef REMAP_DMAChannel)
{
/* Check the parameters */
assert_param(IS_REMAP_DMACHANNEL(REMAP_DMAChannel));
/* Check if the TIM4 DMA channel is selected: bits 4 --> 7 are set */
if ((REMAP_DMAChannel & 0xF0) != RESET)
{
/* Reset the TIM4 DMA channels */
SYSCFG->RMPCR1 &= (uint8_t) (~SYSCFG_RMPCR1_TIM4DMA_REMAP);
}
/* ADC DMA channel is selected: bits 4 --> 7 are reset */
else
{
/* Reset the ADC DMA channels */
SYSCFG->RMPCR1 &= (uint8_t) (~SYSCFG_RMPCR1_ADC1DMA_REMAP);
}
/* Set the DMA Channels remapping */
SYSCFG->RMPCR1 |= (uint8_t) ((uint8_t)0x0F & REMAP_DMAChannel);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_tim4.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the TIM4 peripheral:
* - TimeBase management
* - Interrupts, DMA and flags management
* - Clocks management
* - Synchronization management
*
* @verbatim
*
* ===================================================================
* How to use this driver
* ===================================================================
* This driver provides functions to configure and initialize the TIM4
* peripheral
* These functions are split in 4 groups:
*
* 1. TIM4 TimeBase management: this group includes all needed functions
* to configure the TIM Timebase unit:
* - Set/Get Prescaler
* - Set/Get Autoreload
* - Select the One Pulse mode
* - Update Request Configuration
* - Update Disable Configuration
* - Auto-Preload Configuration
* - Enable/Disable the counter
*
* 2. TIM4 interrupts, DMA and flags management
* - Enable/Disable interrupt sources
* - Get flags status
* - Clear flags/ Pending bits
* - Enable/Disable DMA requests
*
* 3. TIM4 clocks management: this group includes all needed functions
* to configure the clock controller unit:
* - Select internal clock
*
* 4. TIM4 synchronization management: this group includes all needed
* functions to configure the Synchronization unit:
* - Select Input Trigger
* - Select Output Trigger
* - Select Master Slave Mode
*
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_tim4.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup TIM4
* @brief TIM4 driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup TIM4_Private_Functions
* @{
*/
/** @defgroup TIM4_Group1 TimeBase management functions
* @brief TimeBase management functions
*
@verbatim
===============================================================================
TimeBase management functions
===============================================================================
===================================================================
TIM4 Driver: how to use it in Timing(Time base) Mode
===================================================================
To use the Timer in Timing(Time base) mode, the following steps are mandatory:
1. Enable TIM4 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM4, ENABLE) function.
2. Call TIM4_TimeBaseInit() to configure the Time Base unit with the
corresponding configuration.
3. Enable global interrupts if you need to generate the update interrupt.
4. Enable the corresponding interrupt using the function TIM4_ITConfig(TIM4_IT_Update)
5. Call the TIM4_Cmd(ENABLE) function to enable the TIM4 counter.
Note1: All other functions can be used separately to modify, if needed,
a specific feature of the Timer.
@endverbatim
* @{
*/
/**
* @brief Deinitializes the TIM4 peripheral registers to their default reset values.
* @param None
* @retval None
*/
void TIM4_DeInit(void)
{
TIM4->CR1 = TIM4_CR1_RESET_VALUE;
TIM4->CR2 = TIM4_CR2_RESET_VALUE;
TIM4->SMCR = TIM4_SMCR_RESET_VALUE;
TIM4->IER = TIM4_IER_RESET_VALUE;
TIM4->CNTR = TIM4_CNTR_RESET_VALUE;
TIM4->PSCR = TIM4_PSCR_RESET_VALUE;
TIM4->ARR = TIM4_ARR_RESET_VALUE;
TIM4->SR1 = TIM4_SR1_RESET_VALUE;
}
/**
* @brief Initializes the TIM4 Time Base Unit according to the specified parameters.
* @param TIM4_Prescaler: Prescaler
* This parameter can be one of the following values:
* @arg TIM4_Prescaler_1: Time base Prescaler = 1 (No effect)
* @arg TIM4_Prescaler_2: Time base Prescaler = 2
* @arg TIM4_Prescaler_4: Time base Prescaler = 4
* @arg TIM4_Prescaler_8: Time base Prescaler = 8
* @arg TIM4_Prescaler_16: Time base Prescaler = 16
* @arg TIM4_Prescaler_32: Time base Prescaler = 32
* @arg TIM4_Prescaler_64: Time base Prescaler = 64
* @arg TIM4_Prescaler_128: Time base Prescaler = 128
* @arg TIM4_Prescaler_256: Time base Prescaler = 256
* @arg TIM4_Prescaler_512: Time base Prescaler = 512
* @arg TIM4_Prescaler_1024: Time base Prescaler = 1024
* @arg TIM4_Prescaler_2048: Time base Prescaler = 2048
* @arg TIM4_Prescaler_4096: Time base Prescaler = 4096
* @arg TIM4_Prescaler_8192: Time base Prescaler = 8192
* @arg TIM4_Prescaler_16384: Time base Prescaler = 16384
* @arg TIM4_Prescaler_32768: Time base Prescaler = 32768
* @param TIM4_Period: This parameter must be a value between 0x00 and 0xFF.
* @retval None
*/
void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler,
uint8_t TIM4_Period)
{
/* Check TIM4 prescaler value */
assert_param(IS_TIM4_Prescaler(TIM4_Prescaler));
/* Set the Autoreload value */
TIM4->ARR = (uint8_t)(TIM4_Period);
/* Set the Prescaler value */
TIM4->PSCR = (uint8_t)(TIM4_Prescaler);
/* Generate an update event to reload the Prescaler value immediately */
TIM4->EGR = TIM4_EventSource_Update;
}
/**
* @brief Configures the TIM4 Prescaler.
* @param Prescaler: Specifies the Prescaler Register value
* This parameter can be one of the following values:
* @arg TIM4_Prescaler_1: Time base Prescaler = 1 (No effect)
* @arg TIM4_Prescaler_2: Time base Prescaler = 2
* @arg TIM4_Prescaler_4: Time base Prescaler = 4
* @arg TIM4_Prescaler_8: Time base Prescaler = 8
* @arg TIM4_Prescaler_16: Time base Prescaler = 16
* @arg TIM4_Prescaler_32: Time base Prescaler = 32
* @arg TIM4_Prescaler_64: Time base Prescaler = 64
* @arg TIM4_Prescaler_128: Time base Prescaler = 128
* @arg TIM4_Prescaler_256: Time base Prescaler = 256
* @arg TIM4_Prescaler_512: Time base Prescaler = 512
* @arg TIM4_Prescaler_1024: Time base Prescaler = 1024
* @arg TIM4_Prescaler_2048: Time base Prescaler = 2048
* @arg TIM4_Prescaler_4096: Time base Prescaler = 4096
* @arg TIM4_Prescaler_8192: Time base Prescaler = 8192
* @arg TIM4_Prescaler_16384: Time base Prescaler = 16384
* @arg TIM4_Prescaler_32768: Time base Prescaler = 32768
* @param TIM4_PSCReloadMode: Specifies the TIM4 Prescaler Reload mode.
* This parameter can be one of the following values:
* @arg TIM4_PSCReloadMode_Update: Prescaler value is reloaded at every update
* @arg TIM4_PSCReloadMode_Immediate: Prescaler value is reloaded immediately
* @retval None
*/
void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler,
TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
{
/* Check the parameters */
assert_param(IS_TIM4_Prescaler_RELOAD(TIM4_PSCReloadMode));
assert_param(IS_TIM4_Prescaler(Prescaler));
/* Set the Prescaler value */
TIM4->PSCR = (uint8_t) Prescaler;
/* Set or reset the UG Bit */
if (TIM4_PSCReloadMode == TIM4_PSCReloadMode_Immediate)
{
TIM4->EGR |= TIM4_EGR_UG ;
}
else
{
TIM4->EGR &= (uint8_t)(~TIM4_EGR_UG) ;
}
}
/**
* @brief Sets the TIM4 Counter Register value.
* @param Counter: Specifies the Counter register new value.
* This parameter is between 0x00 and 0xFF.
* @retval None
*/
void TIM4_SetCounter(uint8_t Counter)
{
/* Set the Counter Register value */
TIM4->CNTR = (uint8_t)(Counter);
}
/**
* @brief Sets the TIM4 Autoreload Register value.
* @param Autoreload: Specifies the Autoreload register new value.
* This parameter is between 0x00 and 0xFF.
* @retval None
*/
void TIM4_SetAutoreload(uint8_t Autoreload)
{
/* Set the Autoreload Register value */
TIM4->ARR = (uint8_t)(Autoreload);
}
/**
* @brief Gets the TIM4 Counter value.
* @param None
* @retval Counter Register value.
*/
uint8_t TIM4_GetCounter(void)
{
uint8_t tmpcntr = 0;
tmpcntr = TIM4->CNTR;
/* Get the Counter Register value */
return ((uint8_t)tmpcntr);
}
/**
* @brief Gets the TIM4 Prescaler value.
* @param None
* @retval TIM4 Prescaler can be one of the following values:
* - TIM4_Prescaler_1: Time base Prescaler = 1 (No effect)
* - TIM4_Prescaler_2: Time base Prescaler = 2
* - TIM4_Prescaler_4: Time base Prescaler = 4
* - TIM4_Prescaler_8: Time base Prescaler = 8
* - TIM4_Prescaler_16: Time base Prescaler = 16
* - TIM4_Prescaler_32: Time base Prescaler = 32
* - TIM4_Prescaler_64: Time base Prescaler = 64
* - TIM4_Prescaler_128: Time base Prescaler = 128
* - TIM4_Prescaler_256: Time base Prescaler = 256
* - TIM4_Prescaler_512: Time base Prescaler = 512
* - TIM4_Prescaler_1024: Time base Prescaler = 1024
* - TIM4_Prescaler_2048: Time base Prescaler = 2048
* - TIM4_Prescaler_4096: Time base Prescaler = 4096
* - TIM4_Prescaler_8192: Time base Prescaler = 8192
* - TIM4_Prescaler_16384: Time base Prescaler = 16384
* - TIM4_Prescaler_32768: Time base Prescaler = 32768
*/
TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void)
{
/* Get the Prescaler Register value */
return ((TIM4_Prescaler_TypeDef)TIM4->PSCR);
}
/**
* @brief Enables or Disables the TIM4 Update event.
* @param NewState: The new state of the TIM4 peripheral Preload register.
* This parameter can be ENABLE or DISABLE
* @retval None
*/
void TIM4_UpdateDisableConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set or Reset the UDIS Bit */
if (NewState != DISABLE)
{
TIM4->CR1 |= TIM4_CR1_UDIS ;
}
else
{
TIM4->CR1 &= (uint8_t)(~TIM4_CR1_UDIS) ;
}
}
/**
* @brief Selects the TIM4 Update Request Interrupt source.
* @param TIM4_UpdateSource: Specifies the Update source.
* This parameter can be one of the following values:
* @arg TIM4_UpdateSource_Global: Global Update request source
* @arg TIM4_UpdateSource_Regular: Regular Update request source
* @retval None
*/
void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
{
/* Check the parameters */
assert_param(IS_TIM4_UPDATE_SOURCE(TIM4_UpdateSource));
/* Set or Reset the URS Bit */
if (TIM4_UpdateSource == TIM4_UpdateSource_Regular)
{
TIM4->CR1 |= TIM4_CR1_URS ;
}
else
{
TIM4->CR1 &= (uint8_t)(~TIM4_CR1_URS) ;
}
}
/**
* @brief Enables or disables TIM4 peripheral Preload register on ARR.
* @param NewState: The new state of the TIM4 peripheral Preload register.
* This parameter can be ENABLE or DISABLE
* @retval None
*/
void TIM4_ARRPreloadConfig(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set or Reset the ARPE Bit */
if (NewState != DISABLE)
{
TIM4->CR1 |= TIM4_CR1_ARPE ;
}
else
{
TIM4->CR1 &= (uint8_t)(~TIM4_CR1_ARPE) ;
}
}
/**
* @brief Selects the TIM4's One Pulse Mode.
* @param TIM4_OPMode: Specifies the OPM Mode to be used.
* This parameter can be one of the following values:
* @arg TIM4_OPMode_Single: Single one Pulse mode (OPM Active)
* @arg TIM4_OPMode_Repetitive: Repetitive Pulse mode (OPM inactive)
* @retval None
*/
void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode)
{
/* Check the parameters */
assert_param(IS_TIM4_OPM_MODE(TIM4_OPMode));
/* Set or Reset the OPM Bit */
if (TIM4_OPMode == TIM4_OPMode_Single)
{
TIM4->CR1 |= TIM4_CR1_OPM ;
}
else
{
TIM4->CR1 &= (uint8_t)(~TIM4_CR1_OPM) ;
}
}
/**
* @brief Enables or disables the TIM4 peripheral.
* @param NewState: The new state of the TIM4 peripheral.
* This parameter can be ENABLE or DISABLE
* @retval None
*/
void TIM4_Cmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* set or Reset the CEN Bit */
if (NewState != DISABLE)
{
TIM4->CR1 |= TIM4_CR1_CEN ;
}
else
{
TIM4->CR1 &= (uint8_t)(~TIM4_CR1_CEN) ;
}
}
/**
* @}
*/
/** @defgroup TIM4_Group2 Interrupts DMA and flags management functions
* @brief Interrupts, DMA and flags management functions
*
@verbatim
===============================================================================
Interrupts, DMA and flags management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables or disables the specified TIM4 interrupts.
* @param TIM4_IT: Specifies the TIM4 interrupts sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg TIM4_IT_Update: Update
* @arg TIM4_IT_Trigger: Trigger
* @param NewState: The new state of the TIM4 peripheral.
* This parameter can be ENABLE or DISABLE
* @retval None
*/
void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_TIM4_IT(TIM4_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the Interrupt sources */
TIM4->IER |= (uint8_t)TIM4_IT;
}
else
{
/* Disable the Interrupt sources */
TIM4->IER &= (uint8_t)(~(uint8_t)TIM4_IT);
}
}
/**
* @brief Configures the TIM4 event to be generated by software.
* @param TIM4_EventSource: Specifies the event source.
* This parameter can be one of the following values:
* @arg TIM4_EventSource_Update: Update
* @arg TIM4_EventSource_Trigger: Trigger
* @retval None
*/
void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource)
{
/* Check the parameters */
assert_param(IS_TIM4_EVENT_SOURCE((uint8_t)TIM4_EventSource));
/* Set the event sources */
TIM4->EGR |= (uint8_t)TIM4_EventSource;
}
/**
* @brief Checks whether the specified TIM4 flag is set or not.
* @param TIM4_FLAG: Specifies the flag to check.
* This parameter can be one of the following values:
* @arg TIM4_FLAG_Update: Update
* @arg TIM4_FLAG_Trigger: Trigger
* @retval FlagStatus: The new state of TIM4_FLAG.
* This parameter can be SET or RESET.
*/
FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_TIM4_GET_FLAG(TIM4_FLAG));
if ((TIM4->SR1 & (uint8_t)TIM4_FLAG) != 0)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return ((FlagStatus)bitstatus);
}
/**
* @brief Clears the TIM's pending flags.
* @param TIM4_FLAG: Specifies the flag to clear.
* This parameter can be one of the following values:
* @arg TIM4_FLAG_Update: Update
* @arg TIM4_FLAG_Trigger: Trigger
* @retval None
*/
void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG)
{
/* Check the parameters */
assert_param(IS_TIM4_CLEAR_FLAG((uint8_t)TIM4_FLAG));
/* Clear the flags (rc_w0) clear this bit by writing 0. Writing '1' has no effect*/
TIM4->SR1 = (uint8_t)(~((uint8_t)TIM4_FLAG));
}
/**
* @brief Checks whether the TIM4 interrupt has occurred or not.
* @param TIM4_IT: Specifies the TIM4 interrupt source to check.
* This parameter can be one of the following values:
* @arg TIM4_IT_Update: Update
* @arg TIM4_IT_Trigger: Trigger
* @retval ITStatus: The new state of the TIM4_IT.
* This parameter can be SET or RESET
*/
ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT)
{
ITStatus bitstatus = RESET;
uint8_t itStatus = 0x0, itEnable = 0x0;
/* Check the parameters */
assert_param(IS_TIM4_GET_IT(TIM4_IT));
itStatus = (uint8_t)(TIM4->SR1 & (uint8_t)TIM4_IT);
itEnable = (uint8_t)(TIM4->IER & (uint8_t)TIM4_IT);
if ((itStatus != (uint8_t)RESET ) && (itEnable != (uint8_t)RESET ))
{
bitstatus = (ITStatus)SET;
}
else
{
bitstatus = (ITStatus)RESET;
}
return ((ITStatus)bitstatus);
}
/**
* @brief Clears the TIM4's interrupt pending bits.
* @param TIM4_IT: Specifies the pending bit to clear.
* This parameter can be one of the following values:
* @arg TIM4_IT_Update: Update
* @arg TIM4_IT_Trigger: Trigger
* @retval None
*/
void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT)
{
/* Check the parameters */
assert_param(IS_TIM4_IT(TIM4_IT));
/* Clear the IT pending Bit */
TIM4->SR1 = (uint8_t)(~(uint8_t)TIM4_IT);
}
/**
* @brief Enables or disables the TIMx's DMA Requests.
* @param TIM4_DMASources: specifies the DMA Request sources.
* This parameter can be one of the following values:
* @arg TIM4_DMASource_Update: Update
* @param NewState: new state of the DMA Request sources.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void TIM4_DMACmd( TIM4_DMASource_TypeDef TIM4_DMASource, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_TIM4_DMA_SOURCE(TIM4_DMASource));
if (NewState != DISABLE)
{
/* Enable the DMA sources */
TIM4->DER |= (uint8_t)TIM4_DMASource;
}
else
{
/* Disable the DMA sources */
TIM4->DER &= (uint8_t)~TIM4_DMASource;
}
}
/**
* @}
*/
/** @defgroup TIM4_Group3 Clocks management functions
* @brief Clocks management functions
*
@verbatim
===============================================================================
Clocks management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables the TIM4 internal Clock.
* @param None
* @retval None
*/
void TIM4_InternalClockConfig(void)
{
/* Disable slave mode to clock the prescaler directly with the internal clock */
TIM4->SMCR &= (uint8_t)(~TIM4_SMCR_SMS);
}
/**
* @}
*/
/** @defgroup TIM4_Group4 Synchronization management functions
* @brief Synchronization management functions
*
@verbatim
===============================================================================
Synchronization management functions
===============================================================================
===================================================================
TIM4 Driver: how to use it in synchronization Mode
===================================================================
Case of two/several Timers
**************************
1. If TIM4 is used as master to other timers use the following functions:
- TIM4_SelectOutputTrigger()
- TIM4_SelectMasterSlaveMode()
2. If TIM4 is used as slave to other timers use the following functions:
- TIM4_SelectInputTrigger()
- TIM4_SelectSlaveMode()
@endverbatim
* @{
*/
/**
* @brief Selects the TIM4 Input Trigger source.
* @param TIM4_InputTriggerSource: Specifies Input Trigger source.
* This parameter can be one of the following values:
* @arg TIM4_TRGSelection_TIM5: TRIG Input source = TIM5 TRIG Output
* @arg TIM4_TRGSelection_TIM1: TRIG Input source = TIM1 TRIG Output
* @arg TIM4_TRGSelection_TIM3: TRIG Input source = TIM3 TRIG Output
* @arg TIM4_TRGSelection_TIM2: TRIG Input source = TIM2 TRIG Output
* @retval None
*/
void TIM4_SelectInputTrigger(TIM4_TRGSelection_TypeDef TIM4_InputTriggerSource)
{
uint8_t tmpsmcr = 0;
/* Check the parameters */
assert_param(IS_TIM4_TRIGGER_SELECTION(TIM4_InputTriggerSource));
tmpsmcr = TIM4->SMCR;
/* Select the Trigger Source */
tmpsmcr &= (uint8_t)(~TIM4_SMCR_TS);
tmpsmcr |= (uint8_t)TIM4_InputTriggerSource;
TIM4->SMCR = (uint8_t)tmpsmcr;
}
/**
* @brief Selects the TIM4 Trigger Output Mode.
* @param TIM4_TRGOSource: Specifies the Trigger Output source.
* This parameter can be one of the following values:
* @arg TIM4_TRGOSource_Reset: Trigger Output source = Reset
* @arg TIM4_TRGOSource_Enable: Trigger Output source = TIM4 is enabled
* @arg TIM4_TRGOSource_Update: Trigger Output source = Update event
* @retval None
*/
void TIM4_SelectOutputTrigger(TIM4_TRGOSource_TypeDef TIM4_TRGOSource)
{
uint8_t tmpcr2 = 0;
/* Check the parameters */
assert_param(IS_TIM4_TRGO_SOURCE(TIM4_TRGOSource));
tmpcr2 = TIM4->CR2;
/* Reset the MMS Bits */
tmpcr2 &= (uint8_t)(~TIM4_CR2_MMS);
/* Select the TRGO source */
tmpcr2 |= (uint8_t)TIM4_TRGOSource;
TIM4->CR2 = tmpcr2;
}
/**
* @brief Selects the TIM4 Slave Mode.
* @param TIM4_SlaveMode: Specifies the TIM4 Slave Mode.
* This parameter can be one of the following values:
* @arg TIM4_SlaveMode_Disable: Disable slave mode to clock the prescaler
directly with the internal clock
* @arg TIM4_SlaveMode_Reset: Slave Mode Selection = Reset
* @arg TIM4_SlaveMode_Gated: Slave Mode Selection = Gated
* @arg TIM4_SlaveMode_Trigger: Slave Mode Selection = Trigger
* @arg TIM4_SlaveMode_External1: Slave Mode Selection = External 1
* @retval None
*/
void TIM4_SelectSlaveMode(TIM4_SlaveMode_TypeDef TIM4_SlaveMode)
{
uint8_t tmpsmcr = 0;
/* Check the parameters */
assert_param(IS_TIM4_SLAVE_MODE(TIM4_SlaveMode));
tmpsmcr = TIM4->SMCR;
/* Reset the SMS Bits */
tmpsmcr &= (uint8_t)(~TIM4_SMCR_SMS);
/* Select the Slave Mode */
tmpsmcr |= (uint8_t)TIM4_SlaveMode;
TIM4->SMCR = tmpsmcr;
}
/**
* @brief Sets or Resets the TIM4 Master/Slave Mode.
* @param NewState: The new state of the synchronization between TIM4 and its slaves (through TRGO).
* This parameter can be ENABLE or DISABLE
* @retval None
*/
void TIM4_SelectMasterSlaveMode(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* Set or Reset the MSM Bit */
if (NewState != DISABLE)
{
TIM4->SMCR |= TIM4_SMCR_MSM;
}
else
{
TIM4->SMCR &= (uint8_t)(~TIM4_SMCR_MSM);
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm8l15x_wfe.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Wait for Event (WFE) peripheral:
* - WFE Source configuration and management
*
* @verbatim
*
* ===================================================================
* WFE specific features
* ===================================================================
*
* Wait for event mode (WFE) stops the CPU but allows the other peripherals
* and interrupt controller to continue running.
* This mode is entered from Run mode by executing a WFE instruction.
* Peripheral events can be generated by the timers, serial interfaces,
* DMA controller, comparators and I/O ports.
* These are enabled by using the WFE_WakeUpSourceEventCmd() function.
*
* When a peripheral event is enabled, the corresponding interrupts are
* not served and you have to clear the corresponding flag status.
*
* There are two ways to wake up the CPU from WFE mode:
* - Interrupts: When an interrupt occurs, the CPU wakes up from WFE mode
* serves the interrupt then goes back to WFE mode.
* - Wake up event: when a wake up event occurs, the CPU wakes up and
* resumes processing, in this case and to save time and power consumption
* there is no context save/restore activity.
*
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_wfe.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup WFE
* @brief WFE driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup WFE_Private_Functions
* @{
*/
/** @defgroup WFE_Group1 WFE Source configuration and management functions
* @brief WFE Source configuration and management functions
*
@verbatim
===============================================================================
WFE Source configuration and management functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the WFE registers to their default reset value.
* @param None
* @retval None
*/
void WFE_DeInit(void)
{
WFE->CR1 = WFE_CRX_RESET_VALUE;
WFE->CR2 = WFE_CRX_RESET_VALUE;
WFE->CR3 = WFE_CRX_RESET_VALUE;
WFE->CR4 = WFE_CRX_RESET_VALUE;
}
/**
* @brief Set the source that can generate the wake-up event.
* @param WFE_Source: The wake-up event source .
* This parameter can be one of the following values:
* @arg WFE_Source_TIM2_EV0: TIM2 Update/Trigger and Break interrupt
* @arg WFE_Source_TIM2_EV1: TIM2 Capture/Compare interrupt
* @arg WFE_Source_TIM1_EV0: TIM1 Update/Trigger and Break interrupt
* @arg WFE_Source_TIM1_EV1: TIM1 Capture/Compare interrupt
* @arg WFE_Source_EXTI_EV0: I/O port interrupt from Pins 0
* @arg WFE_Source_EXTI_EV1: I/O port interrupt from Pins 1
* @arg WFE_Source_EXTI_EV2: I/O port interrupt from Pins 2
* @arg WFE_Source_EXTI_EV3: I/O port interrupt from Pins 3
* @arg WFE_Source_EXTI_EV4: I/O port interrupt from Pins 4
* @arg WFE_Source_EXTI_EV5: I/O port interrupt from Pins 5
* @arg WFE_Source_EXTI_EV6: I/O port interrupt from Pins 6
* @arg WFE_Source_EXTI_EV7: I/O port interrupt from Pins 7
* @arg WFE_Source_EXTI_EVB_G: I/O port interrupt from port B and G
* @arg WFE_Source_EXTI_EVD_H: I/O port interrupt from Port D and H
* @arg WFE_Source_EXTI_EVE_F: I/O port interrupt from Port E and F
* @arg WFE_Source_ADC1_COMP_EV: ADC1, COMP1 and COMP2 interrupts
* @arg WFE_Source_TIM3_EV0: TIM3 Update/Trigger and Break interrupt
* @arg WFE_Source_TIM3_EV1: TIM3 Capture/Compare interrupt
* @arg WFE_Source_TIM4_EV: TIM4 Update and Trigger interrupt
* @arg WFE_Source_SPI1_EV: SPI1 Rx and Tx interrupt
* @arg WFE_Source_I2C1_EV: I2C1 Rx and Tx interrupt
* @arg WFE_Source_USART1_EV: USART1 Rx and Tx interrupt
* @arg WFE_Source_DMA1CH01_EV: DMA1 channel 0 and 1 interrupt
* @arg WFE_Source_DMA1CH23_EV: DMA1 channel 2 and 3 interrupt
* @arg WFE_Source_RTC_CSS_EV: RTC or CSS on LSE event
* @arg WFE_Source_SPI2_EV: SPI2 Rx and Tx interrupt
* @arg WFE_Source_USART2_EV: USART2 Rx and Tx interrupt
* @arg WFE_Source_USART3_EV: USART3 Rx and Tx interrupt
* @arg WFE_Source_TIM5_EV0: TIM5 Update/Trigger and Break interrupt
* @arg WFE_Source_TIM5_EV1: TIM5 Capture/Compare interrupt
* @param NewState : The wake-up new state.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void WFE_WakeUpSourceEventCmd(WFE_Source_TypeDef WFE_Source, FunctionalState NewState)
{
uint8_t register_index = 0;
/* Check function parameters */
assert_param(IS_WFE_SOURCE(WFE_Source));
assert_param(IS_FUNCTIONAL_STATE(NewState));
/* The mask is reversed in order to */
register_index = (uint8_t)((uint16_t)WFE_Source >> 0x08);
if (NewState != DISABLE)
{
switch (register_index)
{
case 1:
WFE->CR1 |= (uint8_t)WFE_Source;
break;
case 2:
WFE->CR2 |= (uint8_t)WFE_Source;
break;
case 3:
WFE->CR3 |= (uint8_t)WFE_Source;
break;
case 4:
WFE->CR4 |= (uint8_t)WFE_Source;
break;
default:
break;
}
}
else
{
switch (register_index)
{
case 1:
WFE->CR1 &= (uint8_t)(~(uint8_t)WFE_Source);
break;
case 2:
WFE->CR2 &= (uint8_t)(~ (uint8_t)WFE_Source);
break;
case 3:
WFE->CR3 &= (uint8_t)(~(uint8_t)WFE_Source);
break;
case 4:
WFE->CR4 &= (uint8_t)(~(uint8_t)WFE_Source);
break;
default:
break;
}
}
}
/**
* @brief Gets the status of the specified source event.
* @param WFE_Source: The wake-up event source.
* This parameter can be one of the following values:
* @arg WFE_Source_TIM2_EV0: TIM2 Update/Trigger and Break interrupt
* @arg WFE_Source_TIM2_EV1: TIM2 Capture/Compare interrupt
* @arg WFE_Source_TIM1_EV0: TIM1 Update/Trigger and Break interrupt
* @arg WFE_Source_TIM1_EV1: TIM1 Capture/Compare interrupt
* @arg WFE_Source_EXTI_EV0: I/O port interrupt from Pins 0
* @arg WFE_Source_EXTI_EV1: I/O port interrupt from Pins 1
* @arg WFE_Source_EXTI_EV2: I/O port interrupt from Pins 2
* @arg WFE_Source_EXTI_EV3: I/O port interrupt from Pins 3
* @arg WFE_Source_EXTI_EV4: I/O port interrupt from Pins 4
* @arg WFE_Source_EXTI_EV5: I/O port interrupt from Pins 5
* @arg WFE_Source_EXTI_EV6: I/O port interrupt from Pins 6
* @arg WFE_Source_EXTI_EV7: I/O port interrupt from Pins 7
* @arg WFE_Source_EXTI_EVB_G: I/O port interrupt from port B and G
* @arg WFE_Source_EXTI_EVD_H: I/O port interrupt from Port D and H
* @arg WFE_Source_EXTI_EVE_F: I/O port interrupt from Port E and F
* @arg WFE_Source_ADC1_COMP_EV: ADC1, COMP1 and COMP2 interrupts
* @arg WFE_Source_TIM3_EV0: TIM3 Update/Trigger and Break interrupt
* @arg WFE_Source_TIM3_EV1: TIM3 Capture/Compare interrupt
* @arg WFE_Source_TIM4_EV: TIM4 Update and Trigger interrupt
* @arg WFE_Source_SPI1_EV: SPI1 Rx and Tx interrupt
* @arg WFE_Source_I2C1_EV: I2C1 Rx and Tx interrupt
* @arg WFE_Source_USART1_EV: USART1 Rx and Tx interrupt
* @arg WFE_Source_DMA1CH01_EV: DMA1 channel 0 and 1 interrupt
* @arg WFE_Source_DMA1CH23_EV: DMA1 channel 2 and 3 interrupt
* @arg WFE_Source_RTC_CSS_EV: RTC or CSS on LSE event
* @arg WFE_Source_SPI2_EV: SPI2 Rx and Tx interrupt
* @arg WFE_Source_USART2_EV: USART2 Rx and Tx interrupt
* @arg WFE_Source_USART3_EV: USART3 Rx and Tx interrupt
* @arg WFE_Source_TIM5_EV0: TIM5 Update/Trigger and Break interrupt
* @arg WFE_Source_TIM5_EV1: TIM5 Capture/Compare interrupt
* @retval Source Event state, ENABLE or DISABLE
*/
FunctionalState WFE_GetWakeUpSourceEventStatus(WFE_Source_TypeDef WFE_Source)
{
FunctionalState status = DISABLE;
/* Check function parameters */
assert_param(IS_WFE_SOURCE(WFE_Source));
switch (WFE_Source)
{
case WFE_Source_TIM2_EV0:
case WFE_Source_TIM2_EV1:
case WFE_Source_TIM1_EV0:
case WFE_Source_TIM1_EV1:
case WFE_Source_EXTI_EV0:
case WFE_Source_EXTI_EV1:
case WFE_Source_EXTI_EV2:
case WFE_Source_EXTI_EV3:
if ((WFE->CR1 & (uint8_t)WFE_Source) != (uint8_t)0x00)
{
/* The wake-up event source is enabled*/
status = ENABLE;
}
else
{
/* The wake-up event source is disabled*/
status = DISABLE;
}
break;
case WFE_Source_EXTI_EV4:
case WFE_Source_EXTI_EV5:
case WFE_Source_EXTI_EV6:
case WFE_Source_EXTI_EV7:
case WFE_Source_EXTI_EVB_G:
case WFE_Source_EXTI_EVD_H:
case WFE_Source_EXTI_EVE_F:
case WFE_Source_ADC1_COMP_EV:
if ((WFE->CR2 & (uint8_t)WFE_Source) != (uint8_t)0x00)
{
/* The wake-up event source is enabled*/
status = ENABLE;
}
else
{
/* The wake-up event source is disabled*/
status = DISABLE;
}
break;
case WFE_Source_TIM3_EV0:
case WFE_Source_TIM3_EV1:
case WFE_Source_TIM4_EV:
case WFE_Source_SPI1_EV:
case WFE_Source_I2C1_EV:
case WFE_Source_USART1_EV:
case WFE_Source_DMA1CH01_EV:
case WFE_Source_DMA1CH23_EV:
if ((WFE->CR3 & (uint8_t)WFE_Source) != (uint8_t)0x00)
{
/* The wake-up event source is enabled*/
status = ENABLE;
}
else
{
/* The wake-up event source is disabled*/
status = DISABLE;
}
break;
case WFE_Source_TIM5_EV0:
case WFE_Source_TIM5_EV1:
case WFE_Source_AES_EV:
case WFE_Source_SPI2_EV:
case WFE_Source_USART2_EV:
case WFE_Source_USART3_EV:
case WFE_Source_RTC_CSS_EV:
if ((WFE->CR4 & (uint8_t)WFE_Source) != (uint8_t)0x00)
{
/* The wake-up event source is enabled*/
status = ENABLE;
}
else
{
/* The wake-up event source is disabled*/
status = DISABLE;
}
break;
default:
break;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
********************************************************************************
* @file stm8l15x_wwdg.c
* @author MCD Application Team
* @version V1.6.1
* @date 30-September-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Window watchdog (WWDG) peripheral:
* - Refresh window and Counter configuration
* - WWDG activation
* - Couter and software reset management
*
* @verbatim
*
* ===================================================================
* WWDG features
* ===================================================================
*
* Once enabled the WWDG generates a system reset on expiry of a programmed
* time period, unless the program refreshes the counter (downcounter)
* before to reach 0x3F value (i.e. a reset is generated when the counter
* value rolls over from 0x40 to 0x3F).
* An MCU reset is also generated if the counter value is refreshed
* before the counter has reached the refresh window value. This
* implies that the counter must be refreshed in a limited window.
*
* Once enabled the WWDG cannot be disabled except by a system reset.
*
* If the WWDG is activated and the watchdog reset on halt option is
* selected (Option byte), then the HALT instruction will generate a reset.
*
* WWDGF flag in RST_SR register can be used to inform when a WWDG
* reset occurs.
*
* WWDG timeout = (WWDG counter clock) * 12288 * (T[5:0] + 1)
*
* Min-max timeout value @16 MHz(PCLK1): ~0.768 ms / ~49.152 ms
*
* ===================================================================
* How to use this driver
* ===================================================================
* 1. Configure the WWDG refresh window using WWDG_SetWindowValue() function
*
* 2. Set the WWDG counter value and start it using WWDG_Enable() function.
* When the WWDG is enabled the counter value should be configured to
* a value greater than 0x40 to prevent generating an immediate reset.
*
* 3. Then the application program must refresh the WWDG counter at regular
* intervals during normal operation to prevent an MCU reset, using
* WWDG_SetCounter() function. This operation must occur only when
* the counter value is lower than the refresh window value,
* programmed using WWDG_SetWindowValue().
*
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm8l15x_wwdg.h"
/** @addtogroup STM8L15x_StdPeriph_Driver
* @{
*/
/** @defgroup WWDG
* @brief WWDG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define BIT_MASK ((uint8_t)0x7F)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup WWDG_Private_Functions
* @{
*/
/** @defgroup WWDG_Group1 Refresh window and Counter configuration functions
* @brief Refresh window and Counter configuration functions
*
@verbatim
===============================================================================
Refresh window and Counter configuration functions
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Initializes the WWDG peripheral.
* This function set Window Register = WindowValue, Counter Register
* according to Counter and \b ENABLE \b WWDG
* @param Counter : WWDG counter value
* @param WindowValue : specifies the WWDG Window Register, range is 0x00 to 0x7F.
* @retval None
*/
void WWDG_Init(uint8_t Counter, uint8_t WindowValue)
{
/* Check the parameters */
assert_param(IS_WWDG_WINDOW_LIMIT_VALUE(WindowValue));
WWDG->WR = WWDG_WR_RESET_VALUE;
WWDG->CR = (uint8_t)(WWDG_CR_WDGA | Counter);
WWDG->WR = (uint8_t)((uint8_t)BIT_MASK & (uint8_t) WindowValue);
}
/**
* @brief Sets the WWDG window value.
* @param WindowValue: specifies the window value to be compared to the downcounter.
* This parameter value must be lower than 0x80.
* @retval None
*/
void WWDG_SetWindowValue(uint8_t WindowValue)
{
__IO uint8_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_WINDOW_LIMIT_VALUE(WindowValue));
/* Set W[6:0] bits according to WindowValue value */
tmpreg |= (uint8_t) (WindowValue & (uint8_t) BIT_MASK);
/* Store the new value */
WWDG->WR = tmpreg;
}
/**
* @brief Sets the WWDG counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
* an immediate reset)
* @retval None
*/
void WWDG_SetCounter(uint8_t Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER_VALUE(Counter));
/* Write to T[6:0] bits to configure the counter value, no need to do
a read-modify-write; writing a 0 to WDGA bit does nothing */
WWDG->CR = (uint8_t)(Counter & (uint8_t)BIT_MASK);
}
/**
* @}
*/
/** @defgroup WWDG_Group2 WWDG activation function
* @brief WWDG activation function
*
@verbatim
===============================================================================
WWDG activation function
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Enables WWDG and load the counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* @retval None
*/
void WWDG_Enable(uint8_t Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER_VALUE(Counter));
WWDG->CR = (uint8_t)(WWDG_CR_WDGA | Counter);
}
/**
* @}
*/
/** @defgroup WWDG_Group3 WWDG counter and software reset management
* @brief WWDG counter and software reset management
*
@verbatim
===============================================================================
WWDG counter and software reset management
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Gets the WWDG Counter Value.
* This value could be used to check if WWDG is in the window, where
* refresh is allowed.
* @param None
* @retval WWDG Counter Value
*/
uint8_t WWDG_GetCounter(void)
{
return(WWDG->CR);
}
/**
* @brief Generates immediate WWDG RESET.
* @param None
* @retval None
*/
void WWDG_SWReset(void)
{
WWDG->CR = WWDG_CR_WDGA; /* Activate WWDG, with clearing T6 */
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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