add spl, first tries programming
This commit is contained in:
seppl
3091
firmware/inc/stm8l151x/inc/stm8l15x.h
Normal file
3091
firmware/inc/stm8l151x/inc/stm8l15x.h
Normal file
File diff suppressed because it is too large
Load Diff
386
firmware/inc/stm8l151x/inc/stm8l15x_adc.h
Normal file
386
firmware/inc/stm8l151x/inc/stm8l15x_adc.h
Normal file
@@ -0,0 +1,386 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the ADC
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_ADC_H
|
||||
#define __STM8L15x_ADC_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_Channels
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_Channel_0 = ((uint16_t)0x0301), /*!< Channel 00 */
|
||||
ADC_Channel_1 = ((uint16_t)0x0302), /*!< Channel 01 */
|
||||
ADC_Channel_2 = ((uint16_t)0x0304), /*!< Channel 02 */
|
||||
ADC_Channel_3 = ((uint16_t)0x0308), /*!< Channel 03 */
|
||||
ADC_Channel_4 = ((uint16_t)0x0310), /*!< Channel 04 */
|
||||
ADC_Channel_5 = ((uint16_t)0x0320), /*!< Channel 05 */
|
||||
ADC_Channel_6 = ((uint16_t)0x0340), /*!< Channel 06 */
|
||||
ADC_Channel_7 = ((uint16_t)0x0380), /*!< Channel 07 */
|
||||
|
||||
ADC_Channel_8 = ((uint16_t)0x0201), /*!< Channel 08 */
|
||||
ADC_Channel_9 = ((uint16_t)0x0202), /*!< Channel 09 */
|
||||
ADC_Channel_10 = ((uint16_t)0x0204), /*!< Channel 10 */
|
||||
ADC_Channel_11 = ((uint16_t)0x0208), /*!< Channel 11 */
|
||||
ADC_Channel_12 = ((uint16_t)0x0210), /*!< Channel 12 */
|
||||
ADC_Channel_13 = ((uint16_t)0x0220), /*!< Channel 13 */
|
||||
ADC_Channel_14 = ((uint16_t)0x0240), /*!< Channel 14 */
|
||||
ADC_Channel_15 = ((uint16_t)0x0280), /*!< Channel 15 */
|
||||
|
||||
ADC_Channel_16 = ((uint16_t)0x0101), /*!< Channel 16 */
|
||||
ADC_Channel_17 = ((uint16_t)0x0102), /*!< Channel 17 */
|
||||
ADC_Channel_18 = ((uint16_t)0x0104), /*!< Channel 18 */
|
||||
ADC_Channel_19 = ((uint16_t)0x0108), /*!< Channel 19 */
|
||||
ADC_Channel_20 = ((uint16_t)0x0110), /*!< Channel 20 */
|
||||
ADC_Channel_21 = ((uint16_t)0x0120), /*!< Channel 21 */
|
||||
ADC_Channel_22 = ((uint16_t)0x0140), /*!< Channel 22 */
|
||||
ADC_Channel_23 = ((uint16_t)0x0180), /*!< Channel 23 */
|
||||
|
||||
ADC_Channel_24 = ((uint16_t)0x0001), /*!< Channel 24 */
|
||||
ADC_Channel_25 = ((uint16_t)0x0002), /*!< Channel 25 */
|
||||
ADC_Channel_26 = ((uint16_t)0x0004), /*!< Channel 26 */
|
||||
ADC_Channel_27 = ((uint16_t)0x0008), /*!< Channel 27 */
|
||||
|
||||
ADC_Channel_Vrefint = ((uint16_t)0x0010), /*!< Vrefint Channel */
|
||||
ADC_Channel_TempSensor = ((uint16_t)0x0020), /*!< Temperature sensor Channel */
|
||||
|
||||
/* combination*/
|
||||
ADC_Channel_00To07 = ((uint16_t)0x03FF), /*!<select from channel00 to channel07 */
|
||||
ADC_Channel_08To15 = ((uint16_t)0x02FF), /*!<select from channel08 to channel15 */
|
||||
ADC_Channel_16To23 = ((uint16_t)0x01FF), /*!<select from channel16 to channel23 */
|
||||
ADC_Channel_24To27 = ((uint16_t)0x00FF) /*!<select from channel24 to channel27 */
|
||||
|
||||
}ADC_Channel_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Conversion_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_ConversionMode_Single = ((uint8_t)0x00), /*!< Single Conversion Mode */
|
||||
ADC_ConversionMode_Continuous = ((uint8_t)0x04) /*!< Continuous Conversion Mode */
|
||||
}ADC_ConversionMode_TypeDef;
|
||||
|
||||
#define IS_ADC_CONVERSION_MODE(MODE) (((MODE) == ADC_ConversionMode_Single) || \
|
||||
((MODE) == ADC_ConversionMode_Continuous))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Resolution
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_Resolution_12Bit = ((uint8_t)0x00), /*!< 12 bit resolution */
|
||||
ADC_Resolution_10Bit = ((uint8_t)0x20), /*!< 10 bit resolution */
|
||||
ADC_Resolution_8Bit = ((uint8_t)0x40), /*!< 8 bit resolution */
|
||||
ADC_Resolution_6Bit = ((uint8_t)0x60) /*!< 6 bit resolution */
|
||||
}ADC_Resolution_TypeDef;
|
||||
|
||||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12Bit) || \
|
||||
((RESOLUTION) == ADC_Resolution_10Bit) || \
|
||||
((RESOLUTION) == ADC_Resolution_8Bit) || \
|
||||
((RESOLUTION) == ADC_Resolution_6Bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Clock_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_Prescaler_1 = ((uint8_t)0x00), /*!< ADC Clock frequency is divided by 1 */
|
||||
ADC_Prescaler_2 = ((uint8_t)0x80) /*!< ADC Clock frequency is divided by 2 */
|
||||
}ADC_Prescaler_TypeDef;
|
||||
|
||||
#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_1) || \
|
||||
((PRESCALER) == ADC_Prescaler_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_External_Trigger_Sensitivity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_ExtTRGSensitivity_Rising = ((uint8_t)0x20), /*!< External Trigger Sensitivity is Rising Edge */
|
||||
ADC_ExtTRGSensitivity_Falling = ((uint8_t)0x40), /*!< External Trigger Sensitivity is Falling Edge */
|
||||
ADC_ExtTRGSensitivity_All = ((uint8_t)0x60) /*!< External Trigger Sensitivity is Falling and Rising Edge */
|
||||
}ADC_ExtTRGSensitivity_TypeDef;
|
||||
|
||||
#define IS_ADC_EXT_TRG_SENSITIVITY(SENSITIVITY) (((SENSITIVITY) == ADC_ExtTRGSensitivity_Rising) || \
|
||||
((SENSITIVITY) == ADC_ExtTRGSensitivity_Falling) || \
|
||||
((SENSITIVITY) == ADC_ExtTRGSensitivity_All))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_External_Event_Source_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_ExtEventSelection_None = ((uint8_t)0x00), /*!< Conversion starts only by software start */
|
||||
ADC_ExtEventSelection_Trigger1 = ((uint8_t)0x08), /*!< Trigger 1 Enables conversion */
|
||||
ADC_ExtEventSelection_Trigger2 = ((uint8_t)0x10), /*!< Trigger 2 Enables conversion */
|
||||
ADC_ExtEventSelection_Trigger3 = ((uint8_t)0x18) /*!< Trigger 3 Enables conversion */
|
||||
}ADC_ExtEventSelection_TypeDef;
|
||||
|
||||
#define IS_ADC_EXT_EVENT_SELECTION(SELECTION) (((SELECTION) == ADC_ExtEventSelection_None) || \
|
||||
((SELECTION) == ADC_ExtEventSelection_Trigger1) || \
|
||||
((SELECTION) == ADC_ExtEventSelection_Trigger2) || \
|
||||
((SELECTION) == ADC_ExtEventSelection_Trigger3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group_Channel_Definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_Group_SlowChannels = ((uint8_t)0x00), /*!<Slow Channels group(Channel 0 to 23) */
|
||||
ADC_Group_FastChannels = ((uint8_t)0x01) /*!<Fast Channels group Channel 24 to 27,
|
||||
Channel Vrefint, Channel TempSensor)*/
|
||||
}ADC_Group_TypeDef;
|
||||
|
||||
#define IS_ADC_GROUP(GROUP) (((GROUP) == ADC_Group_SlowChannels) || \
|
||||
((GROUP) == ADC_Group_FastChannels))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Sampling_Time
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_SamplingTime_4Cycles = ((uint8_t)0x00), /*!< Sampling Time Cycles is 4 */
|
||||
ADC_SamplingTime_9Cycles = ((uint8_t)0x01), /*!< Sampling Time Cycles is 9 */
|
||||
ADC_SamplingTime_16Cycles = ((uint8_t)0x02), /*!< Sampling Time Cycles is 16 */
|
||||
ADC_SamplingTime_24Cycles = ((uint8_t)0x03), /*!< Sampling Time Cycles is 24 */
|
||||
ADC_SamplingTime_48Cycles = ((uint8_t)0x04), /*!< Sampling Time Cycles is 48 */
|
||||
ADC_SamplingTime_96Cycles = ((uint8_t)0x05), /*!< Sampling Time Cycles is 96 */
|
||||
ADC_SamplingTime_192Cycles = ((uint8_t)0x06), /*!< Sampling Time Cycles is 192 */
|
||||
ADC_SamplingTime_384Cycles = ((uint8_t)0x07) /*!< Sampling Time Cycles is 384 */
|
||||
}ADC_SamplingTime_TypeDef;
|
||||
|
||||
#define IS_ADC_SAMPLING_TIME_CYCLES(TIME) (((TIME) == ADC_SamplingTime_4Cycles) || \
|
||||
((TIME) == ADC_SamplingTime_9Cycles) || \
|
||||
((TIME) == ADC_SamplingTime_16Cycles) || \
|
||||
((TIME) == ADC_SamplingTime_24Cycles) || \
|
||||
((TIME) == ADC_SamplingTime_48Cycles) || \
|
||||
((TIME) == ADC_SamplingTime_96Cycles) || \
|
||||
((TIME) == ADC_SamplingTime_192Cycles) || \
|
||||
((TIME) == ADC_SamplingTime_384Cycles))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Analog_Watchdog_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_AnalogWatchdogSelection_Channel0 = ((uint8_t)0x00), /*!< AWD affected to Channel 0 */
|
||||
ADC_AnalogWatchdogSelection_Channel1 = ((uint8_t)0x01), /*!< AWD affected to Channel 1 */
|
||||
ADC_AnalogWatchdogSelection_Channel2 = ((uint8_t)0x02), /*!< AWD affected to Channel 2 */
|
||||
ADC_AnalogWatchdogSelection_Channel3 = ((uint8_t)0x03), /*!< AWD affected to Channel 3 */
|
||||
ADC_AnalogWatchdogSelection_Channel4 = ((uint8_t)0x04), /*!< AWD affected to Channel 4 */
|
||||
ADC_AnalogWatchdogSelection_Channel5 = ((uint8_t)0x05), /*!< AWD affected to Channel 5 */
|
||||
ADC_AnalogWatchdogSelection_Channel6 = ((uint8_t)0x06), /*!< AWD affected to Channel 6 */
|
||||
ADC_AnalogWatchdogSelection_Channel7 = ((uint8_t)0x07), /*!< AWD affected to Channel 7 */
|
||||
ADC_AnalogWatchdogSelection_Channel8 = ((uint8_t)0x08), /*!< AWD affected to Channel 8 */
|
||||
ADC_AnalogWatchdogSelection_Channel9 = ((uint8_t)0x09), /*!< AWD affected to Channel 9 */
|
||||
ADC_AnalogWatchdogSelection_Channel10 = ((uint8_t)0x0A), /*!< AWD affected to Channel 10 */
|
||||
ADC_AnalogWatchdogSelection_Channel11 = ((uint8_t)0x0B), /*!< AWD affected to Channel 11 */
|
||||
ADC_AnalogWatchdogSelection_Channel12 = ((uint8_t)0x0C), /*!< AWD affected to Channel 12 */
|
||||
ADC_AnalogWatchdogSelection_Channel13 = ((uint8_t)0x0D), /*!< AWD affected to Channel 13 */
|
||||
ADC_AnalogWatchdogSelection_Channel14 = ((uint8_t)0x0E), /*!< AWD affected to Channel 14 */
|
||||
ADC_AnalogWatchdogSelection_Channel15 = ((uint8_t)0x0F), /*!< AWD affected to Channel 15 */
|
||||
ADC_AnalogWatchdogSelection_Channel16 = ((uint8_t)0x10), /*!< AWD affected to Channel 16 */
|
||||
ADC_AnalogWatchdogSelection_Channel17 = ((uint8_t)0x11), /*!< AWD affected to Channel 17 */
|
||||
ADC_AnalogWatchdogSelection_Channel18 = ((uint8_t)0x12), /*!< AWD affected to Channel 18 */
|
||||
ADC_AnalogWatchdogSelection_Channel19 = ((uint8_t)0x13), /*!< AWD affected to Channel 19 */
|
||||
ADC_AnalogWatchdogSelection_Channel20 = ((uint8_t)0x14), /*!< AWD affected to Channel 20 */
|
||||
ADC_AnalogWatchdogSelection_Channel21 = ((uint8_t)0x15), /*!< AWD affected to Channel 21 */
|
||||
ADC_AnalogWatchdogSelection_Channel22 = ((uint8_t)0x16), /*!< AWD affected to Channel 22 */
|
||||
ADC_AnalogWatchdogSelection_Channel23 = ((uint8_t)0x17), /*!< AWD affected to Channel 23 */
|
||||
|
||||
ADC_AnalogWatchdogSelection_Channel24 = ((uint8_t)0x18), /*!< AWD affected to Channel 24 */
|
||||
ADC_AnalogWatchdogSelection_Channel25 = ((uint8_t)0x19), /*!< AWD affected to Channel 25 */
|
||||
ADC_AnalogWatchdogSelection_Channel26 = ((uint8_t)0x1A), /*!< AWD affected to Channel 26 */
|
||||
ADC_AnalogWatchdogSelection_Channel27 = ((uint8_t)0x1B), /*!< AWD affected to Channel 27 */
|
||||
|
||||
ADC_AnalogWatchdogSelection_Vrefint = ((uint8_t)0x1C), /*!< AWD affected to Internal Vref Channel */
|
||||
ADC_AnalogWatchdogSelection_TempSensor = ((uint8_t)0x1D) /*!< AWD affected to Temperature Sensor Channel */
|
||||
}ADC_AnalogWatchdogSelection_TypeDef;
|
||||
|
||||
#define IS_ADC_ANALOGWATCHDOG_SELECTION(CHANNEL) (((CHANNEL) <= 0x1D))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Interrupts
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_IT_EOC = ((uint8_t)0x08), /*!< End of Conversion Interrupt */
|
||||
ADC_IT_AWD = ((uint8_t)0x10), /*!< Analog Watchdog Interrupt */
|
||||
ADC_IT_OVER = ((uint8_t)0x80) /*!< Over Run Interrupt */
|
||||
}ADC_IT_TypeDef;
|
||||
|
||||
#define IS_ADC_IT(IT) ((((IT) & (uint8_t)0x67) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
|
||||
((IT) == ADC_IT_OVER))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Flags
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_FLAG_EOC = ((uint8_t)0x01), /*!< End of Conversion flag */
|
||||
ADC_FLAG_AWD = ((uint8_t)0x02), /*!< Analog Watchdog flag */
|
||||
ADC_FLAG_OVER = ((uint8_t)0x04) /*!< Over Run flag */
|
||||
}ADC_FLAG_TypeDef;
|
||||
|
||||
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xF8) == 0x00) && ((FLAG) != 0x00))
|
||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_AWD) || \
|
||||
((FLAG) == ADC_FLAG_OVER))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported Macros -----------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the ADC configuration to the default reset state *****/
|
||||
void ADC_DeInit(ADC_TypeDef* ADCx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void ADC_Init(ADC_TypeDef* ADCx,
|
||||
ADC_ConversionMode_TypeDef ADC_ConversionMode,
|
||||
ADC_Resolution_TypeDef ADC_Resolution,
|
||||
ADC_Prescaler_TypeDef ADC_Prescaler);
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
|
||||
void ADC_ExternalTrigConfig(ADC_TypeDef* ADCx,
|
||||
ADC_ExtEventSelection_TypeDef ADC_ExtEventSelection,
|
||||
ADC_ExtTRGSensitivity_TypeDef ADC_ExtTRGSensitivity);
|
||||
|
||||
/* Analog Watchdog configuration functions ************************************/
|
||||
void ADC_AnalogWatchdogChannelSelect(ADC_TypeDef* ADCx,
|
||||
ADC_AnalogWatchdogSelection_TypeDef ADC_AnalogWatchdogSelection);
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
|
||||
uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdogConfig(ADC_TypeDef* ADCx,
|
||||
ADC_AnalogWatchdogSelection_TypeDef ADC_AnalogWatchdogSelection,
|
||||
uint16_t HighThreshold,
|
||||
uint16_t LowThreshold);
|
||||
|
||||
/* Temperature Sensor & Vrefint (Voltage Reference internal) management functions */
|
||||
void ADC_TempSensorCmd(FunctionalState NewState);
|
||||
void ADC_VrefintCmd(FunctionalState NewState);
|
||||
|
||||
/* Channels Configuration functions *******************************************/
|
||||
void ADC_ChannelCmd(ADC_TypeDef* ADCx, ADC_Channel_TypeDef ADC_Channels,
|
||||
FunctionalState NewState);
|
||||
|
||||
void ADC_SamplingTimeConfig(ADC_TypeDef* ADCx, ADC_Group_TypeDef ADC_GroupChannels,
|
||||
ADC_SamplingTime_TypeDef ADC_SamplingTime);
|
||||
void ADC_SchmittTriggerConfig(ADC_TypeDef* ADCx, ADC_Channel_TypeDef ADC_Channels,
|
||||
FunctionalState NewState);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||
|
||||
|
||||
|
||||
/* Channels DMA Configuration function ****************************************/
|
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx,
|
||||
ADC_IT_TypeDef ADC_IT,
|
||||
FunctionalState NewState);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, ADC_FLAG_TypeDef ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, ADC_FLAG_TypeDef ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, ADC_IT_TypeDef ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, ADC_IT_TypeDef ADC_IT);
|
||||
|
||||
#endif /*__STM8L15x_ADC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
158
firmware/inc/stm8l151x/inc/stm8l15x_aes.h
Normal file
158
firmware/inc/stm8l151x/inc/stm8l15x_aes.h
Normal file
@@ -0,0 +1,158 @@
|
||||
/**
|
||||
********************************************************************************
|
||||
* @file stm8l15x_aes.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the AES firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_AES_H
|
||||
#define __STM8L15x_AES_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AES
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup AES_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Operation_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
AES_Operation_Encryp = (uint8_t)0x00, /*!< AES in Encryption mode */
|
||||
AES_Operation_KeyDeriv = (uint8_t)0x02, /*!< AES in Key Derivation mode */
|
||||
AES_Operation_Decryp = (uint8_t)0x04, /*!< AES in Decryption mode */
|
||||
AES_Operation_KeyDerivAndDecryp = (uint8_t)0x06 /*!< AES in Key Derivation and Decryption mode */
|
||||
} AES_Operation_TypeDef;
|
||||
|
||||
#define IS_AES_MODE(Operation) (((Operation) == AES_Operation_Encryp) || \
|
||||
((Operation) == AES_Operation_KeyDeriv) || \
|
||||
((Operation) == AES_Operation_Decryp) || \
|
||||
((Operation) == AES_Operation_KeyDerivAndDecryp))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Flags
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
AES_FLAG_CCF = (uint8_t)0x01, /*!< Computation Complete Flag */
|
||||
AES_FLAG_RDERR = (uint8_t)0x02, /*!< Read Error Flag */
|
||||
AES_FLAG_WRERR = (uint8_t)0x04 /*!< Write Error Flag */
|
||||
}AES_FLAG_TypeDef;
|
||||
|
||||
#define IS_AES_FLAG(Flag) (((Flag) == AES_FLAG_CCF) || \
|
||||
((Flag) == AES_FLAG_RDERR) || \
|
||||
((Flag) == AES_FLAG_WRERR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Interrupts
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
AES_IT_CCIE = (uint16_t)0x20, /*!< Computation Complete interrupt enable */
|
||||
AES_IT_ERRIE = (uint16_t)0x40 /*!< Error interrupt enable */
|
||||
}AES_IT_TypeDef;
|
||||
|
||||
#define IS_AES_IT(IT) (((IT) == AES_IT_CCIE) || \
|
||||
((IT) == AES_IT_ERRIE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_DMA_Transfer_Direction
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
AES_DMATransfer_InOut = (uint8_t) 0x80 /*!< DMA requests enabled for input transfer phase
|
||||
as well as for the output transfer phase */
|
||||
}
|
||||
AES_DMATransfer_TypeDef;
|
||||
|
||||
#define IS_AES_DMATRANSFER(Transfer) ((Transfer) == AES_DMATransfer_InOut)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the AES configuration to the default reset state *****/
|
||||
void AES_DeInit(void);
|
||||
|
||||
/* AES Configuration **********************************************************/
|
||||
void AES_OperationModeConfig(AES_Operation_TypeDef AES_Operation);
|
||||
void AES_Cmd(FunctionalState NewState);
|
||||
|
||||
/* AES Read and Write operations **********************************************/
|
||||
void AES_WriteSubData(uint8_t Data);
|
||||
void AES_WriteSubKey(uint8_t Key);
|
||||
uint8_t AES_ReadSubData(void);
|
||||
uint8_t AES_ReadSubKey(void);
|
||||
|
||||
/* DMA transfers management function ******************************************/
|
||||
void AES_DMAConfig(AES_DMATransfer_TypeDef AES_DMATransfer, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void AES_ITConfig(AES_IT_TypeDef AES_IT, FunctionalState NewState);
|
||||
FlagStatus AES_GetFlagStatus(AES_FLAG_TypeDef AES_FLAG);
|
||||
void AES_ClearFlag(AES_FLAG_TypeDef AES_FLAG);
|
||||
ITStatus AES_GetITStatus(AES_IT_TypeDef AES_IT);
|
||||
void AES_ClearITPendingBit(AES_IT_TypeDef AES_IT);
|
||||
|
||||
#endif /* __STM8L15x_AES_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
117
firmware/inc/stm8l151x/inc/stm8l15x_beep.h
Normal file
117
firmware/inc/stm8l151x/inc/stm8l15x_beep.h
Normal file
@@ -0,0 +1,117 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_beep.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the BEEP firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_BEEP_H
|
||||
#define __STM8L15x_BEEP_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup BEEP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup BEEP_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BEEP_Frequency
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
BEEP_Frequency_1KHz = (uint8_t)0x00, /*!< Beep signal output frequency 1 KHz */
|
||||
BEEP_Frequency_2KHz = (uint8_t)0x40, /*!< Beep signal output frequency 2 KHz */
|
||||
BEEP_Frequency_4KHz = (uint8_t)0x80 /*!< Beep signal output frequency 4 KHz */
|
||||
} BEEP_Frequency_TypeDef;
|
||||
|
||||
#define IS_BEEP_FREQUENCY(FREQ) (((FREQ) == BEEP_Frequency_1KHz) || \
|
||||
((FREQ) == BEEP_Frequency_2KHz) || \
|
||||
((FREQ) == BEEP_Frequency_4KHz))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup BEEP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BEEP_CALIBRATION_DEFAULT ((uint8_t)0x01) /*!< Default value when calibration is not done */
|
||||
#define LSI_FREQUENCY_MIN ((uint32_t)25000) /*!< LSI minimum value in Hertz */
|
||||
#define LSI_FREQUENCY_MAX ((uint32_t)75000) /*!< LSI maximum value in Hertz */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup BEEP_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_LSI_FREQUENCY(FREQ) (((FREQ) >= LSI_FREQUENCY_MIN) && ((FREQ) <= LSI_FREQUENCY_MAX))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the BEEP configuration to the default reset state *****/
|
||||
void BEEP_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency);
|
||||
void BEEP_Cmd(FunctionalState NewState);
|
||||
|
||||
/* Low Speed Internal Clock(LSI) Calibration functions ***********************/
|
||||
void BEEP_LSClockToTIMConnectCmd(FunctionalState NewState);
|
||||
void BEEP_LSICalibrationConfig(uint32_t LSIFreqHz);
|
||||
|
||||
|
||||
#endif /* __STM8L15x_BEEP_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
444
firmware/inc/stm8l151x/inc/stm8l15x_clk.h
Normal file
444
firmware/inc/stm8l151x/inc/stm8l15x_clk.h
Normal file
@@ -0,0 +1,444 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_clk.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the CLK firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_CLK_H
|
||||
#define __STM8L15x_CLK_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CLK
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_HSE_Configuration
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_HSE_OFF = (uint8_t)0x00, /*!< HSE Disable */
|
||||
CLK_HSE_ON = (uint8_t)0x01, /*!< HSE Enable */
|
||||
CLK_HSE_Bypass = (uint8_t)0x11 /*!< HSE Bypass and enable */
|
||||
} CLK_HSE_TypeDef;
|
||||
|
||||
#define IS_CLK_HSE(CONFIG) (((CONFIG) == CLK_HSE_ON) ||\
|
||||
((CONFIG) == CLK_HSE_OFF)||\
|
||||
((CONFIG) == CLK_HSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_LSE_Configuration
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_LSE_OFF = (uint8_t)0x00, /*!< LSE Disable */
|
||||
CLK_LSE_ON = (uint8_t)0x04, /*!< LSE Enable */
|
||||
CLK_LSE_Bypass = (uint8_t)0x24 /*!< LSE Bypass and enable */
|
||||
} CLK_LSE_TypeDef;
|
||||
|
||||
#define IS_CLK_LSE(CONFIG) (((CONFIG) == CLK_LSE_OFF) ||\
|
||||
((CONFIG) == CLK_LSE_ON) ||\
|
||||
((CONFIG) == CLK_LSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_System_Clock_Sources
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_SYSCLKSource_HSI = (uint8_t)0x01, /*!< System Clock Source HSI */
|
||||
CLK_SYSCLKSource_LSI = (uint8_t)0x02, /*!< System Clock Source LSI */
|
||||
CLK_SYSCLKSource_HSE = (uint8_t)0x04, /*!< System Clock Source HSE */
|
||||
CLK_SYSCLKSource_LSE = (uint8_t)0x08 /*!< System Clock Source LSE */
|
||||
} CLK_SYSCLKSource_TypeDef;
|
||||
|
||||
#define IS_CLK_SOURCE(SOURCE) (((SOURCE) == CLK_SYSCLKSource_HSI) ||\
|
||||
((SOURCE) == CLK_SYSCLKSource_LSI) ||\
|
||||
((SOURCE) == CLK_SYSCLKSource_HSE) ||\
|
||||
((SOURCE) == CLK_SYSCLKSource_LSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_Clock_Output_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_CCOSource_Off = (uint8_t)0x00, /*!< Clock Output Off */
|
||||
CLK_CCOSource_HSI = (uint8_t)0x02, /*!< HSI Clock Output */
|
||||
CLK_CCOSource_LSI = (uint8_t)0x04, /*!< LSI Clock Output */
|
||||
CLK_CCOSource_HSE = (uint8_t)0x08, /*!< HSE Clock Output */
|
||||
CLK_CCOSource_LSE = (uint8_t)0x10 /*!< LSE Clock Output */
|
||||
} CLK_CCOSource_TypeDef;
|
||||
|
||||
#define IS_CLK_OUTPUT(OUTPUT) (((OUTPUT) == CLK_CCOSource_Off) ||\
|
||||
((OUTPUT) == CLK_CCOSource_HSI) ||\
|
||||
((OUTPUT) == CLK_CCOSource_LSI) ||\
|
||||
((OUTPUT) == CLK_CCOSource_HSE) ||\
|
||||
((OUTPUT) == CLK_CCOSource_LSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_Clock_Output_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_CCODiv_1 = (uint8_t)0x00, /*!< Clock Output Div 1 */
|
||||
CLK_CCODiv_2 = (uint8_t)0x20, /*!< Clock Output Div 2 */
|
||||
CLK_CCODiv_4 = (uint8_t)0x40, /*!< Clock Output Div 4 */
|
||||
CLK_CCODiv_8 = (uint8_t)0x60, /*!< Clock Output Div 8 */
|
||||
CLK_CCODiv_16 = (uint8_t)0x80, /*!< Clock Output Div 16 */
|
||||
CLK_CCODiv_32 = (uint8_t)0xA0, /*!< Clock Output Div 32 */
|
||||
CLK_CCODiv_64 = (uint8_t)0xC0 /*!< Clock Output Div 64 */
|
||||
} CLK_CCODiv_TypeDef;
|
||||
|
||||
#define IS_CLK_OUTPUT_DIVIDER(PRESCALER) (((PRESCALER) == CLK_CCODiv_1) ||\
|
||||
((PRESCALER) == CLK_CCODiv_2) ||\
|
||||
((PRESCALER) == CLK_CCODiv_4) ||\
|
||||
((PRESCALER) == CLK_CCODiv_8) ||\
|
||||
((PRESCALER) == CLK_CCODiv_16) ||\
|
||||
((PRESCALER) == CLK_CCODiv_32) ||\
|
||||
((PRESCALER) == CLK_CCODiv_64))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_Beep_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_BEEPCLKSource_Off = (uint8_t)0x00, /*!< Clock BEEP Off */
|
||||
CLK_BEEPCLKSource_LSI = (uint8_t)0x02, /*!< Clock BEEP : LSI */
|
||||
CLK_BEEPCLKSource_LSE = (uint8_t)0x04 /*!< Clock BEEP : LSE */
|
||||
} CLK_BEEPCLKSource_TypeDef;
|
||||
|
||||
#define IS_CLK_CLOCK_BEEP(OUTPUT) (((OUTPUT) == CLK_BEEPCLKSource_Off) ||\
|
||||
((OUTPUT) == CLK_BEEPCLKSource_LSI) ||\
|
||||
((OUTPUT) == CLK_BEEPCLKSource_LSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_RTC_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_RTCCLKSource_Off = (uint8_t)0x00, /*!< Clock RTC Off */
|
||||
CLK_RTCCLKSource_HSI = (uint8_t)0x02, /*!< Clock RTC : HSI */
|
||||
CLK_RTCCLKSource_LSI = (uint8_t)0x04, /*!< Clock RTC : LSI */
|
||||
CLK_RTCCLKSource_HSE = (uint8_t)0x08, /*!< Clock RTC : HSE */
|
||||
CLK_RTCCLKSource_LSE = (uint8_t)0x10 /*!< Clock RTC : LSE */
|
||||
} CLK_RTCCLKSource_TypeDef;
|
||||
|
||||
#define IS_CLK_CLOCK_RTC(OUTPUT) (((OUTPUT) == CLK_RTCCLKSource_Off) ||\
|
||||
((OUTPUT) == CLK_RTCCLKSource_HSI) ||\
|
||||
((OUTPUT) == CLK_RTCCLKSource_LSI) ||\
|
||||
((OUTPUT) == CLK_RTCCLKSource_HSE) ||\
|
||||
((OUTPUT) == CLK_RTCCLKSource_LSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_RTC_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_RTCCLKDiv_1 = (uint8_t)0x00, /*!< Clock RTC Div 1 */
|
||||
CLK_RTCCLKDiv_2 = (uint8_t)0x20, /*!< Clock RTC Div 2 */
|
||||
CLK_RTCCLKDiv_4 = (uint8_t)0x40, /*!< Clock RTC Div 4 */
|
||||
CLK_RTCCLKDiv_8 = (uint8_t)0x60, /*!< Clock RTC Div 8 */
|
||||
CLK_RTCCLKDiv_16 = (uint8_t)0x80, /*!< Clock RTC Div 16 */
|
||||
CLK_RTCCLKDiv_32 = (uint8_t)0xA0, /*!< Clock RTC Div 32 */
|
||||
CLK_RTCCLKDiv_64 = (uint8_t)0xC0 /*!< Clock RTC Div 64 */
|
||||
} CLK_RTCCLKDiv_TypeDef;
|
||||
|
||||
#define IS_CLK_CLOCK_RTC_DIV(DIV) (((DIV) == CLK_RTCCLKDiv_1) ||\
|
||||
((DIV) == CLK_RTCCLKDiv_2) ||\
|
||||
((DIV) == CLK_RTCCLKDiv_4) ||\
|
||||
((DIV) == CLK_RTCCLKDiv_8) ||\
|
||||
((DIV) == CLK_RTCCLKDiv_16) ||\
|
||||
((DIV) == CLK_RTCCLKDiv_32) ||\
|
||||
((DIV) == CLK_RTCCLKDiv_64))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_Peripherals
|
||||
* @{
|
||||
*/
|
||||
/* Elements values convention: 0xXY
|
||||
X = choice between the peripheral registers
|
||||
X = 0 : PCKENR1
|
||||
X = 1 : PCKENR2
|
||||
X = 2 : PCKENR3
|
||||
Y = Peripheral position in the register
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_Peripheral_TIM2 = (uint8_t)0x00, /*!< Peripheral Clock Enable 1, TIM2 */
|
||||
CLK_Peripheral_TIM3 = (uint8_t)0x01, /*!< Peripheral Clock Enable 1, TIM3 */
|
||||
CLK_Peripheral_TIM4 = (uint8_t)0x02, /*!< Peripheral Clock Enable 1, TIM4 */
|
||||
CLK_Peripheral_I2C1 = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, I2C1 */
|
||||
CLK_Peripheral_SPI1 = (uint8_t)0x04, /*!< Peripheral Clock Enable 1, SPI1 */
|
||||
CLK_Peripheral_USART1 = (uint8_t)0x05, /*!< Peripheral Clock Enable 1, USART1 */
|
||||
CLK_Peripheral_BEEP = (uint8_t)0x06, /*!< Peripheral Clock Enable 1, BEEP */
|
||||
CLK_Peripheral_DAC = (uint8_t)0x07, /*!< Peripheral Clock Enable 1, DAC */
|
||||
CLK_Peripheral_ADC1 = (uint8_t)0x10, /*!< Peripheral Clock Enable 2, ADC1 */
|
||||
CLK_Peripheral_TIM1 = (uint8_t)0x11, /*!< Peripheral Clock Enable 2, TIM1 */
|
||||
CLK_Peripheral_RTC = (uint8_t)0x12, /*!< Peripheral Clock Enable 2, RTC */
|
||||
CLK_Peripheral_LCD = (uint8_t)0x13, /*!< Peripheral Clock Enable 2, LCD */
|
||||
CLK_Peripheral_DMA1 = (uint8_t)0x14, /*!< Peripheral Clock Enable 2, DMA1 */
|
||||
CLK_Peripheral_COMP = (uint8_t)0x15, /*!< Peripheral Clock Enable 2, COMP1 and COMP2 */
|
||||
CLK_Peripheral_BOOTROM = (uint8_t)0x17,/*!< Peripheral Clock Enable 2, Boot ROM */
|
||||
CLK_Peripheral_AES = (uint8_t)0x20, /*!< Peripheral Clock Enable 3, AES */
|
||||
CLK_Peripheral_TIM5 = (uint8_t)0x21, /*!< Peripheral Clock Enable 3, TIM5 */
|
||||
CLK_Peripheral_SPI2 = (uint8_t)0x22, /*!< Peripheral Clock Enable 3, SPI2 */
|
||||
CLK_Peripheral_USART2 = (uint8_t)0x23, /*!< Peripheral Clock Enable 3, USART2 */
|
||||
CLK_Peripheral_USART3 = (uint8_t)0x24, /*!< Peripheral Clock Enable 3, USART3 */
|
||||
CLK_Peripheral_CSSLSE = (uint8_t)0x25 /*!< Peripheral Clock Enable 3, CSS on LSE */
|
||||
} CLK_Peripheral_TypeDef;
|
||||
|
||||
#define IS_CLK_PERIPHERAL(PERIPHERAL) (((PERIPHERAL) == CLK_Peripheral_DAC) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_ADC1) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_DMA1) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_RTC) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_LCD) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_COMP) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_TIM1) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_USART1) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_SPI1) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_I2C1) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_TIM4) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_TIM3) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_BEEP) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_BOOTROM) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_AES) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_TIM5) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_SPI2) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_USART2) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_USART3) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_CSSLSE) ||\
|
||||
((PERIPHERAL) == CLK_Peripheral_TIM2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_System_Clock_Divider
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_SYSCLKDiv_1 = (uint8_t)0x00, /*!< System Clock Divider: 1 */
|
||||
CLK_SYSCLKDiv_2 = (uint8_t)0x01, /*!< System Clock Divider: 2 */
|
||||
CLK_SYSCLKDiv_4 = (uint8_t)0x02, /*!< System Clock Divider: 4 */
|
||||
CLK_SYSCLKDiv_8 = (uint8_t)0x03, /*!< System Clock Divider: 8 */
|
||||
CLK_SYSCLKDiv_16 = (uint8_t)0x04, /*!< System Clock Divider: 16 */
|
||||
CLK_SYSCLKDiv_32 = (uint8_t)0x05, /*!< System Clock Divider: 32 */
|
||||
CLK_SYSCLKDiv_64 = (uint8_t)0x06, /*!< System Clock Divider: 64 */
|
||||
CLK_SYSCLKDiv_128 = (uint8_t)0x07 /*!< System Clock Divider: 128 */
|
||||
} CLK_SYSCLKDiv_TypeDef;
|
||||
|
||||
#define IS_CLK_SYSTEM_DIVIDER(DIV) (((DIV) == CLK_SYSCLKDiv_1) ||\
|
||||
((DIV) == CLK_SYSCLKDiv_2) ||\
|
||||
((DIV) == CLK_SYSCLKDiv_4) ||\
|
||||
((DIV) == CLK_SYSCLKDiv_8) ||\
|
||||
((DIV) == CLK_SYSCLKDiv_16) ||\
|
||||
((DIV) == CLK_SYSCLKDiv_32) ||\
|
||||
((DIV) == CLK_SYSCLKDiv_64) ||\
|
||||
((DIV) == CLK_SYSCLKDiv_128))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_Flags
|
||||
* @{
|
||||
*/
|
||||
/* Elements values convention: 0xXY
|
||||
X = choice between the register's flags
|
||||
X = 0 : CLK_CRTCR
|
||||
X = 1 : CLK_ICKCR
|
||||
X = 2 : CLK_CCOR
|
||||
X = 3 : CLK_ECKCR
|
||||
X = 4 : CLK_SWCR
|
||||
X = 5 : CLK_CSSR
|
||||
X = 6 : CLK_CBEEPR
|
||||
X = 7 : CLK_REGCSRR
|
||||
X = 8 : CSSLSE_CSR
|
||||
Y = flag position in the register
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_FLAG_RTCSWBSY = (uint8_t)0x00, /*!< RTC clock busy in switch Flag */
|
||||
CLK_FLAG_HSIRDY = (uint8_t)0x11, /*!< High speed internal oscillator ready Flag */
|
||||
CLK_FLAG_LSIRDY = (uint8_t)0x13, /*!< Low speed internal oscillator ready Flag */
|
||||
CLK_FLAG_CCOBSY = (uint8_t)0x20, /*!< Configurable clock output busy */
|
||||
CLK_FLAG_HSERDY = (uint8_t)0x31, /*!< High speed external oscillator ready Flag */
|
||||
CLK_FLAG_LSERDY = (uint8_t)0x33, /*!< Low speed external oscillator ready Flag */
|
||||
CLK_FLAG_SWBSY = (uint8_t)0x40, /*!< Switch busy Flag */
|
||||
CLK_FLAG_AUX = (uint8_t)0x51, /*!< Auxiliary oscillator connected to master clock */
|
||||
CLK_FLAG_CSSD = (uint8_t)0x53, /*!< Clock security system detection Flag */
|
||||
CLK_FLAG_BEEPSWBSY = (uint8_t)0x60, /*!< BEEP clock busy in switch Flag*/
|
||||
CLK_FLAG_EEREADY = (uint8_t)0x77, /*!< Flash program memory and Data EEPROM ready Flag */
|
||||
CLK_FLAG_EEBUSY = (uint8_t)0x76, /*!< Flash program memory and Data EEPROM busy Flag */
|
||||
CLK_FLAG_LSEPD = (uint8_t)0x75, /*!< LSE power-down Flag */
|
||||
CLK_FLAG_HSEPD = (uint8_t)0x74, /*!< HSE power-down Flag */
|
||||
CLK_FLAG_LSIPD = (uint8_t)0x73, /*!< LSI power-down Flag */
|
||||
CLK_FLAG_HSIPD = (uint8_t)0x72, /*!< HSI power-down Flag */
|
||||
CLK_FLAG_REGREADY = (uint8_t)0x70, /*!< REGREADY Flag */
|
||||
CLK_FLAG_LSECSSF = (uint8_t)0x83, /*!< CSS on LSE detection Flag */
|
||||
CLK_FLAG_RTCCLKSWF = (uint8_t)0x84 /*!< RTCCLK switch completed flag on LSE failure */
|
||||
}CLK_FLAG_TypeDef;
|
||||
|
||||
#define IS_CLK_FLAGS(FLAG) (((FLAG) == CLK_FLAG_LSIRDY) ||\
|
||||
((FLAG) == CLK_FLAG_HSIRDY) ||\
|
||||
((FLAG) == CLK_FLAG_HSERDY) ||\
|
||||
((FLAG) == CLK_FLAG_SWBSY) ||\
|
||||
((FLAG) == CLK_FLAG_CSSD) ||\
|
||||
((FLAG) == CLK_FLAG_AUX) ||\
|
||||
((FLAG) == CLK_FLAG_LSERDY) ||\
|
||||
((FLAG) == CLK_FLAG_CCOBSY) ||\
|
||||
((FLAG) == CLK_FLAG_RTCSWBSY) ||\
|
||||
((FLAG) == CLK_FLAG_EEREADY) ||\
|
||||
((FLAG) == CLK_FLAG_EEBUSY) ||\
|
||||
((FLAG) == CLK_FLAG_LSEPD) ||\
|
||||
((FLAG) == CLK_FLAG_LSIPD) ||\
|
||||
((FLAG) == CLK_FLAG_HSEPD) ||\
|
||||
((FLAG) == CLK_FLAG_HSIPD) ||\
|
||||
((FLAG) == CLK_FLAG_REGREADY) ||\
|
||||
((FLAG) == CLK_FLAG_BEEPSWBSY)||\
|
||||
((FLAG) == CLK_FLAG_LSECSSF)||\
|
||||
((FLAG) == CLK_FLAG_RTCCLKSWF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_Interrupts
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_IT_CSSD = (uint8_t)0x0C, /*!< Clock security system detection Flag */
|
||||
CLK_IT_SWIF = (uint8_t)0x1C, /*!< Clock switch interrupt Flag */
|
||||
CLK_IT_LSECSSF = (uint8_t)0x2C /*!< LSE Clock security system detection Interrupt */
|
||||
}CLK_IT_TypeDef;
|
||||
#define IS_CLK_IT(IT) (((IT) == CLK_IT_CSSD) ||\
|
||||
((IT) == CLK_IT_SWIF) ||\
|
||||
((IT) == CLK_IT_LSECSSF))
|
||||
|
||||
#define IS_CLK_CLEAR_IT(IT) (((IT) == CLK_IT_SWIF)||\
|
||||
((IT) == CLK_IT_LSECSSF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CLK_Halt_Configuration
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
CLK_Halt_BEEPRunning = (uint8_t)0x40, /*!< BEEP clock Halt/Active-halt mode */
|
||||
CLK_Halt_FastWakeup = (uint8_t)0x20, /*!< Fast wakeup from Halt/Active-halt modes */
|
||||
CLK_Halt_SlowWakeup = (uint8_t)0x10 /*!< Slow Active-halt mode */
|
||||
}
|
||||
CLK_Halt_TypeDef;
|
||||
|
||||
#define IS_CLK_HALT(HALT) (((HALT) == CLK_Halt_BEEPRunning) ||\
|
||||
((HALT) == CLK_Halt_FastWakeup) ||\
|
||||
((HALT) == CLK_Halt_SlowWakeup))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the CLK configuration to the default reset state ******/
|
||||
void CLK_DeInit(void);
|
||||
|
||||
/* Internal/external clocks, CSS and CCO configuration functions **************/
|
||||
void CLK_HSICmd(FunctionalState NewState);
|
||||
void CLK_AdjustHSICalibrationValue(uint8_t CLK_HSICalibrationValue);
|
||||
void CLK_LSICmd(FunctionalState NewState);
|
||||
void CLK_HSEConfig(CLK_HSE_TypeDef CLK_HSE);
|
||||
void CLK_LSEConfig(CLK_LSE_TypeDef CLK_LSE);
|
||||
void CLK_ClockSecuritySystemEnable(void);
|
||||
void CLK_ClockSecuritySytemDeglitchCmd(FunctionalState NewState);
|
||||
void CLK_CCOConfig(CLK_CCOSource_TypeDef CLK_CCOSource, CLK_CCODiv_TypeDef CLK_CCODiv);
|
||||
|
||||
/* System clocks configuration functions ******************/
|
||||
void CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_TypeDef CLK_SYSCLKSource);
|
||||
CLK_SYSCLKSource_TypeDef CLK_GetSYSCLKSource(void);
|
||||
uint32_t CLK_GetClockFreq(void);
|
||||
void CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_TypeDef CLK_SYSCLKDiv);
|
||||
void CLK_SYSCLKSourceSwitchCmd(FunctionalState NewState);
|
||||
|
||||
/* Peripheral clocks configuration functions **********************************/
|
||||
void CLK_RTCClockConfig(CLK_RTCCLKSource_TypeDef CLK_RTCCLKSource, CLK_RTCCLKDiv_TypeDef CLK_RTCCLKDiv);
|
||||
void CLK_BEEPClockConfig(CLK_BEEPCLKSource_TypeDef CLK_BEEPCLKSource);
|
||||
void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState);
|
||||
|
||||
/* CSS on LSE configuration functions *****************************************/
|
||||
void CLK_LSEClockSecuritySystemEnable(void);
|
||||
void CLK_RTCCLKSwitchOnLSEFailureEnable(void);
|
||||
|
||||
/* Low power clock configuration functions ************************************/
|
||||
void CLK_HaltConfig(CLK_Halt_TypeDef CLK_Halt, FunctionalState NewState);
|
||||
void CLK_MainRegulatorCmd(FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState);
|
||||
FlagStatus CLK_GetFlagStatus(CLK_FLAG_TypeDef CLK_FLAG);
|
||||
void CLK_ClearFlag(void);
|
||||
ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT);
|
||||
void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT);
|
||||
|
||||
|
||||
#endif /* __STM8L15x_CLK_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
242
firmware/inc/stm8l151x/inc/stm8l15x_comp.h
Normal file
242
firmware/inc/stm8l151x/inc/stm8l15x_comp.h
Normal file
@@ -0,0 +1,242 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_comp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the COMP firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_COMP_H
|
||||
#define __STM8L15x_COMP_H
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
COMP_Selection_COMP1 = ((uint8_t)0x01), /*!< Selection of Comparator 1. */
|
||||
COMP_Selection_COMP2 = ((uint8_t)0x02) /*!< Selection of Comparator 2. */
|
||||
}COMP_Selection_TypeDef;
|
||||
|
||||
#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
|
||||
((PERIPH) == COMP_Selection_COMP2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Edge
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
COMP_Edge_Falling = ((uint8_t)0x01), /*!< Falling edge selection. */
|
||||
COMP_Edge_Rising = ((uint8_t)0x02), /*!< Rising edge selection. */
|
||||
COMP_Edge_Rising_Falling = ((uint8_t)0x03) /*!< Rising and Falling edge selection. */
|
||||
}COMP_Edge_TypeDef;
|
||||
|
||||
#define IS_COMP_EDGE(EDGE) (((EDGE) == COMP_Edge_Falling) || \
|
||||
((EDGE) == COMP_Edge_Rising) || \
|
||||
((EDGE) == COMP_Edge_Rising_Falling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Inverting_Input_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
COMP_InvertingInput_IO = ((uint8_t)0x08), /*!< Input/Output on comparator inverting input enable.*/
|
||||
COMP_InvertingInput_VREFINT = ((uint8_t)0x10), /*!< VREFINT on comparator inverting input enable. */
|
||||
COMP_InvertingInput_3_4VREFINT = ((uint8_t)0x18), /*!< 3/4 VREFINT on comparator inverting input enable. */
|
||||
COMP_InvertingInput_1_2VREFINT = ((uint8_t)0x20), /*!< 1/2 VREFINT on comparator inverting input enable. */
|
||||
COMP_InvertingInput_1_4VREFINT = ((uint8_t)0x28), /*!< 1/4 VREFINT on comparator inverting input enable. */
|
||||
COMP_InvertingInput_DAC1 = ((uint8_t)0x30), /*!< DAC1 output on comparator inverting input enable. */
|
||||
COMP_InvertingInput_DAC2 = ((uint8_t)0x38) /*!< DAC2 output on comparator inverting input enable. */
|
||||
}COMP_InvertingInput_Typedef;
|
||||
|
||||
#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_IO) || \
|
||||
((INPUT) == COMP_InvertingInput_VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC1) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP2_Output_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
COMP_OutputSelect_TIM2IC2 = ((uint8_t)0x00), /*!< COMP2 output connected to TIM2 Input Capture 2 */
|
||||
COMP_OutputSelect_TIM3IC2 = ((uint8_t)0x40), /*!< COMP2 output connected to TIM3 Input Capture 2 */
|
||||
COMP_OutputSelect_TIM1BRK = ((uint8_t)0x80), /*!< COMP2 output connected to TIM1 Break Input */
|
||||
COMP_OutputSelect_TIM1OCREFCLR = ((uint8_t)0xC0) /*!< COMP2 output connected to TIM1 OCREF Clear */
|
||||
}COMP_OutputSelect_Typedef;
|
||||
|
||||
#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC2) || \
|
||||
((OUTPUT) == COMP_OutputSelect_TIM3IC2) || \
|
||||
((OUTPUT) == COMP_OutputSelect_TIM1BRK) || \
|
||||
((OUTPUT) == COMP_OutputSelect_TIM1OCREFCLR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Speed
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
COMP_Speed_Slow = ((uint8_t)0x00), /*!< Comparator speed: slow */
|
||||
COMP_Speed_Fast = ((uint8_t)0x04) /*!< Comparator speed: fast */
|
||||
}COMP_Speed_TypeDef;
|
||||
|
||||
#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \
|
||||
((SPEED) == COMP_Speed_Fast))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Trigger_Group
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
COMP_TriggerGroup_InvertingInput = ((uint8_t)0x01), /*!< Trigger on comparator 2 inverting input */
|
||||
COMP_TriggerGroup_NonInvertingInput = ((uint8_t)0x02), /*!< Trigger on comparator 2 non inverting input */
|
||||
COMP_TriggerGroup_VREFINTOutput = ((uint8_t)0x03), /*!< Trigger on VREFINT output */
|
||||
COMP_TriggerGroup_DACOutput = ((uint8_t)0x04) /*!< Trigger on DAC output */
|
||||
}COMP_TriggerGroup_TypeDef;
|
||||
|
||||
#define IS_COMP_TRIGGERGROUP(TRIGGERGROUP) (((TRIGGERGROUP) == COMP_TriggerGroup_NonInvertingInput) || \
|
||||
((TRIGGERGROUP) == COMP_TriggerGroup_InvertingInput) || \
|
||||
((TRIGGERGROUP) == COMP_TriggerGroup_VREFINTOutput) || \
|
||||
((TRIGGERGROUP) == COMP_TriggerGroup_DACOutput)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Trigger_Pin
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
COMP_TriggerPin_0 = ((uint8_t)0x01), /*!< PE5 for the non inverting input Trigger Group
|
||||
PC3 for the inverting input Trigger Group
|
||||
PB6 for the DAC output Trigger Group
|
||||
PC2 for the VREFINT output Trigger Group
|
||||
*/
|
||||
COMP_TriggerPin_1 = ((uint8_t)0x02), /*!< PD0 for the non inverting input Trigger Group
|
||||
PC4 for the inverting input Trigger Group
|
||||
PB5 for the DAC output Trigger Group
|
||||
PD7 for the VREFINT output Trigger Group
|
||||
*/
|
||||
COMP_TriggerPin_2 = ((uint8_t)0x04) /*!< PD1 for the non inverting input Trigger Group
|
||||
PC7 for the inverting input Trigger Group
|
||||
PB4 for the DAC output Trigger Group
|
||||
PD6 for the VREFINT output Trigger Group */
|
||||
}COMP_TriggerPin_TypeDef;
|
||||
|
||||
#define IS_COMP_TRIGGERPIN(TRIGGERPIN) ((((uint8_t)(TRIGGERPIN) & (uint8_t)0xF8) == (uint8_t) 0x00) && \
|
||||
((TRIGGERPIN) != (uint8_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Output_Level
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
COMP_OutputLevel_Low = ((uint8_t)0x00), /*!< Comparator output level is low */
|
||||
COMP_OutputLevel_High = ((uint8_t)0x01) /*!< Comparator output level is high */
|
||||
}COMP_OutputLevel_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Function used to set the CLK configuration to the default reset state ******/
|
||||
void COMP_DeInit(void);
|
||||
/* Initialization and Configuration functions ****************************/
|
||||
void COMP_Init(COMP_InvertingInput_Typedef COMP_InvertingInput, COMP_OutputSelect_Typedef COMP_OutputSelect,
|
||||
COMP_Speed_TypeDef COMP_Speed);
|
||||
void COMP_VrefintToCOMP1Connect(FunctionalState NewState);
|
||||
void COMP_EdgeConfig(COMP_Selection_TypeDef COMP_Selection, COMP_Edge_TypeDef COMP_Edge);
|
||||
COMP_OutputLevel_TypeDef COMP_GetOutputLevel(COMP_Selection_TypeDef COMP_Selection);
|
||||
/* Window mode control function ***********************************************/
|
||||
void COMP_WindowCmd(FunctionalState NewState);
|
||||
/* Internal Reference Voltage (VREFINT) output function ***********************/
|
||||
void COMP_VrefintOutputCmd(FunctionalState NewState);
|
||||
/* Comparator channels trigger configuration functions ************************/
|
||||
void COMP_SchmittTriggerCmd(FunctionalState NewState);
|
||||
void COMP_TriggerConfig(COMP_TriggerGroup_TypeDef COMP_TriggerGroup,
|
||||
COMP_TriggerPin_TypeDef COMP_TriggerPin,
|
||||
FunctionalState NewState);
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void COMP_ITConfig(COMP_Selection_TypeDef COMP_Selection, FunctionalState NewState);
|
||||
FlagStatus COMP_GetFlagStatus(COMP_Selection_TypeDef COMP_Selection);
|
||||
void COMP_ClearFlag(COMP_Selection_TypeDef COMP_Selection);
|
||||
ITStatus COMP_GetITStatus(COMP_Selection_TypeDef COMP_Selection);
|
||||
void COMP_ClearITPendingBit(COMP_Selection_TypeDef COMP_Selection);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __STM8L15x_COMP_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
293
firmware/inc/stm8l151x/inc/stm8l15x_dac.h
Normal file
293
firmware/inc/stm8l151x/inc/stm8l15x_dac.h
Normal file
@@ -0,0 +1,293 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_DAC_H
|
||||
#define __STM8L15x_DAC_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_Trigger_None = ((uint8_t)0x30), /*!< DAC trigger None */
|
||||
DAC_Trigger_T4_TRGO = ((uint8_t)0x00), /*!< DAC trigger TIM4 TRGO */
|
||||
DAC_Trigger_T5_TRGO = ((uint8_t)0x08), /*!< DAC trigger TIM5 TRGO */
|
||||
DAC_Trigger_Ext = ((uint8_t)0x10), /*!< DAC trigger External Trigger (PE4) */
|
||||
DAC_Trigger_Software = ((uint8_t)0x38) /*!< DAC trigger software */
|
||||
}DAC_Trigger_TypeDef;
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
||||
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_Ext) || \
|
||||
((TRIGGER) == DAC_Trigger_Software))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_Align_12b_R = ((uint8_t)0x00), /*!< DAC alignment Right 12bit */
|
||||
DAC_Align_12b_L = ((uint8_t)0x04), /*!< DAC alignment Left 12bit */
|
||||
DAC_Align_8b_R = ((uint8_t)0x08) /*!< DAC alignment Right 8bit */
|
||||
}DAC_Align_TypeDef;
|
||||
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
||||
((ALIGN) == DAC_Align_12b_L) || \
|
||||
((ALIGN) == DAC_Align_8b_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_Channel_1 = ((uint8_t)0x00), /*!< DAC Channel 1 selection */
|
||||
DAC_Channel_2 = ((uint8_t)0x01) /*!< DAC Channel 2 selection */
|
||||
}DAC_Channel_TypeDef;
|
||||
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
|
||||
((CHANNEL) == DAC_Channel_2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DAC_Wave_Noise = ((uint8_t)0x40), /*!< Noise Wave Generation */
|
||||
DAC_Wave_Triangle = ((uint8_t)0x80) /*!< Triangle Wave Generation */
|
||||
}DAC_Wave_TypeDef;
|
||||
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
|
||||
((WAVE) == DAC_Wave_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_OutputBuffer_Enable = ((uint8_t)0x00), /*!< DAC output buffer Enabled */
|
||||
DAC_OutputBuffer_Disable = ((uint8_t)0x02) /*!< DAC output buffer Disabled */
|
||||
}DAC_OutputBuffer_TypeDef;
|
||||
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
|
||||
((STATE) == DAC_OutputBuffer_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_IT_DMAUDR = ((uint8_t)0x20) /*!< DMA Underrun Interrupt */
|
||||
}DAC_IT_TypeDef;
|
||||
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_FLAG_DMAUDR = ((uint8_t)0x01) /*!< DMA Underrun flag */
|
||||
}DAC_FLAG_TypeDef;
|
||||
|
||||
#define IS_DAC_GET_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_lfsrunmask
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DAC_LFSRUnmask_Bit0 = ((uint8_t)0x00), /*!< Noise LFSR Unmask 1 LSB */
|
||||
DAC_LFSRUnmask_Bits1_0 = ((uint8_t)0x01), /*!< Noise LFSR Unmask 2 LSB */
|
||||
DAC_LFSRUnmask_Bits2_0 = ((uint8_t)0x02), /*!< Noise LFSR Unmask 3 LSB */
|
||||
DAC_LFSRUnmask_Bits3_0 = ((uint8_t)0x03), /*!< Noise LFSR Unmask 4 LSB */
|
||||
DAC_LFSRUnmask_Bits4_0 = ((uint8_t)0x04), /*!< Noise LFSR Unmask 5 LSB */
|
||||
DAC_LFSRUnmask_Bits5_0 = ((uint8_t)0x05), /*!< Noise LFSR Unmask 6 LSB */
|
||||
DAC_LFSRUnmask_Bits6_0 = ((uint8_t)0x06), /*!< Noise LFSR Unmask 7 LSB */
|
||||
DAC_LFSRUnmask_Bits7_0 = ((uint8_t)0x07), /*!< Noise LFSR Unmask 8 LSB */
|
||||
DAC_LFSRUnmask_Bits8_0 = ((uint8_t)0x08), /*!< Noise LFSR Unmask 9 LSB */
|
||||
DAC_LFSRUnmask_Bits9_0 = ((uint8_t)0x09), /*!< Noise LFSR Unmask 10 LSB */
|
||||
DAC_LFSRUnmask_Bits10_0 = ((uint8_t)0x0A), /*!< Noise LFSR Unmask 11 LSB */
|
||||
DAC_LFSRUnmask_Bits11_0 = ((uint8_t)0x0B) /*!< Noise LFSR Unmask 12 LSB */
|
||||
}DAC_LFSRUnmask_TypeDef;
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) ((VALUE) <= 0x0F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_TriangleAmplitude_1 = ((uint8_t)0x00), /*!< Triangle Amplitude = Vref.(1/4096)*/
|
||||
DAC_TriangleAmplitude_3 = ((uint8_t)0x01), /*!< Triangle Amplitude = Vref.(3/4096)*/
|
||||
DAC_TriangleAmplitude_7 = ((uint8_t)0x02), /*!< Triangle Amplitude = Vref.(7/4096)*/
|
||||
DAC_TriangleAmplitude_15 = ((uint8_t)0x03), /*!< Triangle Amplitude = Vref.(15/4096)*/
|
||||
DAC_TriangleAmplitude_31 = ((uint8_t)0x04), /*!< Triangle Amplitude = Vref.(31/4096)*/
|
||||
DAC_TriangleAmplitude_63 = ((uint8_t)0x05), /*!< Triangle Amplitude = Vref.(63/4096)*/
|
||||
DAC_TriangleAmplitude_127 = ((uint8_t)0x06), /*!< Triangle Amplitude = Vref.(127/4096)*/
|
||||
DAC_TriangleAmplitude_255 = ((uint8_t)0x07), /*!< Triangle Amplitude = Vref.(255/4096)*/
|
||||
DAC_TriangleAmplitude_511 = ((uint8_t)0x08), /*!< Triangle Amplitude = Vref.(511/4096)*/
|
||||
DAC_TriangleAmplitude_1023 = ((uint8_t)0x09), /*!< Triangle Amplitude = Vref.(1023/4096)*/
|
||||
DAC_TriangleAmplitude_2047 = ((uint8_t)0x0A), /*!< Triangle Amplitude = Vref.(2047/4096)*/
|
||||
DAC_TriangleAmplitude_4095 = ((uint8_t)0x0B) /*!< Triangle Amplitude = Vref.(4095/4096)*/
|
||||
}DAC_TriangleAmplitude_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DAC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_DATA_08R(DATA) ((DATA) <= 0x00FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup DAC_Registers_Offset
|
||||
* @{
|
||||
*/
|
||||
#define CR1_Offset ((uint8_t)0x00)
|
||||
#define CR2_Offset ((uint8_t)0x01)
|
||||
#define DCH1RDHRH_Offset ((uint8_t)0x20)
|
||||
#define CH1RDHRH_Offset ((uint8_t)0x08)
|
||||
#define CH2RDHRH_Offset ((uint8_t)0x14)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_legacy
|
||||
* @{
|
||||
*/
|
||||
#define DAC_TriangleWaveAmplitude DAC_SetTriangleWaveAmplitude
|
||||
#define DAC_NoiseWaveLFSR DAC_SetNoiseWaveLFSR
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the DAC configuration to the default reset state *****/
|
||||
void DAC_DeInit(void);
|
||||
|
||||
/* DAC channels configuration: trigger, output buffer, data format functions */
|
||||
void DAC_Init(DAC_Channel_TypeDef DAC_Channel,
|
||||
DAC_Trigger_TypeDef DAC_Trigger,
|
||||
DAC_OutputBuffer_TypeDef DAC_OutputBuffer);
|
||||
void DAC_Cmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState);
|
||||
void DAC_SoftwareTriggerCmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState);
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
|
||||
void DAC_WaveGenerationCmd(DAC_Channel_TypeDef DAC_Channel, DAC_Wave_TypeDef DAC_Wave, FunctionalState NewState);
|
||||
void DAC_SetNoiseWaveLFSR(DAC_Channel_TypeDef DAC_Channel, DAC_LFSRUnmask_TypeDef DAC_LFSRUnmask);
|
||||
void DAC_SetTriangleWaveAmplitude(DAC_Channel_TypeDef DAC_Channel, DAC_TriangleAmplitude_TypeDef DAC_TriangleAmplitude);
|
||||
void DAC_SetChannel1Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data);
|
||||
void DAC_SetChannel2Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data);
|
||||
void DAC_SetDualChannelData(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data2, uint16_t DAC_Data1);
|
||||
uint16_t DAC_GetDataOutputValue(DAC_Channel_TypeDef DAC_Channel);
|
||||
|
||||
/* DMA management function ***************************************************/
|
||||
void DAC_DMACmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DAC_ITConfig(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT, FunctionalState NewState);
|
||||
FlagStatus DAC_GetFlagStatus(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG);
|
||||
void DAC_ClearFlag(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG);
|
||||
ITStatus DAC_GetITStatus(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT);
|
||||
void DAC_ClearITPendingBit(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT);
|
||||
|
||||
#endif /*__STM8L15x_DAC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
341
firmware/inc/stm8l151x/inc/stm8l15x_dma.h
Normal file
341
firmware/inc/stm8l151x/inc/stm8l15x_dma.h
Normal file
@@ -0,0 +1,341 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the DMA
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_DMA_H
|
||||
#define __STM8L15x_DMA_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Data_Transfer_Direction
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_DIR_PeripheralToMemory = ((uint8_t)0x00), /*!< Data transfer direction is Peripheral To Memory */
|
||||
DMA_DIR_MemoryToPeripheral = ((uint8_t)0x08), /*!< Data transfer direction is Memory To Peripheral */
|
||||
DMA_DIR_Memory0ToMemory1 = ((uint8_t)0x40) /*!< Data transfer direction is Memory0 To Memory 1 */
|
||||
}DMA_DIR_TypeDef;
|
||||
|
||||
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_MemoryToPeripheral) || \
|
||||
((DIR) == DMA_DIR_PeripheralToMemory) || \
|
||||
((DIR) == DMA_DIR_Memory0ToMemory1 ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_Mode_Normal = ((uint8_t)0x00), /*!< DMA normal buffer mode*/
|
||||
DMA_Mode_Circular = ((uint8_t)0x10) /*!< DMA circular buffer mode */
|
||||
}DMA_Mode_TypeDef;
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || \
|
||||
((MODE) == DMA_Mode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Incremented_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_MemoryIncMode_Dec = ((uint8_t)0x00), /*!< DMA memory incremented mode is decremental */
|
||||
DMA_MemoryIncMode_Inc = ((uint8_t)0x20) /*!< DMA memory incremented mode is incremental */
|
||||
}DMA_MemoryIncMode_TypeDef;
|
||||
|
||||
#define IS_DMA_MEMORY_INC_MODE(MODE) (((MODE) == DMA_MemoryIncMode_Inc) || \
|
||||
((MODE) == DMA_MemoryIncMode_Dec))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_Priority_Low = ((uint8_t)0x00), /*!< Software Priority is Low */
|
||||
DMA_Priority_Medium = ((uint8_t)0x10), /*!< Software Priority is Medium */
|
||||
DMA_Priority_High = ((uint8_t)0x20), /*!< Software Priority is High */
|
||||
DMA_Priority_VeryHigh = ((uint8_t)0x30) /*!< Software Priority is Very High*/
|
||||
}DMA_Priority_TypeDef;
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
|
||||
((PRIORITY) == DMA_Priority_High) || \
|
||||
((PRIORITY) == DMA_Priority_Medium) || \
|
||||
((PRIORITY) == DMA_Priority_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_Data_Size
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_MemoryDataSize_Byte = ((uint8_t)0x00),/*!< Memory Data Size is 1 Byte */
|
||||
DMA_MemoryDataSize_HalfWord = ((uint8_t)0x08) /*!< Memory Data Size is 2 Bytes */
|
||||
}DMA_MemoryDataSize_TypeDef;
|
||||
|
||||
#define IS_DMA_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
||||
((SIZE) == DMA_MemoryDataSize_HalfWord))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Flags
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA1_FLAG_GB = ((uint16_t)0x0002), /*!< Global Busy Flag */
|
||||
|
||||
DMA1_FLAG_IFC0 = ((uint16_t)0x1001), /*!< Global Interrupt Flag Channel 0 */
|
||||
DMA1_FLAG_IFC1 = ((uint16_t)0x1002), /*!< Global Interrupt Flag Channel 1 */
|
||||
DMA1_FLAG_IFC2 = ((uint16_t)0x1004), /*!< Global Interrupt Flag Channel 2 */
|
||||
DMA1_FLAG_IFC3 = ((uint16_t)0x1008), /*!< Global Interrupt Flag Channel 3 */
|
||||
|
||||
DMA1_FLAG_TC0 = ((uint16_t)0x0102), /*!< Transaction Complete Interrupt Flag Channel 0 */
|
||||
DMA1_FLAG_TC1 = ((uint16_t)0x0202), /*!< Transaction Complete Interrupt Flag Channel 1 */
|
||||
DMA1_FLAG_TC2 = ((uint16_t)0x0402), /*!< Transaction Complete Interrupt Flag Channel 2 */
|
||||
DMA1_FLAG_TC3 = ((uint16_t)0x0802), /*!< Transaction Complete Interrupt Flag Channel 3 */
|
||||
|
||||
DMA1_FLAG_HT0 = ((uint16_t)0x0104), /*!< Half Transaction Interrupt Flag Channel 0 */
|
||||
DMA1_FLAG_HT1 = ((uint16_t)0x0204), /*!< Half Transaction Interrupt Flag Channel 1 */
|
||||
DMA1_FLAG_HT2 = ((uint16_t)0x0404), /*!< Half Transaction Interrupt Flag Channel 2 */
|
||||
DMA1_FLAG_HT3 = ((uint16_t)0x0804), /*!< Half Transaction Interrupt Flag Channel 3 */
|
||||
|
||||
DMA1_FLAG_PEND0 = ((uint16_t)0x0140), /*!< DMA Request pending on Channel 0 */
|
||||
DMA1_FLAG_PEND1 = ((uint16_t)0x0240), /*!< DMA Request pending on Channel 1 */
|
||||
DMA1_FLAG_PEND2 = ((uint16_t)0x0440), /*!< DMA Request pending on Channel 2 */
|
||||
DMA1_FLAG_PEND3 = ((uint16_t)0x0840), /*!< DMA Request pending on Channel 3 */
|
||||
|
||||
DMA1_FLAG_BUSY0 = ((uint16_t)0x0180), /*!< No DMA transfer on going in Channel 0 */
|
||||
DMA1_FLAG_BUSY1 = ((uint16_t)0x0280), /*!< No DMA transfer on going in Channel 1 */
|
||||
DMA1_FLAG_BUSY2 = ((uint16_t)0x0480), /*!< No DMA transfer on going in Channel 2 */
|
||||
DMA1_FLAG_BUSY3 = ((uint16_t)0x0880) /*!< No DMA transfer on going in Channel 3 */
|
||||
}DMA_FLAG_TypeDef;
|
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GB) || \
|
||||
((FLAG) == DMA1_FLAG_IFC0) || \
|
||||
((FLAG) == DMA1_FLAG_IFC1) || \
|
||||
((FLAG) == DMA1_FLAG_IFC2) || \
|
||||
((FLAG) == DMA1_FLAG_IFC3) || \
|
||||
((FLAG) == DMA1_FLAG_TC0) || \
|
||||
((FLAG) == DMA1_FLAG_TC1) || \
|
||||
((FLAG) == DMA1_FLAG_TC2) || \
|
||||
((FLAG) == DMA1_FLAG_TC3) || \
|
||||
((FLAG) == DMA1_FLAG_HT0) || \
|
||||
((FLAG) == DMA1_FLAG_HT1) || \
|
||||
((FLAG) == DMA1_FLAG_HT2) || \
|
||||
((FLAG) == DMA1_FLAG_HT3) || \
|
||||
((FLAG) == DMA1_FLAG_PEND0) || \
|
||||
((FLAG) == DMA1_FLAG_PEND1) || \
|
||||
((FLAG) == DMA1_FLAG_PEND2) || \
|
||||
((FLAG) == DMA1_FLAG_PEND3) || \
|
||||
((FLAG) == DMA1_FLAG_BUSY0) || \
|
||||
((FLAG) == DMA1_FLAG_BUSY1) || \
|
||||
((FLAG) == DMA1_FLAG_BUSY2) || \
|
||||
((FLAG) == DMA1_FLAG_BUSY3))
|
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) (((FLAG) == DMA1_FLAG_TC0) || \
|
||||
((FLAG) == DMA1_FLAG_TC1) || \
|
||||
((FLAG) == DMA1_FLAG_TC2) || \
|
||||
((FLAG) == DMA1_FLAG_TC3) || \
|
||||
((FLAG) == DMA1_FLAG_HT0) || \
|
||||
((FLAG) == DMA1_FLAG_HT1) || \
|
||||
((FLAG) == DMA1_FLAG_HT2) || \
|
||||
((FLAG) == DMA1_FLAG_HT3) || \
|
||||
((FLAG) == (DMA1_FLAG_TC0 |DMA1_FLAG_HT0)) || \
|
||||
((FLAG) == (DMA1_FLAG_TC1 |DMA1_FLAG_HT1)) || \
|
||||
((FLAG) == (DMA1_FLAG_TC2 |DMA1_FLAG_HT2)) || \
|
||||
((FLAG) == (DMA1_FLAG_TC3 |DMA1_FLAG_HT3)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_One_Channel_Interrupts
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_ITx_TC = ((uint8_t)0x02),/*!< Transaction Complete Interrupt */
|
||||
DMA_ITx_HT = ((uint8_t)0x04) /*!< Half Transaction Interrupt*/
|
||||
}DMA_ITx_TypeDef;
|
||||
|
||||
#define IS_DMA_CONFIG_ITX(IT) ((((IT) & 0xF9) == 0x00) && ((IT) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Interrupts
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/* Transaction Complete Interrupts*/
|
||||
DMA1_IT_TC0 = ((uint8_t)0x12), /*!< Transaction Complete Interrupt Channel 0 */
|
||||
DMA1_IT_TC1 = ((uint8_t)0x22), /*!< Transaction Complete Interrupt Channel 1 */
|
||||
DMA1_IT_TC2 = ((uint8_t)0x42), /*!< Transaction Complete Interrupt Channel 2 */
|
||||
DMA1_IT_TC3 = ((uint8_t)0x82), /*!< Transaction Complete Interrupt Channel 3 */
|
||||
/* Half Transaction Interrupts */
|
||||
DMA1_IT_HT0 = ((uint8_t)0x14), /*!< Half Transaction Interrupt Channel 0 */
|
||||
DMA1_IT_HT1 = ((uint8_t)0x24), /*!< Half Transaction Interrupt Channel 1 */
|
||||
DMA1_IT_HT2 = ((uint8_t)0x44), /*!< Half Transaction Interrupt Channel 2 */
|
||||
DMA1_IT_HT3 = ((uint8_t)0x84) /*!< Half Transaction Interrupt Channel 3 */
|
||||
}DMA_IT_TypeDef;
|
||||
|
||||
#define IS_DMA_CLEAR_IT(IT) (((IT) == DMA1_IT_TC0) || \
|
||||
((IT) == DMA1_IT_TC1) || \
|
||||
((IT) == DMA1_IT_TC2) || \
|
||||
((IT) == DMA1_IT_TC3) || \
|
||||
((IT) == DMA1_IT_HT0) || \
|
||||
((IT) == DMA1_IT_HT1) || \
|
||||
((IT) == DMA1_IT_HT2) || \
|
||||
((IT) == DMA1_IT_HT3) || \
|
||||
((IT) == (DMA1_IT_TC0|DMA1_IT_HT0)) || \
|
||||
((IT) == (DMA1_IT_TC1|DMA1_IT_HT1)) || \
|
||||
((IT) == (DMA1_IT_TC2|DMA1_IT_HT2)) || \
|
||||
((IT) == (DMA1_IT_TC3|DMA1_IT_HT3)))
|
||||
|
||||
#define IS_DMA_GET_IT(IT)(((IT) == DMA1_IT_TC0) || \
|
||||
((IT) == DMA1_IT_TC1) || \
|
||||
((IT) == DMA1_IT_TC2) || \
|
||||
((IT) == DMA1_IT_TC3) || \
|
||||
((IT) == DMA1_IT_HT0) || \
|
||||
((IT) == DMA1_IT_HT1) || \
|
||||
((IT) == DMA1_IT_HT2) || \
|
||||
((IT) == DMA1_IT_HT3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @addtogroup DMA_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Channels
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_CHANNEL(PERIPH) (((*(uint16_t*)&(PERIPH)) == DMA1_Channel0_BASE) || \
|
||||
((*(uint16_t*)&(PERIPH)) == DMA1_Channel1_BASE) || \
|
||||
((*(uint16_t*)&(PERIPH)) == DMA1_Channel2_BASE) || \
|
||||
((*(uint16_t*)&(PERIPH)) == DMA1_Channel3_BASE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_Buffer_Size
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) ((SIZE) > (uint8_t)0x0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Timeout
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_TIMEOUT(TIME) ((TIME) < (uint8_t)0x40)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Functions used to set the DMA configuration to the default reset state ****/
|
||||
void DMA_GlobalDeInit(void);
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx,
|
||||
uint32_t DMA_Memory0BaseAddr,
|
||||
uint16_t DMA_PeripheralMemory1BaseAddr,
|
||||
uint8_t DMA_BufferSize,
|
||||
DMA_DIR_TypeDef DMA_DIR,
|
||||
DMA_Mode_TypeDef DMA_Mode,
|
||||
DMA_MemoryIncMode_TypeDef DMA_MemoryIncMode,
|
||||
DMA_Priority_TypeDef DMA_Priority,
|
||||
DMA_MemoryDataSize_TypeDef DMA_MemoryDataSize );
|
||||
void DMA_GlobalCmd(FunctionalState NewState);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState);
|
||||
void DMA_SetTimeOut(uint8_t DMA_TimeOut);
|
||||
|
||||
/* Data Counter functions *****************************************************/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx, uint8_t DataNumber);
|
||||
uint8_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, DMA_ITx_TypeDef DMA_ITx, FunctionalState NewState);
|
||||
FlagStatus DMA_GetFlagStatus(DMA_FLAG_TypeDef DMA_FLAG);
|
||||
void DMA_ClearFlag(DMA_FLAG_TypeDef DMA_FLAG);
|
||||
ITStatus DMA_GetITStatus(DMA_IT_TypeDef DMA_IT);
|
||||
void DMA_ClearITPendingBit(DMA_IT_TypeDef DMA_IT);
|
||||
|
||||
#endif /*__STM8L15x_DMA_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
288
firmware/inc/stm8l151x/inc/stm8l15x_exti.h
Normal file
288
firmware/inc/stm8l151x/inc/stm8l15x_exti.h
Normal file
@@ -0,0 +1,288 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the EXTI firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_EXTI_H
|
||||
#define __STM8L15x_EXTI_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Trigger
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Falling_Low = (uint8_t)0x00, /*!< Interrupt on Falling edge and Low level */
|
||||
EXTI_Trigger_Rising = (uint8_t)0x01, /*!< Interrupt on Rising edge only */
|
||||
EXTI_Trigger_Falling = (uint8_t)0x02, /*!< Interrupt on Falling edge only */
|
||||
EXTI_Trigger_Rising_Falling = (uint8_t)0x03 /*!< Interrupt on Rising and Falling edges */
|
||||
} EXTI_Trigger_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Half_Port
|
||||
*
|
||||
* @brief EXTI halfPort possible values
|
||||
* Values are coded as following:
|
||||
* - Bit 7: 0 => the half port is in EXTI_CONF1 register
|
||||
* 1 => the half port is in EXTI_CONF2 register
|
||||
* - Bits[6:0] => the half port selection mask
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXTI_HalfPort_B_LSB = (uint8_t)0x01, /*!< Interrupt selector PB(3:0) */
|
||||
EXTI_HalfPort_B_MSB = (uint8_t)0x02, /*!< Interrupt selector PB(7:4) */
|
||||
EXTI_HalfPort_D_LSB = (uint8_t)0x04, /*!< Interrupt selector PD(3:0) */
|
||||
EXTI_HalfPort_D_MSB = (uint8_t)0x08, /*!< Interrupt selector PD(7:4) */
|
||||
EXTI_HalfPort_E_LSB = (uint8_t)0x10, /*!< Interrupt selector PE(3:0) */
|
||||
EXTI_HalfPort_E_MSB = (uint8_t)0x20, /*!< Interrupt selector PE(7:4) */
|
||||
EXTI_HalfPort_F_LSB = (uint8_t)0x40, /*!< Interrupt selector PF(3:0) */
|
||||
EXTI_HalfPort_F_MSB = (uint8_t)0x81, /*!< Interrupt selector PF(7:4) */
|
||||
EXTI_HalfPort_G_LSB = (uint8_t)0x82, /*!< Interrupt selector PG(3:0) */
|
||||
EXTI_HalfPort_G_MSB = (uint8_t)0x84, /*!< Interrupt selector PG(7:4) */
|
||||
EXTI_HalfPort_H_LSB = (uint8_t)0x88, /*!< Interrupt selector PH(3:0) */
|
||||
EXTI_HalfPort_H_MSB = (uint8_t)0x90 /*!< Interrupt selector PH(7:4) */
|
||||
} EXTI_HalfPort_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Port
|
||||
*
|
||||
* @brief EXTI Port possible values
|
||||
* Values are coded in 0xXY format where
|
||||
* X: the register index
|
||||
* X = 0: EXTI_CR3
|
||||
* X = 1: EXTI_CR4
|
||||
* Y: the number of shift to be performed
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Port_B = (uint8_t)0x00, /*!< GPIO Port B */
|
||||
EXTI_Port_D = (uint8_t)0x02, /*!< GPIO Port D */
|
||||
EXTI_Port_E = (uint8_t)0x04, /*!< GPIO Port E */
|
||||
EXTI_Port_F = (uint8_t)0x06, /*!< GPIO Port F */
|
||||
EXTI_Port_G = (uint8_t)0x10, /*!< GPIO Port G */
|
||||
EXTI_Port_H = (uint8_t)0x12 /*!< GPIO Port H */
|
||||
} EXTI_Port_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Pin
|
||||
*
|
||||
* @brief EXTI PinNum possible values
|
||||
* Values are coded in 0xXY format where
|
||||
* X: the register index
|
||||
* X = 0: EXTI_CR1
|
||||
* X = 1: EXTI_CR2
|
||||
* Y: the number of shift to be performed
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Pin_0 = (uint8_t)0x00, /*!< GPIO Pin 0 */
|
||||
EXTI_Pin_1 = (uint8_t)0x02, /*!< GPIO Pin 1 */
|
||||
EXTI_Pin_2 = (uint8_t)0x04, /*!< GPIO Pin 2 */
|
||||
EXTI_Pin_3 = (uint8_t)0x06, /*!< GPIO Pin 3 */
|
||||
EXTI_Pin_4 = (uint8_t)0x10, /*!< GPIO Pin 4 */
|
||||
EXTI_Pin_5 = (uint8_t)0x12, /*!< GPIO Pin 5 */
|
||||
EXTI_Pin_6 = (uint8_t)0x14, /*!< GPIO Pin 6 */
|
||||
EXTI_Pin_7 = (uint8_t)0x16 /*!< GPIO Pin 7 */
|
||||
} EXTI_Pin_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Interrupts
|
||||
*
|
||||
* @brief EXTI IT pending bit possible values
|
||||
* Values are coded in 0xXY format where
|
||||
* X: the register index
|
||||
* X = 00: EXTI_SR1
|
||||
* X = 01: EXTI_SR2
|
||||
* Y: the IT pending bit mask
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXTI_IT_Pin0 = (uint16_t)0x0001, /*!< GPIO Pin pos 0 */
|
||||
EXTI_IT_Pin1 = (uint16_t)0x0002, /*!< GPIO Pin pos 1 */
|
||||
EXTI_IT_Pin2 = (uint16_t)0x0004, /*!< GPIO Pin pos 2 */
|
||||
EXTI_IT_Pin3 = (uint16_t)0x0008, /*!< GPIO Pin pos 3 */
|
||||
EXTI_IT_Pin4 = (uint16_t)0x0010, /*!< GPIO Pin pos 4 */
|
||||
EXTI_IT_Pin5 = (uint16_t)0x0020, /*!< GPIO Pin pos 5 */
|
||||
EXTI_IT_Pin6 = (uint16_t)0x0040, /*!< GPIO Pin pos 6 */
|
||||
EXTI_IT_Pin7 = (uint16_t)0x0080, /*!< GPIO Pin pos 7 */
|
||||
EXTI_IT_PortB = (uint16_t)0x0101, /*!< GPIO Port B */
|
||||
EXTI_IT_PortD = (uint16_t)0x0102, /*!< GPIO Port D */
|
||||
EXTI_IT_PortE = (uint16_t)0x0104, /*!< GPIO Port E */
|
||||
EXTI_IT_PortF = (uint16_t)0x0108, /*!< GPIO Port F */
|
||||
EXTI_IT_PortG = (uint16_t)0x0110, /*!< GPIO Port G */
|
||||
EXTI_IT_PortH = (uint16_t)0x0120 /*!< GPIO Port H */
|
||||
} EXTI_IT_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different functions parameters.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different values
|
||||
* of EXTI Sensitivity
|
||||
*/
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) \
|
||||
(((TRIGGER) == EXTI_Trigger_Falling_Low) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* half ports values for configuration.
|
||||
*/
|
||||
#define IS_EXTI_HALFPORT(HALFPORT) \
|
||||
(((HALFPORT) == EXTI_HalfPort_B_LSB) ||\
|
||||
((HALFPORT) == EXTI_HalfPort_B_MSB) ||\
|
||||
((HALFPORT) == EXTI_HalfPort_D_LSB) ||\
|
||||
((HALFPORT) == EXTI_HalfPort_D_MSB) ||\
|
||||
((HALFPORT) == EXTI_HalfPort_E_LSB) ||\
|
||||
((HALFPORT) == EXTI_HalfPort_E_MSB) ||\
|
||||
((HALFPORT) == EXTI_HalfPort_F_LSB) ||\
|
||||
((HALFPORT) == EXTI_HalfPort_F_MSB) ||\
|
||||
((HALFPORT) == EXTI_HalfPort_G_LSB) ||\
|
||||
((HALFPORT) == EXTI_HalfPort_G_MSB) ||\
|
||||
((HALFPORT) == EXTI_HalfPort_H_LSB) ||\
|
||||
((HALFPORT) == EXTI_HalfPort_H_MSB))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different Port Number values
|
||||
*/
|
||||
#define IS_EXTI_PORT(PORT) (((PORT) == EXTI_Port_B) ||\
|
||||
((PORT) == EXTI_Port_D) ||\
|
||||
((PORT) == EXTI_Port_E) ||\
|
||||
((PORT) == EXTI_Port_F) ||\
|
||||
((PORT) == EXTI_Port_G) ||\
|
||||
((PORT) == EXTI_Port_H))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different Pin numbers values
|
||||
*/
|
||||
#define IS_EXTI_PINNUM(PINNUM) \
|
||||
(((PINNUM) == EXTI_Pin_0) ||\
|
||||
((PINNUM) == EXTI_Pin_1) ||\
|
||||
((PINNUM) == EXTI_Pin_2) ||\
|
||||
((PINNUM) == EXTI_Pin_3) ||\
|
||||
((PINNUM) == EXTI_Pin_4) ||\
|
||||
((PINNUM) == EXTI_Pin_5) ||\
|
||||
((PINNUM) == EXTI_Pin_6) ||\
|
||||
((PINNUM) == EXTI_Pin_7))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different flags values
|
||||
*/
|
||||
#define IS_EXTI_ITPENDINGBIT(ITPENDINGBIT) \
|
||||
(((ITPENDINGBIT) == EXTI_IT_Pin0) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_Pin1) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_Pin2) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_Pin3) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_Pin4) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_Pin5) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_Pin6) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_Pin7) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_PortB) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_PortD) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_PortE) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_PortF) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_PortG) ||\
|
||||
((ITPENDINGBIT) == EXTI_IT_PortH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* EXTI configuration *********************************************************/
|
||||
void EXTI_DeInit(void);
|
||||
void EXTI_SetPinSensitivity(EXTI_Pin_TypeDef EXTI_Pin, EXTI_Trigger_TypeDef EXTI_Trigger);
|
||||
void EXTI_SelectPort(EXTI_Port_TypeDef EXTI_Port);
|
||||
void EXTI_SetHalfPortSelection(EXTI_HalfPort_TypeDef EXTI_HalfPort, FunctionalState NewState);
|
||||
void EXTI_SetPortSensitivity(EXTI_Port_TypeDef EXTI_Port, EXTI_Trigger_TypeDef EXTI_Trigger);
|
||||
EXTI_Trigger_TypeDef EXTI_GetPinSensitivity(EXTI_Pin_TypeDef EXTI_Pin);
|
||||
EXTI_Trigger_TypeDef EXTI_GetPortSensitivity(EXTI_Port_TypeDef EXTI_Port);
|
||||
|
||||
/* EXTI Interrupt status management *******************************************/
|
||||
ITStatus EXTI_GetITStatus(EXTI_IT_TypeDef EXTI_IT);
|
||||
void EXTI_ClearITPendingBit(EXTI_IT_TypeDef EXTI_IT);
|
||||
|
||||
#endif /* __STM8L15x_EXTI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
359
firmware/inc/stm8l151x/inc/stm8l15x_flash.h
Normal file
359
firmware/inc/stm8l151x/inc/stm8l15x_flash.h
Normal file
@@ -0,0 +1,359 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the FLASH firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_FLASH_H
|
||||
#define __STM8L15x_FLASH_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_PROGRAM_START_PHYSICAL_ADDRESS ((uint32_t)0x00008000) /*!< Flash: start address */
|
||||
#define FLASH_DATA_EEPROM_START_PHYSICAL_ADDRESS ((uint32_t)0x00001000) /*!< Data Eeprom: start address */
|
||||
|
||||
/* STM8L15x High density devices */
|
||||
#if defined (STM8L15X_HD) || defined (STM8L05X_HD_VL)
|
||||
#define FLASH_PROGRAM_END_PHYSICAL_ADDRESS ((uint32_t)0x00017FFF) /*!< Flash: end address */
|
||||
#define FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS ((uint32_t)0x000017FF) /*!< Data Eeprom: end address */
|
||||
#define FLASH_PROGRAM_BLOCKS_NUMBER ((uint16_t)0x200) /*!< Flash memory: total number of Block */
|
||||
#define FLASH_DATA_EEPROM_BLOCKS_NUMBER ((uint8_t)0x10) /*!< Data EEprom: total number of Block */
|
||||
#define FLASH_BLOCK_SIZE ((uint8_t)0x80) /*!< Number of bytes in a Block
|
||||
(common for Program and Data EEprom memories) */
|
||||
|
||||
/* STM8L15x Medium density and Medium density plus devices */
|
||||
#elif defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8AL31_L_MD) || defined (STM8L05X_MD_VL)
|
||||
#define FLASH_PROGRAM_END_PHYSICAL_ADDRESS ((uint32_t)0x0000FFFF) /*!< Flash: end address */
|
||||
#define FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS ((uint32_t)0x000013FF) /*!< Data Eeprom: end address */
|
||||
#define FLASH_PROGRAM_BLOCKS_NUMBER ((uint16_t)0x100) /*!< Flash memory: total number of Block */
|
||||
#define FLASH_DATA_EEPROM_BLOCKS_NUMBER ((uint8_t)0x8) /*!< Data EEprom: total number of Block */
|
||||
#define FLASH_BLOCK_SIZE ((uint8_t)0x80) /*!< Number of bytes in a Block
|
||||
(common for Program and Data EEprom memories) */
|
||||
|
||||
/* STM8L15x Low density devices */
|
||||
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
|
||||
#define FLASH_PROGRAM_END_PHYSICAL_ADDRESS ((uint32_t)0x00009FFF) /*!< Flash: end address */
|
||||
#define FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS ((uint32_t)0x000010FF) /*!< Data Eeprom: end address */
|
||||
#define FLASH_PROGRAM_BLOCKS_NUMBER ((uint16_t)0x80) /*!< Flash memory: total number of Block */
|
||||
#define FLASH_DATA_EEPROM_BLOCKS_NUMBER ((uint8_t)0x4) /*!< Data EEprom: total number of Block */
|
||||
#define FLASH_BLOCK_SIZE ((uint8_t)0x40) /*!< Number of bytes in a Block
|
||||
(common for Program and Data EEprom memories) */
|
||||
#endif /* STM8L15X_HD or STM8L05X_HD_VL*/
|
||||
|
||||
/*Common defines for all STM8L15x devices */
|
||||
#define FLASH_OPTION_BYTES_START_PHYSICAL_ADDRESS ((uint32_t)0x00004800) /*!< Option bytes: start address */
|
||||
#define FLASH_OPTION_BYTES_END_PHYSICAL_ADDRESS ((uint32_t)0x0000480A) /*!< Option bytes: end address */
|
||||
#define FLASH_RASS_KEY1 ((uint8_t)0x56) /*!< First RASS key */
|
||||
#define FLASH_RASS_KEY2 ((uint8_t)0xAE) /*!< Second RASS key */
|
||||
#define FLASH_READOUTPROTECTION_KEY ((uint8_t)0xAA) /*!< Read out protection key */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Memory_Type
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_MemType_Program = (uint8_t)0xFD, /*!< Program memory */
|
||||
FLASH_MemType_Data = (uint8_t)0xF7 /*!< Data EEPROM memory */
|
||||
} FLASH_MemType_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Programming_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_ProgramMode_Standard = (uint8_t)0x00, /*!< Standard programming mode */
|
||||
FLASH_ProgramMode_Fast = (uint8_t)0x10 /*!< Fast programming mode */
|
||||
} FLASH_ProgramMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Programming_Time
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_ProgramTime_Standard = (uint8_t)0x00, /*!< Standard programming time fixed at 1/2 tprog */
|
||||
FLASH_ProgramTime_TProg = (uint8_t)0x01 /*!< Programming time fixed at tprog */
|
||||
} FLASH_ProgramTime_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Power_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_Power_IDDQ = (uint8_t)0x00, /*!< Flash program and data EEPROM in IDDQ */
|
||||
FLASH_Power_On = (uint8_t)0x01 /*!< Flash program and data EEPROM not in IDDQ */
|
||||
} FLASH_Power_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Status
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_Status_Write_Protection_Error = (uint8_t)0x01, /*!< Write attempted to protected Block */
|
||||
FLASH_Status_TimeOut = (uint8_t)0x02, /*!< Time out error */
|
||||
FLASH_Status_Successful_Operation = (uint8_t)0x04 /*!< End of operation flag */
|
||||
} FLASH_Status_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Power_Status
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_PowerStatus_IDDQDuringWaitMode = (uint8_t)0x04, /*!< Flash program and data EEPROM
|
||||
in IDDQ during Wait mode*/
|
||||
FLASH_PowerStatus_IDDQDuringRunMode = (uint8_t)0x08, /*!< Flash program and data EEPROM
|
||||
in IDDQ mode during Run mode*/
|
||||
FLASH_PowerStatus_IDDQDuringWaitAndRunModes = (uint8_t)0x0C, /*!<Flash program and data EEPROM
|
||||
in IDDQ during Wait and run modes*/
|
||||
FLASH_PowerStatus_On = (uint8_t)0x00 /*!< Flash program and data EEPROM
|
||||
is powered on during Wait and Run modes */
|
||||
} FLASH_PowerStatus_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
FLASH_FLAG_HVOFF = (uint8_t)0x40, /*!< End of high voltage flag */
|
||||
FLASH_FLAG_DUL = (uint8_t)0x08, /*!< Data EEPROM unlocked flag */
|
||||
FLASH_FLAG_EOP = (uint8_t)0x04, /*!< End of programming (write or erase operation) flag */
|
||||
FLASH_FLAG_PUL = (uint8_t)0x02, /*!< Flash Program memory unlocked flag */
|
||||
FLASH_FLAG_WR_PG_DIS = (uint8_t)0x01 /*!< Write attempted to protected page flag */
|
||||
} FLASH_FLAG_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* sensitivity values for the flash Address
|
||||
*/
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(Address) (((Address) >= FLASH_PROGRAM_START_PHYSICAL_ADDRESS) && \
|
||||
((Address) <= FLASH_PROGRAM_END_PHYSICAL_ADDRESS))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* sensitivity values for the data Eeprom Address
|
||||
*/
|
||||
|
||||
#define IS_FLASH_DATA_EEPROM_ADDRESS(Address) (((Address) >= FLASH_DATA_EEPROM_START_PHYSICAL_ADDRESS) && \
|
||||
((Address) <= FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* sensitivity values for the data eeprom and flash program Address
|
||||
*/
|
||||
#define IS_FLASH_ADDRESS(Address)((((Address) >= FLASH_PROGRAM_START_PHYSICAL_ADDRESS) && ((Address) <= FLASH_PROGRAM_END_PHYSICAL_ADDRESS)) || \
|
||||
(((Address) >= FLASH_DATA_EEPROM_START_PHYSICAL_ADDRESS) && ((Address) <= FLASH_DATA_EEPROM_END_PHYSICAL_ADDRESS)))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* sensitivity values for the option bytes Address
|
||||
*/
|
||||
#define IS_OPTION_BYTE_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OPTION_BYTES_START_PHYSICAL_ADDRESS) && \
|
||||
((ADDRESS) <= FLASH_OPTION_BYTES_END_PHYSICAL_ADDRESS))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* sensitivity values for the flash Block number
|
||||
*/
|
||||
#define IS_FLASH_PROGRAM_BLOCK_NUMBER(BlockNum) ((BlockNum) < FLASH_PROGRAM_BLOCKS_NUMBER)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* sensitivity values for the data eeprom Block number
|
||||
*/
|
||||
#define IS_FLASH_DATA_EEPROM_BLOCK_NUMBER(BlockNum) ((BlockNum) < FLASH_DATA_EEPROM_BLOCKS_NUMBER)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* sensitivity values for the flash memory type
|
||||
*/
|
||||
#define IS_FLASH_MEMORY_TYPE(MemType) (((MemType) == FLASH_MemType_Program) || \
|
||||
((MemType) == FLASH_MemType_Data))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* sensitivity values for the flash program block mode
|
||||
*/
|
||||
#define IS_FLASH_PROGRAM_MODE(Mode) (((Mode) == FLASH_ProgramMode_Standard) || \
|
||||
((Mode) == FLASH_ProgramMode_Fast))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the program time mode
|
||||
*/
|
||||
#define IS_FLASH_PROGRAM_TIME(Time) (((Time) == FLASH_ProgramTime_Standard) || \
|
||||
((Time) == FLASH_ProgramTime_TProg))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the power mode
|
||||
*/
|
||||
#define IS_FLASH_POWER(Power) (((Power) == FLASH_Power_IDDQ) || \
|
||||
((Power) == FLASH_Power_On))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the power status during wait and run modes
|
||||
*/
|
||||
#define IS_FLASH_POWERSTATUS(PowerStatus) (((PowerStatus) == FLASH_PowerStatus_IDDQDuringWaitMode) || \
|
||||
((PowerStatus) == FLASH_PowerStatus_IDDQDuringRunMode ) || \
|
||||
((PowerStatus) == FLASH_PowerStatus_IDDQDuringWaitAndRunModes) || \
|
||||
((PowerStatus) == FLASH_Power_On))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different flags values
|
||||
*/
|
||||
#define IS_FLASH_FLAGS(FLAG) (((FLAG) == FLASH_FLAG_HVOFF) || \
|
||||
((FLAG) == FLASH_FLAG_DUL) || \
|
||||
((FLAG) == FLASH_FLAG_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_PUL) || \
|
||||
((FLAG) == FLASH_FLAG_WR_PG_DIS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* FLASH program and Data EEPROM memories interface configuration functions ***/
|
||||
FLASH_ProgramTime_TypeDef FLASH_GetProgrammingTime(void);
|
||||
void FLASH_SetProgrammingTime(FLASH_ProgramTime_TypeDef FLASH_ProgTime);
|
||||
void FLASH_PowerWaitModeConfig(FLASH_Power_TypeDef FLASH_Power);
|
||||
|
||||
/* FLASH program and Data EEPROM memories Programming functions ***************/
|
||||
void FLASH_DeInit(void);
|
||||
void FLASH_Unlock(FLASH_MemType_TypeDef FLASH_MemType);
|
||||
void FLASH_Lock(FLASH_MemType_TypeDef FLASH_MemType);
|
||||
void FLASH_ProgramByte(uint32_t Address, uint8_t Data);
|
||||
void FLASH_EraseByte(uint32_t Address);
|
||||
void FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
uint8_t FLASH_ReadByte(uint32_t Address);
|
||||
|
||||
/* Option Bytes Programming functions *****************************************/
|
||||
uint16_t FLASH_GetBootSize(void);
|
||||
uint16_t FLASH_GetCodeSize(void);
|
||||
FunctionalState FLASH_GetReadOutProtectionStatus(void);
|
||||
void FLASH_ProgramOptionByte(uint16_t Address, uint8_t Data);
|
||||
void FLASH_EraseOptionByte(uint16_t Address);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void FLASH_ITConfig(FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(FLASH_FLAG_TypeDef FLASH_FLAG);
|
||||
|
||||
/* Functions to be executed from RAM ******************************************/
|
||||
|
||||
/**
|
||||
@code
|
||||
All the functions declared below must be executed from RAM exclusively, except
|
||||
for the FLASH_WaitForLastOperation function which can be executed from Flash.
|
||||
|
||||
Steps of the execution from RAM differs from one toolchain to another.
|
||||
for more details refer to stm8l15x_flash.c file.
|
||||
|
||||
To enable execution from RAM you can either uncomment the following define
|
||||
in the stm8s.h file or define it in your toolchain compiler preprocessor
|
||||
- #define RAM_EXECUTION (1)
|
||||
|
||||
@endcode
|
||||
*/
|
||||
|
||||
IN_RAM(void FLASH_PowerRunModeConfig(FLASH_Power_TypeDef FLASH_Power));
|
||||
IN_RAM(FLASH_PowerStatus_TypeDef FLASH_GetPowerStatus(void));
|
||||
|
||||
IN_RAM(void FLASH_ProgramBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType,
|
||||
FLASH_ProgramMode_TypeDef FLASH_ProgMode, uint8_t *Buffer));
|
||||
IN_RAM(void FLASH_EraseBlock(uint16_t BlockNum, FLASH_MemType_TypeDef FLASH_MemType));
|
||||
|
||||
IN_RAM(FLASH_Status_TypeDef FLASH_WaitForLastOperation(FLASH_MemType_TypeDef FLASH_MemType));
|
||||
|
||||
#endif /*__STM8L15x_FLASH_H*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
179
firmware/inc/stm8l151x/inc/stm8l15x_gpio.h
Normal file
179
firmware/inc/stm8l151x/inc/stm8l15x_gpio.h
Normal file
@@ -0,0 +1,179 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the GPIO firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_GPIO_H
|
||||
#define __STM8L15x_GPIO_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup GPIO_Modes
|
||||
*
|
||||
* @brief
|
||||
*
|
||||
* Bits definitions:
|
||||
* - Bit 7: 0 = INPUT mode
|
||||
* 1 = OUTPUT mode
|
||||
* 1 = PULL-UP (input) or PUSH-PULL (output)
|
||||
* - Bit 5: 0 = No external interrupt (input) or No slope control (output)
|
||||
* 1 = External interrupt (input) or Slow control enabled (output)
|
||||
* - Bit 4: 0 = Low level (output)
|
||||
* 1 = High level (output push-pull) or HI-Z (output open-drain)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_In_FL_No_IT = (uint8_t)0x00, /*!< Input floating, no external interrupt */
|
||||
GPIO_Mode_In_PU_No_IT = (uint8_t)0x40, /*!< Input pull-up, no external interrupt */
|
||||
GPIO_Mode_In_FL_IT = (uint8_t)0x20, /*!< Input floating, external interrupt */
|
||||
GPIO_Mode_In_PU_IT = (uint8_t)0x60, /*!< Input pull-up, external interrupt */
|
||||
GPIO_Mode_Out_OD_Low_Fast = (uint8_t)0xA0, /*!< Output open-drain, low level, 10MHz */
|
||||
GPIO_Mode_Out_PP_Low_Fast = (uint8_t)0xE0, /*!< Output push-pull, low level, 10MHz */
|
||||
GPIO_Mode_Out_OD_Low_Slow = (uint8_t)0x80, /*!< Output open-drain, low level, 2MHz */
|
||||
GPIO_Mode_Out_PP_Low_Slow = (uint8_t)0xC0, /*!< Output push-pull, low level, 2MHz */
|
||||
GPIO_Mode_Out_OD_HiZ_Fast = (uint8_t)0xB0, /*!< Output open-drain, high-impedance level, 10MHz */
|
||||
GPIO_Mode_Out_PP_High_Fast = (uint8_t)0xF0, /*!< Output push-pull, high level, 10MHz */
|
||||
GPIO_Mode_Out_OD_HiZ_Slow = (uint8_t)0x90, /*!< Output open-drain, high-impedance level, 2MHz */
|
||||
GPIO_Mode_Out_PP_High_Slow = (uint8_t)0xD0 /*!< Output push-pull, high level, 2MHz */
|
||||
}GPIO_Mode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Pin
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Pin_0 = ((uint8_t)0x01), /*!< Pin 0 selected */
|
||||
GPIO_Pin_1 = ((uint8_t)0x02), /*!< Pin 1 selected */
|
||||
GPIO_Pin_2 = ((uint8_t)0x04), /*!< Pin 2 selected */
|
||||
GPIO_Pin_3 = ((uint8_t)0x08), /*!< Pin 3 selected */
|
||||
GPIO_Pin_4 = ((uint8_t)0x10), /*!< Pin 4 selected */
|
||||
GPIO_Pin_5 = ((uint8_t)0x20), /*!< Pin 5 selected */
|
||||
GPIO_Pin_6 = ((uint8_t)0x40), /*!< Pin 6 selected */
|
||||
GPIO_Pin_7 = ((uint8_t)0x80), /*!< Pin 7 selected */
|
||||
GPIO_Pin_LNib = ((uint8_t)0x0F), /*!< Low nibble pins selected */
|
||||
GPIO_Pin_HNib = ((uint8_t)0xF0), /*!< High nibble pins selected */
|
||||
GPIO_Pin_All = ((uint8_t)0xFF) /*!< All pins selected */
|
||||
}GPIO_Pin_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different functions parameters.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* values of GPIOMode_TypeDef.
|
||||
*/
|
||||
#define IS_GPIO_MODE(MODE) \
|
||||
(((MODE) == GPIO_Mode_In_FL_No_IT) || \
|
||||
((MODE) == GPIO_Mode_In_PU_No_IT) || \
|
||||
((MODE) == GPIO_Mode_In_FL_IT) || \
|
||||
((MODE) == GPIO_Mode_In_PU_IT) || \
|
||||
((MODE) == GPIO_Mode_Out_OD_Low_Fast) || \
|
||||
((MODE) == GPIO_Mode_Out_PP_Low_Fast) || \
|
||||
((MODE) == GPIO_Mode_Out_OD_Low_Slow) || \
|
||||
((MODE) == GPIO_Mode_Out_PP_Low_Slow) || \
|
||||
((MODE) == GPIO_Mode_Out_OD_HiZ_Fast) || \
|
||||
((MODE) == GPIO_Mode_Out_PP_High_Fast) || \
|
||||
((MODE) == GPIO_Mode_Out_OD_HiZ_Slow) || \
|
||||
((MODE) == GPIO_Mode_Out_PP_High_Slow))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* values of GPIO_Pins.
|
||||
*/
|
||||
#define IS_GPIO_PIN(PIN) ((PIN) != (uint8_t)0x00)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Initialization and Configuration *******************************************/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode);
|
||||
void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, FunctionalState NewState);
|
||||
|
||||
/* GPIO Read and Write ********************************************************/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t GPIO_PortVal);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction GPIO_BitVal);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin);
|
||||
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin);
|
||||
uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
BitStatus GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
|
||||
BitStatus GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin);
|
||||
|
||||
#endif /* __STM8L15x_GPIO_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
809
firmware/inc/stm8l151x/inc/stm8l15x_i2c.h
Normal file
809
firmware/inc/stm8l151x/inc/stm8l15x_i2c.h
Normal file
@@ -0,0 +1,809 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the I2C firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_I2C_H
|
||||
#define __STM8L15x_I2C_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup I2C_mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_Mode_I2C = (uint8_t)0x00, /*!< I2C mode */
|
||||
I2C_Mode_SMBusDevice = (uint8_t)0x02, /*!< SMBus Device mode */
|
||||
I2C_Mode_SMBusHost = (uint8_t)0x0A /*!< SMBus Host mode */
|
||||
} I2C_Mode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_duty_cycle_in_fast_mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_DutyCycle_2 = (uint8_t)0x00, /*!< Fast mode Tlow/THigh = 2 */
|
||||
I2C_DutyCycle_16_9 = (uint8_t)0x40 /*!< Fast mode Tlow/Thigh = 16/9 */
|
||||
} I2C_DutyCycle_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledgement
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_Ack_Disable = (uint8_t)0x00, /*!< No acknowledge */
|
||||
I2C_Ack_Enable = (uint8_t)0x04 /*!< Acknowledge Enabled */
|
||||
} I2C_Ack_TypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Position_Acknowledgement
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_AckPosition_Current = (uint8_t)0x00, /*!< Acknowledge on the current byte */
|
||||
I2C_AckPosition_Next = (uint8_t)0x08 /*!< Acknowledge on the next byte */
|
||||
} I2C_AckPosition_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledged_address
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_AcknowledgedAddress_7bit = (uint8_t)0x00, /*!< 7-bit slave address (10-bit address not acknowledged) */
|
||||
I2C_AcknowledgedAddress_10bit = (uint8_t)0x80 /*!< 10-bit slave address (7-bit address not acknowledged) */
|
||||
} I2C_AcknowledgedAddress_TypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* Warning: the values correspond to the ADD0 bit position in the OARL register
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_Direction_Transmitter = (uint8_t)0x00, /*!< Transmission direction */
|
||||
I2C_Direction_Receiver = (uint8_t)0x01 /*!< Reception direction */
|
||||
} I2C_Direction_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_SMBus_alert_pin_level
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_SMBusAlert_High = (uint8_t)0x00, /*!< SMBAlert pin high */
|
||||
I2C_SMBusAlert_Low = (uint8_t)0x01 /*!< SMBAlert pin Low */
|
||||
} I2C_SMBusAlert_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_PEC_position
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_PECPosition_Current = (uint8_t)0x00, /*!< Current byte in shift register is PEC */
|
||||
I2C_PECPosition_Next = (uint8_t)0x08 /*!< Next byte in shift register is PEC */
|
||||
} I2C_PECPosition_TypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Elements values convention: 0xXXYY
|
||||
* X = SRx registers index
|
||||
* X = 1 : SR1
|
||||
* X = 2 : SR2
|
||||
* X = 3 : SR3
|
||||
* Y = Flag mask in the register
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
/* SR1 register flags */
|
||||
I2C_FLAG_TXE = (uint16_t)0x0180, /*!< Transmit Data Register Empty flag */
|
||||
I2C_FLAG_RXNE = (uint16_t)0x0140, /*!< Read Data Register Not Empty flag */
|
||||
I2C_FLAG_STOPF = (uint16_t)0x0110, /*!< Stop detected flag */
|
||||
I2C_FLAG_ADD10 = (uint16_t)0x0108, /*!< 10-bit Header sent flag */
|
||||
I2C_FLAG_BTF = (uint16_t)0x0104, /*!< Data Byte Transfer Finished flag */
|
||||
I2C_FLAG_ADDR = (uint16_t)0x0102, /*!< Address Sent/Matched (master/slave) flag */
|
||||
I2C_FLAG_SB = (uint16_t)0x0101, /*!< Start bit sent flag */
|
||||
|
||||
/* SR2 register flags */
|
||||
I2C_FLAG_SMBALERT = (uint16_t)0x0280, /*!< SMBUS Alert flag */
|
||||
I2C_FLAG_TIMEOUT = (uint16_t)0x0240, /*!< Time out flag */
|
||||
I2C_FLAG_WUFH = (uint16_t)0x0220, /*!< Wake Up From Halt flag */
|
||||
I2C_FLAG_PECERR = (uint16_t)0x0210, /*!< PEC error flag */
|
||||
I2C_FLAG_OVR = (uint16_t)0x0208, /*!< Overrun/Underrun flag */
|
||||
I2C_FLAG_AF = (uint16_t)0x0204, /*!< Acknowledge Failure flag */
|
||||
I2C_FLAG_ARLO = (uint16_t)0x0202, /*!< Arbitration Loss flag */
|
||||
I2C_FLAG_BERR = (uint16_t)0x0201, /*!< Misplaced Start or Stop condition */
|
||||
|
||||
/* SR3 register flags */
|
||||
I2C_FLAG_DUALF = (uint16_t)0x0380, /*!< DUAL Flag */
|
||||
I2C_FLAG_SMBHOST = (uint16_t)0x0340, /*!< SMBUS host Flag */
|
||||
I2C_FLAG_SMBDEFAULT = (uint16_t)0x0320, /*!< SMBUS default flag */
|
||||
I2C_FLAG_GENCALL = (uint16_t)0x0310, /*!< General Call header received Flag */
|
||||
I2C_FLAG_TRA = (uint16_t)0x0304, /*!< Transmitter Receiver flag */
|
||||
I2C_FLAG_BUSY = (uint16_t)0x0302, /*!< Bus Busy flag */
|
||||
I2C_FLAG_MSL = (uint16_t)0x0301 /*!< Master Slave flag */
|
||||
} I2C_FLAG_TypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2C Pending bits
|
||||
* Elements values convention: 0xXYZZ
|
||||
* X = SRx registers index
|
||||
* X = 0 : ITR
|
||||
* X = 1 : SR1
|
||||
* X = 2 : SR2
|
||||
* Y = Position of the corresponding Interrupt
|
||||
* ZZ = flag mask in the dedicated register(X register)
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_IT_ERR = (uint16_t)0x0001, /*!< Error Interruption */
|
||||
I2C_IT_EVT = (uint16_t)0x0002, /*!< Event Interruption */
|
||||
I2C_IT_BUF = (uint16_t)0x0004, /*!< Buffer Interruption */
|
||||
/* SR1 register*/
|
||||
I2C_IT_TXE = (uint16_t)0x1680, /*!< Transmit Data Register Empty */
|
||||
I2C_IT_RXNE = (uint16_t)0x1640, /*!< Read Data Register Not Empty */
|
||||
I2C_IT_STOPF = (uint16_t)0x1210, /*!< Stop detected */
|
||||
I2C_IT_ADD10 = (uint16_t)0x1208, /*!< 10-bit Header sent */
|
||||
I2C_IT_BTF = (uint16_t)0x1204, /*!< Data Byte Transfer Finished */
|
||||
I2C_IT_ADDR = (uint16_t)0x1202, /*!< Address Sent/Matched (master/slave) */
|
||||
I2C_IT_SB = (uint16_t)0x1201, /*!< Start bit sent */
|
||||
|
||||
/* SR2 register*/
|
||||
I2C_IT_SMBALERT = (uint16_t)0x2180, /*!< SMBUS alert */
|
||||
I2C_IT_TIMEOUT = (uint16_t)0x2140, /*!< Time out */
|
||||
I2C_IT_WUFH = (uint16_t)0x2220, /*!< PEC error */
|
||||
I2C_IT_PECERR = (uint16_t)0x2110, /*!< Wake Up From Halt */
|
||||
I2C_IT_OVR = (uint16_t)0x2108, /*!< Overrun/Underrun */
|
||||
I2C_IT_AF = (uint16_t)0x2104, /*!< Acknowledge Failure */
|
||||
I2C_IT_ARLO = (uint16_t)0x2102, /*!< Arbitration Loss */
|
||||
I2C_IT_BERR = (uint16_t)0x2101 /*!< Misplaced Start or Stop condition */
|
||||
} I2C_IT_TypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Events
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2C possible events
|
||||
* Values convention: 0xXXYY
|
||||
* XX = Event SR3 corresponding value
|
||||
* YY = Event SR1 corresponding value
|
||||
* @note if Event = EV3_2 the rule above does not apply
|
||||
* YY = Event SR2 corresponding value
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
/**
|
||||
===============================================================================
|
||||
I2C Master Events (Events grouped in order of communication)
|
||||
===============================================================================
|
||||
*/
|
||||
/**
|
||||
* @brief Communication start
|
||||
*
|
||||
* After sending the START condition (I2C_GenerateSTART() function) the master
|
||||
* has to wait for this event. It means that the Start condition has been correctly
|
||||
* released on the I2C bus (the bus is free, no other devices is communicating).
|
||||
*
|
||||
*/
|
||||
/* --EV5 */
|
||||
I2C_EVENT_MASTER_MODE_SELECT = (uint16_t)0x0301, /*!< BUSY, MSL and SB flag */
|
||||
|
||||
/**
|
||||
* @brief Address Acknowledge
|
||||
*
|
||||
* After checking on EV5 (start condition correctly released on the bus), the
|
||||
* master sends the address of the slave(s) with which it will communicate
|
||||
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
|
||||
* Master transmitter or Receiver).
|
||||
* Then the master has to wait that a slave acknowledges his address.
|
||||
* If an acknowledge is sent on the bus, one of the following events will
|
||||
* be set:
|
||||
*
|
||||
* 1) In case of Master Receiver (7-bit addressing):
|
||||
* the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set.
|
||||
*
|
||||
* 2) In case of Master Transmitter (7-bit addressing):
|
||||
* the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set
|
||||
*
|
||||
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
|
||||
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
|
||||
* function).
|
||||
* Then master should wait on EV9. It means that the 10-bit addressing
|
||||
* header has been correctly sent on the bus.
|
||||
* Then master should send the second part of the 10-bit address (LSB) using
|
||||
* the function I2C_Send7bitAddress(). Then master should wait for event EV6.
|
||||
*
|
||||
*/
|
||||
/* --EV6 */
|
||||
I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782, /*!< BUSY, MSL, ADDR, TXE and TRA flags */
|
||||
I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = (uint16_t)0x0302, /*!< BUSY, MSL and ADDR flags */
|
||||
/* --EV9 */
|
||||
I2C_EVENT_MASTER_MODE_ADDRESS10 = (uint16_t)0x0308, /*!< BUSY, MSL and ADD10 flags */
|
||||
|
||||
/**
|
||||
* @brief Communication events
|
||||
*
|
||||
* If a communication is established (START condition generated and slave address
|
||||
* acknowledged) then the master has to check on one of the following events for
|
||||
* communication procedures:
|
||||
*
|
||||
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
|
||||
* the data received from the slave (I2C_ReceiveData() function).
|
||||
*
|
||||
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
|
||||
* function) then to wait on event EV8 or EV8_2.
|
||||
* These two events are similar:
|
||||
* - EV8 means that the data has been written in the data register and is
|
||||
* being shifted out.
|
||||
* - EV8_2 means that the data has been physically shifted out and output
|
||||
* on the bus.
|
||||
* In most cases, using EV8 is sufficient for the application.
|
||||
* Using EV8_2 leads to a slower communication but ensure more reliable test.
|
||||
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
|
||||
* (before Stop condition generation).
|
||||
*
|
||||
* @note In case the user software does not guarantee that this event EV7 is
|
||||
* managed before the current byte end of transfer, then user may check on EV7
|
||||
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
||||
* In this case the communication may be slower.
|
||||
*
|
||||
*/
|
||||
/* Master RECEIVER mode -----------------------------*/
|
||||
/* --EV7 */
|
||||
I2C_EVENT_MASTER_BYTE_RECEIVED = (uint16_t)0x0340, /*!< BUSY, MSL and RXNE flags */
|
||||
|
||||
/* Master TRANSMITTER mode --------------------------*/
|
||||
/* --EV8 */
|
||||
I2C_EVENT_MASTER_BYTE_TRANSMITTING = (uint16_t)0x0780, /*!< TRA, BUSY, MSL, TXE flags */
|
||||
/* --EV8_2 */
|
||||
|
||||
I2C_EVENT_MASTER_BYTE_TRANSMITTED = (uint16_t)0x0784, /*!< EV8_2: TRA, BUSY, MSL, TXE and BTF flags */
|
||||
|
||||
/**
|
||||
===============================================================================
|
||||
I2C Slave Events (Events grouped in order of communication)
|
||||
===============================================================================
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Communication start events
|
||||
*
|
||||
* Wait on one of these events at the start of the communication. It means that
|
||||
* the I2C peripheral detected a Start condition on the bus (generated by master
|
||||
* device) followed by the peripheral address.
|
||||
* The peripheral generates an ACK condition on the bus (if the acknowledge
|
||||
* feature is enabled through function I2C_AcknowledgeConfig()) and the events
|
||||
* listed above are set :
|
||||
*
|
||||
* 1) In normal case (only one address managed by the slave), when the address
|
||||
* sent by the master matches the own address of the peripheral (configured by
|
||||
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
||||
* (where XXX could be TRANSMITTER or RECEIVER).
|
||||
*
|
||||
* 2) In case the address sent by the master matches the second address of the
|
||||
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
|
||||
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
||||
* (where XXX could be TRANSMITTER or RECEIVER) are set.
|
||||
*
|
||||
* 3) In case the address sent by the master is General Call (address 0x00) and
|
||||
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
|
||||
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
|
||||
*
|
||||
*/
|
||||
|
||||
/* --EV1 (all the events below are variants of EV1) */
|
||||
/* 1) Case of One Single Address managed by the slave */
|
||||
I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = (uint16_t)0x0202, /*!< BUSY and ADDR flags */
|
||||
I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682, /*!< TRA, BUSY, TXE and ADDR flags */
|
||||
|
||||
/* 2) Case of Dual address managed by the slave */
|
||||
I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED = (uint16_t)0x8200, /*! DUALF and BUSY flags */
|
||||
I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED = (uint16_t)0x8680, /*! DUALF, TRA, BUSY and TXE flags */
|
||||
|
||||
/* 3) Case of General Call enabled for the slave */
|
||||
I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = (uint16_t)0x1200, /*!< EV2: GENCALL and BUSY flags */
|
||||
|
||||
/**
|
||||
* @brief Communication events
|
||||
*
|
||||
* Wait on one of these events when EV1 has already been checked :
|
||||
*
|
||||
* - Slave RECEIVER mode:
|
||||
* - EV2: When the application is expecting a data byte to be received.
|
||||
* - EV4: When the application is expecting the end of the communication:
|
||||
* master sends a stop condition and data transmission is stopped.
|
||||
*
|
||||
* - Slave Transmitter mode:
|
||||
* - EV3: When a byte has been transmitted by the slave and the application
|
||||
* is expecting the end of the byte transmission.
|
||||
* The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING
|
||||
* are similar. The second one can optionally be used when the user software
|
||||
* doesn't guarantee the EV3 is managed before the current byte end of transfer.
|
||||
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
|
||||
* shall end (before sending the STOP condition).
|
||||
* In this case slave has to stop sending data bytes and expect a Stop
|
||||
* condition on the bus.
|
||||
*
|
||||
* @note In case the user software does not guarantee that the event EV2 is
|
||||
* managed before the current byte end of transfer, then user may check on EV2
|
||||
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
||||
* In this case the communication may be slower.
|
||||
*
|
||||
*/
|
||||
/* Slave RECEIVER mode --------------------------*/
|
||||
/* --EV2 */
|
||||
I2C_EVENT_SLAVE_BYTE_RECEIVED = (uint16_t)0x0240, /*!< BUSY and RXNE flags */
|
||||
/* --EV4 */
|
||||
I2C_EVENT_SLAVE_STOP_DETECTED = (uint16_t)0x0010, /*!< STOPF flag */
|
||||
|
||||
/* Slave TRANSMITTER mode -----------------------*/
|
||||
/* --EV3 */
|
||||
I2C_EVENT_SLAVE_BYTE_TRANSMITTED = (uint16_t)0x0684, /*!< TRA, BUSY, TXE and BTF flags */
|
||||
I2C_EVENT_SLAVE_BYTE_TRANSMITTING = (uint16_t)0x0680, /*!< TRA, BUSY and TXE flags */
|
||||
/* --EV3_2 */
|
||||
I2C_EVENT_SLAVE_ACK_FAILURE = (uint16_t)0x0004 /*!< AF flag */
|
||||
} I2C_Event_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Registers
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_Register_CR1 = (uint8_t)0x00, /*!< Control register 1 */
|
||||
I2C_Register_CR2 = (uint8_t)0x01, /*!< Control register 2 */
|
||||
I2C_Register_FREQR = (uint8_t)0x02, /*!< Frequency register */
|
||||
I2C_Register_OARL = (uint8_t)0x03, /*!< Own address register LSB */
|
||||
I2C_Register_OARH = (uint8_t)0x04, /*!< Own address register MSB */
|
||||
I2C_Register_DR = (uint8_t)0x06, /*!< Data register */
|
||||
I2C_Register_SR1 = (uint8_t)0x07, /*!< Status register 1 */
|
||||
I2C_Register_SR2 = (uint8_t)0x08, /*!< Status register 2 */
|
||||
I2C_Register_SR3 = (uint8_t)0x09, /*!< Status register 3 */
|
||||
I2C_Register_ITR = (uint8_t)0x0A, /*!< Interrupt and DMA register */
|
||||
I2C_Register_CCRL = (uint8_t)0x0B, /*!< Clock control register low */
|
||||
I2C_Register_CCRH = (uint8_t)0x0C, /*!< Clock control register high */
|
||||
I2C_Register_TRISER = (uint8_t)0x0D, /*!< TRISE register */
|
||||
I2C_Register_PECR = (uint8_t)0x0E /*!< PEC register */
|
||||
} I2C_Register_TypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MAX_STANDARD_FREQ ((uint32_t)100000)
|
||||
#define I2C_MAX_FAST_FREQ ((uint32_t)400000)
|
||||
|
||||
/**
|
||||
*@}
|
||||
*/
|
||||
|
||||
/* Exported macro -----------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different functions parameters.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C modes.
|
||||
*/
|
||||
#define IS_I2C_MODE(MODE)(((MODE) == I2C_Mode_I2C) || \
|
||||
((MODE) == I2C_Mode_SMBusDevice) || \
|
||||
((MODE) == I2C_Mode_SMBusHost))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C duty cycles.
|
||||
*/
|
||||
#define IS_I2C_DUTY_CYCLE(CYCLE)(((CYCLE) == I2C_DutyCycle_2) || \
|
||||
((CYCLE) == I2C_DutyCycle_16_9))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different acknowledgement configuration
|
||||
*/
|
||||
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Disable) || \
|
||||
((STATE) == I2C_Ack_Enable))
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different acknowledgement position
|
||||
*/
|
||||
#define IS_I2C_ACK_POSITION(POSITION) (((POSITION) == I2C_AckPosition_Next) || \
|
||||
((POSITION) == I2C_AckPosition_Current))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C PEC positions.
|
||||
*/
|
||||
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Current) || \
|
||||
((POSITION) == I2C_PECPosition_Next))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C addressing modes.
|
||||
*/
|
||||
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDMODE) (((ADDMODE) == I2C_AcknowledgedAddress_7bit) || \
|
||||
((ADDMODE) == I2C_AcknowledgedAddress_10bit))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C SMBus Alert pin configuration.
|
||||
*/
|
||||
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_High) || \
|
||||
((ALERT) == I2C_SMBusAlert_Low))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C communication direction.
|
||||
*/
|
||||
#define IS_I2C_DIRECTION(DIR)(((DIR) == I2C_Direction_Transmitter) || \
|
||||
((DIR) == I2C_Direction_Receiver ))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C flags.
|
||||
*/
|
||||
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || \
|
||||
((FLAG) == I2C_FLAG_RXNE) || \
|
||||
((FLAG) == I2C_FLAG_STOPF) || \
|
||||
((FLAG) == I2C_FLAG_ADD10) || \
|
||||
((FLAG) == I2C_FLAG_BTF) || \
|
||||
((FLAG) == I2C_FLAG_ADDR) || \
|
||||
((FLAG) == I2C_FLAG_SB) || \
|
||||
((FLAG) == I2C_FLAG_SMBALERT) || \
|
||||
((FLAG) == I2C_FLAG_TIMEOUT) || \
|
||||
((FLAG) == I2C_FLAG_WUFH) || \
|
||||
((FLAG) == I2C_FLAG_PECERR) || \
|
||||
((FLAG) == I2C_FLAG_OVR) || \
|
||||
((FLAG) == I2C_FLAG_AF) || \
|
||||
((FLAG) == I2C_FLAG_ARLO) || \
|
||||
((FLAG) == I2C_FLAG_BERR) || \
|
||||
((FLAG) == I2C_FLAG_DUALF) || \
|
||||
((FLAG) == I2C_FLAG_SMBHOST) || \
|
||||
((FLAG) == I2C_FLAG_SMBDEFAULT) || \
|
||||
((FLAG) == I2C_FLAG_GENCALL) || \
|
||||
((FLAG) == I2C_FLAG_TRA) || \
|
||||
((FLAG) == I2C_FLAG_BUSY) || \
|
||||
((FLAG) == I2C_FLAG_MSL))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the I2C flags to clear.
|
||||
*/
|
||||
#define IS_I2C_CLEAR_FLAG(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xFD00) == 0x00) && ((uint16_t)(FLAG) != 0x00))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the different
|
||||
* sensitivity values for the Interrupts
|
||||
*/
|
||||
#define IS_I2C_CONFIG_IT(IT) ((((uint16_t)(IT) & (uint16_t)0xFFF8) == 0x00) && ((uint16_t)(IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C possible
|
||||
* pending bits to clear by writing 0.
|
||||
*/
|
||||
#define IS_I2C_CLEAR_IT(IT) ((((uint16_t)(IT) & (uint16_t)0xDC00) == 0x00) && ((uint16_t)(IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C possible pending bits.
|
||||
*/
|
||||
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_OVR) ||\
|
||||
((IT) == I2C_IT_AF) ||\
|
||||
((IT) == I2C_IT_ARLO) ||\
|
||||
((IT) == I2C_IT_BERR) ||\
|
||||
((IT) == I2C_IT_TXE) ||\
|
||||
((IT) == I2C_IT_RXNE) ||\
|
||||
((IT) == I2C_IT_STOPF) ||\
|
||||
((IT) == I2C_IT_ADD10) ||\
|
||||
((IT) == I2C_IT_BTF) ||\
|
||||
((IT) == I2C_IT_ADDR) ||\
|
||||
((IT) == I2C_IT_PECERR) ||\
|
||||
((IT) == I2C_IT_TIMEOUT) ||\
|
||||
((IT) == I2C_IT_SMBALERT) ||\
|
||||
((IT) == I2C_IT_WUFH) ||\
|
||||
((IT) == I2C_IT_SB))
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C possible events.
|
||||
*/
|
||||
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_DUALF)) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_GENCALL)) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_DUALF)) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_GENCALL)) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10))
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C registers.
|
||||
*/
|
||||
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
|
||||
((REGISTER) == I2C_Register_CR2) || \
|
||||
((REGISTER) == I2C_Register_FREQR) || \
|
||||
((REGISTER) == I2C_Register_OARL) || \
|
||||
((REGISTER) == I2C_Register_OARH) || \
|
||||
((REGISTER) == I2C_Register_DR) || \
|
||||
((REGISTER) == I2C_Register_SR1) || \
|
||||
((REGISTER) == I2C_Register_SR2) || \
|
||||
((REGISTER) == I2C_Register_SR3) || \
|
||||
((REGISTER) == I2C_Register_ITR) || \
|
||||
((REGISTER) == I2C_Register_CCRL) || \
|
||||
((REGISTER) == I2C_Register_CCRH) || \
|
||||
((REGISTER) == I2C_Register_TRISER) || \
|
||||
((REGISTER) == I2C_Register_PECR))
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C possible own address.
|
||||
*/
|
||||
#define IS_I2C_OWN_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different I2C address
|
||||
* The address must be even
|
||||
*/
|
||||
#define IS_I2C_ADDRESS(ADD) (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.
|
||||
*/
|
||||
#define IS_I2C_OUTPUT_CLOCK_FREQ(FREQ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the I2C configuration to the default reset state *****/
|
||||
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void I2C_Init(I2C_TypeDef* I2Cx, uint32_t OutputClockFrequency, uint16_t OwnAddress,
|
||||
I2C_Mode_TypeDef I2C_Mode, I2C_DutyCycle_TypeDef I2C_DutyCycle,
|
||||
I2C_Ack_TypeDef I2C_Ack, I2C_AcknowledgedAddress_TypeDef I2C_AcknowledgedAddress);
|
||||
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_AckPositionConfig(I2C_TypeDef* I2Cx, I2C_AckPosition_TypeDef I2C_AckPosition);
|
||||
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, I2C_DutyCycle_TypeDef I2C_DutyCycle);
|
||||
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, I2C_SMBusAlert_TypeDef I2C_SMBusAlert);
|
||||
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, I2C_Direction_TypeDef I2C_Direction);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* PEC management functions ***************************************************/
|
||||
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, I2C_PECPosition_TypeDef I2C_PECPosition);
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
|
||||
/* Interrupts, events and flags management functions **************************/
|
||||
|
||||
void I2C_ITConfig(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT, FunctionalState NewState);
|
||||
uint8_t I2C_ReadRegister(I2C_TypeDef* I2Cx, I2C_Register_TypeDef I2C_Register);
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
@verbatim
|
||||
================================================================================
|
||||
I2C State Monitoring Functions
|
||||
================================================================================
|
||||
This I2C driver provides three different ways for I2C state monitoring
|
||||
depending on the application requirements and constraints:
|
||||
|
||||
|
||||
1) Basic state monitoring:
|
||||
Using I2C_CheckEvent() function:
|
||||
It compares the status registers (SR1, SR2 and SR3) content to a given event
|
||||
(can be the combination of one or more flags).
|
||||
It returns SUCCESS if the current status includes the given flags
|
||||
and returns ERROR if one or more flags are missing in the current status.
|
||||
- When to use:
|
||||
- This function is suitable for most applications as well as for startup
|
||||
activity since the events are fully described in the product reference manual
|
||||
(RM0031).
|
||||
- It is also suitable for users who need to define their own events.
|
||||
- Limitations:
|
||||
- If an error occurs (ie. error flags are set besides to the monitored flags),
|
||||
the I2C_CheckEvent() function may return SUCCESS despite the communication
|
||||
hold or corrupted real state.
|
||||
In this case, it is advised to use error interrupts to monitor the error
|
||||
events and handle them in the interrupt IRQ handler.
|
||||
|
||||
@note
|
||||
For error management, it is advised to use the following functions:
|
||||
- I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
|
||||
- I2Cx_IRQHandler() which is called when the I2C interrupts occur.
|
||||
Where x is the peripheral instance (I2C1,...)
|
||||
- I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
|
||||
I2Cx_IRQHandler() function in order to determine which error occurred.
|
||||
- I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
|
||||
and/or I2C_GenerateStop() in order to clear the error flag and
|
||||
source and return to correct communication status.
|
||||
|
||||
|
||||
2) Advanced state monitoring:
|
||||
Using the function I2C_GetLastEvent() which returns the image of both SR1
|
||||
& SR3 status registers in a single word (uint16_t) (Status Register 3 value
|
||||
is shifted left by 8 bits and concatenated to Status Register 1).
|
||||
- When to use:
|
||||
- This function is suitable for the same applications above but it allows to
|
||||
overcome the limitations of I2C_GetFlagStatus() function (see below).
|
||||
The returned value could be compared to events already defined in the
|
||||
library (stm8l15x_i2c.h) or to custom values defined by user.
|
||||
- This function is suitable when multiple flags are monitored at the same time.
|
||||
- At the opposite of I2C_CheckEvent() function, this function allows user to
|
||||
choose when an event is accepted (when all events flags are set and no
|
||||
other flags are set or just when the needed flags are set like
|
||||
I2C_CheckEvent() function).
|
||||
- Limitations:
|
||||
- User may need to define his own events.
|
||||
- Same remark concerning the error management is applicable for this
|
||||
function if user decides to check only regular communication flags (and
|
||||
ignores error flags).
|
||||
|
||||
|
||||
3) Flag-based state monitoring:
|
||||
Using the function I2C_GetFlagStatus() which simply returns the status of
|
||||
one single flag (ie. I2C_FLAG_RXNE ...).
|
||||
- When to use:
|
||||
- This function could be used for specific applications or in debug phase.
|
||||
- It is suitable when only one flag checking is needed (most I2C events
|
||||
are monitored through multiple flags).
|
||||
- Limitations:
|
||||
- When calling this function, the Status register is accessed. Some flags are
|
||||
cleared when the status register is accessed. So checking the status
|
||||
of one Flag, may clear other ones.
|
||||
- Function may need to be called twice or more in order to monitor one
|
||||
single event.
|
||||
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
===============================================================================
|
||||
1. Basic state monitoring
|
||||
===============================================================================
|
||||
*/
|
||||
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, I2C_Event_TypeDef I2C_Event);
|
||||
/**
|
||||
===============================================================================
|
||||
2. Advanced state monitoring
|
||||
===============================================================================
|
||||
*/
|
||||
I2C_Event_TypeDef I2C_GetLastEvent(I2C_TypeDef* I2Cx);
|
||||
/**
|
||||
===============================================================================
|
||||
3. Flag-based state monitoring
|
||||
===============================================================================
|
||||
*/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, I2C_FLAG_TypeDef I2C_FLAG);
|
||||
|
||||
void I2C_ClearFlag(I2C_TypeDef* I2Cx, I2C_FLAG_TypeDef I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT);
|
||||
|
||||
#endif /* __STM8L15x_I2C_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
68
firmware/inc/stm8l151x/inc/stm8l15x_irtim.h
Normal file
68
firmware/inc/stm8l151x/inc/stm8l15x_irtim.h
Normal file
@@ -0,0 +1,68 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_irtim.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the IRTIM firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_IRTIM_H
|
||||
#define __STM8L15x_IRTIM_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRTIM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* IRTIM configuration ********************************************************/
|
||||
void IRTIM_DeInit(void);
|
||||
void IRTIM_Cmd(FunctionalState NewState);
|
||||
void IRTIM_HighSinkODCmd(FunctionalState NewState);
|
||||
|
||||
/* IRITM status management ****************************************************/
|
||||
FunctionalState IRTIM_GetStatus(void);
|
||||
FunctionalState IRTIM_GetHighSinkODStatus(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __STM8L15x_IRTIM_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
272
firmware/inc/stm8l151x/inc/stm8l15x_itc.h
Normal file
272
firmware/inc/stm8l151x/inc/stm8l15x_itc.h
Normal file
@@ -0,0 +1,272 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_itc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the ITC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_ITC_H
|
||||
#define __STM8L15x_ITC_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ITC
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ITC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ITC_Interrupt_Lines_selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
FLASH_IRQn = (uint8_t)1, /*!< Flash interrupt */
|
||||
DMA1_CHANNEL0_1_IRQn = (uint8_t)2, /*!< DMA Channels 0/1 */
|
||||
DMA1_CHANNEL2_3_IRQn = (uint8_t)3, /*!< DMA Channels 2/3 */
|
||||
EXTIE_F_PVD_IRQn = (uint8_t)5, /*!< GPIOE/F and PVD interrupt */
|
||||
EXTI0_IRQn = (uint8_t)8, /*!< PIN0 interrupt */
|
||||
EXTI1_IRQn = (uint8_t)9, /*!< PIN1 interrupt */
|
||||
EXTI2_IRQn = (uint8_t)10, /*!< PIN2 interrupt */
|
||||
EXTI3_IRQn = (uint8_t)11, /*!< PIN3 interrupt */
|
||||
EXTI4_IRQn = (uint8_t)12, /*!< PIN4 interrupt */
|
||||
EXTI5_IRQn = (uint8_t)13, /*!< PIN5 interrupt */
|
||||
EXTI6_IRQn = (uint8_t)14, /*!< PIN6 interrupt */
|
||||
EXTI7_IRQn = (uint8_t)15, /*!< PIN7 interrupt */
|
||||
ADC1_COMP_IRQn = (uint8_t)18, /*!< ADC1/Comparator interrupt */
|
||||
TIM4_UPD_OVF_TRG_IRQn = (uint8_t)25, /*!< TIM4 Update/Overflow/Trigger interrupt */
|
||||
SPI1_IRQn = (uint8_t)26, /*!< SPI1 interrupt */
|
||||
#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
|
||||
RTC_IRQn = (uint8_t)4, /*!< RTC interrupt */
|
||||
EXTIB_IRQn = (uint8_t)6, /*!< GPIOB interrupt */
|
||||
EXTID_IRQn = (uint8_t)7, /*!< GPIOD interrupt */
|
||||
LCD_IRQn = (uint8_t)16, /*!< LCD Driver interrupt */
|
||||
SWITCH_CSS_BREAK_DAC_IRQn = (uint8_t)17, /*!< Clock switch/CSS interrupt/TIM1 Break /DAC interrupt */
|
||||
TIM2_UPD_OVF_TRG_BRK_IRQn = (uint8_t)19, /*!< TIM2 Update/Overflow/Trigger/Break interrupt*/
|
||||
TIM2_CC_IRQn = (uint8_t)20, /*!< TIM2 input captute/output compare interrupt */
|
||||
TIM3_UPD_OVF_TRG_BRK_IRQn = (uint8_t)21, /*!< TIM3 Update/Overflow/Trigger/Break interrupt */
|
||||
TIM3_CC_IRQn = (uint8_t)22, /*!< TIM3 capture/compare interrupt */
|
||||
TIM1_UPD_OVF_TRG_IRQn = (uint8_t)23, /*!< TIM1 TIM1 Update/Overflow/Trigger interrupt */
|
||||
TIM1_CC_IRQn = (uint8_t)24, /*!< TIM1 capture/compare interrupt */
|
||||
USART1_TX_IRQn = (uint8_t)27, /*!< USART1 TX interrupt */
|
||||
USART1_RX_IRQn = (uint8_t)28, /*!< USART1 RX interrupt */
|
||||
I2C1_IRQn = (uint8_t)29 /*!< I2C1 interrupt */
|
||||
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
|
||||
RTC_CSSLSE_IRQn = (uint8_t)4, /*!< RTC / CSSLSE interrupt */
|
||||
EXTIB_IRQn = (uint8_t)6, /*!< GPIOB interrupt */
|
||||
EXTID_IRQn = (uint8_t)7, /*!< GPIOD interrupt */
|
||||
SWITCH_CSS_IRQn = (uint8_t)17, /*!< Clock switch/CSS interrupt/TIM1 Break /DAC interrupt */
|
||||
TIM2_UPD_OVF_TRG_BRK_IRQn = (uint8_t)19, /*!< TIM2 Update/Overflow/Trigger/Break interrupt*/
|
||||
TIM2_CC_IRQn = (uint8_t)20, /*!< TIM2 input captute/output compare interrupt */
|
||||
TIM3_UPD_OVF_TRG_BRK_IRQn = (uint8_t)21, /*!< TIM3 Update/Overflow/Trigger/Break interrupt */
|
||||
TIM3_CC_IRQn = (uint8_t)22, /*!< TIM3 capture/compare interrupt */
|
||||
USART1_TX_IRQn = (uint8_t)27, /*!< USART1 TX interrupt */
|
||||
USART1_RX_IRQn = (uint8_t)28, /*!< USART1 RX interrupt */
|
||||
I2C1_IRQn = (uint8_t)29 /*!< I2C1 interrupt */
|
||||
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
|
||||
RTC_CSSLSE_IRQn = (uint8_t)4, /*!< RTC / CSSLSE interrupt */
|
||||
EXTIB_G_IRQn = (uint8_t)6, /*!< GPIOB / G interrupt */
|
||||
EXTID_H_IRQn = (uint8_t)7, /*!< GPIOD / H interrupt */
|
||||
LCD_AES_IRQn = (uint8_t)16, /*!< LCD / AES interrupt */
|
||||
SWITCH_CSS_BREAK_DAC_IRQn = (uint8_t)17, /*!< Clock switch/CSS interrupt/TIM1 Break /DAC interrupt */
|
||||
TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn = (uint8_t)19, /*!< TIM2 Update/Overflow/Trigger/Break /USART2 TX interrupt*/
|
||||
TIM2_CC_USART2_RX_IRQn = (uint8_t)20, /*!< TIM2 capture/compare / USART2 RX interrupt */
|
||||
TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn = (uint8_t)21, /*!< TIM3 Update/Overflow/Trigger/Break / USART3 TX interrupt */
|
||||
TIM3_CC_USART3_RX_IRQn = (uint8_t)22, /*!< TIM3 capture/compare / USART3 RX interrupt */
|
||||
TIM1_UPD_OVF_TRG_IRQn = (uint8_t)23, /*!< TIM1 TIM1 Update/Overflow/Trigger interrupt */
|
||||
TIM1_CC_IRQn = (uint8_t)24, /*!< TIM1 capture/compare interrupt */
|
||||
USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn = (uint8_t)27, /*!< USART1 TX / TIM5 Update/Overflow/Trigger/Break interrupt */
|
||||
USART1_RX_TIM5_CC_IRQn = (uint8_t)28, /*!< USART1 RX / TIM5 capture/compare interrupt */
|
||||
I2C1_SPI2_IRQn = (uint8_t)29 /*!< I2C1 / SPI2 interrupt */
|
||||
#endif /* STM8L15X_MD */
|
||||
}IRQn_TypeDef;
|
||||
|
||||
#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
|
||||
#define IS_ITC_IRQ(Irq) (((Irq) == FLASH_IRQn) || \
|
||||
((Irq) == DMA1_CHANNEL0_1_IRQn) || \
|
||||
((Irq) == DMA1_CHANNEL2_3_IRQn) || \
|
||||
((Irq) == RTC_IRQn) || \
|
||||
((Irq) == EXTIE_F_PVD_IRQn) || \
|
||||
((Irq) == EXTIB_IRQn) || \
|
||||
((Irq) == EXTID_IRQn) || \
|
||||
((Irq) == EXTI0_IRQn) || \
|
||||
((Irq) == EXTI1_IRQn) || \
|
||||
((Irq) == EXTI2_IRQn) || \
|
||||
((Irq) == EXTI3_IRQn) || \
|
||||
((Irq) == EXTI4_IRQn) || \
|
||||
((Irq) == EXTI5_IRQn) || \
|
||||
((Irq) == EXTI6_IRQn) || \
|
||||
((Irq) == EXTI7_IRQn) || \
|
||||
((Irq) == LCD_IRQn) || \
|
||||
((Irq) == SWITCH_CSS_BREAK_DAC_IRQn) || \
|
||||
((Irq) == ADC1_COMP_IRQn) || \
|
||||
((Irq) == TIM2_UPD_OVF_TRG_BRK_IRQn) || \
|
||||
((Irq) == TIM2_CC_IRQn) || \
|
||||
((Irq) == TIM3_UPD_OVF_TRG_BRK_IRQn) || \
|
||||
((Irq) == TIM3_CC_IRQn) || \
|
||||
((Irq) == TIM1_UPD_OVF_TRG_IRQn) || \
|
||||
((Irq) == TIM1_CC_IRQn) || \
|
||||
((Irq) == TIM4_UPD_OVF_TRG_IRQn) || \
|
||||
((Irq) == SPI1_IRQn) || \
|
||||
((Irq) == USART1_TX_IRQn) || \
|
||||
((Irq) == USART1_RX_IRQn) || \
|
||||
((Irq) == I2C1_IRQn))
|
||||
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
|
||||
#define IS_ITC_IRQ(Irq) (((Irq) == FLASH_IRQn) || \
|
||||
((Irq) == DMA1_CHANNEL0_1_IRQn) || \
|
||||
((Irq) == DMA1_CHANNEL2_3_IRQn) || \
|
||||
((Irq) == RTC_CSSLSE_IRQn) || \
|
||||
((Irq) == EXTIE_F_PVD_IRQn) || \
|
||||
((Irq) == EXTIB_IRQn) || \
|
||||
((Irq) == EXTID_IRQn) || \
|
||||
((Irq) == EXTI0_IRQn) || \
|
||||
((Irq) == EXTI1_IRQn) || \
|
||||
((Irq) == EXTI2_IRQn) || \
|
||||
((Irq) == EXTI3_IRQn) || \
|
||||
((Irq) == EXTI4_IRQn) || \
|
||||
((Irq) == EXTI5_IRQn) || \
|
||||
((Irq) == EXTI6_IRQn) || \
|
||||
((Irq) == EXTI7_IRQn) || \
|
||||
((Irq) == SWITCH_CSS_IRQn) || \
|
||||
((Irq) == ADC1_COMP_IRQn) || \
|
||||
((Irq) == TIM2_UPD_OVF_TRG_BRK_IRQn) || \
|
||||
((Irq) == TIM2_CC_IRQn) || \
|
||||
((Irq) == TIM3_UPD_OVF_TRG_BRK_IRQn) || \
|
||||
((Irq) == TIM3_CC_IRQn) || \
|
||||
((Irq) == TIM4_UPD_OVF_TRG_IRQn) || \
|
||||
((Irq) == SPI1_IRQn) || \
|
||||
((Irq) == USART1_TX_IRQn) || \
|
||||
((Irq) == USART1_RX_IRQn) || \
|
||||
((Irq) == I2C1_IRQn))
|
||||
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
|
||||
#define IS_ITC_IRQ(Irq) (((Irq) == FLASH_IRQn) || \
|
||||
((Irq) == DMA1_CHANNEL0_1_IRQn) || \
|
||||
((Irq) == DMA1_CHANNEL2_3_IRQn) || \
|
||||
((Irq) == RTC_CSSLSE_IRQn) || \
|
||||
((Irq) == EXTIE_F_PVD_IRQn) || \
|
||||
((Irq) == EXTIB_G_IRQn) || \
|
||||
((Irq) == EXTID_H_IRQn) || \
|
||||
((Irq) == EXTI0_IRQn) || \
|
||||
((Irq) == EXTI1_IRQn) || \
|
||||
((Irq) == EXTI2_IRQn) || \
|
||||
((Irq) == EXTI3_IRQn) || \
|
||||
((Irq) == EXTI4_IRQn) || \
|
||||
((Irq) == EXTI5_IRQn) || \
|
||||
((Irq) == EXTI6_IRQn) || \
|
||||
((Irq) == EXTI7_IRQn) || \
|
||||
((Irq) == LCD_AES_IRQn) || \
|
||||
((Irq) == SWITCH_CSS_BREAK_DAC_IRQn) || \
|
||||
((Irq) == ADC1_COMP_IRQn) || \
|
||||
((Irq) == TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn) || \
|
||||
((Irq) == TIM2_CC_USART2_RX_IRQn) || \
|
||||
((Irq) == TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn) || \
|
||||
((Irq) == TIM3_CC_USART3_RX_IRQn) || \
|
||||
((Irq) == TIM1_UPD_OVF_TRG_IRQn) || \
|
||||
((Irq) == TIM1_CC_IRQn) || \
|
||||
((Irq) == TIM4_UPD_OVF_TRG_IRQn) || \
|
||||
((Irq) == SPI1_IRQn) || \
|
||||
((Irq) == USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn) || \
|
||||
((Irq) == USART1_RX_TIM5_CC_IRQn) || \
|
||||
((Irq) == I2C1_SPI2_IRQn))
|
||||
#endif /* STM8L15X_MD */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ITC_Priority_Level_selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
ITC_PriorityLevel_0 = (uint8_t)0x02, /*!< Software priority level 0 (cannot be written) */
|
||||
ITC_PriorityLevel_1 = (uint8_t)0x01, /*!< Software priority level 1 */
|
||||
ITC_PriorityLevel_2 = (uint8_t)0x00, /*!< Software priority level 2 */
|
||||
ITC_PriorityLevel_3 = (uint8_t)0x03 /*!< Software priority level 3 */
|
||||
} ITC_PriorityLevel_TypeDef;
|
||||
|
||||
#define IS_ITC_PRIORITY(PriorityValue) \
|
||||
(((PriorityValue) == ITC_PriorityLevel_0) || \
|
||||
((PriorityValue) == ITC_PriorityLevel_1) || \
|
||||
((PriorityValue) == ITC_PriorityLevel_2) || \
|
||||
((PriorityValue) == ITC_PriorityLevel_3))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ITC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CPU_SOFT_INT_DISABLED ((uint8_t)0x28) /*!< Mask for I1 and I0 bits in CPU_CC register */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ITC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the ITC configuration to the default reset state ******/
|
||||
void ITC_DeInit(void);
|
||||
|
||||
/* ITC configuration and management functions ******/
|
||||
uint8_t ITC_GetCPUCC(void);
|
||||
uint8_t ITC_GetSoftIntStatus(void);
|
||||
void ITC_SetSoftwarePriority(IRQn_TypeDef IRQn, ITC_PriorityLevel_TypeDef ITC_PriorityLevel);
|
||||
ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(IRQn_TypeDef IRQn);
|
||||
|
||||
#endif /* __STM8L15x_ITC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
140
firmware/inc/stm8l151x/inc/stm8l15x_iwdg.h
Normal file
140
firmware/inc/stm8l151x/inc/stm8l15x_iwdg.h
Normal file
@@ -0,0 +1,140 @@
|
||||
/*******************************************************************************
|
||||
* @file stm8l15x_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the IWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_IWDG_H
|
||||
#define __STM8L15x_IWDG_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported variables ------------------------------------------------------- */
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_KeyRefresh
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_KEY_REFRESH ((uint8_t)0xAA) /*!< This value written in the Key
|
||||
register prevent the watchdog reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_KeyEnable
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_KEY_ENABLE ((uint8_t)0xCC) /*!< This value written in the Key
|
||||
register start the watchdog counting down*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_WriteAccess
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IWDG_WriteAccess_Enable = (uint8_t)0x55,
|
||||
IWDG_WriteAccess_Disable = (uint8_t)0x00
|
||||
} IWDG_WriteAccess_TypeDef;
|
||||
#define IS_IWDG_WRITE_ACCESS_MODE(MODE) (((MODE) == IWDG_WriteAccess_Enable) || \
|
||||
((MODE) == IWDG_WriteAccess_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IWDG_Prescaler_4 = (uint8_t)0x00, /*!< Used to set prescaler register to 4 */
|
||||
IWDG_Prescaler_8 = (uint8_t)0x01, /*!< Used to set prescaler register to 8 */
|
||||
IWDG_Prescaler_16 = (uint8_t)0x02, /*!< Used to set prescaler register to 16 */
|
||||
IWDG_Prescaler_32 = (uint8_t)0x03, /*!< Used to set prescaler register to 32 */
|
||||
IWDG_Prescaler_64 = (uint8_t)0x04, /*!< Used to set prescaler register to 64 */
|
||||
IWDG_Prescaler_128 = (uint8_t)0x05, /*!< Used to set prescaler register to 128 */
|
||||
IWDG_Prescaler_256 = (uint8_t)0x06 /*!< Used to set prescaler register to 256 */
|
||||
} IWDG_Prescaler_TypeDef;
|
||||
#define IS_IWDG_PRESCALER_VALUE(VALUE) (((VALUE) == IWDG_Prescaler_4) || \
|
||||
((VALUE) == IWDG_Prescaler_8) || \
|
||||
((VALUE) == IWDG_Prescaler_16) || \
|
||||
((VALUE) == IWDG_Prescaler_32) || \
|
||||
((VALUE) == IWDG_Prescaler_64) || \
|
||||
((VALUE) == IWDG_Prescaler_128) || \
|
||||
((VALUE) == IWDG_Prescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Prescaler and Counter configuration functions ******************************/
|
||||
void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess);
|
||||
void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler);
|
||||
void IWDG_SetReload(uint8_t IWDG_Reload);
|
||||
void IWDG_ReloadCounter(void);
|
||||
|
||||
/* IWDG activation function ***************************************************/
|
||||
void IWDG_Enable(void);
|
||||
|
||||
#endif /* __STM8L15x_IWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
473
firmware/inc/stm8l151x/inc/stm8l15x_lcd.h
Normal file
473
firmware/inc/stm8l151x/inc/stm8l15x_lcd.h
Normal file
@@ -0,0 +1,473 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_lcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the LCD firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_LCD_H
|
||||
#define __STM8L15x_LCD_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup LCD_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Duty
|
||||
* @brief element values correspond to the bits position
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
LCD_Duty_Static = (uint8_t)0x00, /*!< Static duty */
|
||||
LCD_Duty_1_2 = (uint8_t)0x02, /*!< 1/2 duty */
|
||||
LCD_Duty_1_3 = (uint8_t)0x04, /*!< 1/3 duty */
|
||||
LCD_Duty_1_4 = (uint8_t)0x06, /*!< 1/4 duty */
|
||||
LCD_Duty_1_8 = (uint8_t)0x20 /*!< 1/8 duty */
|
||||
} LCD_Duty_TypeDef;
|
||||
|
||||
#define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_Duty_Static) || ((DUTY) == LCD_Duty_1_2) || \
|
||||
((DUTY) == LCD_Duty_1_3) || ((DUTY) == LCD_Duty_1_4) || \
|
||||
((DUTY) == LCD_Duty_1_8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Bias
|
||||
* @brief element values correspond to the bits position
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LCD_Bias_1_4 = (uint8_t)0x10, /*!< 1/4 bias */
|
||||
LCD_Bias_1_3 = (uint8_t)0x00, /*!< 1/3 bias */
|
||||
LCD_Bias_1_2 = (uint8_t)0x01 /*!< 1/2 bias */
|
||||
} LCD_Bias_TypeDef;
|
||||
|
||||
#define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_Bias_1_4) || \
|
||||
((BIAS) == LCD_Bias_1_3) || \
|
||||
((BIAS) == LCD_Bias_1_2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Clock_Prescaler
|
||||
* @brief element values correspond to the bits position
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LCD_Prescaler_1 = (uint8_t)0x00, /*!< CLKprescaler = ClKinput */
|
||||
LCD_Prescaler_2 = (uint8_t)0x10, /*!< CLKprescaler = ClKinput/2 */
|
||||
LCD_Prescaler_4 = (uint8_t)0x20, /*!< CLKprescaler = ClKinput/4 */
|
||||
LCD_Prescaler_8 = (uint8_t)0x30, /*!< CLKprescaler = ClKinput/8 */
|
||||
LCD_Prescaler_16 = (uint8_t)0x40, /*!< CLKprescaler = ClKinput/16 */
|
||||
LCD_Prescaler_32 = (uint8_t)0x50, /*!< CLKprescaler = ClKinput/32 */
|
||||
LCD_Prescaler_64 = (uint8_t)0x60, /*!< CLKprescaler = ClKinput/64 */
|
||||
LCD_Prescaler_128 = (uint8_t)0x70, /*!< CLKprescaler = ClKinput/128 */
|
||||
LCD_Prescaler_256 = (uint8_t)0x80, /*!< CLKprescaler = ClKinput/256 */
|
||||
LCD_Prescaler_512 = (uint8_t)0x90, /*!< CLKprescaler = ClKinput/512 */
|
||||
LCD_Prescaler_1024 = (uint8_t)0xA0, /*!< CLKprescaler = ClKinput/1024 */
|
||||
LCD_Prescaler_2048 = (uint8_t)0xB0, /*!< CLKprescaler = ClKinput/2048 */
|
||||
LCD_Prescaler_4096 = (uint8_t)0xC0, /*!< CLKprescaler = ClKinput/4096 */
|
||||
LCD_Prescaler_8192 = (uint8_t)0xD0, /*!< CLKprescaler = ClKinput/8192 */
|
||||
LCD_Prescaler_16384 = (uint8_t)0xE0, /*!< CLKprescaler = ClKinput/16384 */
|
||||
LCD_Prescaler_32768 = (uint8_t)0xF0 /*!< CLKprescaler = ClKinput/32768 */
|
||||
} LCD_Prescaler_TypeDef;
|
||||
|
||||
#define IS_LCD_CLOCK_PRESCALER(PRESCALER) (((PRESCALER) == LCD_Prescaler_1) || \
|
||||
((PRESCALER) == LCD_Prescaler_2) || \
|
||||
((PRESCALER) == LCD_Prescaler_4) || \
|
||||
((PRESCALER) == LCD_Prescaler_8) || \
|
||||
((PRESCALER) == LCD_Prescaler_16) || \
|
||||
((PRESCALER) == LCD_Prescaler_32) || \
|
||||
((PRESCALER) == LCD_Prescaler_64) || \
|
||||
((PRESCALER) == LCD_Prescaler_128) || \
|
||||
((PRESCALER) == LCD_Prescaler_256) || \
|
||||
((PRESCALER) == LCD_Prescaler_512) || \
|
||||
((PRESCALER) == LCD_Prescaler_1024) || \
|
||||
((PRESCALER) == LCD_Prescaler_2048) || \
|
||||
((PRESCALER) == LCD_Prescaler_4096) || \
|
||||
((PRESCALER) == LCD_Prescaler_8192) || \
|
||||
((PRESCALER) == LCD_Prescaler_16384) || \
|
||||
((PRESCALER) == LCD_Prescaler_32768))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Clock_Divider
|
||||
* @brief element values correspond to the bits position
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LCD_Divider_16 = (uint8_t)0x00, /*!< LCD frequency = CLKprescaler/16 */
|
||||
LCD_Divider_17 = (uint8_t)0x01, /*!< LCD frequency = CLKprescaler/17 */
|
||||
LCD_Divider_18 = (uint8_t)0x02, /*!< LCD frequency = CLKprescaler/18 */
|
||||
LCD_Divider_19 = (uint8_t)0x03, /*!< LCD frequency = CLKprescaler/19 */
|
||||
LCD_Divider_20 = (uint8_t)0x04, /*!< LCD frequency = CLKprescaler/20 */
|
||||
LCD_Divider_21 = (uint8_t)0x05, /*!< LCD frequency = CLKprescaler/21 */
|
||||
LCD_Divider_22 = (uint8_t)0x06, /*!< LCD frequency = CLKprescaler/22 */
|
||||
LCD_Divider_23 = (uint8_t)0x07, /*!< LCD frequency = CLKprescaler/23 */
|
||||
LCD_Divider_24 = (uint8_t)0x08, /*!< LCD frequency = CLKprescaler/24 */
|
||||
LCD_Divider_25 = (uint8_t)0x09, /*!< LCD frequency = CLKprescaler/25 */
|
||||
LCD_Divider_26 = (uint8_t)0x0A, /*!< LCD frequency = CLKprescaler/26 */
|
||||
LCD_Divider_27 = (uint8_t)0x0B, /*!< LCD frequency = CLKprescaler/27 */
|
||||
LCD_Divider_28 = (uint8_t)0x0C, /*!< LCD frequency = CLKprescaler/28 */
|
||||
LCD_Divider_29 = (uint8_t)0x0D, /*!< LCD frequency = CLKprescaler/29 */
|
||||
LCD_Divider_30 = (uint8_t)0x0E, /*!< LCD frequency = CLKprescaler/30 */
|
||||
LCD_Divider_31 = (uint8_t)0x0F /*!< LCD frequency = CLKprescaler/31 */
|
||||
} LCD_Divider_TypeDef;
|
||||
|
||||
#define IS_LCD_CLOCK_DIVIDER(DIVIDER) (((DIVIDER) == LCD_Divider_16) || \
|
||||
((DIVIDER) == LCD_Divider_17) || \
|
||||
((DIVIDER) == LCD_Divider_18) || \
|
||||
((DIVIDER) == LCD_Divider_19) || \
|
||||
((DIVIDER) == LCD_Divider_20) || \
|
||||
((DIVIDER) == LCD_Divider_21) || \
|
||||
((DIVIDER) == LCD_Divider_22) || \
|
||||
((DIVIDER) == LCD_Divider_23) || \
|
||||
((DIVIDER) == LCD_Divider_24) || \
|
||||
((DIVIDER) == LCD_Divider_25) || \
|
||||
((DIVIDER) == LCD_Divider_26) || \
|
||||
((DIVIDER) == LCD_Divider_27) || \
|
||||
((DIVIDER) == LCD_Divider_28) || \
|
||||
((DIVIDER) == LCD_Divider_29) || \
|
||||
((DIVIDER) == LCD_Divider_30) || \
|
||||
((DIVIDER) == LCD_Divider_31))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Contrast
|
||||
* @brief element values correspond to the bits position
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LCD_Contrast_Level_0 = (uint8_t)0x00, /*!< Medium Density / High Density Maximum Voltage = 2.60V / 2.60V */
|
||||
LCD_Contrast_Level_1 = (uint8_t)0x02, /*!< Medium Density / High Density Maximum Voltage = 2.70V / 2.73V */
|
||||
LCD_Contrast_Level_2 = (uint8_t)0x04, /*!< Medium Density / High Density Maximum Voltage = 2.80V / 2.86V */
|
||||
LCD_Contrast_Level_3 = (uint8_t)0x06, /*!< Medium Density / High Density Maximum Voltage = 2.90V / 2.99V */
|
||||
LCD_Contrast_Level_4 = (uint8_t)0x08, /*!< Medium Density / High Density Maximum Voltage = 3.00V / 3.12V */
|
||||
LCD_Contrast_Level_5 = (uint8_t)0x0A, /*!< Medium Density / High Density Maximum Voltage = 3.10V / 3.25V */
|
||||
LCD_Contrast_Level_6 = (uint8_t)0x0C, /*!< Medium Density / High Density Maximum Voltage = 3.20V / 3.38V */
|
||||
LCD_Contrast_Level_7 = (uint8_t)0x0E /*!< Medium Density / High Density Maximum Voltage = 3.30V / 3.51V */
|
||||
} LCD_Contrast_TypeDef;
|
||||
|
||||
#define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_Contrast_Level_0) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_1) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_2) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_3) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_4) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_5) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_6) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_7))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Voltage_Source
|
||||
* @brief element values correspond to the bits position
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LCD_VoltageSource_Internal = (uint8_t)0x00, /*!< Internal voltage source for the LCD */
|
||||
LCD_VoltageSource_External = (uint8_t)0x01 /*!< External voltage source for the LCD */
|
||||
} LCD_VoltageSource_TypeDef;
|
||||
|
||||
#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VoltageSource_Internal) || \
|
||||
((SOURCE) == LCD_VoltageSource_External))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Pulse_On_Duration
|
||||
* @brief element values correspond to the bits position
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LCD_PulseOnDuration_0 = (uint8_t)0x00, /*!< Pulse on duration = 0/CLKprescaler */
|
||||
LCD_PulseOnDuration_1 = (uint8_t)0x20, /*!< Pulse on duration = 1/CLKprescaler */
|
||||
LCD_PulseOnDuration_2 = (uint8_t)0x40, /*!< Pulse on duration = 2/CLKprescaler */
|
||||
LCD_PulseOnDuration_3 = (uint8_t)0x60, /*!< Pulse on duration = 3/CLKprescaler */
|
||||
LCD_PulseOnDuration_4 = (uint8_t)0x80, /*!< Pulse on duration = 4/CLKprescaler */
|
||||
LCD_PulseOnDuration_5 = (uint8_t)0xA0, /*!< Pulse on duration = 5/CLKprescaler */
|
||||
LCD_PulseOnDuration_6 = (uint8_t)0xC0, /*!< Pulse on duration = 6/CLKprescaler */
|
||||
LCD_PulseOnDuration_7 = (uint8_t)0xE0 /*!< Pulse on duration = 7/CLKprescaler */
|
||||
} LCD_PulseOnDuration_TypeDef;
|
||||
|
||||
#define IS_LCD_PULSE_DURATION(DURATION) (((DURATION) == LCD_PulseOnDuration_0) || \
|
||||
((DURATION) == LCD_PulseOnDuration_1) || \
|
||||
((DURATION) == LCD_PulseOnDuration_2) || \
|
||||
((DURATION) == LCD_PulseOnDuration_3) || \
|
||||
((DURATION) == LCD_PulseOnDuration_4) || \
|
||||
((DURATION) == LCD_PulseOnDuration_5) || \
|
||||
((DURATION) == LCD_PulseOnDuration_6) || \
|
||||
((DURATION) == LCD_PulseOnDuration_7))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Dead_Time
|
||||
* @brief element values correspond to the bits position
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LCD_DeadTime_0 = (uint8_t)0x00, /*!< No dead Time */
|
||||
LCD_DeadTime_1 = (uint8_t)0x01, /*!< One Phase between different couple of Frame */
|
||||
LCD_DeadTime_2 = (uint8_t)0x02, /*!< Two Phase between different couple of Frame */
|
||||
LCD_DeadTime_3 = (uint8_t)0x03, /*!< Tree Phase between different couple of Frame */
|
||||
LCD_DeadTime_4 = (uint8_t)0x04, /*!< Four Phase between different couple of Frame */
|
||||
LCD_DeadTime_5 = (uint8_t)0x05, /*!< Five Phase between different couple of Frame */
|
||||
LCD_DeadTime_6 = (uint8_t)0x06, /*!< Six Phase between different couple of Frame */
|
||||
LCD_DeadTime_7 = (uint8_t)0x07 /*!< Seven Phase between different couple of Frame */
|
||||
} LCD_DeadTime_TypeDef;
|
||||
|
||||
#define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DeadTime_0) || \
|
||||
((TIME) == LCD_DeadTime_1) || \
|
||||
((TIME) == LCD_DeadTime_2) || \
|
||||
((TIME) == LCD_DeadTime_3) || \
|
||||
((TIME) == LCD_DeadTime_4) || \
|
||||
((TIME) == LCD_DeadTime_5) || \
|
||||
((TIME) == LCD_DeadTime_6) || \
|
||||
((TIME) == LCD_DeadTime_7))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_BlinkMode
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LCD_BlinkMode_Off = (uint8_t)0x00, /*!< Blink inactive */
|
||||
LCD_BlinkMode_SEG0_COM0 = (uint8_t)0x40, /*!< SEG0 on COM0 blink */
|
||||
LCD_BlinkMode_SEG0_AllCOM = (uint8_t)0x80, /*!< SEG0 on All COM blink */
|
||||
LCD_BlinkMode_AllSEG_AllCOM = (uint8_t)0xC0 /*!< All SEG on All COm Blink */
|
||||
} LCD_BlinkMode_TypeDef;
|
||||
|
||||
#define IS_LCD_BLINK_MODE(BLINK) (((BLINK) == LCD_BlinkMode_Off) || \
|
||||
((BLINK) == LCD_BlinkMode_SEG0_COM0) || \
|
||||
((BLINK) == LCD_BlinkMode_SEG0_AllCOM) || \
|
||||
((BLINK) == LCD_BlinkMode_AllSEG_AllCOM))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Blink_Frequency
|
||||
* @brief element values correspond to the bits position
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LCD_BlinkFrequency_Div8 = (uint8_t)0x00, /*!< The Blink frequency = fLcd/8 */
|
||||
LCD_BlinkFrequency_Div16 = (uint8_t)0x08, /*!< The Blink frequency = fLcd/16 */
|
||||
LCD_BlinkFrequency_Div32 = (uint8_t)0x10, /*!< The Blink frequency = fLcd/32 */
|
||||
LCD_BlinkFrequency_Div64 = (uint8_t)0x18, /*!< The Blink frequency = fLcd/64 */
|
||||
LCD_BlinkFrequency_Div128 = (uint8_t)0x20, /*!< The Blink frequency = fLcd/128 */
|
||||
LCD_BlinkFrequency_Div256 = (uint8_t)0x28, /*!< The Blink frequency = fLcd/256 */
|
||||
LCD_BlinkFrequency_Div512 = (uint8_t)0x30, /*!< The Blink frequency = fLcd/512 */
|
||||
LCD_BlinkFrequency_Div1024 = (uint8_t)0x38 /*!< The Blink frequency = fLcd/1024 */
|
||||
} LCD_BlinkFrequency_TypeDef;
|
||||
|
||||
#define IS_LCD_BLINK_FREQUENCY(BLINKF) (((BLINKF) == LCD_BlinkFrequency_Div8) || \
|
||||
((BLINKF) == LCD_BlinkFrequency_Div16) || \
|
||||
((BLINKF) == LCD_BlinkFrequency_Div32) || \
|
||||
((BLINKF) == LCD_BlinkFrequency_Div64) || \
|
||||
((BLINKF) == LCD_BlinkFrequency_Div128) || \
|
||||
((BLINKF) == LCD_BlinkFrequency_Div256) || \
|
||||
((BLINKF) == LCD_BlinkFrequency_Div512) || \
|
||||
((BLINKF) == LCD_BlinkFrequency_Div1024))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_RAMRegister
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LCD_RAMRegister_0 = (uint8_t)0x00, /*!< RAM Register 0 */
|
||||
LCD_RAMRegister_1 = (uint8_t)0x01, /*!< RAM Register 1 */
|
||||
LCD_RAMRegister_2 = (uint8_t)0x02, /*!< RAM Register 2 */
|
||||
LCD_RAMRegister_3 = (uint8_t)0x03, /*!< RAM Register 3 */
|
||||
LCD_RAMRegister_4 = (uint8_t)0x04, /*!< RAM Register 4 */
|
||||
LCD_RAMRegister_5 = (uint8_t)0x05, /*!< RAM Register 5 */
|
||||
LCD_RAMRegister_6 = (uint8_t)0x06, /*!< RAM Register 6 */
|
||||
LCD_RAMRegister_7 = (uint8_t)0x07, /*!< RAM Register 7 */
|
||||
LCD_RAMRegister_8 = (uint8_t)0x08, /*!< RAM Register 8 */
|
||||
LCD_RAMRegister_9 = (uint8_t)0x09, /*!< RAM Register 9 */
|
||||
LCD_RAMRegister_10 = (uint8_t)0x0A, /*!< RAM Register 10 */
|
||||
LCD_RAMRegister_11 = (uint8_t)0x0B, /*!< RAM Register 11 */
|
||||
LCD_RAMRegister_12 = (uint8_t)0x0C, /*!< RAM Register 12 */
|
||||
LCD_RAMRegister_13 = (uint8_t)0x0D, /*!< RAM Register 13 */
|
||||
LCD_RAMRegister_14 = (uint8_t)0x0E, /*!< RAM Register 14 */
|
||||
LCD_RAMRegister_15 = (uint8_t)0x0F, /*!< RAM Register 15 */
|
||||
LCD_RAMRegister_16 = (uint8_t)0x10, /*!< RAM Register 16 */
|
||||
LCD_RAMRegister_17 = (uint8_t)0x11, /*!< RAM Register 17 */
|
||||
LCD_RAMRegister_18 = (uint8_t)0x12, /*!< RAM Register 18 */
|
||||
LCD_RAMRegister_19 = (uint8_t)0x13, /*!< RAM Register 19 */
|
||||
LCD_RAMRegister_20 = (uint8_t)0x14, /*!< RAM Register 20 */
|
||||
LCD_RAMRegister_21 = (uint8_t)0x15 /*!< RAM Register 21 */
|
||||
} LCD_RAMRegister_TypeDef;
|
||||
|
||||
#define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAMRegister_0) || \
|
||||
((REGISTER) == LCD_RAMRegister_1) || \
|
||||
((REGISTER) == LCD_RAMRegister_2) || \
|
||||
((REGISTER) == LCD_RAMRegister_3) || \
|
||||
((REGISTER) == LCD_RAMRegister_4) || \
|
||||
((REGISTER) == LCD_RAMRegister_5) || \
|
||||
((REGISTER) == LCD_RAMRegister_6) || \
|
||||
((REGISTER) == LCD_RAMRegister_7) || \
|
||||
((REGISTER) == LCD_RAMRegister_8) || \
|
||||
((REGISTER) == LCD_RAMRegister_9) || \
|
||||
((REGISTER) == LCD_RAMRegister_10) || \
|
||||
((REGISTER) == LCD_RAMRegister_11) || \
|
||||
((REGISTER) == LCD_RAMRegister_12) || \
|
||||
((REGISTER) == LCD_RAMRegister_13) || \
|
||||
((REGISTER) == LCD_RAMRegister_14) || \
|
||||
((REGISTER) == LCD_RAMRegister_15) || \
|
||||
((REGISTER) == LCD_RAMRegister_16) || \
|
||||
((REGISTER) == LCD_RAMRegister_17) || \
|
||||
((REGISTER) == LCD_RAMRegister_18) || \
|
||||
((REGISTER) == LCD_RAMRegister_19) || \
|
||||
((REGISTER) == LCD_RAMRegister_20) || \
|
||||
((REGISTER) == LCD_RAMRegister_21))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Port_Mask_Register
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LCD_PortMaskRegister_0 = (uint8_t)0x00, /*!< PortMask Register 0 */
|
||||
LCD_PortMaskRegister_1 = (uint8_t)0x01, /*!< PortMask Register 1 */
|
||||
LCD_PortMaskRegister_2 = (uint8_t)0x02, /*!< PortMask Register 2 */
|
||||
LCD_PortMaskRegister_3 = (uint8_t)0x03, /*!< PortMask Register 3 */
|
||||
LCD_PortMaskRegister_4 = (uint8_t)0x04, /*!< PortMask Register 4 */
|
||||
LCD_PortMaskRegister_5 = (uint8_t)0x05 /*!< PortMask Register 5 */
|
||||
} LCD_PortMaskRegister_TypeDef;
|
||||
|
||||
#define IS_LCD_PORT_MASK(MASK) (((MASK) == LCD_PortMaskRegister_0) || \
|
||||
((MASK) == LCD_PortMaskRegister_1) || \
|
||||
((MASK) == LCD_PortMaskRegister_2) || \
|
||||
((MASK) == LCD_PortMaskRegister_3) || \
|
||||
((MASK) == LCD_PortMaskRegister_4) || \
|
||||
((MASK) == LCD_PortMaskRegister_5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Page_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
LCD_PageSelection_FirstPage = (uint8_t)0x00, /*!< The LCD RAM is selected as the first page */
|
||||
LCD_PageSelection_SecondPage = (uint8_t)0x04 /*!< The LCD RAM is selected as the second page */
|
||||
} LCD_PageSelection_TypeDef;
|
||||
|
||||
#define IS_LCD_PAGE_SELECT(PAGE) (((PAGE) == LCD_PageSelection_FirstPage) || \
|
||||
((PAGE) == LCD_PageSelection_SecondPage))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* LCD Legacy defines */
|
||||
/** @defgroup LCD_Private_Define
|
||||
* @ brief LCD Legacy defines
|
||||
* @{
|
||||
*/
|
||||
#define LCD_Contrast_2V6 ((uint8_t)LCD_Contrast_Level_0)
|
||||
#define LCD_Contrast_2V7 ((uint8_t)LCD_Contrast_Level_1)
|
||||
#define LCD_Contrast_2V8 ((uint8_t)LCD_Contrast_Level_2)
|
||||
#define LCD_Contrast_2V9 ((uint8_t)LCD_Contrast_Level_3)
|
||||
#define LCD_Contrast_3V0 ((uint8_t)LCD_Contrast_Level_4)
|
||||
#define LCD_Contrast_3V1 ((uint8_t)LCD_Contrast_Level_5)
|
||||
#define LCD_Contrast_3V2 ((uint8_t)LCD_Contrast_Level_6)
|
||||
#define LCD_Contrast_3V3 ((uint8_t)LCD_Contrast_Level_7)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the LCD configuration to the default reset state *****/
|
||||
void LCD_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void LCD_Init(LCD_Prescaler_TypeDef LCD_Prescaler, LCD_Divider_TypeDef LCD_Divider,
|
||||
LCD_Duty_TypeDef LCD_Duty, LCD_Bias_TypeDef LCD_Bias, LCD_VoltageSource_TypeDef LCD_VoltageSource);
|
||||
void LCD_PortMaskConfig(LCD_PortMaskRegister_TypeDef LCD_PortMaskRegister, uint8_t LCD_Mask);
|
||||
void LCD_Cmd(FunctionalState NewState);
|
||||
void LCD_HighDriveCmd(FunctionalState NewState);
|
||||
void LCD_PulseOnDurationConfig(LCD_PulseOnDuration_TypeDef LCD_PulseOnDuration);
|
||||
void LCD_DeadTimeConfig(LCD_DeadTime_TypeDef LCD_DeadTime);
|
||||
void LCD_BlinkConfig(LCD_BlinkMode_TypeDef LCD_BlinkMode, LCD_BlinkFrequency_TypeDef LCD_BlinkFrequency);
|
||||
void LCD_ContrastConfig(LCD_Contrast_TypeDef LCD_Contrast);
|
||||
|
||||
/* LCD RAM memory write functions *********************************************/
|
||||
void LCD_WriteRAM(LCD_RAMRegister_TypeDef LCD_RAMRegister, uint8_t LCD_Data);
|
||||
void LCD_PageSelect(LCD_PageSelection_TypeDef LCD_PageSelection);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void LCD_ITConfig(FunctionalState NewState);
|
||||
FlagStatus LCD_GetFlagStatus(void);
|
||||
void LCD_ClearFlag(void);
|
||||
ITStatus LCD_GetITStatus(void);
|
||||
void LCD_ClearITPendingBit(void);
|
||||
|
||||
#endif /* __STM8L15x_LCD_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
131
firmware/inc/stm8l151x/inc/stm8l15x_pwr.h
Normal file
131
firmware/inc/stm8l151x/inc/stm8l15x_pwr.h
Normal file
@@ -0,0 +1,131 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the PWR firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_PWR_H
|
||||
#define __STM8L15x_PWR_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PVD_detection_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
PWR_PVDLevel_1V85 = (uint8_t)0x00, /*!< PVD threshold = 1.85 V */
|
||||
PWR_PVDLevel_2V05 = (uint8_t)0x02, /*!< PVD threshold = 2.05 V */
|
||||
PWR_PVDLevel_2V26 = (uint8_t)0x04, /*!< PVD threshold = 2.26 V */
|
||||
PWR_PVDLevel_2V45 = (uint8_t)0x06, /*!< PVD threshold = 2.45 V */
|
||||
PWR_PVDLevel_2V65 = (uint8_t)0x08, /*!< PVD threshold = 2.65 V */
|
||||
PWR_PVDLevel_2V85 = (uint8_t)0x0A, /*!< PVD threshold = 2.85 V */
|
||||
PWR_PVDLevel_3V05 = (uint8_t)0x0C, /*!< PVD threshold = 3.05 V */
|
||||
PWR_PVDLevel_PVDIn = (uint8_t)0x0E /*!< PVD threshold = PVD_IN input pin */
|
||||
} PWR_PVDLevel_TypeDef;
|
||||
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_1V85) || \
|
||||
((LEVEL) == PWR_PVDLevel_2V05) || \
|
||||
((LEVEL) == PWR_PVDLevel_2V26) || \
|
||||
((LEVEL) == PWR_PVDLevel_2V45) || \
|
||||
((LEVEL) == PWR_PVDLevel_2V65) || \
|
||||
((LEVEL) == PWR_PVDLevel_2V85) || \
|
||||
((LEVEL) == PWR_PVDLevel_3V05) || \
|
||||
((LEVEL) == PWR_PVDLevel_PVDIn))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
PWR_FLAG_PVDOF = (uint8_t)0x40,/*!< PVD output flag */
|
||||
PWR_FLAG_PVDIF = (uint8_t)0x20, /*!< PVD Interrupt flag */
|
||||
PWR_FLAG_VREFINTF = (uint8_t)0x01 /*!< Internal reference voltage status flag */
|
||||
} PWR_FLAG_TypeDef;
|
||||
|
||||
#define IS_PWR_FLAG(FLAG) (((FLAG) == PWR_FLAG_PVDOF) || \
|
||||
((FLAG) == PWR_FLAG_PVDIF) || \
|
||||
((FLAG) == PWR_FLAG_VREFINTF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the PWR configuration to the default reset state ******/
|
||||
void PWR_DeInit(void);
|
||||
|
||||
/* PVD configuration functions ************************************************/
|
||||
void PWR_PVDLevelConfig(PWR_PVDLevel_TypeDef PWR_PVDLevel);
|
||||
void PWR_PVDCmd(FunctionalState NewState);
|
||||
|
||||
/* Ultra Low Power mode configuration functions *******************************/
|
||||
void PWR_FastWakeUpCmd(FunctionalState NewState);
|
||||
void PWR_UltraLowPowerCmd(FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void PWR_PVDITConfig(FunctionalState NewState);
|
||||
ITStatus PWR_PVDGetITStatus(void);
|
||||
FlagStatus PWR_GetFlagStatus(PWR_FLAG_TypeDef PWR_FLAG);
|
||||
void PWR_PVDClearFlag(void);
|
||||
void PWR_PVDClearITPendingBit(void);
|
||||
|
||||
#endif /* __STM8L15x_PWR_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
91
firmware/inc/stm8l151x/inc/stm8l15x_rst.h
Normal file
91
firmware/inc/stm8l151x/inc/stm8l15x_rst.h
Normal file
@@ -0,0 +1,91 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_rst.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the RST firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_RST_H
|
||||
#define __STM8L15x_RST_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RST
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported variables ------------------------------------------------------- */
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RST_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RST_Flags
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
RST_FLAG_PORF = (uint8_t)0x01, /*!< POR reset flag */
|
||||
RST_FLAG_SWIMF = (uint8_t)0x08, /*!< SWIM reset flag */
|
||||
RST_FLAG_ILLOPF = (uint8_t)0x04, /*!< Illegal opcode reset flag */
|
||||
RST_FLAG_IWDGF = (uint8_t)0x02, /*!< Independent watchdog reset flag */
|
||||
RST_FLAG_WWDGF = (uint8_t)0x10, /*!< Window watchdog reset flag */
|
||||
RST_FLAG_BORF = (uint8_t)0x20 /*!< BOR reset flag */
|
||||
} RST_FLAG_TypeDef;
|
||||
|
||||
#define IS_RST_FLAG(FLAG) (((FLAG) == RST_FLAG_PORF) || ((FLAG) == RST_FLAG_BORF) || \
|
||||
((FLAG) == RST_FLAG_IWDGF) || ((FLAG) == RST_FLAG_ILLOPF) || \
|
||||
((FLAG) == RST_FLAG_WWDGF) || ((FLAG) == RST_FLAG_SWIMF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Flag management functions **************************************************/
|
||||
FlagStatus RST_GetFlagStatus(RST_FLAG_TypeDef RST_Flag);
|
||||
void RST_ClearFlag(RST_FLAG_TypeDef RST_Flag);
|
||||
|
||||
/* NRST Pin configuration function ********************************************/
|
||||
void RST_GPOutputEnable(void);
|
||||
|
||||
#endif /* __STM8L15x_RST_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
956
firmware/inc/stm8l151x/inc/stm8l15x_rtc.h
Normal file
956
firmware/inc/stm8l151x/inc/stm8l15x_rtc.h
Normal file
@@ -0,0 +1,956 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the RTC
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_RTC_H
|
||||
#define __STM8L15x_RTC_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Weekdays
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_Weekday_Monday = ((uint8_t)0x01), /*!< WeekDay is Monday */
|
||||
RTC_Weekday_Tuesday = ((uint8_t)0x02), /*!< WeekDay is Tuesday */
|
||||
RTC_Weekday_Wednesday = ((uint8_t)0x03), /*!< WeekDay is Wednesday */
|
||||
RTC_Weekday_Thursday = ((uint8_t)0x04), /*!< WeekDay is Thursday */
|
||||
RTC_Weekday_Friday = ((uint8_t)0x05), /*!< WeekDay is Friday */
|
||||
RTC_Weekday_Saturday = ((uint8_t)0x06), /*!< WeekDay is Saturday */
|
||||
RTC_Weekday_Sunday = ((uint8_t)0x07) /*!< WeekDay is Sunday */
|
||||
}
|
||||
RTC_Weekday_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Months
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_Month_January = ((uint8_t)0x01), /*!< Month is January */
|
||||
RTC_Month_February = ((uint8_t)0x02), /*!< Month is February */
|
||||
RTC_Month_March = ((uint8_t)0x03), /*!< Month is March */
|
||||
RTC_Month_April = ((uint8_t)0x04), /*!< Month is April */
|
||||
RTC_Month_May = ((uint8_t)0x05), /*!< Month is May */
|
||||
RTC_Month_June = ((uint8_t)0x06), /*!< Month is June */
|
||||
RTC_Month_July = ((uint8_t)0x07), /*!< Month is July */
|
||||
RTC_Month_August = ((uint8_t)0x08), /*!< Month is August */
|
||||
RTC_Month_September = ((uint8_t)0x09), /*!< Month is September */
|
||||
RTC_Month_October = ((uint8_t)0x10), /*!< Month is October */
|
||||
RTC_Month_November = ((uint8_t)0x11), /*!< Month is November */
|
||||
RTC_Month_December = ((uint8_t)0x12) /*!< Month is December */
|
||||
}
|
||||
RTC_Month_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Hour_Format
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_HourFormat_24 = ((uint8_t)0x00), /*!< Hour Format is 24H */
|
||||
RTC_HourFormat_12 = ((uint8_t)0x40) /*!< Hour Format is 12H (using AM/PM) */
|
||||
}
|
||||
RTC_HourFormat_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Time
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_H12_AM = ((uint8_t)0x00), /*!< AM/PM notation is AM or 24 hour format */
|
||||
RTC_H12_PM = ((uint8_t)0x40) /*!< AM/PM notation is PM */
|
||||
}
|
||||
RTC_H12_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_WeekDay_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_AlarmDateWeekDaySel_Date = ((uint8_t)0x00), /*!< Date/WeekDay selection is Date */
|
||||
RTC_AlarmDateWeekDaySel_WeekDay = ((uint8_t)0x40) /*!< Date/WeekDay selection is WeekDay */
|
||||
}
|
||||
RTC_AlarmDateWeekDaySel_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Mask
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_AlarmMask_None = ((uint8_t)0x00), /*!< Alarm Masks disabled */
|
||||
RTC_AlarmMask_Seconds = ((uint8_t)0x80), /*!< Alarm Seconds Mask */
|
||||
RTC_AlarmMask_Minutes = ((uint8_t)0x40), /*!< Alarm Minutes Mask */
|
||||
RTC_AlarmMask_Hours = ((uint8_t)0x20), /*!< Alarm Hours Mask */
|
||||
RTC_AlarmMask_DateWeekDay = ((uint8_t)0x10), /*!< Alarm Date/WeekDay Mask */
|
||||
RTC_AlarmMask_All = ((uint8_t)0xF0) /*!< Alarm All Mask are enabled */
|
||||
}
|
||||
RTC_AlarmMask_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Sub_Second_Alarm_Mask
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_AlarmSubSecondMask_All = ((uint8_t)0x00), /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
|
||||
RTC_AlarmSubSecondMask_None = ((uint8_t)0x0F), /*!< SS[14:0] are compared and must match to activate alarm. */
|
||||
RTC_AlarmSubSecondMask_SS14_1 = ((uint8_t)0x01), /*!< SS[14:1] are not used in Alarm comparison. Only SS[0] is compared. */
|
||||
RTC_AlarmSubSecondMask_SS14_2 = ((uint8_t)0x02), /*!< SS[14:2] are not used in Alarm comparison. Only SS[1:0] are compared */
|
||||
RTC_AlarmSubSecondMask_SS14_3 = ((uint8_t)0x03), /*!< SS[14:3] are not used in Alarm comparison. Only SS[1:0] are compared */
|
||||
RTC_AlarmSubSecondMask_SS14_4 = ((uint8_t)0x04), /*!< SS[14:4] are not used in Alarm comparison. Only SS[1:0] are compared */
|
||||
RTC_AlarmSubSecondMask_SS14_5 = ((uint8_t)0x05), /*!< SS[14:5] are not used in Alarm comparison. Only SS[1:0] are compared */
|
||||
RTC_AlarmSubSecondMask_SS14_6 = ((uint8_t)0x06), /*!< SS[14:6] are not used in Alarm comparison. Only SS[1:0] are compared */
|
||||
RTC_AlarmSubSecondMask_SS14_7 = ((uint8_t)0x07), /*!< SS[14:7] are not used in Alarm comparison. Only SS[1:0] are compared */
|
||||
RTC_AlarmSubSecondMask_SS14_8 = ((uint8_t)0x08), /*!< SS[14:8] are not used in Alarm comparison. Only SS[1:0] are compared */
|
||||
RTC_AlarmSubSecondMask_SS14_9 = ((uint8_t)0x09), /*!< SS[14:9] are not used in Alarm comparison. Only SS[1:0] are compared */
|
||||
RTC_AlarmSubSecondMask_SS14_10 = ((uint8_t)0x0A), /*!< SS[14:10] are not used in Alarm comparison. Only SS[1:0] are compared */
|
||||
RTC_AlarmSubSecondMask_SS14_11 = ((uint8_t)0x0B), /*!< SS[14:11] are not used in Alarm comparison. Only SS[1:0] are compared */
|
||||
RTC_AlarmSubSecondMask_SS14_12 = ((uint8_t)0x0C), /*!< SS[14:12] are not used in Alarm comparison. Only SS[1:0] are compared */
|
||||
RTC_AlarmSubSecondMask_SS14_13 = ((uint8_t)0x0D), /*!< SS[14:13] are not used in Alarm comparison. Only SS[1:0] are compared */
|
||||
RTC_AlarmSubSecondMask_SS14 = ((uint8_t)0x0E) /*!< SS[14] is not used in Alarm comparison. Only SS[13:0] are compared */
|
||||
}
|
||||
RTC_AlarmSubSecondMask_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Wakeup_Clock
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_WakeUpClock_RTCCLK_Div16 = ((uint8_t)0x00), /*!< (RTC clock) div 16*/
|
||||
RTC_WakeUpClock_RTCCLK_Div8 = ((uint8_t)0x01), /*!< (RTC clock) div 8*/
|
||||
RTC_WakeUpClock_RTCCLK_Div4 = ((uint8_t)0x02), /*!< (RTC clock) div 4*/
|
||||
RTC_WakeUpClock_RTCCLK_Div2 = ((uint8_t)0x03), /*!< (RTC clock) div 2*/
|
||||
RTC_WakeUpClock_CK_SPRE_16bits = ((uint8_t)0x04), /*!< CK SPRE with a counter from 0x0000 to 0xFFFF */
|
||||
RTC_WakeUpClock_CK_SPRE_17bits = ((uint8_t)0x06) /*!< CK SPRE with a counter from 0x10000 to 0x1FFFF */
|
||||
}
|
||||
RTC_WakeUpClock_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_Output_Disable = ((uint8_t)0x00), /*!< RTC Alternate function Output is disabled */
|
||||
RTC_Output_Alarm = ((uint8_t)0x20), /*!< RTC Alternate function Output is the Alarm A event*/
|
||||
RTC_Output_WakeUp = ((uint8_t)0x60) /*!< RTC Alternate function Output is the WakeUp event */
|
||||
}
|
||||
RTC_Output_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_OutputPolarity_High = ((uint8_t)0x00), /*!< RTC Alternate function Output Polarity is High */
|
||||
RTC_OutputPolarity_Low = ((uint8_t)0x10) /*!< RTC Alternate function Output Polarity is Low */
|
||||
}
|
||||
RTC_OutputPolarity_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Calibration_Output
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_CalibOutput_512Hz = ((uint8_t)0x00), /*!< RTC Calibration Output is 512Hz */
|
||||
RTC_CalibOutput_1Hz = ((uint8_t)0x80) /*!< RTC Calibration Output is 1Hz */
|
||||
}
|
||||
RTC_CalibOutput_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_DayLight_Saving
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_DayLightSaving_SUB1H = ((uint8_t)0x02), /*!< Substract 1 hour to the current Time (Winter Time Adjustment) */
|
||||
RTC_DayLightSaving_ADD1H = ((uint8_t)0x01) /*!< Add 1 hour to the current Time (Summer Time Adjustment) */
|
||||
}
|
||||
RTC_DayLightSaving_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Store_Operation
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_StoreOperation_Set = ((uint8_t)0x04), /*!< Store Operation Set */
|
||||
RTC_StoreOperation_Reset = ((uint8_t)0x00) /*!< Store Operation Reset */
|
||||
}
|
||||
RTC_StoreOperation_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_Parameter_Format
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_Format_BIN = ((uint8_t)0x00), /*!< Binary Format is used */
|
||||
RTC_Format_BCD = ((uint8_t)0x01) /*!< BCD Format is used */
|
||||
}
|
||||
RTC_Format_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_FLAG_TAMP3F = ((uint16_t)0x0080), /*!< TAMPER3 detection Flag. If set, tamper detection event is detected on tamper input 3 */
|
||||
RTC_FLAG_TAMP2F = ((uint16_t)0x0040), /*!< TAMPER2 detection Flag. If set, tamper detection event is detected on tamper input 2 */
|
||||
RTC_FLAG_TAMP1F = ((uint16_t)0x0020), /*!< TAMPER1 detection Flag. If set, tamper detection event is detected on tamper input 1 */
|
||||
|
||||
RTC_FLAG_WUTF = ((uint16_t)0x0004), /*!< Wake up Timer Flag. If set, the Wake Up down counter reaches 0 */
|
||||
RTC_FLAG_ALRAF = ((uint16_t)0x0001), /*!< Alarm A Flag. If set, the Time/Date registers matches Alarm A registers */
|
||||
|
||||
RTC_FLAG_INITF = ((uint16_t)0x4000), /*!< Initialisation Flag. If set,Calender registers has been initialized */
|
||||
RTC_FLAG_RSF = ((uint16_t)0x2000), /*!< Registers Synchronization Flag. If set,Calender registers synchronized */
|
||||
RTC_FLAG_INITS = ((uint16_t)0x1000), /*!< Initialisation Status Flag. If set,Calender update is allowed */
|
||||
|
||||
RTC_FLAG_SHPF = ((uint16_t)0x0800), /*!< Shift operation pending Flag. This flag is set by hardware as soon as a shift operation is
|
||||
initiated by a write to the RTC_SHIFTRL. It is cleared by hardware as soon as the corresponding
|
||||
shift operation has completed. */
|
||||
|
||||
RTC_FLAG_WUTWF = ((uint16_t)0x0400), /*!< Wake up Timer write Flag. If set, Wake up Timer update is allowed */
|
||||
RTC_FLAG_RECALPF = ((uint16_t)0x0200), /*!< Recalibration pending Flag, The status flag RECALPF is automatically set to <20>1<EFBFBD> when software
|
||||
writes to the register RTC_CALRL, indicating that the RTC_CALRx registers are blocked.
|
||||
When the new calibration settings are taken into account, this Flag returns by hardware to <20>0<EFBFBD>. */
|
||||
RTC_FLAG_ALRAWF = ((uint16_t)0x0100) /*!< Alarm A write Flag. If set, Alarm A update is allowed */
|
||||
}
|
||||
RTC_Flag_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_IT_WUT = ((uint16_t)0x0040), /*!< Wake up Timer Interrupt */
|
||||
RTC_IT_ALRA = ((uint16_t)0x0010), /*!< Alarm A Interrupt */
|
||||
RTC_IT_TAMP = ((uint16_t)0x0F01) /*!< Tamper Interrupt */
|
||||
}
|
||||
RTC_IT_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Level
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_TamperLevel_Low = ((uint8_t)0x00), /*!< Tamper staying low triggers a tamper detection event. */
|
||||
RTC_TamperLevel_High = ((uint8_t)0x54) /*!< Tamper staying high triggers a tamper detection event. */
|
||||
}
|
||||
RTC_TamperLevel_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_State
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_TamperState_Disable = ((uint8_t)0x00), /*!< Tamper State is Disable */
|
||||
RTC_TamperState_Enable = ((uint8_t)0x01) /*!< Tamper State is Enable */
|
||||
}
|
||||
RTC_TamperState_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_Tamper_1 = ((uint8_t)0x02), /*!< Tamper 1 selection */
|
||||
RTC_Tamper_2 = ((uint8_t)0x08), /*!< Tamper 2 selection */
|
||||
RTC_Tamper_3 = ((uint8_t)0x20) /*!< Tamper 3 selection */
|
||||
}
|
||||
RTC_Tamper_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Precharge_Duration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_TamperPrechargeDuration_None = ((uint8_t)0x80), /*!< Tamper pins are not precharged before sampling */
|
||||
RTC_TamperPrechargeDuration_1RTCCLK = ((uint8_t)0x00), /*!< Tamper pins are precharged before sampling during 1 RTCCLK cycle */
|
||||
RTC_TamperPrechargeDuration_2RTCCLK = ((uint8_t)0x20), /*!< Tamper pins are precharged before sampling during 2 RTCCLK cycles */
|
||||
RTC_TamperPrechargeDuration_4RTCCLK = ((uint8_t)0x40), /*!< Tamper pins are precharged before sampling during 4 RTCCLK cycles */
|
||||
RTC_TamperPrechargeDuration_8RTCCLK = ((uint8_t)0x60) /*!< Tamper pins are precharged before sampling during 8 RTCCLK cycles */
|
||||
}
|
||||
RTC_TamperPrechargeDuration_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Filter
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_TamperFilter_1Sample = ((uint8_t)0x00), /*!< Tamper is activated after 1 sample at the active level */
|
||||
RTC_TamperFilter_2Sample = ((uint8_t)0x08), /*!< Tamper is activated after 2 consecutive samples at the active level. */
|
||||
RTC_TamperFilter_4Sample = ((uint8_t)0x10), /*!< Tamper is activated after 4 consecutive samples at the active level. */
|
||||
RTC_TamperFilter_8Sample = ((uint8_t)0x18) /*!< Tamper is activated after 8 consecutive samples at the active level. */
|
||||
}
|
||||
RTC_TamperFilter_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Sampling_Frequency
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_TamperSamplingFreq_RTCCLK_Div32768 = ((uint8_t)0x00), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 32768 */
|
||||
RTC_TamperSamplingFreq_RTCCLK_Div16384 = ((uint8_t)0x01), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 16384 */
|
||||
RTC_TamperSamplingFreq_RTCCLK_Div8192 = ((uint8_t)0x02), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 8192 */
|
||||
RTC_TamperSamplingFreq_RTCCLK_Div4096 = ((uint8_t)0x03), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 4096 */
|
||||
RTC_TamperSamplingFreq_RTCCLK_Div2048 = ((uint8_t)0x04), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 2048 */
|
||||
RTC_TamperSamplingFreq_RTCCLK_Div1024 = ((uint8_t)0x05), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 1024 */
|
||||
RTC_TamperSamplingFreq_RTCCLK_Div512 = ((uint8_t)0x06), /*!< Tamper inputs are sampled with a frequency = RTCCLK / 512 */
|
||||
RTC_TamperSamplingFreq_RTCCLK_Div256 = ((uint8_t)0x07) /*!< Tamper inputs are sampled with a frequency = RTCCLK / 256 */
|
||||
}
|
||||
RTC_TamperSamplingFreq_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Shift_Add_1s
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_ShiftAdd1S_Set = ((uint8_t)0x80), /*!< Add 1 Second */
|
||||
RTC_ShiftAdd1S_Reset = ((uint8_t)0x00) /*!< Do not Add 1 Second */
|
||||
}
|
||||
RTC_ShiftAdd1S_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_Calibration_Period
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_SmoothCalibPeriod_32sec = ((uint8_t)0x00), /*!< if RTCCLK = 32768 Hz, Smooth calibration period is 32s, else 2exp20 RTCCLK seconds */
|
||||
RTC_SmoothCalibPeriod_16sec = ((uint8_t)0x20), /*!< if RTCCLK = 32768 Hz, Smooth calibration period is 16s, else 2exp19 RTCCLK seconds */
|
||||
RTC_SmoothCalibPeriod_8sec = ((uint8_t)0x40) /*!< if RTCCLK = 32768 Hz, Smooth calibration period is 8s, else 2exp18 RTCCLK seconds */
|
||||
}
|
||||
RTC_SmoothCalibPeriod_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_Calibration_Pulses
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RTC_SmoothCalibPlusPulses_Set = ((uint8_t)0x80), /*!< The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0].
|
||||
with Y = 512, 256, 128 when X = 32, 16, 8 */
|
||||
RTC_SmoothCalibPlusPulses_Reset = ((uint8_t)0x00) /*!< The number of RTCCLK pulses substituted during a 32-second window = CALM[8:0]. */
|
||||
|
||||
}
|
||||
RTC_SmoothCalibPlusPulses_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief RTC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
RTC_HourFormat_TypeDef RTC_HourFormat; /*!< RTC Hour Format */
|
||||
|
||||
uint8_t RTC_AsynchPrediv; /*!< RTC Asynchronous Predivider.
|
||||
This parameter can be any value from
|
||||
0x00 to 0x7F.*/
|
||||
|
||||
uint16_t RTC_SynchPrediv; /*!< RTC Synchronous Predivider.
|
||||
This parameter can be any value from
|
||||
0x0000 to 0x7FFF.*/
|
||||
}
|
||||
RTC_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RTC_Hours; /*!< RTC Hours.
|
||||
If Binary format is selected :
|
||||
- If RTC_Hour format is RTC_Hour format_12,
|
||||
this parameter can be any value from 1 to 12.
|
||||
- If RTC_Hour format is RTC_Hour format_24,
|
||||
this parameter can be any value from 0 to 23.
|
||||
If BCD format is selected :
|
||||
- If RTC_Hour format is RTC_Hour format_12,
|
||||
this parameter can be any BCD value from
|
||||
0x01 to 0x12.
|
||||
- If RTC_Hour format is RTC_Hour format_24,
|
||||
this parameter can be any BCD value from
|
||||
0x00 to 0x23.*/
|
||||
uint8_t RTC_Minutes; /*!< RTC Minutes.
|
||||
If Binary format is selected, this parameter can
|
||||
be any value from 0 to 59.
|
||||
If BCD format is selected, this parameter can
|
||||
be any BCD value from 0x00 to 0x59.*/
|
||||
uint8_t RTC_Seconds; /*!< RTC Seconds.
|
||||
If Binary format is selected, this parameter can
|
||||
be any value from 0 to 59.
|
||||
If BCD format is selected, this parameter can
|
||||
be any BCD value from 0x00 to 0x59.*/
|
||||
RTC_H12_TypeDef RTC_H12; /*!< RTC 12-hour clock period (AM/PM) */
|
||||
}
|
||||
RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_Weekday_TypeDef RTC_WeekDay; /*!< The RTC Calender Weekday. */
|
||||
|
||||
RTC_Month_TypeDef RTC_Month; /*!< The RTC Calender Month. */
|
||||
|
||||
uint8_t RTC_Date; /*!< The RTC Calender Date.
|
||||
If Binary format is selected, this
|
||||
parameter can be any value from 1 to 31.
|
||||
If BCD format is selected, this parameter
|
||||
can be any BCD value from 0x01 to 0x31.*/
|
||||
|
||||
uint8_t RTC_Year; /*!< The RTC Calender Date.
|
||||
If Binary format is selected, this parameter
|
||||
can be any value from 0 to 99.
|
||||
If BCD format is selected, this parameter
|
||||
can be any BCD value from 0x00 to 0x99.*/
|
||||
}
|
||||
RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef RTC_AlarmTime; /*!< RTC Alarm Time */
|
||||
|
||||
uint8_t RTC_AlarmMask; /*!< The RTC Alarm Fields Masks. */
|
||||
|
||||
RTC_AlarmDateWeekDaySel_TypeDef RTC_AlarmDateWeekDaySel; /*!< The RTC Alarm Date/WeekDay selection. */
|
||||
|
||||
uint8_t RTC_AlarmDateWeekDay; /*!< The RTC Alarm Date/WeekDay value.
|
||||
- If RTC Alarm Date/WeekDay selection is Date
|
||||
and if If Binary format is selected, this
|
||||
parameter can be any value from 1 to 31.
|
||||
- If RTC Alarm Date/WeekDay selection is WeekDay,
|
||||
this parameter can be one of the
|
||||
@ref RTC_Weekday_TypeDef enumeration.*/
|
||||
}
|
||||
RTC_AlarmTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Calender Hour format
|
||||
*/
|
||||
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
|
||||
((FORMAT) == RTC_HourFormat_24))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Asynchronous Predivider
|
||||
*/
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Synchronous Predivider
|
||||
*/
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Calender Hours value (format 12h)
|
||||
*/
|
||||
#define IS_RTC_HOUR12_MAX(HOUR) ((HOUR) <= (uint8_t)12)
|
||||
#define IS_RTC_HOUR12_MIN(HOUR) ((HOUR) > (uint8_t)0)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Calender Hours value (format 24h)
|
||||
*/
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Calender minutes value
|
||||
*/
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Calender seconds value
|
||||
*/
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Calender H12 mode
|
||||
*/
|
||||
#define IS_RTC_H12(PM) (((PM) == (RTC_H12_AM)) || ((PM) == (RTC_H12_PM)))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Calender Year value
|
||||
*/
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Calender month value
|
||||
*/
|
||||
#define IS_RTC_MONTH_MAX(MONTH) ((MONTH) <= (uint8_t)12)
|
||||
#define IS_RTC_MONTH_MIN(MONTH) ((MONTH) >= (uint8_t)1)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Calender Date value
|
||||
*/
|
||||
#define IS_RTC_DATE_MAX(DATE) ((DATE) <= (uint8_t)31)
|
||||
#define IS_RTC_DATE_MIN(DATE) ((DATE) >= (uint8_t)1)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Calender Week day value
|
||||
*/
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Tuesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Wednesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Thursday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Friday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Saturday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Sunday))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Alarm Date/week day selection
|
||||
*/
|
||||
#define IS_RTC_ALARM_DATEWEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
|
||||
((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Alarm Mask
|
||||
*/
|
||||
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x0F) == (uint8_t)(RESET))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* wakeup clock source
|
||||
*/
|
||||
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
|
||||
((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
|
||||
((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Output selection
|
||||
*/
|
||||
#define IS_RTC_OUTPUT_SEL(SEL) (((SEL) == RTC_Output_Disable) || \
|
||||
((SEL) == RTC_Output_Alarm) || \
|
||||
((SEL) == RTC_Output_WakeUp))
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Output polarity
|
||||
*/
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
|
||||
((POL) == RTC_OutputPolarity_Low))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Daylight saving mode
|
||||
*/
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
|
||||
((SAVE) == RTC_DayLightSaving_ADD1H))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Store Operation status
|
||||
*/
|
||||
#define IS_RTC_STORE_OPERATION(OP) (((OP) == RTC_StoreOperation_Set) || \
|
||||
((OP) == RTC_StoreOperation_Reset))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* format (bin/bcd) for data user insert
|
||||
*/
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || \
|
||||
((FORMAT) == RTC_Format_BCD))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Flag to get
|
||||
*/
|
||||
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_WUTF) || \
|
||||
((FLAG) == RTC_FLAG_ALRAF) || \
|
||||
((FLAG) == RTC_FLAG_INITF) || \
|
||||
((FLAG) == RTC_FLAG_RSF) || \
|
||||
((FLAG) == RTC_FLAG_INITS) || \
|
||||
((FLAG) == RTC_FLAG_WUTWF) || \
|
||||
((FLAG) == RTC_FLAG_TAMP3F)|| \
|
||||
((FLAG) == RTC_FLAG_TAMP2F)|| \
|
||||
((FLAG) == RTC_FLAG_TAMP1F)|| \
|
||||
((FLAG) == RTC_FLAG_SHPF) || \
|
||||
((FLAG) == RTC_FLAG_RECALPF) || \
|
||||
((FLAG) == RTC_FLAG_ALRAWF))
|
||||
|
||||
/* RTC_FLAG_ALRAWF is for Medium Density only but supported by High Density
|
||||
Devices*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Flag to clear
|
||||
*/
|
||||
#define RTC_FLAG_CLRBLE (RTC_FLAG_RSF | RTC_FLAG_ALRAF | RTC_FLAG_WUTF| RTC_FLAG_TAMP1F|RTC_FLAG_TAMP2F|RTC_FLAG_TAMP3F)
|
||||
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != RESET) && ((uint16_t)((FLAG) & (uint16_t)(~(RTC_FLAG_CLRBLE))) == RESET))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Interrupt to configure
|
||||
*/
|
||||
#define IS_RTC_CONFIG_IT(IT) (((uint16_t)(IT) != (uint8_t)RESET) && ((uint16_t)((uint16_t)(IT) & (uint16_t)(~(uint16_t)(RTC_IT_WUT|RTC_IT_ALRA|RTC_IT_TAMP))) == (uint8_t)RESET))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Interrupt to get
|
||||
*/
|
||||
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_WUT) || \
|
||||
((IT) == RTC_IT_ALRA)|| \
|
||||
((IT) == RTC_IT_TAMP) )
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Interrupt to clear
|
||||
*/
|
||||
#define IS_RTC_CLEAR_IT(IT) (((IT) != RESET) && ((uint16_t)((IT) & (uint16_t)(~(uint16_t)(RTC_IT_WUT|RTC_IT_ALRA|RTC_IT_TAMP))) == RESET))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Tamper Levels
|
||||
*/
|
||||
#define IS_RTC_TAMPER_LEVEL(LEVEL) (((LEVEL) == RTC_TamperLevel_Low) || \
|
||||
((LEVEL) == RTC_TamperLevel_High))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Tamper
|
||||
*/
|
||||
#define NOT_CORRECT_TAMPER (uint8_t)~(uint8_t)( RTC_Tamper_1 | \
|
||||
RTC_Tamper_2 | \
|
||||
RTC_Tamper_3)
|
||||
#define IS_RTC_TAMPER(TAMPER) (((uint8_t)((TAMPER) & NOT_CORRECT_TAMPER) == RESET) && ((TAMPER) != RESET))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Tampers Filter
|
||||
*/
|
||||
#define IS_RTC_TAMPER_FILTER(SEL) (((SEL) == RTC_TamperFilter_1Sample) || \
|
||||
((SEL) == RTC_TamperFilter_2Sample) || \
|
||||
((SEL) == RTC_TamperFilter_4Sample) || \
|
||||
((SEL) == RTC_TamperFilter_8Sample))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Tampers Sampling Frequencies
|
||||
*/
|
||||
#define IS_RTC_TAMPER_SAMPLING_FREQ(SEL) ((SEL) <= RTC_TamperSamplingFreq_RTCCLK_Div256)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Tampers Pins precharge duration
|
||||
*/
|
||||
#define IS_RTC_TAMPER_PINS_PRECHAR_DURATION(SEL) (((SEL) == RTC_TamperPrechargeDuration_None) || \
|
||||
((SEL) == RTC_TamperPrechargeDuration_1RTCCLK) || \
|
||||
((SEL) == RTC_TamperPrechargeDuration_2RTCCLK) || \
|
||||
((SEL) == RTC_TamperPrechargeDuration_4RTCCLK) || \
|
||||
((SEL) == RTC_TamperPrechargeDuration_8RTCCLK))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Smooth calibration period
|
||||
*/
|
||||
#define IS_RTC_SMOOTH_CALIB_PERIOD(SEL) (((SEL) == RTC_SmoothCalibPeriod_32sec) || \
|
||||
((SEL) == RTC_SmoothCalibPeriod_16sec) || \
|
||||
((SEL) == RTC_SmoothCalibPeriod_8sec))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Smooth calibration Plus pulses
|
||||
*/
|
||||
#define IS_RTC_SMOOTH_CALIB_PLUS(SEL) (((SEL) == RTC_SmoothCalibPlusPulses_Set) || \
|
||||
((SEL) == RTC_SmoothCalibPlusPulses_Reset))
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Smooth calibration Minus pulses
|
||||
*/
|
||||
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x01FF)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Output Selection
|
||||
*/
|
||||
#define IS_RTC_OUTPUT_SELECT(SEL) (((SEL) == RTC_Output_Disable) || \
|
||||
((SEL) == RTC_Output_Alarm) || \
|
||||
((SEL) == RTC_Output_WakeUp))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the
|
||||
* used calibration Output Selection
|
||||
*/
|
||||
#define IS_RTC_CALOUTPUT_SELECT(SEL) (((SEL) == RTC_CalibOutput_512Hz) || \
|
||||
((SEL) == RTC_CalibOutput_1Hz))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Alarm sub second value
|
||||
*/
|
||||
#define IS_RTC_ALARM_SS_VALUE(SS) ((SS) <= 0x7FFF)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* Alarm sub second mask
|
||||
*/
|
||||
#define IS_RTC_ALARM_SS_MASK(MASK) ((MASK) <= 0x0F)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the used
|
||||
* fraction of seconds to sub
|
||||
*/
|
||||
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x7FFF)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the
|
||||
* parameter of 1 second to add
|
||||
*/
|
||||
#define IS_RTC_SHIFT_ADD1S(VAL) (((VAL) == RTC_ShiftAdd1S_Set) || \
|
||||
((VAL) == RTC_ShiftAdd1S_Reset))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the RTC configuration to the default reset state *****/
|
||||
ErrorStatus RTC_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
|
||||
void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
|
||||
void RTC_WriteProtectionCmd(FunctionalState NewState);
|
||||
ErrorStatus RTC_EnterInitMode(void);
|
||||
void RTC_ExitInitMode(void);
|
||||
ErrorStatus RTC_WaitForSynchro(void);
|
||||
void RTC_RatioCmd(FunctionalState NewState);
|
||||
void RTC_BypassShadowCmd(FunctionalState NewState);
|
||||
|
||||
/* Time and Date configuration functions **************************************/
|
||||
ErrorStatus RTC_SetTime(RTC_Format_TypeDef RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
void RTC_GetTime(RTC_Format_TypeDef RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
uint16_t RTC_GetSubSecond(void);
|
||||
ErrorStatus RTC_SetDate(RTC_Format_TypeDef RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
|
||||
void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
|
||||
void RTC_GetDate(RTC_Format_TypeDef RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
|
||||
|
||||
/* Alarm configuration functions *********************************************/
|
||||
void RTC_SetAlarm(RTC_Format_TypeDef RTC_Format, RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
void RTC_GetAlarm(RTC_Format_TypeDef RTC_Format, RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
ErrorStatus RTC_AlarmCmd(FunctionalState NewState);
|
||||
ErrorStatus RTC_AlarmSubSecondConfig(uint16_t RTC_AlarmSubSecondValue,
|
||||
RTC_AlarmSubSecondMask_TypeDef RTC_AlarmSubSecondMask);
|
||||
|
||||
/* WakeUp Timer configuration functions ***************************************/
|
||||
void RTC_WakeUpClockConfig(RTC_WakeUpClock_TypeDef RTC_WakeUpClock);
|
||||
void RTC_SetWakeUpCounter(uint16_t RTC_WakeupCounter);
|
||||
uint16_t RTC_GetWakeUpCounter(void);
|
||||
ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
|
||||
|
||||
/* Daylight Saving configuration functions ************************************/
|
||||
void RTC_DayLightSavingConfig(RTC_DayLightSaving_TypeDef RTC_DayLightSaving,
|
||||
RTC_StoreOperation_TypeDef RTC_StoreOperation);
|
||||
RTC_StoreOperation_TypeDef RTC_GetStoreOperation(void);
|
||||
|
||||
/* Output pin Configuration function ******************************************/
|
||||
void RTC_OutputConfig(RTC_Output_TypeDef RTC_Output,
|
||||
RTC_OutputPolarity_TypeDef RTC_OutputPolarity);
|
||||
|
||||
/* Shift control synchronisation function ************************************/
|
||||
ErrorStatus RTC_SynchroShiftConfig(RTC_ShiftAdd1S_TypeDef RTC_ShiftAdd1S,
|
||||
uint16_t RTC_ShiftSubFS);
|
||||
|
||||
/* Smooth Calibration functions **********************************************/
|
||||
ErrorStatus RTC_SmoothCalibConfig(RTC_SmoothCalibPeriod_TypeDef RTC_SmoothCalibPeriod,
|
||||
RTC_SmoothCalibPlusPulses_TypeDef RTC_SmoothCalibPlusPulses,
|
||||
uint16_t RTC_SmouthCalibMinusPulsesValue);
|
||||
|
||||
/* Calibration configuration functions ****************************************/
|
||||
void RTC_CalibOutputConfig(RTC_CalibOutput_TypeDef RTC_CalibOutput);
|
||||
void RTC_CalibOutputCmd(FunctionalState NewState);
|
||||
|
||||
/* Tampers configuration functions ********************************************/
|
||||
void RTC_TamperLevelConfig(RTC_Tamper_TypeDef RTC_Tamper,
|
||||
RTC_TamperLevel_TypeDef RTC_TamperLevel);
|
||||
void RTC_TamperFilterConfig(RTC_TamperFilter_TypeDef RTC_TamperFilter);
|
||||
void RTC_TamperSamplingFreqConfig(RTC_TamperSamplingFreq_TypeDef RTC_TamperSamplingFreq);
|
||||
void RTC_TamperPinsPrechargeDuration(RTC_TamperPrechargeDuration_TypeDef RTC_TamperPrechargeDuration);
|
||||
void RTC_TamperCmd(RTC_Tamper_TypeDef RTC_Tamper,
|
||||
FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RTC_ITConfig(RTC_IT_TypeDef RTC_IT, FunctionalState NewState);
|
||||
FlagStatus RTC_GetFlagStatus(RTC_Flag_TypeDef RTC_FLAG);
|
||||
void RTC_ClearFlag(RTC_Flag_TypeDef RTC_FLAG);
|
||||
ITStatus RTC_GetITStatus(RTC_IT_TypeDef RTC_IT);
|
||||
void RTC_ClearITPendingBit(RTC_IT_TypeDef RTC_IT);
|
||||
|
||||
#endif /*__STM8L15x_RTC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
404
firmware/inc/stm8l151x/inc/stm8l15x_spi.h
Normal file
404
firmware/inc/stm8l151x/inc/stm8l15x_spi.h
Normal file
@@ -0,0 +1,404 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the SPI firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_SPI_H
|
||||
#define __STM8L15x_SPI_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SPI_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Direction_Mode
|
||||
* @brief element values correspond to BDM, BDOE, RXONLY bits position
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
SPI_Direction_2Lines_FullDuplex = (uint8_t)0x00, /*!< 2-line uni-directional data mode enable */
|
||||
SPI_Direction_2Lines_RxOnly = (uint8_t)0x04, /*!< Receiver only in 2 line uni-directional data mode */
|
||||
SPI_Direction_1Line_Rx = (uint8_t)0x80, /*!< Receiver only in 1 line bi-directional data mode */
|
||||
SPI_Direction_1Line_Tx = (uint8_t)0xC0 /*!< Transmit only in 1 line bi-directional data mode */
|
||||
} SPI_DirectionMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_SlaveSelect_Management
|
||||
* @brief element values correspond to LSBFIRST bit position
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_NSS_Soft = (uint8_t)0x02, /*!< Software slave management disabled */
|
||||
SPI_NSS_Hard = (uint8_t)0x00 /*!< Software slave management enabled */
|
||||
} SPI_NSS_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Direction
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_Direction_Rx = (uint8_t)0x00, /*!< Select Rx receive direction in bi-directional mode */
|
||||
SPI_Direction_Tx = (uint8_t)0x01 /*!< Select Tx transmission direction in bi-directional mode */
|
||||
} SPI_Direction_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_Mode_Master = (uint8_t)0x04, /*!< SPI Master configuration */
|
||||
SPI_Mode_Slave = (uint8_t)0x00 /*!< SPI Slave configuration */
|
||||
} SPI_Mode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
SPI_BaudRatePrescaler_2 = (uint8_t)0x00, /*!< SPI frequency = frequency(CPU)/2 */
|
||||
SPI_BaudRatePrescaler_4 = (uint8_t)0x08, /*!< SPI frequency = frequency(CPU)/4 */
|
||||
SPI_BaudRatePrescaler_8 = (uint8_t)0x10, /*!< SPI frequency = frequency(CPU)/8 */
|
||||
SPI_BaudRatePrescaler_16 = (uint8_t)0x18, /*!< SPI frequency = frequency(CPU)/16 */
|
||||
SPI_BaudRatePrescaler_32 = (uint8_t)0x20, /*!< SPI frequency = frequency(CPU)/32 */
|
||||
SPI_BaudRatePrescaler_64 = (uint8_t)0x28, /*!< SPI frequency = frequency(CPU)/64 */
|
||||
SPI_BaudRatePrescaler_128 = (uint8_t)0x30, /*!< SPI frequency = frequency(CPU)/128 */
|
||||
SPI_BaudRatePrescaler_256 = (uint8_t)0x38 /*!< SPI frequency = frequency(CPU)/256 */
|
||||
} SPI_BaudRatePrescaler_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CPOL_Low = (uint8_t)0x00, /*!< Clock to 0 when idle */
|
||||
SPI_CPOL_High = (uint8_t)0x02 /*!< Clock to 1 when idle */
|
||||
} SPI_CPOL_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CPHA_1Edge = (uint8_t)0x00, /*!< The first clock transition is the first data capture edge */
|
||||
SPI_CPHA_2Edge = (uint8_t)0x01 /*!< The second clock transition is the first data capture edge */
|
||||
} SPI_CPHA_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Frame_Format
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_FirstBit_MSB = (uint8_t)0x00, /*!< MSB bit will be transmitted first */
|
||||
SPI_FirstBit_LSB = (uint8_t)0x80 /*!< LSB bit will be transmitted first */
|
||||
} SPI_FirstBit_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_DMA_requests
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
SPI_DMAReq_RX = (uint8_t)0x01, /*!< SPI DMA Rx transfer requests */
|
||||
SPI_DMAReq_TX = (uint8_t)0x02 /*!< SPI DMA Tx transfer requests */
|
||||
} SPI_DMAReq_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
SPI_CRC_RX = (uint8_t)0x00, /*!< Select Tx CRC register */
|
||||
SPI_CRC_TX = (uint8_t)0x01 /*!< Select Rx CRC register */
|
||||
} SPI_CRC_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Flags
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
SPI_FLAG_BSY = (uint8_t)0x80, /*!< Busy flag */
|
||||
SPI_FLAG_OVR = (uint8_t)0x40, /*!< Overrun flag */
|
||||
SPI_FLAG_MODF = (uint8_t)0x20, /*!< Mode fault */
|
||||
SPI_FLAG_CRCERR = (uint8_t)0x10, /*!< CRC error flag */
|
||||
SPI_FLAG_WKUP = (uint8_t)0x08, /*!< Wake-up flag */
|
||||
SPI_FLAG_TXE = (uint8_t)0x02, /*!< Transmit buffer empty */
|
||||
SPI_FLAG_RXNE = (uint8_t)0x01 /*!< Receive buffer empty */
|
||||
} SPI_FLAG_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Interrupts
|
||||
* @brief SPI_IT possible values
|
||||
* Elements values convention: 0xYX
|
||||
* X: Position of the corresponding Interrupt
|
||||
* Y: ITPENDINGBIT position
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_IT_WKUP = (uint8_t)0x34, /*!< Wake-up interrupt*/
|
||||
SPI_IT_OVR = (uint8_t)0x65, /*!< Overrun interrupt*/
|
||||
SPI_IT_MODF = (uint8_t)0x55, /*!< Mode fault interrupt*/
|
||||
SPI_IT_CRCERR = (uint8_t)0x45, /*!< CRC error interrupt*/
|
||||
SPI_IT_TXE = (uint8_t)0x17, /*!< Transmit buffer empty interrupt*/
|
||||
SPI_IT_RXNE = (uint8_t)0x06, /*!< Receive buffer not empty interrupt*/
|
||||
SPI_IT_ERR = (uint8_t)0x05 /*!< Error interrupt*/
|
||||
} SPI_IT_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SPI_Exported_Macros
|
||||
* @brief Macros used by the assert_param function to check the different functions parameters.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the data direction mode values
|
||||
*/
|
||||
#define IS_SPI_DATA_DIRECTION(Mode) (((Mode) == SPI_Direction_2Lines_FullDuplex) || \
|
||||
((Mode) == SPI_Direction_2Lines_RxOnly) || \
|
||||
((Mode) == SPI_Direction_1Line_Rx) || \
|
||||
((Mode) == SPI_Direction_1Line_Tx))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the mode half duplex data direction values
|
||||
*/
|
||||
#define IS_SPI_DIRECTION(Direction) (((Direction) == SPI_Direction_Rx) || \
|
||||
((Direction) == SPI_Direction_Tx))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the NSS management values
|
||||
*/
|
||||
#define IS_SPI_SLAVEMANAGEMENT(NSS) (((NSS) == SPI_NSS_Soft) || \
|
||||
((NSS) == SPI_NSS_Hard))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the different
|
||||
* sensitivity values for the CRC polynomial
|
||||
*/
|
||||
#define IS_SPI_CRC_POLYNOMIAL(Polynomial) ((Polynomial) > (uint8_t)0x00)
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the SPI Mode values
|
||||
*/
|
||||
#define IS_SPI_MODE(Mode) (((Mode) == SPI_Mode_Master) || \
|
||||
((Mode) == SPI_Mode_Slave))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the baudrate values
|
||||
*/
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(Prescaler) (((Prescaler) == SPI_BaudRatePrescaler_2) || \
|
||||
((Prescaler) == SPI_BaudRatePrescaler_4) || \
|
||||
((Prescaler) == SPI_BaudRatePrescaler_8) || \
|
||||
((Prescaler) == SPI_BaudRatePrescaler_16) || \
|
||||
((Prescaler) == SPI_BaudRatePrescaler_32) || \
|
||||
((Prescaler) == SPI_BaudRatePrescaler_64) || \
|
||||
((Prescaler) == SPI_BaudRatePrescaler_128) || \
|
||||
((Prescaler) == SPI_BaudRatePrescaler_256))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the polarity values
|
||||
*/
|
||||
#define IS_SPI_POLARITY(ClkPol) (((ClkPol) == SPI_CPOL_Low) || \
|
||||
((ClkPol) == SPI_CPOL_High))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the phase values
|
||||
*/
|
||||
#define IS_SPI_PHASE(ClkPha) (((ClkPha) == SPI_CPHA_1Edge) || \
|
||||
((ClkPha) == SPI_CPHA_2Edge))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the first bit
|
||||
* to be transmitted values
|
||||
*/
|
||||
#define IS_SPI_FIRSTBIT(Bit) (((Bit) == SPI_FirstBit_MSB) || \
|
||||
((Bit) == SPI_FirstBit_LSB))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the CRC Transmit/Receive
|
||||
*/
|
||||
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || \
|
||||
((CRC) == SPI_CRC_RX))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the DMA transfer requests
|
||||
*/
|
||||
#define IS_SPI_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the different flags values
|
||||
*/
|
||||
#define IS_SPI_FLAG(Flag) (((Flag) == SPI_FLAG_OVR) || \
|
||||
((Flag) == SPI_FLAG_MODF) || \
|
||||
((Flag) == SPI_FLAG_CRCERR) || \
|
||||
((Flag) == SPI_FLAG_WKUP) || \
|
||||
((Flag) == SPI_FLAG_TXE) || \
|
||||
((Flag) == SPI_FLAG_RXNE) || \
|
||||
((Flag) == SPI_FLAG_BSY))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the different
|
||||
* sensitivity values for the flag that can be cleared by writing 0
|
||||
*/
|
||||
#define IS_SPI_CLEAR_FLAG(Flag) (((Flag) == SPI_FLAG_CRCERR) || \
|
||||
((Flag) == SPI_FLAG_WKUP))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the different
|
||||
* sensitivity values for the Interrupts
|
||||
*/
|
||||
#define IS_SPI_CONFIG_IT(Interrupt) (((Interrupt) == SPI_IT_TXE) || \
|
||||
((Interrupt) == SPI_IT_RXNE) || \
|
||||
((Interrupt) == SPI_IT_ERR) || \
|
||||
((Interrupt) == SPI_IT_WKUP))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the different
|
||||
* sensitivity values for the pending bit
|
||||
*/
|
||||
#define IS_SPI_GET_IT(ITPendingBit) (((ITPendingBit) == SPI_IT_OVR) || \
|
||||
((ITPendingBit) == SPI_IT_MODF) || \
|
||||
((ITPendingBit) == SPI_IT_CRCERR) || \
|
||||
((ITPendingBit) == SPI_IT_WKUP) || \
|
||||
((ITPendingBit) == SPI_IT_TXE) || \
|
||||
((ITPendingBit) == SPI_IT_RXNE))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert_param function in order to check the different
|
||||
* sensitivity values for the pending bit that can be cleared by writing 0
|
||||
*/
|
||||
#define IS_SPI_CLEAR_IT(ITPendingBit) (((ITPendingBit) == SPI_IT_CRCERR) || \
|
||||
((ITPendingBit) == SPI_IT_WKUP))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the SPI configuration to the default reset state *****/
|
||||
void SPI_DeInit(SPI_TypeDef* SPIx);
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void SPI_Init(SPI_TypeDef* SPIx, SPI_FirstBit_TypeDef SPI_FirstBit,
|
||||
SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler,
|
||||
SPI_Mode_TypeDef SPI_Mode, SPI_CPOL_TypeDef SPI_CPOL,
|
||||
SPI_CPHA_TypeDef SPI_CPHA, SPI_DirectionMode_TypeDef SPI_Data_Direction,
|
||||
SPI_NSS_TypeDef SPI_Slave_Management, uint8_t CRCPolynomial);
|
||||
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_NSSInternalSoftwareCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, SPI_Direction_TypeDef SPI_Direction);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void SPI_SendData(SPI_TypeDef* SPIx, uint8_t Data);
|
||||
uint8_t SPI_ReceiveData(SPI_TypeDef* SPIx);
|
||||
|
||||
/* Hardware CRC Calculation functions *****************************************/
|
||||
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
|
||||
void SPI_CalculateCRCCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
uint8_t SPI_GetCRC(SPI_TypeDef* SPIx, SPI_CRC_TypeDef SPI_CRC);
|
||||
void SPI_ResetCRC(SPI_TypeDef* SPIx);
|
||||
uint8_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
|
||||
|
||||
/* DMA transfer management functions *****************************************/
|
||||
void SPI_DMACmd(SPI_TypeDef* SPIx, SPI_DMAReq_TypeDef SPI_DMAReq, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void SPI_ITConfig(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT, FunctionalState NewState);
|
||||
FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG);
|
||||
void SPI_ClearFlag(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG);
|
||||
ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT);
|
||||
void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT);
|
||||
|
||||
#endif /* __STM8L15x_SPI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
424
firmware/inc/stm8l151x/inc/stm8l15x_syscfg.h
Normal file
424
firmware/inc/stm8l151x/inc/stm8l15x_syscfg.h
Normal file
@@ -0,0 +1,424 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_syscfg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the SYSCFG firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_SYSCFG_H
|
||||
#define __STM8L15x_SYSCFG_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SYSCFG
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SYSCFG_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RI_Input_Capture
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RI_InputCapture_IC2 = ((uint8_t) 0x02), /*!< TIM1 Input Capture 2 is routed */
|
||||
RI_InputCapture_IC3 = ((uint8_t) 0x03) /*!< TIM1 Input Capture 3 is routed */
|
||||
}RI_InputCapture_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RI_Input_Capture_Routing
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RI_InputCaptureRouting_0 = ((uint8_t) 0x00), /*!< TIM1 IC2 is routed to PD4, IC3 to PD5 */
|
||||
RI_InputCaptureRouting_1 = ((uint8_t) 0x01), /*!< TIM1 IC2 is routed to PF0, IC3 to PF1 */
|
||||
RI_InputCaptureRouting_2 = ((uint8_t) 0x02), /*!< TIM1 IC2 is routed to PF2, IC3 to PF3 */
|
||||
RI_InputCaptureRouting_3 = ((uint8_t) 0x03), /*!< TIM1 IC2 is routed to PE0, IC3 to PE1 */
|
||||
RI_InputCaptureRouting_4 = ((uint8_t) 0x04), /*!< TIM1 IC2 is routed to PE2, IC3 to PE3 */
|
||||
RI_InputCaptureRouting_5 = ((uint8_t) 0x05), /*!< TIM1 IC2 is routed to PE4, IC3 to PE5 */
|
||||
RI_InputCaptureRouting_6 = ((uint8_t) 0x06), /*!< TIM1 IC2 is routed to PE6, IC3 to PE7 */
|
||||
RI_InputCaptureRouting_7 = ((uint8_t) 0x07), /*!< TIM1 IC2 is routed to PD0, IC3 to PD1 */
|
||||
RI_InputCaptureRouting_8 = ((uint8_t) 0x08), /*!< TIM1 IC2 is routed to PD2, IC3 to PD3 */
|
||||
RI_InputCaptureRouting_9 = ((uint8_t) 0x09), /*!< TIM1 IC2 is routed to PD4, IC3 to PD5 */
|
||||
RI_InputCaptureRouting_10 = ((uint8_t) 0x0A), /*!< TIM1 IC2 is routed to PD6, IC3 to PD7 */
|
||||
RI_InputCaptureRouting_11 = ((uint8_t) 0x0B), /*!< TIM1 IC2 is routed to PC0, IC3 to PC1 */
|
||||
RI_InputCaptureRouting_12 = ((uint8_t) 0x0C), /*!< TIM1 IC2 is routed to PC2, IC3 to PC3 */
|
||||
RI_InputCaptureRouting_13 = ((uint8_t) 0x0D), /*!< TIM1 IC2 is routed to PC4, IC3 to PC5 */
|
||||
RI_InputCaptureRouting_14 = ((uint8_t) 0x0E), /*!< TIM1 IC2 is routed to PC6, IC3 to PC7 */
|
||||
RI_InputCaptureRouting_15 = ((uint8_t) 0x0F), /*!< TIM1 IC2 is routed to PB0, IC3 to PB1 */
|
||||
RI_InputCaptureRouting_16 = ((uint8_t) 0x10), /*!< TIM1 IC2 is routed to PB2, IC3 to PB3 */
|
||||
RI_InputCaptureRouting_17 = ((uint8_t) 0x11), /*!< TIM1 IC2 is routed to PB4, IC3 to PB5 */
|
||||
RI_InputCaptureRouting_18 = ((uint8_t) 0x12), /*!< TIM1 IC2 is routed to PB6, IC3 to PB7 */
|
||||
RI_InputCaptureRouting_19 = ((uint8_t) 0x13), /*!< TIM1 IC2 is routed to PA0, IC3 to PA2 */
|
||||
RI_InputCaptureRouting_20 = ((uint8_t) 0x14), /*!< TIM1 IC2 is routed to PA3, IC3 to PA4 */
|
||||
RI_InputCaptureRouting_21 = ((uint8_t) 0x15), /*!< TIM1 IC2 is routed to PA5, IC3 to PA6 */
|
||||
RI_InputCaptureRouting_22 = ((uint8_t) 0x16) /*!< TIM1 IC2 is routed to PA7, IC3 to PD5 */
|
||||
}RI_InputCaptureRouting_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RI_Analog_Switch
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Definition of the Analog Switch to be controlled.
|
||||
* Values are coded in 0xXY format where
|
||||
* X: the register index (1: RI_ASCR1, 2: RI_ASCR2)
|
||||
* Y: the bit position which corresponds with the Analog Switch
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RI_AnalogSwitch_0 = ((uint8_t) 0x10), /*!< Analog switch 0 */
|
||||
RI_AnalogSwitch_1 = ((uint8_t) 0x11), /*!< Analog switch 1 */
|
||||
RI_AnalogSwitch_2 = ((uint8_t) 0x12), /*!< Analog switch 2 */
|
||||
RI_AnalogSwitch_3 = ((uint8_t) 0x13), /*!< Analog switch 3 */
|
||||
RI_AnalogSwitch_4 = ((uint8_t) 0x14), /*!< Analog switch 4 */
|
||||
RI_AnalogSwitch_5 = ((uint8_t) 0x15), /*!< Analog switch 5 */
|
||||
RI_AnalogSwitch_6 = ((uint8_t) 0x16), /*!< Analog switch 6 */
|
||||
RI_AnalogSwitch_7 = ((uint8_t) 0x17), /*!< Analog switch 7 */
|
||||
RI_AnalogSwitch_8 = ((uint8_t) 0x20), /*!< Analog switch 8 */
|
||||
RI_AnalogSwitch_9 = ((uint8_t) 0x21), /*!< Analog switch 9 */
|
||||
RI_AnalogSwitch_10 = ((uint8_t) 0x22), /*!< Analog switch 10 */
|
||||
RI_AnalogSwitch_11 = ((uint8_t) 0x23), /*!< Analog switch 11 */
|
||||
RI_AnalogSwitch_14 = ((uint8_t) 0x26) /*!< Analog switch 14 */
|
||||
}RI_AnalogSwitch_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RI_IO_Switch
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Definition of the I/O Switch to be controlled.
|
||||
* Values are coded in 0xXY format where
|
||||
* X: the register index (1: RI_IOSR1, 2: RI_IOSR2, 3: RI_IOSR3 or 4: RI_IOSR4)
|
||||
* Y: the bit index of the Input Output Switch in RI_IOSRx register
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RI_IOSwitch_1 = ((uint8_t) 0x10), /*!< Input Output Switch switch 1 */
|
||||
RI_IOSwitch_2 = ((uint8_t) 0x20), /*!< Input Output Switch switch 2 */
|
||||
RI_IOSwitch_3 = ((uint8_t) 0x30), /*!< Input Output Switch switch 3 */
|
||||
RI_IOSwitch_4 = ((uint8_t) 0x11), /*!< Input Output Switch switch 4 */
|
||||
RI_IOSwitch_5 = ((uint8_t) 0x21), /*!< Input Output Switch switch 4 */
|
||||
RI_IOSwitch_6 = ((uint8_t) 0x31), /*!< Input Output Switch switch 6 */
|
||||
RI_IOSwitch_7 = ((uint8_t) 0x12), /*!< Input Output Switch switch 7 */
|
||||
RI_IOSwitch_8 = ((uint8_t) 0x22), /*!< Input Output Switch switch 8 */
|
||||
RI_IOSwitch_9 = ((uint8_t) 0x32), /*!< Input Output Switch switch 9 */
|
||||
RI_IOSwitch_10 = ((uint8_t) 0x13), /*!< Input Output Switch switch 10 */
|
||||
RI_IOSwitch_11 = ((uint8_t) 0x23), /*!< Input Output Switch switch 11 */
|
||||
RI_IOSwitch_12 = ((uint8_t) 0x33), /*!< Input Output Switch switch 12 */
|
||||
RI_IOSwitch_13 = ((uint8_t) 0x14), /*!< Input Output Switch switch 13 */
|
||||
RI_IOSwitch_14 = ((uint8_t) 0x24), /*!< Input Output Switch switch 14 */
|
||||
RI_IOSwitch_15 = ((uint8_t) 0x34), /*!< Input Output Switch switch 15 */
|
||||
RI_IOSwitch_16 = ((uint8_t) 0x15), /*!< Input Output Switch switch 16 */
|
||||
RI_IOSwitch_17 = ((uint8_t) 0x25), /*!< Input Output Switch switch 17 */
|
||||
RI_IOSwitch_18 = ((uint8_t) 0x35), /*!< Input Output Switch switch 18 */
|
||||
RI_IOSwitch_19 = ((uint8_t) 0x16), /*!< Input Output Switch switch 19 */
|
||||
RI_IOSwitch_20 = ((uint8_t) 0x26), /*!< Input Output Switch switch 20 */
|
||||
RI_IOSwitch_21 = ((uint8_t) 0x36), /*!< Input Output Switch switch 21 */
|
||||
RI_IOSwitch_22 = ((uint8_t) 0x17), /*!< Input Output Switch switch 22 */
|
||||
RI_IOSwitch_23 = ((uint8_t) 0x27), /*!< Input Output Switch switch 23 */
|
||||
RI_IOSwitch_24 = ((uint8_t) 0x37), /*!< Input Output Switch switch 24 */
|
||||
RI_IOSwitch_26 = ((uint8_t) 0x41), /*!< Input Output Switch switch 26 */
|
||||
RI_IOSwitch_27 = ((uint8_t) 0x46), /*!< Input Output Switch switch 27 */
|
||||
RI_IOSwitch_28 = ((uint8_t) 0x47), /*!< Input Output Switch switch 28 */
|
||||
RI_IOSwitch_29 = ((uint8_t) 0x40) /*!< Input Output Switch switch 29 */
|
||||
}RI_IOSwitch_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RI_Resistor
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Definition of the pull-up and pull-down resistors for COMP1 and ADC.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RI_Resistor_10KPU = ((uint8_t) 0x01),
|
||||
RI_Resistor_400KPU = ((uint8_t) 0x02),
|
||||
RI_Resistor_10KPD = ((uint8_t) 0x04),
|
||||
RI_Resistor_400KPD = ((uint8_t) 0x08)
|
||||
}RI_Resistor_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup REMAP_Pin
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Definition of the REMAP pins.
|
||||
* Elements values convention: 0xXY
|
||||
* X = RMPCRx registers index
|
||||
* X = 0x01 : RMPCR1
|
||||
* X = 0x02 : RMPCR2
|
||||
* X = 0x03 : RMPCR3
|
||||
* Y = Mask for setting/resetting bits in RMPCRx register
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/* RMPCR1 register bits */
|
||||
REMAP_Pin_USART1TxRxPortA = ((uint16_t)0x011C), /*!< USART1 Tx- Rx (PC3- PC2) remapping to PA2- PA3 */
|
||||
REMAP_Pin_USART1TxRxPortC = ((uint16_t)0x012C), /*!< USART1 Tx- Rx (PC3- PC2) remapping to PC5- PC6 */
|
||||
REMAP_Pin_USART1Clk = ((uint16_t)0x014B), /*!< USART1 CK (PC4) remapping to PA0 */
|
||||
REMAP_Pin_SPI1Full = ((uint16_t)0x0187), /*!< SPI1 MISO- MOSI- SCK- NSS(PB7- PB6- PB5- PB4)
|
||||
remapping to PA2- PA3- PC6- PC5 */
|
||||
/* RMPCR2 register bits */
|
||||
REMAP_Pin_ADC1ExtTRIG1 = ((uint16_t)0x0201), /*!< ADC1 External Trigger 1 (PA6) remapping to PD0 */
|
||||
REMAP_Pin_TIM2TRIGPortA = ((uint16_t)0x0202), /*!< TIM2 Trigger (PB3) remapping to PA4 */
|
||||
REMAP_Pin_TIM3TRIGPortA = ((uint16_t)0x0204), /*!< TIM3 Trigger (PD1) remapping to PA5 */
|
||||
REMAP_Pin_TIM2TRIGLSE = ((uint16_t)0x0208), /*!< TIM2 Trigger remapping to LSE */
|
||||
REMAP_Pin_TIM3TRIGLSE = ((uint16_t)0x0210), /*!< TIM3 Trigger remapping to LSE */
|
||||
REMAP_Pin_SPI2Full = ((uint16_t)0x0220), /*!< SPI2 MISO- MOSI- SCK- NSS(PG7- PG6- PG5- PG4)
|
||||
remapping to PI3- PI2- PI1- PI0 */
|
||||
REMAP_Pin_TIM3TRIGPortG = ((uint16_t)0x0240), /*!< TIM3 Trigger (PD1) remapping to PG3 */
|
||||
REMAP_Pin_TIM23BKIN = ((uint16_t)0x0280), /*!< TIM2 Break Input (PA4) remapping to PG0
|
||||
and TIM3 Break Input (PA5) remapping to PG1 */
|
||||
/* RMPCR3 register bits */
|
||||
REMAP_Pin_SPI1PortF = ((uint16_t)0x0301), /*!< SPI1 MISO- MOSI- SCK- NSS(PB7- PB6- PB5- PB4)
|
||||
remapping to PF0- PF1- PF2- PF3 */
|
||||
REMAP_Pin_USART3TxRxPortF = ((uint16_t)0x0302), /*!< USART3 Tx- Rx (PG1- PG0) remapping to PF0- PF1 */
|
||||
REMAP_Pin_USART3Clk = ((uint16_t)0x0304), /*!< USART3 CK (PG2) remapping to PF2 */
|
||||
REMAP_Pin_TIM3Channel1 = ((uint16_t)0x0308), /*!< TIM3 Channel 1 (PB1) remapping to PI0 */
|
||||
REMAP_Pin_TIM3Channel2 = ((uint16_t)0x0310), /*!< TIM3 Channel 2 (PD0) remapping to PI3 */
|
||||
REMAP_Pin_CCO = ((uint16_t)0x0320), /*!< CCO (PC4) remapping to PE2 */
|
||||
REMAP_Pin_TIM2Channel1 = ((uint16_t)0x0340), /*!< TIM2 Channel 1 (PB0) remapping to PC5 */
|
||||
REMAP_Pin_TIM2Channel2 = ((uint16_t)0x0380) /*!< TIM2 Channel 2 (PB2) remapping to PC6 */
|
||||
}REMAP_Pin_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup REMAP_DMA_Channel
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
REMAP_DMA1Channel_ADC1ToChannel0 = ((uint8_t)0x00), /*!< ADC1 DMA1 req/ack mapped on DMA1 channel 0 */
|
||||
REMAP_DMA1Channel_ADC1ToChannel1 = ((uint8_t)0x01), /*!< ADC1 DMA1 req/ack mapped on DMA1 channel 1 */
|
||||
REMAP_DMA1Channel_ADC1ToChannel2 = ((uint8_t)0x02), /*!< ADC1 DMA1 req/ack mapped on DMA1 channel 2 */
|
||||
REMAP_DMA1Channel_ADC1ToChannel3 = ((uint8_t)0x03), /*!< ADC1 DMA1 req/ack mapped on DMA1 channel 3 */
|
||||
REMAP_DMA1Channel_TIM4ToChannel0 = ((uint8_t)0xF0), /*!< TIM4 DMA1 req/ack mapped on DMA1 channel 0 */
|
||||
REMAP_DMA1Channel_TIM4ToChannel1 = ((uint8_t)0xF4), /*!< TIM4 DMA1 req/ack mapped on DMA1 channel 1 */
|
||||
REMAP_DMA1Channel_TIM4ToChannel2 = ((uint8_t)0xF8), /*!< TIM4 DMA1 req/ack mapped on DMA1 channel 2 */
|
||||
REMAP_DMA1Channel_TIM4ToChannel3 = ((uint8_t)0xFC) /*!< TIM4 DMA1 req/ack mapped on DMA1 channel 3 */
|
||||
}REMAP_DMAChannel_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup SYSCFG_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* values of @ref RI_InputCaptureTypeDef enum.
|
||||
*/
|
||||
#define IS_RI_INPUTCAPTURE(RI_IC) (((RI_IC) == RI_InputCapture_IC2) || \
|
||||
((RI_IC) == RI_InputCapture_IC3))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* values of @ref RI_InputCaptureRoutingTypeDef enum.
|
||||
*/
|
||||
#define IS_RI_INPUTCAPTUREROUTING(RI_IC_ROUTING) (((RI_IC_ROUTING) == RI_InputCaptureRouting_0) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_1) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_2) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_3) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_4) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_5) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_6) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_7) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_8) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_9) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_10) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_11) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_12) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_13) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_14) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_15) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_16) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_17) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_18) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_19) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_20) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_21) || \
|
||||
((RI_IC_ROUTING) == RI_InputCaptureRouting_22))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* values of @ref RI_AnalogSwitch_TypeDef enum.
|
||||
*/
|
||||
#define IS_RI_ANALOGSWITCH(RI_ANALOGSWITCH) (((RI_ANALOGSWITCH) == RI_AnalogSwitch_0) || \
|
||||
((RI_ANALOGSWITCH) == RI_AnalogSwitch_1) || \
|
||||
((RI_ANALOGSWITCH) == RI_AnalogSwitch_2) || \
|
||||
((RI_ANALOGSWITCH) == RI_AnalogSwitch_3) || \
|
||||
((RI_ANALOGSWITCH) == RI_AnalogSwitch_4) || \
|
||||
((RI_ANALOGSWITCH) == RI_AnalogSwitch_5) || \
|
||||
((RI_ANALOGSWITCH) == RI_AnalogSwitch_6) || \
|
||||
((RI_ANALOGSWITCH) == RI_AnalogSwitch_7) || \
|
||||
((RI_ANALOGSWITCH) == RI_AnalogSwitch_8) || \
|
||||
((RI_ANALOGSWITCH) == RI_AnalogSwitch_9) || \
|
||||
((RI_ANALOGSWITCH) == RI_AnalogSwitch_10)|| \
|
||||
((RI_ANALOGSWITCH) == RI_AnalogSwitch_11)|| \
|
||||
((RI_ANALOGSWITCH) == RI_AnalogSwitch_14))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* values of @ref RI_IOSwitch_TypeDef enum.
|
||||
*/
|
||||
#define IS_RI_IOSWITCH(RI_IOSWITCH) (((RI_IOSWITCH) == RI_IOSwitch_1) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_2) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_3) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_4) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_5) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_6) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_7) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_8) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_9) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_10) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_11) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_12) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_13) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_14) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_15) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_16) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_17) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_18) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_19) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_20) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_21) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_22) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_23) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_24) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_26) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_27) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_28) || \
|
||||
((RI_IOSWITCH) == RI_IOSwitch_29))
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* values of @ref RI_ResistorTypeDef enum.
|
||||
*/
|
||||
#define IS_RI_RESISTOR(RI_RESISTOR) (((RI_RESISTOR) == RI_Resistor_10KPU) || \
|
||||
((RI_RESISTOR) == RI_Resistor_400KPU) || \
|
||||
((RI_RESISTOR) == RI_Resistor_10KPD) || \
|
||||
((RI_RESISTOR) == RI_Resistor_400KPD))
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* values of @ref REMAP_Pin_TypeDef enum.
|
||||
*/
|
||||
#define IS_REMAP_PIN(PIN) (((PIN) == REMAP_Pin_USART1TxRxPortA) || \
|
||||
((PIN) == REMAP_Pin_USART1TxRxPortC) || \
|
||||
((PIN) == REMAP_Pin_USART1Clk) || \
|
||||
((PIN) == REMAP_Pin_SPI1Full) || \
|
||||
((PIN) == REMAP_Pin_ADC1ExtTRIG1) || \
|
||||
((PIN) == REMAP_Pin_TIM2TRIGPortA) || \
|
||||
((PIN) == REMAP_Pin_TIM3TRIGPortA) || \
|
||||
((PIN) == REMAP_Pin_TIM2TRIGLSE) || \
|
||||
((PIN) == REMAP_Pin_TIM3TRIGLSE) || \
|
||||
((PIN) == REMAP_Pin_SPI2Full) || \
|
||||
((PIN) == REMAP_Pin_TIM3TRIGPortG) || \
|
||||
((PIN) == REMAP_Pin_TIM23BKIN) || \
|
||||
((PIN) == REMAP_Pin_SPI1PortF) || \
|
||||
((PIN) == REMAP_Pin_USART3TxRxPortF) || \
|
||||
((PIN) == REMAP_Pin_USART3Clk) || \
|
||||
((PIN) == REMAP_Pin_TIM3Channel1) || \
|
||||
((PIN) == REMAP_Pin_TIM3Channel2) || \
|
||||
((PIN) == REMAP_Pin_CCO) || \
|
||||
((PIN) == REMAP_Pin_TIM2Channel1) || \
|
||||
((PIN) == REMAP_Pin_TIM2Channel2))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function in order to check the different
|
||||
* values of the @ref REMAP_DMAChannel_TypeDef enum.
|
||||
*/
|
||||
#define IS_REMAP_DMACHANNEL(MAP) (((MAP) == REMAP_DMA1Channel_ADC1ToChannel0) || \
|
||||
((MAP) == REMAP_DMA1Channel_ADC1ToChannel1) || \
|
||||
((MAP) == REMAP_DMA1Channel_ADC1ToChannel2) || \
|
||||
((MAP) == REMAP_DMA1Channel_ADC1ToChannel3) || \
|
||||
((MAP) == REMAP_DMA1Channel_TIM4ToChannel0) || \
|
||||
((MAP) == REMAP_DMA1Channel_TIM4ToChannel1) || \
|
||||
((MAP) == REMAP_DMA1Channel_TIM4ToChannel2) || \
|
||||
((MAP) == REMAP_DMA1Channel_TIM4ToChannel3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Routing Interface (RI) configuration ***************************************/
|
||||
void SYSCFG_RIDeInit(void);
|
||||
void SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_TypeDef RI_InputCapture,
|
||||
RI_InputCaptureRouting_TypeDef RI_InputCaptureRouting);
|
||||
void SYSCFG_RIAnalogSwitchConfig(RI_AnalogSwitch_TypeDef RI_AnalogSwitch,
|
||||
FunctionalState NewState);
|
||||
void SYSCFG_RIIOSwitchConfig(RI_IOSwitch_TypeDef RI_IOSwitch, FunctionalState NewState);
|
||||
void SYSCFG_RIResistorConfig(RI_Resistor_TypeDef RI_Resistor, FunctionalState NewState);
|
||||
|
||||
/* SYSCFG configuration *******************************************************/
|
||||
void SYSCFG_REMAPDeInit(void);
|
||||
void SYSCFG_REMAPPinConfig(REMAP_Pin_TypeDef REMAP_Pin, FunctionalState NewState);
|
||||
void SYSCFG_REMAPDMAChannelConfig(REMAP_DMAChannel_TypeDef REMAP_DMAChannel);
|
||||
|
||||
#endif /* __STM8L15x_SYSCFG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
1044
firmware/inc/stm8l151x/inc/stm8l15x_tim1.h
Normal file
1044
firmware/inc/stm8l151x/inc/stm8l15x_tim1.h
Normal file
File diff suppressed because it is too large
Load Diff
905
firmware/inc/stm8l151x/inc/stm8l15x_tim2.h
Normal file
905
firmware/inc/stm8l151x/inc/stm8l15x_tim2.h
Normal file
@@ -0,0 +1,905 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_tim2.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the TIM2 firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_TIM2_H
|
||||
#define __STM8L15x_TIM2_H
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TIM2_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Forced_Action
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_ForcedAction_Active = ((uint8_t)0x50), /*!< Output Reference is forced low */
|
||||
TIM2_ForcedAction_Inactive = ((uint8_t)0x40) /*!< Output Reference is forced high */
|
||||
}
|
||||
TIM2_ForcedAction_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_Prescaler_1 = ((uint8_t)0x00), /*!< Time base Prescaler = 1 (No effect)*/
|
||||
TIM2_Prescaler_2 = ((uint8_t)0x01), /*!< Time base Prescaler = 2 */
|
||||
TIM2_Prescaler_4 = ((uint8_t)0x02), /*!< Time base Prescaler = 4 */
|
||||
TIM2_Prescaler_8 = ((uint8_t)0x03), /*!< Time base Prescaler = 8 */
|
||||
TIM2_Prescaler_16 = ((uint8_t)0x04), /*!< Time base Prescaler = 16 */
|
||||
TIM2_Prescaler_32 = ((uint8_t)0x05), /*!< Time base Prescaler = 32 */
|
||||
TIM2_Prescaler_64 = ((uint8_t)0x06), /*!< Time base Prescaler = 64 */
|
||||
TIM2_Prescaler_128 = ((uint8_t)0x07) /*!< Time base Prescaler = 128 */
|
||||
}TIM2_Prescaler_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_OCMode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_OCMode_Timing = ((uint8_t)0x00), /*!< Timing (Frozen) Mode*/
|
||||
TIM2_OCMode_Active = ((uint8_t)0x10), /*!< Active Mode*/
|
||||
TIM2_OCMode_Inactive = ((uint8_t)0x20), /*!< Inactive Mode*/
|
||||
TIM2_OCMode_Toggle = ((uint8_t)0x30), /*!< Toggle Mode*/
|
||||
TIM2_OCMode_PWM1 = ((uint8_t)0x60), /*!< PWM Mode 1*/
|
||||
TIM2_OCMode_PWM2 = ((uint8_t)0x70) /*!< PWM Mode 2*/
|
||||
}TIM2_OCMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_OnePulseMode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_OPMode_Single = ((uint8_t)0x01), /*!< Single one Pulse mode (OPM Active) */
|
||||
TIM2_OPMode_Repetitive = ((uint8_t)0x00) /*!< Repetitive Pulse mode (OPM inactive) */
|
||||
}TIM2_OPMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Channel
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_Channel_1 = ((uint8_t)0x00), /*!< Channel 1*/
|
||||
TIM2_Channel_2 = ((uint8_t)0x01) /*!< Channel 2*/
|
||||
}TIM2_Channel_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_CounterMode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_CounterMode_Up = ((uint8_t)0x00), /*!< Counter Up Mode */
|
||||
TIM2_CounterMode_Down = ((uint8_t)0x10), /*!< Counter Down Mode */
|
||||
TIM2_CounterMode_CenterAligned1 = ((uint8_t)0x20), /*!< Counter Central aligned Mode 1 */
|
||||
TIM2_CounterMode_CenterAligned2 = ((uint8_t)0x40), /*!< Counter Central aligned Mode 2 */
|
||||
TIM2_CounterMode_CenterAligned3 = ((uint8_t)0x60) /*!< Counter Central aligned Mode 3 */
|
||||
}TIM2_CounterMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Output_Compare_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_OCPolarity_High = ((uint8_t)0x00), /*!< Output compare polarity = High */
|
||||
TIM2_OCPolarity_Low = ((uint8_t)0x01) /*!< Output compare polarity = Low */
|
||||
}TIM2_OCPolarity_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Output_State
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_OutputState_Disable = ((uint8_t)0x00), /*!< Output compare State disabled (channel output disabled) */
|
||||
TIM2_OutputState_Enable = ((uint8_t)0x01) /*!< Output compare State enabled (channel output enabled) */
|
||||
}TIM2_OutputState_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Break_State
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_BreakState_Disable = ((uint8_t)0x00), /*!< Break State disabled (break option disabled) */
|
||||
TIM2_BreakState_Enable = ((uint8_t)0x10) /*!< Break State enabled (break option enabled) */
|
||||
|
||||
}TIM2_BreakState_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Break_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_BreakPolarity_High = ((uint8_t)0x20), /*!< if Break, channel polarity = High */
|
||||
TIM2_BreakPolarity_Low = ((uint8_t)0x00) /*!< if Break, channel polarity = Low */
|
||||
|
||||
}TIM2_BreakPolarity_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Automatic_Output
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_AutomaticOutput_Enable = ((uint8_t)0x40), /*!< Automatic Output option enabled */
|
||||
TIM2_AutomaticOutput_Disable = ((uint8_t)0x00) /*!< Automatic Output option disabled */
|
||||
}TIM2_AutomaticOutput_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Lock_Level
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_LockLevel_Off = ((uint8_t)0x00), /*!< Lock option disabled */
|
||||
TIM2_LockLevel_1 = ((uint8_t)0x01), /*!< Select Lock Level 1 */
|
||||
TIM2_LockLevel_2 = ((uint8_t)0x02), /*!< Select Lock Level 2 */
|
||||
TIM2_LockLevel_3 = ((uint8_t)0x03) /*!< Select Lock Level 3 */
|
||||
}TIM2_LockLevel_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_OSSI_State
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_OSSIState_Enable = ((uint8_t)0x04), /*!< Off-State Selection for Idle mode enabled */
|
||||
TIM2_OSSIState_Disable = ((uint8_t)0x00) /*!< Off-State Selection for Idle mode disabled */
|
||||
}TIM2_OSSIState_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Output_Compare_Idle_state
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_OCIdleState_Reset = ((uint8_t)0x00), /*!< Output Compare Idle state = Reset */
|
||||
TIM2_OCIdleState_Set = ((uint8_t)0x01) /*!< Output Compare Idle state = Set */
|
||||
}TIM2_OCIdleState_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Input_Capture_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_ICPolarity_Rising = ((uint8_t)0x00), /*!< Input Capture on Rising Edge*/
|
||||
TIM2_ICPolarity_Falling = ((uint8_t)0x01) /*!< Input Capture on Falling Edge*/
|
||||
}TIM2_ICPolarity_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Input_Capture_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_ICSelection_DirectTI = ((uint8_t)0x01), /*!< Input Capture mapped on the direct input*/
|
||||
TIM2_ICSelection_IndirectTI = ((uint8_t)0x02), /*!< Input Capture mapped on the indirect input*/
|
||||
TIM2_ICSelection_TRGI = ((uint8_t)0x03) /*!< Input Capture mapped on the Trigger Input*/
|
||||
}TIM2_ICSelection_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Input_Capture_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_ICPSC_DIV1 = ((uint8_t)0x00), /*!< Input Capture Prescaler = 1 (one capture every 1 event) */
|
||||
TIM2_ICPSC_DIV2 = ((uint8_t)0x04), /*!< Input Capture Prescaler = 2 (one capture every 2 events) */
|
||||
TIM2_ICPSC_DIV4 = ((uint8_t)0x08), /*!< Input Capture Prescaler = 4 (one capture every 4 events) */
|
||||
TIM2_ICPSC_DIV8 = ((uint8_t)0x0C) /*!< Input Capture Prescaler = 8 (one capture every 8 events) */
|
||||
}TIM2_ICPSC_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Interrupts
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_IT_Update = ((uint8_t)0x01), /*!< Update Interrupt*/
|
||||
TIM2_IT_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Interrupt*/
|
||||
TIM2_IT_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Interrupt*/
|
||||
TIM2_IT_Trigger = ((uint8_t)0x40), /*!< Trigger Interrupt*/
|
||||
TIM2_IT_Break = ((uint8_t)0x80) /*!< Break Interrupt*/
|
||||
}TIM2_IT_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_External_Trigger_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_ExtTRGPSC_OFF = ((uint8_t)0x00), /*!< No External Trigger prescaler */
|
||||
TIM2_ExtTRGPSC_DIV2 = ((uint8_t)0x10), /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */
|
||||
TIM2_ExtTRGPSC_DIV4 = ((uint8_t)0x20), /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */
|
||||
TIM2_ExtTRGPSC_DIV8 = ((uint8_t)0x30) /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */
|
||||
}TIM2_ExtTRGPSC_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Internal_Trigger_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_TRGSelection_TIM4 = ((uint8_t)0x00), /*!< TRIG Input source = TIM TRIG Output */
|
||||
TIM2_TRGSelection_TIM1 = ((uint8_t)0x10), /*!< TRIG Input source = TIM TRIG Output */
|
||||
TIM2_TRGSelection_TIM3 = ((uint8_t)0x20), /*!< TRIG Input source = TIM TRIG Output */
|
||||
TIM2_TRGSelection_TIM5 = ((uint8_t)0x30), /*!< TRIG Input source = TIM TRIG Output */
|
||||
TIM2_TRGSelection_TI1F_ED = ((uint8_t)0x40), /*!< TRIG Input source = TI1F_ED (TI1 Edge Detector) */
|
||||
TIM2_TRGSelection_TI1FP1 = ((uint8_t)0x50), /*!< TRIG Input source = TI1FP1 (Filtered Timer Input 1) */
|
||||
TIM2_TRGSelection_TI2FP2 = ((uint8_t)0x60), /*!< TRIG Input source = TI2FP2 (Filtered Timer Input 2) */
|
||||
TIM2_TRGSelection_ETRF = ((uint8_t)0x70) /*!< TRIG Input source = ETRF (External Trigger Input ) */
|
||||
}TIM2_TRGSelection_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_TI_External_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_TIxExternalCLK1Source_TI1ED = ((uint8_t)0x40), /*!< External Clock mode 1 source = TI1ED */
|
||||
TIM2_TIxExternalCLK1Source_TI1 = ((uint8_t)0x50), /*!< External Clock mode 1 source = TI1 */
|
||||
TIM2_TIxExternalCLK1Source_TI2 = ((uint8_t)0x60) /*!< External Clock mode 1 source = TI2 */
|
||||
}TIM2_TIxExternalCLK1Source_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_External_Trigger_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_ExtTRGPolarity_Inverted = ((uint8_t)0x80), /*!< External Trigger Polarity = inverted */
|
||||
TIM2_ExtTRGPolarity_NonInverted = ((uint8_t)0x00) /*!< External Trigger Polarity = non inverted */
|
||||
}TIM2_ExtTRGPolarity_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Prescaler_Reload_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_PSCReloadMode_Update = ((uint8_t)0x00), /*!< Prescaler value is reloaded at every update*/
|
||||
TIM2_PSCReloadMode_Immediate = ((uint8_t)0x01) /*!< Prescaler value is reloaded immediatly*/
|
||||
}TIM2_PSCReloadMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Encoder_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_EncoderMode_TI1 = ((uint8_t)0x01), /*!< Encoder mode 1*/
|
||||
TIM2_EncoderMode_TI2 = ((uint8_t)0x02), /*!< Encoder mode 2*/
|
||||
TIM2_EncoderMode_TI12 = ((uint8_t)0x03) /*!< Encoder mode 3*/
|
||||
}TIM2_EncoderMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Event_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_EventSource_Update = ((uint8_t)0x01), /*!< Update Event*/
|
||||
TIM2_EventSource_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Event*/
|
||||
TIM2_EventSource_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Event*/
|
||||
TIM2_EventSource_Trigger = ((uint8_t)0x40), /*!< Trigger Event*/
|
||||
TIM2_EventSource_Break = ((uint8_t)0x80) /*!< Break Event*/
|
||||
}TIM2_EventSource_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Update_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_UpdateSource_Global = ((uint8_t)0x00), /*!< Global Update request source */
|
||||
TIM2_UpdateSource_Regular = ((uint8_t)0x01) /*!< Regular Update request source */
|
||||
}TIM2_UpdateSource_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Trigger_Output_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_TRGOSource_Reset = ((uint8_t)0x00), /*!< Trigger Output source = Reset*/
|
||||
TIM2_TRGOSource_Enable = ((uint8_t)0x10), /*!< Trigger Output source = TIM2 is enabled*/
|
||||
TIM2_TRGOSource_Update = ((uint8_t)0x20), /*!< Trigger Output source = Update event*/
|
||||
TIM2_TRGOSource_OC1 = ((uint8_t)0x30), /*!< Trigger Output source = output compare channel1 */
|
||||
TIM2_TRGOSource_OC1REF = ((uint8_t)0x40), /*!< Trigger Output source = output compare channel 1 reference */
|
||||
TIM2_TRGOSource_OC2REF = ((uint8_t)0x50) /*!< Trigger Output source = output compare channel 2 reference */
|
||||
}TIM2_TRGOSource_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Slave_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_SlaveMode_Reset = ((uint8_t)0x04), /*!< Slave Mode Selection = Reset*/
|
||||
TIM2_SlaveMode_Gated = ((uint8_t)0x05), /*!< Slave Mode Selection = Gated*/
|
||||
TIM2_SlaveMode_Trigger = ((uint8_t)0x06), /*!< Slave Mode Selection = Trigger*/
|
||||
TIM2_SlaveMode_External1 = ((uint8_t)0x07) /*!< Slave Mode Selection = External 1*/
|
||||
}TIM2_SlaveMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_Flags
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_FLAG_Update = ((uint16_t)0x0001), /*!< Update Flag */
|
||||
TIM2_FLAG_CC1 = ((uint16_t)0x0002), /*!< Capture compare 1 Flag */
|
||||
TIM2_FLAG_CC2 = ((uint16_t)0x0004), /*!< Capture compare 2 Flag */
|
||||
TIM2_FLAG_Trigger = ((uint16_t)0x0040), /*!< Trigger Flag */
|
||||
TIM2_FLAG_Break = ((uint16_t)0x0080), /*!< Break Flag */
|
||||
TIM2_FLAG_CC1OF = ((uint16_t)0x0200), /*!< Capture compare 1 over capture Flag */
|
||||
TIM2_FLAG_CC2OF = ((uint16_t)0x0400) /*!< Capture compare 2 over capture Flag */
|
||||
}TIM2_FLAG_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM2_DMA_Source_Requests
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM2_DMASource_Update = ((uint8_t)0x01), /*!< TIM2 DMA Update Request*/
|
||||
TIM2_DMASource_CC1 = ((uint8_t)0x02), /*!< TIM2 DMA CC1 Request*/
|
||||
TIM2_DMASource_CC2 = ((uint8_t)0x04) /*!< TIM2 DMA CC2 Request*/
|
||||
}TIM2_DMASource_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TIM2_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different functions parameters.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 Forced Action
|
||||
*/
|
||||
#define IS_TIM2_FORCED_ACTION(ACTION) \
|
||||
(((ACTION) == TIM2_ForcedAction_Active) || \
|
||||
((ACTION) == TIM2_ForcedAction_Inactive))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 Prescaler
|
||||
*/
|
||||
#define IS_TIM2_PRESCALER(PRESCALER) \
|
||||
(((PRESCALER) == TIM2_Prescaler_1) || \
|
||||
((PRESCALER) == TIM2_Prescaler_2) || \
|
||||
((PRESCALER) == TIM2_Prescaler_4) || \
|
||||
((PRESCALER) == TIM2_Prescaler_8) || \
|
||||
((PRESCALER) == TIM2_Prescaler_16) || \
|
||||
((PRESCALER) == TIM2_Prescaler_32) || \
|
||||
((PRESCALER) == TIM2_Prescaler_64) || \
|
||||
((PRESCALER) == TIM2_Prescaler_128))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 Output Compare and PWM modes
|
||||
*/
|
||||
#define IS_TIM2_OC_MODE(MODE) \
|
||||
(((MODE) == TIM2_OCMode_Timing) || \
|
||||
((MODE) == TIM2_OCMode_Active) || \
|
||||
((MODE) == TIM2_OCMode_Inactive) || \
|
||||
((MODE) == TIM2_OCMode_Toggle) || \
|
||||
((MODE) == TIM2_OCMode_PWM1) || \
|
||||
((MODE) == TIM2_OCMode_PWM2))
|
||||
|
||||
#define IS_TIM2_OCM(MODE) \
|
||||
(((MODE) == TIM2_OCMode_Timing) || \
|
||||
((MODE) == TIM2_OCMode_Active) || \
|
||||
((MODE) == TIM2_OCMode_Inactive) || \
|
||||
((MODE) == TIM2_OCMode_Toggle) || \
|
||||
((MODE) == TIM2_OCMode_PWM1) || \
|
||||
((MODE) == TIM2_OCMode_PWM2) || \
|
||||
((MODE) == (uint8_t)TIM2_ForcedAction_Active) || \
|
||||
((MODE) == (uint8_t)TIM2_ForcedAction_Inactive))
|
||||
/**
|
||||
* @brief Macro TIM2 One Pulse Mode
|
||||
*/
|
||||
#define IS_TIM2_OPM_MODE(MODE) \
|
||||
(((MODE) == TIM2_OPMode_Single) || \
|
||||
((MODE) == TIM2_OPMode_Repetitive))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 Channel
|
||||
*/
|
||||
#define IS_TIM2_CHANNEL(CHANNEL) \
|
||||
(((CHANNEL) == TIM2_Channel_1) || \
|
||||
((CHANNEL) == TIM2_Channel_2) )
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 Counter Mode
|
||||
*/
|
||||
#define IS_TIM2_COUNTER_MODE(MODE) \
|
||||
(((MODE) == TIM2_CounterMode_Up) || \
|
||||
((MODE) == TIM2_CounterMode_Down) || \
|
||||
((MODE) == TIM2_CounterMode_CenterAligned1) || \
|
||||
((MODE) == TIM2_CounterMode_CenterAligned2) || \
|
||||
((MODE) == TIM2_CounterMode_CenterAligned3))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 Output Compare Polarity
|
||||
*/
|
||||
#define IS_TIM2_OC_POLARITY(POLARITY) \
|
||||
(((POLARITY) == TIM2_OCPolarity_High) || \
|
||||
((POLARITY) == TIM2_OCPolarity_Low))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 Output Compare states
|
||||
*/
|
||||
#define IS_TIM2_OUTPUT_STATE(STATE) \
|
||||
(((STATE) == TIM2_OutputState_Disable) || \
|
||||
((STATE) == TIM2_OutputState_Enable))
|
||||
|
||||
/**
|
||||
* @brief Macro Break Input enable/disable
|
||||
*/
|
||||
#define IS_TIM2_BREAK_STATE(STATE) \
|
||||
(((STATE) == TIM2_BreakState_Enable) || \
|
||||
((STATE) == TIM2_BreakState_Disable))
|
||||
|
||||
/**
|
||||
* @brief Macro Break Polarity
|
||||
*/
|
||||
#define IS_TIM2_BREAK_POLARITY(POLARITY) \
|
||||
(((POLARITY) == TIM2_BreakPolarity_Low) || \
|
||||
((POLARITY) == TIM2_BreakPolarity_High))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 AOE Bit Set/Reset
|
||||
*/
|
||||
#define IS_TIM2_AUTOMATIC_OUTPUT_STATE(STATE) \
|
||||
(((STATE) == TIM2_AutomaticOutput_Enable) || \
|
||||
((STATE) == TIM2_AutomaticOutput_Disable))
|
||||
|
||||
/**
|
||||
* @brief Macro Lock levels
|
||||
*/
|
||||
#define IS_TIM2_LOCK_LEVEL(LEVEL) \
|
||||
(((LEVEL) == TIM2_LockLevel_Off) || \
|
||||
((LEVEL) == TIM2_LockLevel_1) || \
|
||||
((LEVEL) == TIM2_LockLevel_2) || \
|
||||
((LEVEL) == TIM2_LockLevel_3))
|
||||
|
||||
/**
|
||||
* @brief Macro OSSI: Off-State Selection for Idle mode states
|
||||
*/
|
||||
#define IS_TIM2_OSSI_STATE(STATE) \
|
||||
(((STATE) == TIM2_OSSIState_Enable) || \
|
||||
((STATE) == TIM2_OSSIState_Disable))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 OC IDLE STATE
|
||||
*/
|
||||
#define IS_TIM2_OCIDLE_STATE(STATE) \
|
||||
(((STATE) == TIM2_OCIdleState_Set) || \
|
||||
((STATE) == TIM2_OCIdleState_Reset))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 IC POLARITY
|
||||
*/
|
||||
|
||||
#define IS_TIM2_IC_POLARITY(POLARITY) \
|
||||
(((POLARITY) == TIM2_ICPolarity_Rising) || \
|
||||
((POLARITY) == TIM2_ICPolarity_Falling))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 IC SELECTION
|
||||
*/
|
||||
#define IS_TIM2_IC_SELECTION(SELECTION) \
|
||||
(((SELECTION) == TIM2_ICSelection_DirectTI) || \
|
||||
((SELECTION) == TIM2_ICSelection_IndirectTI) || \
|
||||
((SELECTION) == TIM2_ICSelection_TRGI))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 IC PRESCALER
|
||||
*/
|
||||
#define IS_TIM2_IC_PRESCALER(PRESCALER) \
|
||||
(((PRESCALER) == TIM2_ICPSC_DIV1) || \
|
||||
((PRESCALER) == TIM2_ICPSC_DIV2) || \
|
||||
((PRESCALER) == TIM2_ICPSC_DIV4) || \
|
||||
((PRESCALER) == TIM2_ICPSC_DIV8))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 Input Capture Filter Value
|
||||
*/
|
||||
#define IS_TIM2_IC_FILTER(ICFILTER) \
|
||||
((ICFILTER) <= 0x0F)
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 Interrupts
|
||||
*/
|
||||
#define IS_TIM2_IT(IT) \
|
||||
((IT) != 0x00)
|
||||
|
||||
#define IS_TIM2_GET_IT(IT) \
|
||||
(((IT) == TIM2_IT_Update) || \
|
||||
((IT) == TIM2_IT_CC1) || \
|
||||
((IT) == TIM2_IT_CC2) || \
|
||||
((IT) == TIM2_IT_Trigger) || \
|
||||
((IT) == TIM2_IT_Break))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 external trigger prescaler
|
||||
*/
|
||||
#define IS_TIM2_EXT_PRESCALER(PRESCALER) \
|
||||
(((PRESCALER) == TIM2_ExtTRGPSC_OFF) || \
|
||||
((PRESCALER) == TIM2_ExtTRGPSC_DIV2) || \
|
||||
((PRESCALER) == TIM2_ExtTRGPSC_DIV4) || \
|
||||
((PRESCALER) == TIM2_ExtTRGPSC_DIV8))
|
||||
/**
|
||||
* @brief Macro TIM2 Trigger Selection
|
||||
*/
|
||||
#define IS_TIM2_TRIGGER_SELECTION(SELECTION) \
|
||||
(((SELECTION) == TIM2_TRGSelection_TIM4) || \
|
||||
((SELECTION) == TIM2_TRGSelection_TIM1) || \
|
||||
((SELECTION) == TIM2_TRGSelection_TIM3) || \
|
||||
((SELECTION) == TIM2_TRGSelection_TIM5) || \
|
||||
((SELECTION) == TIM2_TRGSelection_TI1F_ED) || \
|
||||
((SELECTION) == TIM2_TRGSelection_TI1FP1) || \
|
||||
((SELECTION) == TIM2_TRGSelection_TI2FP2) || \
|
||||
((SELECTION) == TIM2_TRGSelection_ETRF))
|
||||
|
||||
|
||||
#define IS_TIM2_TIX_TRIGGER_SELECTION(SELECTION) \
|
||||
(((SELECTION) == TIM2_TRGSelection_TI1F_ED) || \
|
||||
((SELECTION) == TIM2_TRGSelection_TI1FP1) || \
|
||||
((SELECTION) == TIM2_TRGSelection_TI2FP2))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 TIx external Clock Selection
|
||||
*/
|
||||
#define IS_TIM2_TIXCLK_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM2_TIxExternalCLK1Source_TI1ED) || \
|
||||
((SOURCE) == TIM2_TIxExternalCLK1Source_TI2) || \
|
||||
((SOURCE) == TIM2_TIxExternalCLK1Source_TI1))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 Trigger Polarity
|
||||
*/
|
||||
#define IS_TIM2_EXT_POLARITY(POLARITY) \
|
||||
(((POLARITY) == TIM2_ExtTRGPolarity_Inverted) || \
|
||||
((POLARITY) == TIM2_ExtTRGPolarity_NonInverted))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 External Trigger Filter
|
||||
*/
|
||||
#define IS_TIM2_EXT_FILTER(EXTFILTER) \
|
||||
((EXTFILTER) <= 0x0F)
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 Prescaler Reload
|
||||
*/
|
||||
#define IS_TIM2_PRESCALER_RELOAD(RELOAD) \
|
||||
(((RELOAD) == TIM2_PSCReloadMode_Update) || \
|
||||
((RELOAD) == TIM2_PSCReloadMode_Immediate))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 encoder mode
|
||||
*/
|
||||
#define IS_TIM2_ENCODER_MODE(MODE) \
|
||||
(((MODE) == TIM2_EncoderMode_TI1) || \
|
||||
((MODE) == TIM2_EncoderMode_TI2) || \
|
||||
((MODE) == TIM2_EncoderMode_TI12))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 event source
|
||||
*/
|
||||
#define IS_TIM2_EVENT_SOURCE(SOURCE) \
|
||||
((((SOURCE) & (uint8_t)0x18) == 0x00) && \
|
||||
((SOURCE) != 0x00))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 update source
|
||||
*/
|
||||
#define IS_TIM2_UPDATE_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM2_UpdateSource_Global) || \
|
||||
((SOURCE) == TIM2_UpdateSource_Regular))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 TRGO source
|
||||
*/
|
||||
#define IS_TIM2_TRGO_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM2_TRGOSource_Reset) || \
|
||||
((SOURCE) == TIM2_TRGOSource_Enable) || \
|
||||
((SOURCE) == TIM2_TRGOSource_Update) || \
|
||||
((SOURCE) == TIM2_TRGOSource_OC1) || \
|
||||
((SOURCE) == TIM2_TRGOSource_OC1REF) || \
|
||||
((SOURCE) == TIM2_TRGOSource_OC2REF))
|
||||
/**
|
||||
* @brief Macro TIM2 Slave mode
|
||||
*/
|
||||
#define IS_TIM2_SLAVE_MODE(MODE) \
|
||||
(((MODE) == TIM2_SlaveMode_Reset) || \
|
||||
((MODE) == TIM2_SlaveMode_Gated) || \
|
||||
((MODE) == TIM2_SlaveMode_Trigger) || \
|
||||
((MODE) == TIM2_SlaveMode_External1))
|
||||
/**
|
||||
* @brief Macro TIM2 Flags
|
||||
*/
|
||||
#define IS_TIM2_GET_FLAG(FLAG) \
|
||||
(((FLAG) == TIM2_FLAG_Update) || \
|
||||
((FLAG) == TIM2_FLAG_CC1) || \
|
||||
((FLAG) == TIM2_FLAG_CC2) || \
|
||||
((FLAG) == TIM2_FLAG_Trigger) || \
|
||||
((FLAG) == TIM2_FLAG_Break) || \
|
||||
((FLAG) == TIM2_FLAG_CC1OF) || \
|
||||
((FLAG) == TIM2_FLAG_CC2OF))
|
||||
|
||||
#define IS_TIM2_CLEAR_FLAG(FLAG) \
|
||||
((((FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM2 DMA sources
|
||||
*/
|
||||
|
||||
#define IS_TIM2_DMA_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM2_DMASource_Update) || \
|
||||
((SOURCE) == TIM2_DMASource_CC1) || \
|
||||
((SOURCE) == TIM2_DMASource_CC2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* TimeBase management ********************************************************/
|
||||
void TIM2_DeInit(void);
|
||||
void TIM2_TimeBaseInit(TIM2_Prescaler_TypeDef TIM2_Prescaler,
|
||||
TIM2_CounterMode_TypeDef TIM2_CounterMode, uint16_t TIM2_Period);
|
||||
void TIM2_PrescalerConfig(TIM2_Prescaler_TypeDef Prescaler,
|
||||
TIM2_PSCReloadMode_TypeDef TIM2_PSCReloadMode);
|
||||
void TIM2_CounterModeConfig(TIM2_CounterMode_TypeDef TIM2_CounterMode);
|
||||
void TIM2_SetCounter(uint16_t Counter);
|
||||
void TIM2_SetAutoreload(uint16_t Autoreload);
|
||||
uint16_t TIM2_GetCounter(void);
|
||||
TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void);
|
||||
void TIM2_UpdateDisableConfig(FunctionalState NewState);
|
||||
void TIM2_UpdateRequestConfig(TIM2_UpdateSource_TypeDef TIM2_UpdateSource);
|
||||
void TIM2_ARRPreloadConfig(FunctionalState NewState);
|
||||
void TIM2_SelectOnePulseMode(TIM2_OPMode_TypeDef TIM2_OPMode);
|
||||
void TIM2_Cmd(FunctionalState NewState);
|
||||
|
||||
/* Output Compare management **************************************************/
|
||||
void TIM2_OC1Init(TIM2_OCMode_TypeDef TIM2_OCMode,
|
||||
TIM2_OutputState_TypeDef TIM2_OutputState,
|
||||
uint16_t TIM2_Pulse,
|
||||
TIM2_OCPolarity_TypeDef TIM2_OCPolarity,
|
||||
TIM2_OCIdleState_TypeDef TIM2_OCIdleState);
|
||||
void TIM2_OC2Init(TIM2_OCMode_TypeDef TIM2_OCMode,
|
||||
TIM2_OutputState_TypeDef TIM2_OutputState,
|
||||
uint16_t TIM2_Pulse,
|
||||
TIM2_OCPolarity_TypeDef TIM2_OCPolarity,
|
||||
TIM2_OCIdleState_TypeDef TIM2_OCIdleState);
|
||||
void TIM2_BKRConfig(TIM2_OSSIState_TypeDef TIM2_OSSIState,
|
||||
TIM2_LockLevel_TypeDef TIM2_LockLevel,
|
||||
TIM2_BreakState_TypeDef TIM2_BreakState,
|
||||
TIM2_BreakPolarity_TypeDef TIM2_BreakPolarity,
|
||||
TIM2_AutomaticOutput_TypeDef TIM2_AutomaticOutput);
|
||||
void TIM2_CtrlPWMOutputs(FunctionalState NewState);
|
||||
void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode);
|
||||
void TIM2_SetCompare1(uint16_t Compare);
|
||||
void TIM2_SetCompare2(uint16_t Compare);
|
||||
void TIM2_ForcedOC1Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);
|
||||
void TIM2_ForcedOC2Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction);
|
||||
void TIM2_OC1PreloadConfig(FunctionalState NewState);
|
||||
void TIM2_OC2PreloadConfig(FunctionalState NewState);
|
||||
void TIM2_OC1FastConfig(FunctionalState NewState);
|
||||
void TIM2_OC2FastConfig(FunctionalState NewState);
|
||||
void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
|
||||
void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity);
|
||||
void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState);
|
||||
|
||||
/* Input Capture management ***************************************************/
|
||||
void TIM2_ICInit(TIM2_Channel_TypeDef TIM2_Channel,
|
||||
TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
|
||||
TIM2_ICSelection_TypeDef TIM2_ICSelection,
|
||||
TIM2_ICPSC_TypeDef TIM2_ICPrescaler,
|
||||
uint8_t TIM2_ICFilter);
|
||||
void TIM2_PWMIConfig(TIM2_Channel_TypeDef TIM2_Channel,
|
||||
TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
|
||||
TIM2_ICSelection_TypeDef TIM2_ICSelection,
|
||||
TIM2_ICPSC_TypeDef TIM2_ICPrescaler,
|
||||
uint8_t TIM2_ICFilter);
|
||||
uint16_t TIM2_GetCapture1(void);
|
||||
uint16_t TIM2_GetCapture2(void);
|
||||
void TIM2_SetIC1Prescaler(TIM2_ICPSC_TypeDef TIM2_IC1Prescaler);
|
||||
void TIM2_SetIC2Prescaler(TIM2_ICPSC_TypeDef TIM2_IC2Prescaler);
|
||||
|
||||
/* Interrupts, DMA and flags management ***************************************/
|
||||
void TIM2_ITConfig(TIM2_IT_TypeDef TIM2_IT, FunctionalState NewState);
|
||||
void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource);
|
||||
FlagStatus TIM2_GetFlagStatus(TIM2_FLAG_TypeDef TIM2_FLAG);
|
||||
void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG);
|
||||
ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT);
|
||||
void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT);
|
||||
void TIM2_DMACmd(TIM2_DMASource_TypeDef TIM2_DMASource, FunctionalState NewState);
|
||||
void TIM2_SelectCCDMA(FunctionalState NewState);
|
||||
|
||||
/* Clocks management **********************************************************/
|
||||
void TIM2_InternalClockConfig(void);
|
||||
void TIM2_TIxExternalClockConfig(TIM2_TIxExternalCLK1Source_TypeDef TIM2_TIxExternalCLKSource,
|
||||
TIM2_ICPolarity_TypeDef TIM2_ICPolarity,
|
||||
uint8_t ICFilter);
|
||||
void TIM2_ETRClockMode1Config(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
|
||||
TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
|
||||
uint8_t ExtTRGFilter);
|
||||
void TIM2_ETRClockMode2Config(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
|
||||
TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
|
||||
uint8_t ExtTRGFilter);
|
||||
|
||||
/* Synchronization management *************************************************/
|
||||
void TIM2_SelectInputTrigger(TIM2_TRGSelection_TypeDef TIM2_InputTriggerSource);
|
||||
void TIM2_SelectOutputTrigger(TIM2_TRGOSource_TypeDef TIM2_TRGOSource);
|
||||
void TIM2_SelectSlaveMode(TIM2_SlaveMode_TypeDef TIM2_SlaveMode);
|
||||
void TIM2_SelectMasterSlaveMode(FunctionalState NewState);
|
||||
void TIM2_ETRConfig(TIM2_ExtTRGPSC_TypeDef TIM2_ExtTRGPrescaler,
|
||||
TIM2_ExtTRGPolarity_TypeDef TIM2_ExtTRGPolarity,
|
||||
uint8_t ExtTRGFilter);
|
||||
|
||||
/* Specific interface management **********************************************/
|
||||
void TIM2_EncoderInterfaceConfig(TIM2_EncoderMode_TypeDef TIM2_EncoderMode,
|
||||
TIM2_ICPolarity_TypeDef TIM2_IC1Polarity,
|
||||
TIM2_ICPolarity_TypeDef TIM2_IC2Polarity);
|
||||
void TIM2_SelectHallSensor(FunctionalState NewState);
|
||||
|
||||
#endif /* __STM8L15x_TIM2_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
909
firmware/inc/stm8l151x/inc/stm8l15x_tim3.h
Normal file
909
firmware/inc/stm8l151x/inc/stm8l15x_tim3.h
Normal file
@@ -0,0 +1,909 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_tim3.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the TIM3 firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_TIM3_H
|
||||
#define __STM8L15x_TIM3_H
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @defgroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TIM3_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Forced_Action
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_ForcedAction_Active = ((uint8_t)0x50), /*!< Output Reference is forced low */
|
||||
TIM3_ForcedAction_Inactive = ((uint8_t)0x40) /*!< Output Reference is forced high */
|
||||
}
|
||||
TIM3_ForcedAction_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_Prescaler_1 = ((uint8_t)0x00), /*!< Time base Prescaler = 1 (No effect)*/
|
||||
TIM3_Prescaler_2 = ((uint8_t)0x01), /*!< Time base Prescaler = 2 */
|
||||
TIM3_Prescaler_4 = ((uint8_t)0x02), /*!< Time base Prescaler = 4 */
|
||||
TIM3_Prescaler_8 = ((uint8_t)0x03), /*!< Time base Prescaler = 8 */
|
||||
TIM3_Prescaler_16 = ((uint8_t)0x04), /*!< Time base Prescaler = 16 */
|
||||
TIM3_Prescaler_32 = ((uint8_t)0x05), /*!< Time base Prescaler = 32 */
|
||||
TIM3_Prescaler_64 = ((uint8_t)0x06), /*!< Time base Prescaler = 64 */
|
||||
TIM3_Prescaler_128 = ((uint8_t)0x07) /*!< Time base Prescaler = 128 */
|
||||
}TIM3_Prescaler_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_OCMode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_OCMode_Timing = ((uint8_t)0x00), /*!< Timing (Frozen) Mode*/
|
||||
TIM3_OCMode_Active = ((uint8_t)0x10), /*!< Active Mode*/
|
||||
TIM3_OCMode_Inactive = ((uint8_t)0x20), /*!< Inactive Mode*/
|
||||
TIM3_OCMode_Toggle = ((uint8_t)0x30), /*!< Toggle Mode*/
|
||||
TIM3_OCMode_PWM1 = ((uint8_t)0x60), /*!< PWM Mode 1*/
|
||||
TIM3_OCMode_PWM2 = ((uint8_t)0x70) /*!< PWM Mode 2*/
|
||||
}TIM3_OCMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_OnePulseMode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_OPMode_Single = ((uint8_t)0x01), /*!< Single one Pulse mode (OPM Active) */
|
||||
TIM3_OPMode_Repetitive = ((uint8_t)0x00) /*!< Repetitive Pulse mode (OPM inactive) */
|
||||
}TIM3_OPMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Channel
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_Channel_1 = ((uint8_t)0x00), /*!< Channel 1*/
|
||||
TIM3_Channel_2 = ((uint8_t)0x01) /*!< Channel 2*/
|
||||
}TIM3_Channel_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_CounterMode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_CounterMode_Up = ((uint8_t)0x00), /*!< Counter Up Mode */
|
||||
TIM3_CounterMode_Down = ((uint8_t)0x10), /*!< Counter Down Mode */
|
||||
TIM3_CounterMode_CenterAligned1 = ((uint8_t)0x20), /*!< Counter Central aligned Mode 1 */
|
||||
TIM3_CounterMode_CenterAligned2 = ((uint8_t)0x40), /*!< Counter Central aligned Mode 2 */
|
||||
TIM3_CounterMode_CenterAligned3 = ((uint8_t)0x60) /*!< Counter Central aligned Mode 3 */
|
||||
}TIM3_CounterMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Output_Compare_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_OCPolarity_High = ((uint8_t)0x00), /*!< Output compare polarity = High */
|
||||
TIM3_OCPolarity_Low = ((uint8_t)0x01) /*!< Output compare polarity = Low */
|
||||
}TIM3_OCPolarity_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Output_State
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_OutputState_Disable = ((uint8_t)0x00), /*!< Output compare State disabled
|
||||
(channel output disabled) */
|
||||
TIM3_OutputState_Enable = ((uint8_t)0x01) /*!< Output compare State enabled
|
||||
(channel output enabled) */
|
||||
}TIM3_OutputState_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Break_State
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_BreakState_Disable = ((uint8_t)0x00), /*!< Break State disabled (break option disabled) */
|
||||
TIM3_BreakState_Enable = ((uint8_t)0x10) /*!< Break State enabled (break option enabled) */
|
||||
}TIM3_BreakState_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Break_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_BreakPolarity_High = ((uint8_t)0x20), /*!< if Break, channel polarity = High */
|
||||
TIM3_BreakPolarity_Low = ((uint8_t)0x00) /*!< if Break, channel polarity = Low */
|
||||
}TIM3_BreakPolarity_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Automatic_Output
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_AutomaticOutput_Enable = ((uint8_t)0x40), /*!< Automatic Output option enabled */
|
||||
TIM3_AutomaticOutput_Disable = ((uint8_t)0x00) /*!< Automatic Output option disabled */
|
||||
}TIM3_AutomaticOutput_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Lock_Level
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_LockLevel_Off = ((uint8_t)0x00), /*!< Lock option disabled */
|
||||
TIM3_LockLevel_1 = ((uint8_t)0x01), /*!< Select Lock Level 1 */
|
||||
TIM3_LockLevel_2 = ((uint8_t)0x02), /*!< Select Lock Level 2 */
|
||||
TIM3_LockLevel_3 = ((uint8_t)0x03) /*!< Select Lock Level 3 */
|
||||
}TIM3_LockLevel_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_OSSI_State
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_OSSIState_Enable = ((uint8_t)0x04), /*!< Off-State Selection for Idle mode enabled */
|
||||
TIM3_OSSIState_Disable = ((uint8_t)0x00) /*!< Off-State Selection for Idle mode disabled */
|
||||
}TIM3_OSSIState_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Output_Compare_Idle_state
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_OCIdleState_Reset = ((uint8_t)0x00), /*!< Output Compare Idle state = Reset */
|
||||
TIM3_OCIdleState_Set = ((uint8_t)0x01) /*!< Output Compare Idle state = Set */
|
||||
}TIM3_OCIdleState_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Input_Capture_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_ICPolarity_Rising = ((uint8_t)0x00), /*!< Input Capture on Rising Edge*/
|
||||
TIM3_ICPolarity_Falling = ((uint8_t)0x01) /*!< Input Capture on Falling Edge*/
|
||||
}TIM3_ICPolarity_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Input_Capture_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_ICSelection_DirectTI = ((uint8_t)0x01), /*!< Input Capture mapped on the direct input*/
|
||||
TIM3_ICSelection_IndirectTI = ((uint8_t)0x02), /*!< Input Capture mapped on the indirect input*/
|
||||
TIM3_ICSelection_TRGI = ((uint8_t)0x03) /*!< Input Capture mapped on the Trigger Input*/
|
||||
}TIM3_ICSelection_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Input_Capture_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_ICPSC_DIV1 = ((uint8_t)0x00), /*!< Input Capture Prescaler = 1 (one capture every 1 event) */
|
||||
TIM3_ICPSC_DIV2 = ((uint8_t)0x04), /*!< Input Capture Prescaler = 2 (one capture every 2 events) */
|
||||
TIM3_ICPSC_DIV4 = ((uint8_t)0x08), /*!< Input Capture Prescaler = 4 (one capture every 4 events) */
|
||||
TIM3_ICPSC_DIV8 = ((uint8_t)0x0C) /*!< Input Capture Prescaler = 8 (one capture every 8 events) */
|
||||
}TIM3_ICPSC_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Interrupts
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_IT_Update = ((uint8_t)0x01), /*!< Update Interrupt*/
|
||||
TIM3_IT_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Interrupt*/
|
||||
TIM3_IT_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Interrupt*/
|
||||
TIM3_IT_Trigger = ((uint8_t)0x40), /*!< Trigger Interrupt*/
|
||||
TIM3_IT_Break = ((uint8_t)0x80) /*!< Break Interrupt*/
|
||||
}TIM3_IT_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_External_Trigger_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_ExtTRGPSC_OFF = ((uint8_t)0x00), /*!< No External Trigger prescaler */
|
||||
TIM3_ExtTRGPSC_DIV2 = ((uint8_t)0x10), /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */
|
||||
TIM3_ExtTRGPSC_DIV4 = ((uint8_t)0x20), /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */
|
||||
TIM3_ExtTRGPSC_DIV8 = ((uint8_t)0x30) /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */
|
||||
}TIM3_ExtTRGPSC_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Internal_Trigger_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_TRGSelection_TIM4 = ((uint8_t)0x00), /*!< TRIG Input source = TIM TRIG Output */
|
||||
TIM3_TRGSelection_TIM1 = ((uint8_t)0x10), /*!< TRIG Input source = TIM TRIG Output */
|
||||
TIM3_TRGSelection_TIM5 = ((uint8_t)0x20), /*!< TRIG Input source = TIM TRIG Output */
|
||||
TIM3_TRGSelection_TIM2 = ((uint8_t)0x30), /*!< TRIG Input source = TIM TRIG Output */
|
||||
TIM3_TRGSelection_TI1F_ED = ((uint8_t)0x40), /*!< TRIG Input source = TI1F_ED (TI1 Edge Detector) */
|
||||
TIM3_TRGSelection_TI1FP1 = ((uint8_t)0x50), /*!< TRIG Input source = TI1FP1 (Filtered Timer Input 1) */
|
||||
TIM3_TRGSelection_TI2FP2 = ((uint8_t)0x60), /*!< TRIG Input source = TI2FP2 (Filtered Timer Input 2) */
|
||||
TIM3_TRGSelection_ETRF = ((uint8_t)0x70) /*!< TRIG Input source = ETRF (External Trigger Input ) */
|
||||
}TIM3_TRGSelection_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_TI_External_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_TIxExternalCLK1Source_TI1ED = ((uint8_t)0x40), /*!< External Clock mode 1 source = TI1ED */
|
||||
TIM3_TIxExternalCLK1Source_TI1 = ((uint8_t)0x50), /*!< External Clock mode 1 source = TI1 */
|
||||
TIM3_TIxExternalCLK1Source_TI2 = ((uint8_t)0x60) /*!< External Clock mode 1 source = TI2 */
|
||||
}TIM3_TIxExternalCLK1Source_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_External_Trigger_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_ExtTRGPolarity_Inverted = ((uint8_t)0x80), /*!< External Trigger Polarity = inverted */
|
||||
TIM3_ExtTRGPolarity_NonInverted = ((uint8_t)0x00) /*!< External Trigger Polarity = non inverted */
|
||||
}TIM3_ExtTRGPolarity_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Prescaler_Reload_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_PSCReloadMode_Update = ((uint8_t)0x00), /*!< Prescaler value is reloaded at every update*/
|
||||
TIM3_PSCReloadMode_Immediate = ((uint8_t)0x01) /*!< Prescaler value is reloaded immediatly*/
|
||||
}TIM3_PSCReloadMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Encoder_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_EncoderMode_TI1 = ((uint8_t)0x01), /*!< Encoder mode 1*/
|
||||
TIM3_EncoderMode_TI2 = ((uint8_t)0x02), /*!< Encoder mode 2*/
|
||||
TIM3_EncoderMode_TI12 = ((uint8_t)0x03) /*!< Encoder mode 3*/
|
||||
}TIM3_EncoderMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Event_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_EventSource_Update = ((uint8_t)0x01), /*!< Update Event*/
|
||||
TIM3_EventSource_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Event*/
|
||||
TIM3_EventSource_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Event*/
|
||||
TIM3_EventSource_Trigger = ((uint8_t)0x40), /*!< Trigger Event*/
|
||||
TIM3_EventSource_Break = ((uint8_t)0x80) /*!< Break Event*/
|
||||
}TIM3_EventSource_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Update_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_UpdateSource_Global = ((uint8_t)0x00), /*!< Global Update request source */
|
||||
TIM3_UpdateSource_Regular = ((uint8_t)0x01) /*!< Regular Update request source */
|
||||
}TIM3_UpdateSource_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Trigger_Output_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_TRGOSource_Reset = ((uint8_t)0x00), /*!< Trigger Output source = Reset*/
|
||||
TIM3_TRGOSource_Enable = ((uint8_t)0x10), /*!< Trigger Output source = TIM3 is enabled*/
|
||||
TIM3_TRGOSource_Update = ((uint8_t)0x20), /*!< Trigger Output source = Update event*/
|
||||
TIM3_TRGOSource_OC1 = ((uint8_t)0x30), /*!< Trigger Output source = output compare channel1 */
|
||||
TIM3_TRGOSource_OC1REF = ((uint8_t)0x40), /*!< Trigger Output source = output compare channel 1 reference */
|
||||
TIM3_TRGOSource_OC2REF = ((uint8_t)0x50) /*!< Trigger Output source = output compare channel 2 reference */
|
||||
}TIM3_TRGOSource_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Slave_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_SlaveMode_Reset = ((uint8_t)0x04), /*!< Slave Mode Selection = Reset*/
|
||||
TIM3_SlaveMode_Gated = ((uint8_t)0x05), /*!< Slave Mode Selection = Gated*/
|
||||
TIM3_SlaveMode_Trigger = ((uint8_t)0x06), /*!< Slave Mode Selection = Trigger*/
|
||||
TIM3_SlaveMode_External1 = ((uint8_t)0x07) /*!< Slave Mode Selection = External 1*/
|
||||
}TIM3_SlaveMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_Flags
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_FLAG_Update = ((uint16_t)0x0001), /*!< Update Flag */
|
||||
TIM3_FLAG_CC1 = ((uint16_t)0x0002), /*!< Capture compare 1 Flag */
|
||||
TIM3_FLAG_CC2 = ((uint16_t)0x0004), /*!< Capture compare 2 Flag */
|
||||
TIM3_FLAG_Trigger = ((uint16_t)0x0040), /*!< Trigger Flag */
|
||||
TIM3_FLAG_Break = ((uint16_t)0x0080), /*!< Break Flag */
|
||||
TIM3_FLAG_CC1OF = ((uint16_t)0x0200), /*!< Capture compare 1 over capture Flag */
|
||||
TIM3_FLAG_CC2OF = ((uint16_t)0x0400) /*!< Capture compare 2 over capture Flag */
|
||||
}TIM3_FLAG_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM3_DMA_Source_Requests
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM3_DMASource_Update = ((uint8_t)0x01), /*!< TIM3 DMA Update Request*/
|
||||
TIM3_DMASource_CC1 = ((uint8_t)0x02),
|
||||
TIM3_DMASource_CC2 = ((uint8_t)0x04)
|
||||
}TIM3_DMASource_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TIM3_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different functions parameters.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 Forced Action
|
||||
*/
|
||||
#define IS_TIM3_FORCED_ACTION(ACTION) \
|
||||
(((ACTION) == TIM3_ForcedAction_Active) || \
|
||||
((ACTION) == TIM3_ForcedAction_Inactive))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 Prescaler
|
||||
*/
|
||||
#define IS_TIM3_PRESCALER(PRESCALER) \
|
||||
(((PRESCALER) == TIM3_Prescaler_1) || \
|
||||
((PRESCALER) == TIM3_Prescaler_2) || \
|
||||
((PRESCALER) == TIM3_Prescaler_4) || \
|
||||
((PRESCALER) == TIM3_Prescaler_8) || \
|
||||
((PRESCALER) == TIM3_Prescaler_16) || \
|
||||
((PRESCALER) == TIM3_Prescaler_32) || \
|
||||
((PRESCALER) == TIM3_Prescaler_64) || \
|
||||
((PRESCALER) == TIM3_Prescaler_128))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 Output Compare and PWM modes
|
||||
*/
|
||||
#define IS_TIM3_OC_MODE(MODE) \
|
||||
(((MODE) == TIM3_OCMode_Timing) || \
|
||||
((MODE) == TIM3_OCMode_Active) || \
|
||||
((MODE) == TIM3_OCMode_Inactive) || \
|
||||
((MODE) == TIM3_OCMode_Toggle) || \
|
||||
((MODE) == TIM3_OCMode_PWM1) || \
|
||||
((MODE) == TIM3_OCMode_PWM2))
|
||||
|
||||
#define IS_TIM3_OCM(MODE) \
|
||||
(((MODE) == TIM3_OCMode_Timing) || \
|
||||
((MODE) == TIM3_OCMode_Active) || \
|
||||
((MODE) == TIM3_OCMode_Inactive) || \
|
||||
((MODE) == TIM3_OCMode_Toggle) || \
|
||||
((MODE) == TIM3_OCMode_PWM1) || \
|
||||
((MODE) == TIM3_OCMode_PWM2) || \
|
||||
((MODE) == (uint8_t)TIM3_ForcedAction_Active) || \
|
||||
((MODE) == (uint8_t)TIM3_ForcedAction_Inactive))
|
||||
/**
|
||||
* @brief Macro TIM3 One Pulse Mode
|
||||
*/
|
||||
#define IS_TIM3_OPM_MODE(MODE) \
|
||||
(((MODE) == TIM3_OPMode_Single) || \
|
||||
((MODE) == TIM3_OPMode_Repetitive))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 Channel
|
||||
*/
|
||||
#define IS_TIM3_CHANNEL(CHANNEL) \
|
||||
(((CHANNEL) == TIM3_Channel_1) || \
|
||||
((CHANNEL) == TIM3_Channel_2) )
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 Counter Mode
|
||||
*/
|
||||
#define IS_TIM3_COUNTER_MODE(MODE) \
|
||||
(((MODE) == TIM3_CounterMode_Up) || \
|
||||
((MODE) == TIM3_CounterMode_Down) || \
|
||||
((MODE) == TIM3_CounterMode_CenterAligned1) || \
|
||||
((MODE) == TIM3_CounterMode_CenterAligned2) || \
|
||||
((MODE) == TIM3_CounterMode_CenterAligned3))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 Output Compare Polarity
|
||||
*/
|
||||
#define IS_TIM3_OC_POLARITY(POLARITY) \
|
||||
(((POLARITY) == TIM3_OCPolarity_High) || \
|
||||
((POLARITY) == TIM3_OCPolarity_Low))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 Output Compare states
|
||||
*/
|
||||
#define IS_TIM3_OUTPUT_STATE(STATE) \
|
||||
(((STATE) == TIM3_OutputState_Disable) || \
|
||||
((STATE) == TIM3_OutputState_Enable))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Macro Break Input enable/disable
|
||||
*/
|
||||
#define IS_TIM3_BREAK_STATE(STATE) \
|
||||
(((STATE) == TIM3_BreakState_Enable) || \
|
||||
((STATE) == TIM3_BreakState_Disable))
|
||||
|
||||
/**
|
||||
* @brief Macro Break Polarity
|
||||
*/
|
||||
#define IS_TIM3_BREAK_POLARITY(POLARITY) \
|
||||
(((POLARITY) == TIM3_BreakPolarity_Low) || \
|
||||
((POLARITY) == TIM3_BreakPolarity_High))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 AOE Bit Set/Reset
|
||||
*/
|
||||
#define IS_TIM3_AUTOMATIC_OUTPUT_STATE(STATE) \
|
||||
(((STATE) == TIM3_AutomaticOutput_Enable) || \
|
||||
((STATE) == TIM3_AutomaticOutput_Disable))
|
||||
|
||||
/**
|
||||
* @brief Macro Lock levels
|
||||
*/
|
||||
#define IS_TIM3_LOCK_LEVEL(LEVEL) \
|
||||
(((LEVEL) == TIM3_LockLevel_Off) || \
|
||||
((LEVEL) == TIM3_LockLevel_1) || \
|
||||
((LEVEL) == TIM3_LockLevel_2) || \
|
||||
((LEVEL) == TIM3_LockLevel_3))
|
||||
|
||||
/**
|
||||
* @brief Macro OSSI: Off-State Selection for Idle mode states
|
||||
*/
|
||||
#define IS_TIM3_OSSI_STATE(STATE) \
|
||||
(((STATE) == TIM3_OSSIState_Enable) || \
|
||||
((STATE) == TIM3_OSSIState_Disable))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 OC IDLE STATE
|
||||
*/
|
||||
#define IS_TIM3_OCIDLE_STATE(STATE) \
|
||||
(((STATE) == TIM3_OCIdleState_Set) || \
|
||||
((STATE) == TIM3_OCIdleState_Reset))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 IC POLARITY
|
||||
*/
|
||||
|
||||
#define IS_TIM3_IC_POLARITY(POLARITY) \
|
||||
(((POLARITY) == TIM3_ICPolarity_Rising) || \
|
||||
((POLARITY) == TIM3_ICPolarity_Falling))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 IC SELECTION
|
||||
*/
|
||||
#define IS_TIM3_IC_SELECTION(SELECTION) \
|
||||
(((SELECTION) == TIM3_ICSelection_DirectTI) || \
|
||||
((SELECTION) == TIM3_ICSelection_IndirectTI) || \
|
||||
((SELECTION) == TIM3_ICSelection_TRGI))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 IC PRESCALER
|
||||
*/
|
||||
#define IS_TIM3_IC_PRESCALER(PRESCALER) \
|
||||
(((PRESCALER) == TIM3_ICPSC_DIV1) || \
|
||||
((PRESCALER) == TIM3_ICPSC_DIV2) || \
|
||||
((PRESCALER) == TIM3_ICPSC_DIV4) || \
|
||||
((PRESCALER) == TIM3_ICPSC_DIV8))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 Input Capture Filter Value
|
||||
*/
|
||||
#define IS_TIM3_IC_FILTER(ICFILTER) \
|
||||
((ICFILTER) <= 0x0F)
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 Interrupts
|
||||
*/
|
||||
#define IS_TIM3_IT(IT) \
|
||||
((IT) != 0x00)
|
||||
|
||||
#define IS_TIM3_GET_IT(IT) \
|
||||
(((IT) == TIM3_IT_Update) || \
|
||||
((IT) == TIM3_IT_CC1) || \
|
||||
((IT) == TIM3_IT_CC2) || \
|
||||
((IT) == TIM3_IT_Trigger) || \
|
||||
((IT) == TIM3_IT_Break))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 external trigger prescaler
|
||||
*/
|
||||
#define IS_TIM3_EXT_PRESCALER(PRESCALER) \
|
||||
(((PRESCALER) == TIM3_ExtTRGPSC_OFF) || \
|
||||
((PRESCALER) == TIM3_ExtTRGPSC_DIV2) || \
|
||||
((PRESCALER) == TIM3_ExtTRGPSC_DIV4) || \
|
||||
((PRESCALER) == TIM3_ExtTRGPSC_DIV8))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 Trigger Selection
|
||||
*/
|
||||
#define IS_TIM3_TRIGGER_SELECTION(SELECTION) \
|
||||
(((SELECTION) == TIM3_TRGSelection_TI1F_ED) || \
|
||||
((SELECTION) == TIM3_TRGSelection_TI1FP1) || \
|
||||
((SELECTION) == TIM3_TRGSelection_TI2FP2) || \
|
||||
((SELECTION) == TIM3_TRGSelection_TIM4) || \
|
||||
((SELECTION) == TIM3_TRGSelection_TIM1) || \
|
||||
((SELECTION) == TIM3_TRGSelection_TIM5) || \
|
||||
((SELECTION) == TIM3_TRGSelection_TIM2) || \
|
||||
((SELECTION) == TIM3_TRGSelection_ETRF))
|
||||
|
||||
|
||||
#define IS_TIM3_TIX_TRIGGER_SELECTION(SELECTION) \
|
||||
(((SELECTION) == TIM3_TRGSelection_TI1F_ED) || \
|
||||
((SELECTION) == TIM3_TRGSelection_TI1FP1) || \
|
||||
((SELECTION) == TIM3_TRGSelection_TI2FP2))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 TIx external Clock Selection
|
||||
*/
|
||||
#define IS_TIM3_TIXCLK_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM3_TIxExternalCLK1Source_TI1ED) || \
|
||||
((SOURCE) == TIM3_TIxExternalCLK1Source_TI2) || \
|
||||
((SOURCE) == TIM3_TIxExternalCLK1Source_TI1))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 Trigger Polarity
|
||||
*/
|
||||
#define IS_TIM3_EXT_POLARITY(POLARITY) \
|
||||
(((POLARITY) == TIM3_ExtTRGPolarity_Inverted) || \
|
||||
((POLARITY) == TIM3_ExtTRGPolarity_NonInverted))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 External Trigger Filter
|
||||
*/
|
||||
#define IS_TIM3_EXT_FILTER(EXTFILTER) \
|
||||
((EXTFILTER) <= 0x0F)
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 Prescaler Reload
|
||||
*/
|
||||
#define IS_TIM3_PRESCALER_RELOAD(RELOAD) \
|
||||
(((RELOAD) == TIM3_PSCReloadMode_Update) || \
|
||||
((RELOAD) == TIM3_PSCReloadMode_Immediate))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 encoder mode
|
||||
*/
|
||||
#define IS_TIM3_ENCODER_MODE(MODE) \
|
||||
(((MODE) == TIM3_EncoderMode_TI1) || \
|
||||
((MODE) == TIM3_EncoderMode_TI2) || \
|
||||
((MODE) == TIM3_EncoderMode_TI12))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 event source
|
||||
*/
|
||||
#define IS_TIM3_EVENT_SOURCE(SOURCE) \
|
||||
((((SOURCE) & (uint8_t)0x18) == 0x00) && ((SOURCE) != 0x00))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 update source
|
||||
*/
|
||||
#define IS_TIM3_UPDATE_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM3_UpdateSource_Global) || \
|
||||
((SOURCE) == TIM3_UpdateSource_Regular))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 TRGO source
|
||||
*/
|
||||
#define IS_TIM3_TRGO_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM3_TRGOSource_Reset) || \
|
||||
((SOURCE) == TIM3_TRGOSource_Enable) || \
|
||||
((SOURCE) == TIM3_TRGOSource_Update) || \
|
||||
((SOURCE) == TIM3_TRGOSource_OC1) || \
|
||||
((SOURCE) == TIM3_TRGOSource_OC1REF) || \
|
||||
((SOURCE) == TIM3_TRGOSource_OC2REF))
|
||||
/**
|
||||
* @brief Macro TIM3 Slave mode
|
||||
*/
|
||||
#define IS_TIM3_SLAVE_MODE(MODE) \
|
||||
(((MODE) == TIM3_SlaveMode_Reset) || \
|
||||
((MODE) == TIM3_SlaveMode_Gated) || \
|
||||
((MODE) == TIM3_SlaveMode_Trigger) || \
|
||||
((MODE) == TIM3_SlaveMode_External1))
|
||||
/**
|
||||
* @brief Macro TIM3 Flags
|
||||
*/
|
||||
#define IS_TIM3_GET_FLAG(FLAG) \
|
||||
(((FLAG) == TIM3_FLAG_Update) || \
|
||||
((FLAG) == TIM3_FLAG_CC1) || \
|
||||
((FLAG) == TIM3_FLAG_CC2) || \
|
||||
((FLAG) == TIM3_FLAG_Trigger) || \
|
||||
((FLAG) == TIM3_FLAG_Break) || \
|
||||
((FLAG) == TIM3_FLAG_CC1OF) || \
|
||||
((FLAG) == TIM3_FLAG_CC2OF))
|
||||
|
||||
#define IS_TIM3_CLEAR_FLAG(FLAG) \
|
||||
((((FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM3 DMA sources
|
||||
*/
|
||||
|
||||
#define IS_TIM3_DMA_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM3_DMASource_Update) || \
|
||||
((SOURCE) == TIM3_DMASource_CC1) || \
|
||||
((SOURCE) == TIM3_DMASource_CC2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* TimeBase management ********************************************************/
|
||||
void TIM3_DeInit(void);
|
||||
void TIM3_TimeBaseInit(TIM3_Prescaler_TypeDef TIM3_Prescaler,
|
||||
TIM3_CounterMode_TypeDef TIM3_CounterMode,
|
||||
uint16_t TIM3_Period);
|
||||
void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler,
|
||||
TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode);
|
||||
void TIM3_CounterModeConfig(TIM3_CounterMode_TypeDef TIM3_CounterMode);
|
||||
void TIM3_SetCounter(uint16_t Counter);
|
||||
void TIM3_SetAutoreload(uint16_t Autoreload);
|
||||
uint16_t TIM3_GetCounter(void);
|
||||
TIM3_Prescaler_TypeDef TIM3_GetPrescaler(void);
|
||||
void TIM3_UpdateDisableConfig(FunctionalState NewState);
|
||||
void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource);
|
||||
void TIM3_ARRPreloadConfig(FunctionalState NewState);
|
||||
void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode);
|
||||
void TIM3_Cmd(FunctionalState NewState);
|
||||
|
||||
/* Output Compare management **************************************************/
|
||||
void TIM3_OC1Init(TIM3_OCMode_TypeDef TIM3_OCMode,
|
||||
TIM3_OutputState_TypeDef TIM3_OutputState,
|
||||
uint16_t TIM3_Pulse,
|
||||
TIM3_OCPolarity_TypeDef TIM3_OCPolarity,
|
||||
TIM3_OCIdleState_TypeDef TIM3_OCIdleState);
|
||||
void TIM3_OC2Init(TIM3_OCMode_TypeDef TIM3_OCMode,
|
||||
TIM3_OutputState_TypeDef TIM3_OutputState,
|
||||
uint16_t TIM3_Pulse,
|
||||
TIM3_OCPolarity_TypeDef TIM3_OCPolarity,
|
||||
TIM3_OCIdleState_TypeDef TIM3_OCIdleState);
|
||||
void TIM3_BKRConfig(TIM3_OSSIState_TypeDef TIM3_OSSIState,
|
||||
TIM3_LockLevel_TypeDef TIM3_LockLevel,
|
||||
TIM3_BreakState_TypeDef TIM3_BreakState,
|
||||
TIM3_BreakPolarity_TypeDef TIM3_BreakPolarity,
|
||||
TIM3_AutomaticOutput_TypeDef TIM3_AutomaticOutput);
|
||||
void TIM3_CtrlPWMOutputs(FunctionalState NewState);
|
||||
void TIM3_SelectOCxM(TIM3_Channel_TypeDef TIM3_Channel,
|
||||
TIM3_OCMode_TypeDef TIM3_OCMode);
|
||||
void TIM3_SetCompare1(uint16_t Compare);
|
||||
void TIM3_SetCompare2(uint16_t Compare);
|
||||
void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction);
|
||||
void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction);
|
||||
void TIM3_OC1PreloadConfig(FunctionalState NewState);
|
||||
void TIM3_OC2PreloadConfig(FunctionalState NewState);
|
||||
void TIM3_OC1FastConfig(FunctionalState NewState);
|
||||
void TIM3_OC2FastConfig(FunctionalState NewState);
|
||||
void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
|
||||
void TIM3_OC2PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity);
|
||||
void TIM3_CCxCmd(TIM3_Channel_TypeDef TIM3_Channel, FunctionalState NewState);
|
||||
|
||||
/* Input Capture management ***************************************************/
|
||||
void TIM3_ICInit(TIM3_Channel_TypeDef TIM3_Channel,
|
||||
TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
|
||||
TIM3_ICSelection_TypeDef TIM3_ICSelection,
|
||||
TIM3_ICPSC_TypeDef TIM3_ICPrescaler,
|
||||
uint8_t TIM3_ICFilter);
|
||||
void TIM3_PWMIConfig(TIM3_Channel_TypeDef TIM3_Channel,
|
||||
TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
|
||||
TIM3_ICSelection_TypeDef TIM3_ICSelection,
|
||||
TIM3_ICPSC_TypeDef TIM3_ICPrescaler,
|
||||
uint8_t TIM3_ICFilter);
|
||||
uint16_t TIM3_GetCapture1(void);
|
||||
uint16_t TIM3_GetCapture2(void);
|
||||
void TIM3_SetIC1Prescaler(TIM3_ICPSC_TypeDef TIM3_IC1Prescaler);
|
||||
void TIM3_SetIC2Prescaler(TIM3_ICPSC_TypeDef TIM3_IC2Prescaler);
|
||||
|
||||
/* Interrupts, DMA and flags management ***************************************/
|
||||
void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState);
|
||||
void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource);
|
||||
FlagStatus TIM3_GetFlagStatus(TIM3_FLAG_TypeDef TIM3_FLAG);
|
||||
void TIM3_ClearFlag(TIM3_FLAG_TypeDef TIM3_FLAG);
|
||||
ITStatus TIM3_GetITStatus(TIM3_IT_TypeDef TIM3_IT);
|
||||
void TIM3_ClearITPendingBit(TIM3_IT_TypeDef TIM3_IT);
|
||||
void TIM3_DMACmd(TIM3_DMASource_TypeDef TIM3_DMASource, FunctionalState NewState);
|
||||
void TIM3_SelectCCDMA(FunctionalState NewState);
|
||||
|
||||
/* Clocks management **********************************************************/
|
||||
void TIM3_InternalClockConfig(void);
|
||||
void TIM3_TIxExternalClockConfig(TIM3_TIxExternalCLK1Source_TypeDef TIM3_TIxExternalCLKSource,
|
||||
TIM3_ICPolarity_TypeDef TIM3_ICPolarity,
|
||||
uint8_t ICFilter);
|
||||
void TIM3_ETRClockMode1Config(TIM3_ExtTRGPSC_TypeDef TIM3_ExtTRGPrescaler,
|
||||
TIM3_ExtTRGPolarity_TypeDef TIM3_ExtTRGPolarity,
|
||||
uint8_t ExtTRGFilter);
|
||||
void TIM3_ETRClockMode2Config(TIM3_ExtTRGPSC_TypeDef TIM3_ExtTRGPrescaler,
|
||||
TIM3_ExtTRGPolarity_TypeDef TIM3_ExtTRGPolarity,
|
||||
uint8_t ExtTRGFilter);
|
||||
|
||||
/* Synchronization management *************************************************/
|
||||
void TIM3_SelectInputTrigger(TIM3_TRGSelection_TypeDef TIM3_InputTriggerSource);
|
||||
void TIM3_SelectOutputTrigger(TIM3_TRGOSource_TypeDef TIM3_TRGOSource);
|
||||
void TIM3_SelectSlaveMode(TIM3_SlaveMode_TypeDef TIM3_SlaveMode);
|
||||
void TIM3_SelectMasterSlaveMode(FunctionalState NewState);
|
||||
void TIM3_ETRConfig(TIM3_ExtTRGPSC_TypeDef TIM3_ExtTRGPrescaler,
|
||||
TIM3_ExtTRGPolarity_TypeDef TIM3_ExtTRGPolarity,
|
||||
uint8_t ExtTRGFilter);
|
||||
|
||||
/* Specific interface management **********************************************/
|
||||
void TIM3_EncoderInterfaceConfig(TIM3_EncoderMode_TypeDef TIM3_EncoderMode,
|
||||
TIM3_ICPolarity_TypeDef TIM3_IC1Polarity,
|
||||
TIM3_ICPolarity_TypeDef TIM3_IC2Polarity);
|
||||
void TIM3_SelectHallSensor(FunctionalState NewState);
|
||||
|
||||
#endif /* __STM8L15x_TIM3_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
374
firmware/inc/stm8l151x/inc/stm8l15x_tim4.h
Normal file
374
firmware/inc/stm8l151x/inc/stm8l15x_tim4.h
Normal file
@@ -0,0 +1,374 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_tim4.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the TIM4 firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_TIM4_H
|
||||
#define __STM8L15x_TIM4_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM4
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TIM4_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup TIM4_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM4_Prescaler_1 = ((uint8_t)0x00), /*!< Time base Prescaler = 1 (No effect)*/
|
||||
TIM4_Prescaler_2 = ((uint8_t)0x01), /*!< Time base Prescaler = 2 */
|
||||
TIM4_Prescaler_4 = ((uint8_t)0x02), /*!< Time base Prescaler = 4 */
|
||||
TIM4_Prescaler_8 = ((uint8_t)0x03), /*!< Time base Prescaler = 8 */
|
||||
TIM4_Prescaler_16 = ((uint8_t)0x04), /*!< Time base Prescaler = 16 */
|
||||
TIM4_Prescaler_32 = ((uint8_t)0x05), /*!< Time base Prescaler = 32 */
|
||||
TIM4_Prescaler_64 = ((uint8_t)0x06), /*!< Time base Prescaler = 64 */
|
||||
TIM4_Prescaler_128 = ((uint8_t)0x07), /*!< Time base Prescaler = 128 */
|
||||
TIM4_Prescaler_256 = ((uint8_t)0x08), /*!< Time base Prescaler = 256 */
|
||||
TIM4_Prescaler_512 = ((uint8_t)0x09), /*!< Time base Prescaler = 512 */
|
||||
TIM4_Prescaler_1024 = ((uint8_t)0x0A), /*!< Time base Prescaler = 1024 */
|
||||
TIM4_Prescaler_2048 = ((uint8_t)0x0B), /*!< Time base Prescaler = 2048 */
|
||||
TIM4_Prescaler_4096 = ((uint8_t)0x0C), /*!< Time base Prescaler = 4096 */
|
||||
TIM4_Prescaler_8192 = ((uint8_t)0x0D), /*!< Time base Prescaler = 8196 */
|
||||
TIM4_Prescaler_16384 = ((uint8_t)0x0E), /*!< Time base Prescaler = 16384 */
|
||||
TIM4_Prescaler_32768 = ((uint8_t)0x0F) /*!< Time base Prescaler = 32768 */
|
||||
}TIM4_Prescaler_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_One_Pulse_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM4_OPMode_Single = ((uint8_t) 0x01), /*!< Single one Pulse mode (OPM Active) */
|
||||
TIM4_OPMode_Repetitive = ((uint8_t) 0x00) /*!< Repetitive Pulse mode (OPM inactive) */
|
||||
}TIM4_OPMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_Reload_Mode_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM4_PSCReloadMode_Update = ((uint8_t)0x00), /*!< Prescaler value is reloaded at every update */
|
||||
TIM4_PSCReloadMode_Immediate = ((uint8_t)0x01) /*!< Prescaler value is reloaded immediatly */
|
||||
}TIM4_PSCReloadMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_Update_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM4_UpdateSource_Global = ((uint8_t)0x00), /*!< Global Update request source */
|
||||
TIM4_UpdateSource_Regular = ((uint8_t)0x01) /*!< Regular Update request source */
|
||||
}TIM4_UpdateSource_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_Event_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM4_EventSource_Update = ((uint8_t)0x01), /*!< Update Event */
|
||||
TIM4_EventSource_Trigger = ((uint8_t)0x40) /*!< Trigger Event */
|
||||
}TIM4_EventSource_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_Trigger_Output_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM4_TRGOSource_Reset = ((uint8_t)0x00), /*!< Trigger Output source = Reset */
|
||||
TIM4_TRGOSource_Enable = ((uint8_t)0x10), /*!< Trigger Output source = TIM4 is enabled */
|
||||
TIM4_TRGOSource_Update = ((uint8_t)0x20) /*!< Trigger Output source = Update event */
|
||||
}TIM4_TRGOSource_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_Salve_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM4_SlaveMode_Disable = ((uint8_t)0x00), /*!< Disable slave mode to clock the prescaler
|
||||
directly with the internal clock */
|
||||
TIM4_SlaveMode_Reset = ((uint8_t)0x04), /*!< Slave Mode Selection = Reset*/
|
||||
TIM4_SlaveMode_Gated = ((uint8_t)0x05), /*!< Slave Mode Selection = Gated*/
|
||||
TIM4_SlaveMode_Trigger = ((uint8_t)0x06), /*!< Slave Mode Selection = Trigger*/
|
||||
TIM4_SlaveMode_External1 = ((uint8_t)0x07) /*!< Slave Mode Selection = External 1*/
|
||||
}TIM4_SlaveMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_Flags
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM4_FLAG_Update = ((uint8_t)0x01), /*!< Update Flag */
|
||||
TIM4_FLAG_Trigger = ((uint8_t)0x40) /*!< Trigger Flag */
|
||||
}TIM4_FLAG_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_Interrupts
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM4_IT_Update = ((uint8_t)0x01), /*!< Update Interrupt*/
|
||||
TIM4_IT_Trigger = ((uint8_t)0x40) /*!< Trigger Interrupt*/
|
||||
}TIM4_IT_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_Internal_Trigger_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM4_TRGSelection_TIM5 = ((uint8_t)0x00), /*!< TRIG Input source = TIM5 TRIG Output */
|
||||
TIM4_TRGSelection_TIM1 = ((uint8_t)0x10), /*!< TRIG Input source = TIM1 TRIG Output */
|
||||
TIM4_TRGSelection_TIM3 = ((uint8_t)0x20), /*!< TRIG Input source = TIM3 TRIG Output */
|
||||
TIM4_TRGSelection_TIM2 = ((uint8_t)0x30) /*!< TRIG Input source = TIM2 TRIG Output */
|
||||
}TIM4_TRGSelection_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_DMA_source_requests
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM4_DMASource_Update = ((uint8_t)0x01) /*!< TIM4 DMA Update Request*/
|
||||
}TIM4_DMASource_TypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TIM4_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro used by the assert function to check the different functions parameters.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro TIM4 Prescaler
|
||||
*/
|
||||
#define IS_TIM4_Prescaler(PRESCALER) \
|
||||
(((PRESCALER) == TIM4_Prescaler_1) || \
|
||||
((PRESCALER) == TIM4_Prescaler_2) || \
|
||||
((PRESCALER) == TIM4_Prescaler_4) || \
|
||||
((PRESCALER) == TIM4_Prescaler_8) || \
|
||||
((PRESCALER) == TIM4_Prescaler_16) || \
|
||||
((PRESCALER) == TIM4_Prescaler_32) || \
|
||||
((PRESCALER) == TIM4_Prescaler_64) || \
|
||||
((PRESCALER) == TIM4_Prescaler_128) || \
|
||||
((PRESCALER) == TIM4_Prescaler_256) || \
|
||||
((PRESCALER) == TIM4_Prescaler_512) || \
|
||||
((PRESCALER) == TIM4_Prescaler_1024) || \
|
||||
((PRESCALER) == TIM4_Prescaler_2048) || \
|
||||
((PRESCALER) == TIM4_Prescaler_4096) || \
|
||||
((PRESCALER) == TIM4_Prescaler_8192) || \
|
||||
((PRESCALER) == TIM4_Prescaler_16384)|| \
|
||||
((PRESCALER) == TIM4_Prescaler_32768))
|
||||
/**
|
||||
* @brief Macro TIM4 One Pulse Mode
|
||||
*/
|
||||
#define IS_TIM4_OPM_MODE(MODE) \
|
||||
(((MODE) == TIM4_OPMode_Single) || \
|
||||
((MODE) == TIM4_OPMode_Repetitive))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM4 Prescaler reload
|
||||
*/
|
||||
#define IS_TIM4_Prescaler_RELOAD(RELOAD) \
|
||||
(((RELOAD) == TIM4_PSCReloadMode_Update) || \
|
||||
((RELOAD) == TIM4_PSCReloadMode_Immediate))
|
||||
/**
|
||||
* @brief Macro TIM4 Update source
|
||||
*/
|
||||
#define IS_TIM4_UPDATE_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM4_UpdateSource_Global) || \
|
||||
((SOURCE) == TIM4_UpdateSource_Regular))
|
||||
/**
|
||||
* @brief Macro TIM4 Event source
|
||||
*/
|
||||
#define IS_TIM4_EVENT_SOURCE(SOURCE) \
|
||||
((((SOURCE) & (uint8_t)0xBE) == 0x00) && \
|
||||
((SOURCE) != 0x00))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM4 TRGO source
|
||||
*/
|
||||
#define IS_TIM4_TRGO_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM4_TRGOSource_Reset) || \
|
||||
((SOURCE) == TIM4_TRGOSource_Enable)|| \
|
||||
((SOURCE) == TIM4_TRGOSource_Update))
|
||||
/**
|
||||
* @brief Macro TIM4 Slave mode
|
||||
*/
|
||||
#define IS_TIM4_SLAVE_MODE(MODE) \
|
||||
(((MODE) == TIM4_SlaveMode_Disable) || \
|
||||
((MODE) == TIM4_SlaveMode_Reset) || \
|
||||
((MODE) == TIM4_SlaveMode_Gated) || \
|
||||
((MODE) == TIM4_SlaveMode_Trigger) || \
|
||||
((MODE) == TIM4_SlaveMode_External1))
|
||||
/**
|
||||
* @brief Macro TIM4 Flags
|
||||
*/
|
||||
#define IS_TIM4_GET_FLAG(FLAG) \
|
||||
(((FLAG) == TIM4_FLAG_Update) || \
|
||||
((FLAG) == TIM4_FLAG_Trigger))
|
||||
|
||||
#define IS_TIM4_CLEAR_FLAG(FLAG) \
|
||||
((((FLAG) & (uint8_t)0xBE) == 0x00) && ((FLAG) != 0x00))
|
||||
/**
|
||||
* @brief Macro TIM4 interrupts
|
||||
*/
|
||||
#define IS_TIM4_IT(IT) \
|
||||
(((IT) != 0x00) && \
|
||||
(((uint8_t)(IT) & (uint8_t)(~(uint8_t)(0x41)))== 0x00))
|
||||
|
||||
#define IS_TIM4_GET_IT(IT) \
|
||||
(((IT) == TIM4_IT_Update) || \
|
||||
((IT) == TIM4_IT_Trigger))
|
||||
/**
|
||||
* @brief Macro TIM4 Trigger selection
|
||||
*/
|
||||
#define IS_TIM4_TRIGGER_SELECTION(SELECTION) \
|
||||
(((SELECTION) == TIM4_TRGSelection_TIM5) || \
|
||||
((SELECTION) == TIM4_TRGSelection_TIM1) || \
|
||||
((SELECTION) == TIM4_TRGSelection_TIM3) || \
|
||||
((SELECTION) == TIM4_TRGSelection_TIM2))
|
||||
|
||||
/**
|
||||
* @brief Macro TIM4 DMA sources
|
||||
*/
|
||||
|
||||
#define IS_TIM4_DMA_SOURCE(SOURCE) (((SOURCE) == TIM4_DMASource_Update))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* TimeBase management ********************************************************/
|
||||
void TIM4_DeInit(void);
|
||||
void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler,
|
||||
uint8_t TIM4_Period);
|
||||
void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler,
|
||||
TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode);
|
||||
void TIM4_SetCounter(uint8_t Counter);
|
||||
void TIM4_SetAutoreload(uint8_t Autoreload);
|
||||
uint8_t TIM4_GetCounter(void);
|
||||
TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void);
|
||||
void TIM4_UpdateDisableConfig(FunctionalState NewState);
|
||||
void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource);
|
||||
void TIM4_ARRPreloadConfig(FunctionalState NewState);
|
||||
void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode);
|
||||
void TIM4_Cmd(FunctionalState NewState);
|
||||
|
||||
/* Interrupts, DMA and flags management ***************************************/
|
||||
void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState);
|
||||
void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource);
|
||||
FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG);
|
||||
void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG);
|
||||
ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT);
|
||||
void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT);
|
||||
void TIM4_DMACmd(TIM4_DMASource_TypeDef TIM4_DMASource, FunctionalState NewState);
|
||||
|
||||
/* Clocks management **********************************************************/
|
||||
void TIM4_InternalClockConfig(void);
|
||||
|
||||
/* Synchronization management *************************************************/
|
||||
void TIM4_SelectInputTrigger(TIM4_TRGSelection_TypeDef TIM4_InputTriggerSource);
|
||||
void TIM4_SelectOutputTrigger(TIM4_TRGOSource_TypeDef TIM4_TRGOSource);
|
||||
void TIM4_SelectSlaveMode(TIM4_SlaveMode_TypeDef TIM4_SlaveMode);
|
||||
void TIM4_SelectMasterSlaveMode(FunctionalState NewState);
|
||||
|
||||
#endif /* __STM8L15x_TIM4_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
771
firmware/inc/stm8l151x/inc/stm8l15x_tim5.h
Normal file
771
firmware/inc/stm8l151x/inc/stm8l15x_tim5.h
Normal file
@@ -0,0 +1,771 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_tim5.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the TIM5 firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_TIM5_H
|
||||
#define __STM8L15x_TIM5_H
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM5
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TIM5_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Forced_Action
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_ForcedAction_Active = ((uint8_t)0x50), /*!< Output Reference is forced low */
|
||||
TIM5_ForcedAction_Inactive = ((uint8_t)0x40) /*!< Output Reference is forced high */
|
||||
}
|
||||
TIM5_ForcedAction_TypeDef;
|
||||
|
||||
#define IS_TIM5_FORCED_ACTION(ACTION) (((ACTION) == TIM5_ForcedAction_Active) || \
|
||||
((ACTION) == TIM5_ForcedAction_Inactive))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_Prescaler_1 = ((uint8_t)0x00), /*!< Time base Prescaler = 1 (No effect)*/
|
||||
TIM5_Prescaler_2 = ((uint8_t)0x01), /*!< Time base Prescaler = 2 */
|
||||
TIM5_Prescaler_4 = ((uint8_t)0x02), /*!< Time base Prescaler = 4 */
|
||||
TIM5_Prescaler_8 = ((uint8_t)0x03), /*!< Time base Prescaler = 8 */
|
||||
TIM5_Prescaler_16 = ((uint8_t)0x04), /*!< Time base Prescaler = 16 */
|
||||
TIM5_Prescaler_32 = ((uint8_t)0x05), /*!< Time base Prescaler = 32 */
|
||||
TIM5_Prescaler_64 = ((uint8_t)0x06), /*!< Time base Prescaler = 64 */
|
||||
TIM5_Prescaler_128 = ((uint8_t)0x07) /*!< Time base Prescaler = 128 */
|
||||
}TIM5_Prescaler_TypeDef;
|
||||
|
||||
#define IS_TIM5_PRESCALER(PRESCALER) (((PRESCALER) == TIM5_Prescaler_1) || \
|
||||
((PRESCALER) == TIM5_Prescaler_2) || \
|
||||
((PRESCALER) == TIM5_Prescaler_4) || \
|
||||
((PRESCALER) == TIM5_Prescaler_8) || \
|
||||
((PRESCALER) == TIM5_Prescaler_16) || \
|
||||
((PRESCALER) == TIM5_Prescaler_32) || \
|
||||
((PRESCALER) == TIM5_Prescaler_64) || \
|
||||
((PRESCALER) == TIM5_Prescaler_128))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_OCMode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_OCMode_Timing = ((uint8_t)0x00), /*!< Timing (Frozen) Mode*/
|
||||
TIM5_OCMode_Active = ((uint8_t)0x10), /*!< Active Mode*/
|
||||
TIM5_OCMode_Inactive = ((uint8_t)0x20), /*!< Inactive Mode*/
|
||||
TIM5_OCMode_Toggle = ((uint8_t)0x30), /*!< Toggle Mode*/
|
||||
TIM5_OCMode_PWM1 = ((uint8_t)0x60), /*!< PWM Mode 1*/
|
||||
TIM5_OCMode_PWM2 = ((uint8_t)0x70) /*!< PWM Mode 2*/
|
||||
}TIM5_OCMode_TypeDef;
|
||||
|
||||
#define IS_TIM5_OC_MODE(MODE) (((MODE) == TIM5_OCMode_Timing) || \
|
||||
((MODE) == TIM5_OCMode_Active) || \
|
||||
((MODE) == TIM5_OCMode_Inactive) || \
|
||||
((MODE) == TIM5_OCMode_Toggle) || \
|
||||
((MODE) == TIM5_OCMode_PWM1) || \
|
||||
((MODE) == TIM5_OCMode_PWM2))
|
||||
|
||||
#define IS_TIM5_OCM(MODE) (((MODE) == TIM5_OCMode_Timing) || \
|
||||
((MODE) == TIM5_OCMode_Active) || \
|
||||
((MODE) == TIM5_OCMode_Inactive) || \
|
||||
((MODE) == TIM5_OCMode_Toggle) || \
|
||||
((MODE) == TIM5_OCMode_PWM1) || \
|
||||
((MODE) == TIM5_OCMode_PWM2) || \
|
||||
((MODE) == (uint8_t)TIM5_ForcedAction_Active) || \
|
||||
((MODE) == (uint8_t)TIM5_ForcedAction_Inactive))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_OnePulseMode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_OPMode_Single = ((uint8_t)0x01), /*!< Single one Pulse mode (OPM Active) */
|
||||
TIM5_OPMode_Repetitive = ((uint8_t)0x00) /*!< Repetitive Pulse mode (OPM inactive) */
|
||||
}TIM5_OPMode_TypeDef;
|
||||
|
||||
#define IS_TIM5_OPM_MODE(MODE) (((MODE) == TIM5_OPMode_Single) || \
|
||||
((MODE) == TIM5_OPMode_Repetitive))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Channel
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_Channel_1 = ((uint8_t)0x00), /*!< Channel 1*/
|
||||
TIM5_Channel_2 = ((uint8_t)0x01) /*!< Channel 2*/
|
||||
}TIM5_Channel_TypeDef;
|
||||
|
||||
#define IS_TIM5_CHANNEL(CHANNEL) (((CHANNEL) == TIM5_Channel_1) || \
|
||||
((CHANNEL) == TIM5_Channel_2) )
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_CounterMode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_CounterMode_Up = ((uint8_t)0x00), /*!< Counter Up Mode */
|
||||
TIM5_CounterMode_Down = ((uint8_t)0x10), /*!< Counter Down Mode */
|
||||
TIM5_CounterMode_CenterAligned1 = ((uint8_t)0x20), /*!< Counter Central aligned Mode 1 */
|
||||
TIM5_CounterMode_CenterAligned2 = ((uint8_t)0x40), /*!< Counter Central aligned Mode 2 */
|
||||
TIM5_CounterMode_CenterAligned3 = ((uint8_t)0x60) /*!< Counter Central aligned Mode 3 */
|
||||
}TIM5_CounterMode_TypeDef;
|
||||
|
||||
#define IS_TIM5_COUNTER_MODE(MODE) (((MODE) == TIM5_CounterMode_Up) || \
|
||||
((MODE) == TIM5_CounterMode_Down) || \
|
||||
((MODE) == TIM5_CounterMode_CenterAligned1) || \
|
||||
((MODE) == TIM5_CounterMode_CenterAligned2) || \
|
||||
((MODE) == TIM5_CounterMode_CenterAligned3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Output_Compare_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_OCPolarity_High = ((uint8_t)0x00), /*!< Output compare polarity = High */
|
||||
TIM5_OCPolarity_Low = ((uint8_t)0x01) /*!< Output compare polarity = Low */
|
||||
}TIM5_OCPolarity_TypeDef;
|
||||
|
||||
#define IS_TIM5_OC_POLARITY(POLARITY) (((POLARITY) == TIM5_OCPolarity_High) || \
|
||||
((POLARITY) == TIM5_OCPolarity_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Output_State
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_OutputState_Disable = ((uint8_t)0x00), /*!< Output compare State disabled (channel output disabled) */
|
||||
TIM5_OutputState_Enable = ((uint8_t)0x01) /*!< Output compare State enabled (channel output enabled) */
|
||||
}TIM5_OutputState_TypeDef;
|
||||
|
||||
#define IS_TIM5_OUTPUT_STATE(STATE) (((STATE) == TIM5_OutputState_Disable) || \
|
||||
((STATE) == TIM5_OutputState_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Break_State
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_BreakState_Disable = ((uint8_t)0x00), /*!< Break State disabled (break option disabled) */
|
||||
TIM5_BreakState_Enable = ((uint8_t)0x10) /*!< Break State enabled (break option enabled) */
|
||||
}TIM5_BreakState_TypeDef;
|
||||
|
||||
#define IS_TIM5_BREAK_STATE(STATE) (((STATE) == TIM5_BreakState_Enable) || \
|
||||
((STATE) == TIM5_BreakState_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Break_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_BreakPolarity_High = ((uint8_t)0x20), /*!< if Break, channel polarity = High */
|
||||
TIM5_BreakPolarity_Low = ((uint8_t)0x00) /*!< if Break, channel polarity = Low */
|
||||
}TIM5_BreakPolarity_TypeDef;
|
||||
|
||||
#define IS_TIM5_BREAK_POLARITY(POLARITY) \
|
||||
(((POLARITY) == TIM5_BreakPolarity_Low) || \
|
||||
((POLARITY) == TIM5_BreakPolarity_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Automatic_Output
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_AutomaticOutput_Enable = ((uint8_t)0x40), /*!< Automatic Output option enabled */
|
||||
TIM5_AutomaticOutput_Disable = ((uint8_t)0x00) /*!< Automatic Output option disabled */
|
||||
}TIM5_AutomaticOutput_TypeDef;
|
||||
|
||||
#define IS_TIM5_AUTOMATIC_OUTPUT_STATE(STATE) \
|
||||
(((STATE) == TIM5_AutomaticOutput_Enable) || \
|
||||
((STATE) == TIM5_AutomaticOutput_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Lock_Level
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_LockLevel_Off = ((uint8_t)0x00), /*!< Lock option disabled */
|
||||
TIM5_LockLevel_1 = ((uint8_t)0x01), /*!< Select Lock Level 1 */
|
||||
TIM5_LockLevel_2 = ((uint8_t)0x02), /*!< Select Lock Level 2 */
|
||||
TIM5_LockLevel_3 = ((uint8_t)0x03) /*!< Select Lock Level 3 */
|
||||
}TIM5_LockLevel_TypeDef;
|
||||
|
||||
#define IS_TIM5_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM5_LockLevel_Off) || \
|
||||
((LEVEL) == TIM5_LockLevel_1) || \
|
||||
((LEVEL) == TIM5_LockLevel_2) || \
|
||||
((LEVEL) == TIM5_LockLevel_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_OSSI_State
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_OSSIState_Enable = ((uint8_t)0x04), /*!< Off-State Selection for Idle mode enabled */
|
||||
TIM5_OSSIState_Disable = ((uint8_t)0x00) /*!< Off-State Selection for Idle mode disabled */
|
||||
}TIM5_OSSIState_TypeDef;
|
||||
|
||||
#define IS_TIM5_OSSI_STATE(STATE) \
|
||||
(((STATE) == TIM5_OSSIState_Enable) || \
|
||||
((STATE) == TIM5_OSSIState_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Output_Compare_Idle_state
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_OCIdleState_Reset = ((uint8_t)0x00), /*!< Output Compare Idle state = Reset */
|
||||
TIM5_OCIdleState_Set = ((uint8_t)0x01) /*!< Output Compare Idle state = Set */
|
||||
}TIM5_OCIdleState_TypeDef;
|
||||
|
||||
#define IS_TIM5_OCIDLE_STATE(STATE) \
|
||||
(((STATE) == TIM5_OCIdleState_Set) || \
|
||||
((STATE) == TIM5_OCIdleState_Reset))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Input_Capture_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_ICPolarity_Rising = ((uint8_t)0x00), /*!< Input Capture on Rising Edge*/
|
||||
TIM5_ICPolarity_Falling = ((uint8_t)0x01) /*!< Input Capture on Falling Edge*/
|
||||
}TIM5_ICPolarity_TypeDef;
|
||||
|
||||
#define IS_TIM5_IC_POLARITY(POLARITY) \
|
||||
(((POLARITY) == TIM5_ICPolarity_Rising) || \
|
||||
((POLARITY) == TIM5_ICPolarity_Falling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Input_Capture_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_ICSelection_DirectTI = ((uint8_t)0x01), /*!< Input Capture mapped on the direct input*/
|
||||
TIM5_ICSelection_IndirectTI = ((uint8_t)0x02), /*!< Input Capture mapped on the indirect input*/
|
||||
TIM5_ICSelection_TRGI = ((uint8_t)0x03) /*!< Input Capture mapped on the Trigger Input*/
|
||||
}TIM5_ICSelection_TypeDef;
|
||||
|
||||
#define IS_TIM5_IC_SELECTION(SELECTION) \
|
||||
(((SELECTION) == TIM5_ICSelection_DirectTI) || \
|
||||
((SELECTION) == TIM5_ICSelection_IndirectTI) || \
|
||||
((SELECTION) == TIM5_ICSelection_TRGI))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Input_Capture_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_ICPSC_DIV1 = ((uint8_t)0x00), /*!< Input Capture Prescaler = 1 (one capture every 1 event) */
|
||||
TIM5_ICPSC_DIV2 = ((uint8_t)0x04), /*!< Input Capture Prescaler = 2 (one capture every 2 events) */
|
||||
TIM5_ICPSC_DIV4 = ((uint8_t)0x08), /*!< Input Capture Prescaler = 4 (one capture every 4 events) */
|
||||
TIM5_ICPSC_DIV8 = ((uint8_t)0x0C) /*!< Input Capture Prescaler = 8 (one capture every 8 events) */
|
||||
}TIM5_ICPSC_TypeDef;
|
||||
|
||||
#define IS_TIM5_IC_PRESCALER(PRESCALER) \
|
||||
(((PRESCALER) == TIM5_ICPSC_DIV1) || \
|
||||
((PRESCALER) == TIM5_ICPSC_DIV2) || \
|
||||
((PRESCALER) == TIM5_ICPSC_DIV4) || \
|
||||
((PRESCALER) == TIM5_ICPSC_DIV8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Interrupts
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_IT_Update = ((uint8_t)0x01), /*!< Update Interrupt*/
|
||||
TIM5_IT_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Interrupt*/
|
||||
TIM5_IT_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Interrupt*/
|
||||
TIM5_IT_Trigger = ((uint8_t)0x40), /*!< Trigger Interrupt*/
|
||||
TIM5_IT_Break = ((uint8_t)0x80) /*!< Break Interrupt*/
|
||||
}TIM5_IT_TypeDef;
|
||||
|
||||
#define IS_TIM5_IT(IT) \
|
||||
((IT) != 0x00)
|
||||
|
||||
#define IS_TIM5_GET_IT(IT) \
|
||||
(((IT) == TIM5_IT_Update) || \
|
||||
((IT) == TIM5_IT_CC1) || \
|
||||
((IT) == TIM5_IT_CC2) || \
|
||||
((IT) == TIM5_IT_Trigger) || \
|
||||
((IT) == TIM5_IT_Break))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_External_Trigger_Prescaler
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_ExtTRGPSC_OFF = ((uint8_t)0x00), /*!< No External Trigger prescaler */
|
||||
TIM5_ExtTRGPSC_DIV2 = ((uint8_t)0x10), /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */
|
||||
TIM5_ExtTRGPSC_DIV4 = ((uint8_t)0x20), /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */
|
||||
TIM5_ExtTRGPSC_DIV8 = ((uint8_t)0x30) /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */
|
||||
}TIM5_ExtTRGPSC_TypeDef;
|
||||
|
||||
#define IS_TIM5_EXT_PRESCALER(PRESCALER) \
|
||||
(((PRESCALER) == TIM5_ExtTRGPSC_OFF) || \
|
||||
((PRESCALER) == TIM5_ExtTRGPSC_DIV2) || \
|
||||
((PRESCALER) == TIM5_ExtTRGPSC_DIV4) || \
|
||||
((PRESCALER) == TIM5_ExtTRGPSC_DIV8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Internal_Trigger_Selection
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_TRGSelection_TIM4 = ((uint8_t)0x00), /*!< TRIG Input source = TIM TRIG Output */
|
||||
TIM5_TRGSelection_TIM1 = ((uint8_t)0x10), /*!< TRIG Input source = TIM TRIG Output */
|
||||
TIM5_TRGSelection_TIM3 = ((uint8_t)0x20), /*!< TRIG Input source = TIM TRIG Output */
|
||||
TIM5_TRGSelection_TIM2 = ((uint8_t)0x30), /*!< TRIG Input source = TIM TRIG Output */
|
||||
TIM5_TRGSelection_TI1F_ED = ((uint8_t)0x40), /*!< TRIG Input source = TI1F_ED (TI1 Edge Detector) */
|
||||
TIM5_TRGSelection_TI1FP1 = ((uint8_t)0x50), /*!< TRIG Input source = TI1FP1 (Filtered Timer Input 1) */
|
||||
TIM5_TRGSelection_TI2FP2 = ((uint8_t)0x60), /*!< TRIG Input source = TI2FP2 (Filtered Timer Input 2) */
|
||||
TIM5_TRGSelection_ETRF = ((uint8_t)0x70) /*!< TRIG Input source = ETRF (External Trigger Input ) */
|
||||
}TIM5_TRGSelection_TypeDef;
|
||||
|
||||
#define IS_TIM5_TRIGGER_SELECTION(SELECTION) \
|
||||
(((SELECTION) == TIM5_TRGSelection_TIM4) || \
|
||||
((SELECTION) == TIM5_TRGSelection_TIM1) || \
|
||||
((SELECTION) == TIM5_TRGSelection_TIM3) || \
|
||||
((SELECTION) == TIM5_TRGSelection_TIM2) || \
|
||||
((SELECTION) == TIM5_TRGSelection_TI1F_ED) || \
|
||||
((SELECTION) == TIM5_TRGSelection_TI1FP1) || \
|
||||
((SELECTION) == TIM5_TRGSelection_TI2FP2) || \
|
||||
((SELECTION) == TIM5_TRGSelection_ETRF))
|
||||
|
||||
|
||||
#define IS_TIM5_TIX_TRIGGER_SELECTION(SELECTION) \
|
||||
(((SELECTION) == TIM5_TRGSelection_TI1F_ED) || \
|
||||
((SELECTION) == TIM5_TRGSelection_TI1FP1) || \
|
||||
((SELECTION) == TIM5_TRGSelection_TI2FP2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_TI_External_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_TIxExternalCLK1Source_TI1ED = ((uint8_t)0x40), /*!< External Clock mode 1 source = TI1ED */
|
||||
TIM5_TIxExternalCLK1Source_TI1 = ((uint8_t)0x50), /*!< External Clock mode 1 source = TI1 */
|
||||
TIM5_TIxExternalCLK1Source_TI2 = ((uint8_t)0x60) /*!< External Clock mode 1 source = TI2 */
|
||||
}TIM5_TIxExternalCLK1Source_TypeDef;
|
||||
|
||||
#define IS_TIM5_TIXCLK_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM5_TIxExternalCLK1Source_TI1ED) || \
|
||||
((SOURCE) == TIM5_TIxExternalCLK1Source_TI2) || \
|
||||
((SOURCE) == TIM5_TIxExternalCLK1Source_TI1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_External_Trigger_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_ExtTRGPolarity_Inverted = ((uint8_t)0x80), /*!< External Trigger Polarity = inverted */
|
||||
TIM5_ExtTRGPolarity_NonInverted = ((uint8_t)0x00) /*!< External Trigger Polarity = non inverted */
|
||||
}TIM5_ExtTRGPolarity_TypeDef;
|
||||
|
||||
#define IS_TIM5_EXT_POLARITY(POLARITY) \
|
||||
(((POLARITY) == TIM5_ExtTRGPolarity_Inverted) || \
|
||||
((POLARITY) == TIM5_ExtTRGPolarity_NonInverted))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Prescaler_Reload_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_PSCReloadMode_Update = ((uint8_t)0x00), /*!< Prescaler value is reloaded at every update*/
|
||||
TIM5_PSCReloadMode_Immediate = ((uint8_t)0x01) /*!< Prescaler value is reloaded immediatly*/
|
||||
}TIM5_PSCReloadMode_TypeDef;
|
||||
|
||||
#define IS_TIM5_PRESCALER_RELOAD(RELOAD) \
|
||||
(((RELOAD) == TIM5_PSCReloadMode_Update) || \
|
||||
((RELOAD) == TIM5_PSCReloadMode_Immediate))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Encoder_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_EncoderMode_TI1 = ((uint8_t)0x01), /*!< Encoder mode 1*/
|
||||
TIM5_EncoderMode_TI2 = ((uint8_t)0x02), /*!< Encoder mode 2*/
|
||||
TIM5_EncoderMode_TI12 = ((uint8_t)0x03) /*!< Encoder mode 3*/
|
||||
}TIM5_EncoderMode_TypeDef;
|
||||
|
||||
#define IS_TIM5_ENCODER_MODE(MODE) \
|
||||
(((MODE) == TIM5_EncoderMode_TI1) || \
|
||||
((MODE) == TIM5_EncoderMode_TI2) || \
|
||||
((MODE) == TIM5_EncoderMode_TI12))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Event_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_EventSource_Update = ((uint8_t)0x01), /*!< Update Event*/
|
||||
TIM5_EventSource_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Event*/
|
||||
TIM5_EventSource_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Event*/
|
||||
TIM5_EventSource_Trigger = ((uint8_t)0x40), /*!< Trigger Event*/
|
||||
TIM5_EventSource_Break = ((uint8_t)0x80) /*!< Break Event*/
|
||||
}TIM5_EventSource_TypeDef;
|
||||
|
||||
#define IS_TIM5_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint8_t)0x18) == 0x00) && \
|
||||
((SOURCE) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Update_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_UpdateSource_Global = ((uint8_t)0x00), /*!< Global Update request source */
|
||||
TIM5_UpdateSource_Regular = ((uint8_t)0x01) /*!< Regular Update request source */
|
||||
}TIM5_UpdateSource_TypeDef;
|
||||
|
||||
#define IS_TIM5_UPDATE_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM5_UpdateSource_Global) || \
|
||||
((SOURCE) == TIM5_UpdateSource_Regular))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Trigger_Output_Source
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_TRGOSource_Reset = ((uint8_t)0x00), /*!< Trigger Output source = Reset*/
|
||||
TIM5_TRGOSource_Enable = ((uint8_t)0x10), /*!< Trigger Output source = TIM5 is enabled*/
|
||||
TIM5_TRGOSource_Update = ((uint8_t)0x20), /*!< Trigger Output source = Update event*/
|
||||
TIM5_TRGOSource_OC1 = ((uint8_t)0x30), /*!< Trigger Output source = output compare channel1 */
|
||||
TIM5_TRGOSource_OC1REF = ((uint8_t)0x40), /*!< Trigger Output source = output compare channel 1 reference */
|
||||
TIM5_TRGOSource_OC2REF = ((uint8_t)0x50) /*!< Trigger Output source = output compare channel 2 reference */
|
||||
}TIM5_TRGOSource_TypeDef;
|
||||
|
||||
#define IS_TIM5_TRGO_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM5_TRGOSource_Reset) || \
|
||||
((SOURCE) == TIM5_TRGOSource_Enable) || \
|
||||
((SOURCE) == TIM5_TRGOSource_Update) || \
|
||||
((SOURCE) == TIM5_TRGOSource_OC1) || \
|
||||
((SOURCE) == TIM5_TRGOSource_OC1REF) || \
|
||||
((SOURCE) == TIM5_TRGOSource_OC2REF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Slave_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_SlaveMode_Reset = ((uint8_t)0x04), /*!< Slave Mode Selection = Reset*/
|
||||
TIM5_SlaveMode_Gated = ((uint8_t)0x05), /*!< Slave Mode Selection = Gated*/
|
||||
TIM5_SlaveMode_Trigger = ((uint8_t)0x06), /*!< Slave Mode Selection = Trigger*/
|
||||
TIM5_SlaveMode_External1 = ((uint8_t)0x07) /*!< Slave Mode Selection = External 1*/
|
||||
}TIM5_SlaveMode_TypeDef;
|
||||
|
||||
#define IS_TIM5_SLAVE_MODE(MODE) \
|
||||
(((MODE) == TIM5_SlaveMode_Reset) || \
|
||||
((MODE) == TIM5_SlaveMode_Gated) || \
|
||||
((MODE) == TIM5_SlaveMode_Trigger) || \
|
||||
((MODE) == TIM5_SlaveMode_External1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_Flags
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_FLAG_Update = ((uint16_t)0x0001), /*!< Update Flag */
|
||||
TIM5_FLAG_CC1 = ((uint16_t)0x0002), /*!< Capture compare 1 Flag */
|
||||
TIM5_FLAG_CC2 = ((uint16_t)0x0004), /*!< Capture compare 2 Flag */
|
||||
TIM5_FLAG_Trigger = ((uint16_t)0x0040), /*!< Trigger Flag */
|
||||
TIM5_FLAG_Break = ((uint16_t)0x0080), /*!< Break Flag */
|
||||
TIM5_FLAG_CC1OF = ((uint16_t)0x0200), /*!< Capture compare 1 over capture Flag */
|
||||
TIM5_FLAG_CC2OF = ((uint16_t)0x0400) /*!< Capture compare 2 over capture Flag */
|
||||
}TIM5_FLAG_TypeDef;
|
||||
|
||||
#define IS_TIM5_GET_FLAG(FLAG) \
|
||||
(((FLAG) == TIM5_FLAG_Update) || \
|
||||
((FLAG) == TIM5_FLAG_CC1) || \
|
||||
((FLAG) == TIM5_FLAG_CC2) || \
|
||||
((FLAG) == TIM5_FLAG_Trigger) || \
|
||||
((FLAG) == TIM5_FLAG_Break) || \
|
||||
((FLAG) == TIM5_FLAG_CC1OF) || \
|
||||
((FLAG) == TIM5_FLAG_CC2OF))
|
||||
|
||||
#define IS_TIM5_CLEAR_FLAG(FLAG) \
|
||||
((((FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM5_DMA_Source_Requests
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TIM5_DMASource_Update = ((uint8_t)0x01), /*!< TIM5 DMA Update Request*/
|
||||
TIM5_DMASource_CC1 = ((uint8_t)0x02), /*!< TIM5 DMA CC1 Request*/
|
||||
TIM5_DMASource_CC2 = ((uint8_t)0x04) /*!< TIM5 DMA CC2 Request*/
|
||||
}TIM5_DMASource_TypeDef;
|
||||
|
||||
#define IS_TIM5_DMA_SOURCE(SOURCE) \
|
||||
(((SOURCE) == TIM5_DMASource_Update) || \
|
||||
((SOURCE) == TIM5_DMASource_CC1) || \
|
||||
((SOURCE) == TIM5_DMASource_CC2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup TIM5_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro TIM5 Input Capture Filter Value
|
||||
*/
|
||||
#define IS_TIM5_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F)
|
||||
|
||||
/**
|
||||
* @brief Macro TIM5 External Trigger Filter
|
||||
*/
|
||||
#define IS_TIM5_EXT_FILTER(EXTFILTER) \
|
||||
((EXTFILTER) <= 0x0F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* TimeBase management ********************************************************/
|
||||
void TIM5_DeInit(void);
|
||||
void TIM5_TimeBaseInit(TIM5_Prescaler_TypeDef TIM5_Prescaler,
|
||||
TIM5_CounterMode_TypeDef TIM5_CounterMode, uint16_t TIM5_Period);
|
||||
void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler,
|
||||
TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode);
|
||||
void TIM5_CounterModeConfig(TIM5_CounterMode_TypeDef TIM5_CounterMode);
|
||||
void TIM5_SetCounter(uint16_t Counter);
|
||||
void TIM5_SetAutoreload(uint16_t Autoreload);
|
||||
uint16_t TIM5_GetCounter(void);
|
||||
TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void);
|
||||
void TIM5_UpdateDisableConfig(FunctionalState NewState);
|
||||
void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource);
|
||||
void TIM5_ARRPreloadConfig(FunctionalState NewState);
|
||||
void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode);
|
||||
void TIM5_Cmd(FunctionalState NewState);
|
||||
|
||||
/* Output Compare management **************************************************/
|
||||
void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode,
|
||||
TIM5_OutputState_TypeDef TIM5_OutputState,
|
||||
uint16_t TIM5_Pulse,
|
||||
TIM5_OCPolarity_TypeDef TIM5_OCPolarity,
|
||||
TIM5_OCIdleState_TypeDef TIM5_OCIdleState);
|
||||
void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode,
|
||||
TIM5_OutputState_TypeDef TIM5_OutputState,
|
||||
uint16_t TIM5_Pulse,
|
||||
TIM5_OCPolarity_TypeDef TIM5_OCPolarity,
|
||||
TIM5_OCIdleState_TypeDef TIM5_OCIdleState);
|
||||
void TIM5_BKRConfig(TIM5_OSSIState_TypeDef TIM5_OSSIState,
|
||||
TIM5_LockLevel_TypeDef TIM5_LockLevel,
|
||||
TIM5_BreakState_TypeDef TIM5_BreakState,
|
||||
TIM5_BreakPolarity_TypeDef TIM5_BreakPolarity,
|
||||
TIM5_AutomaticOutput_TypeDef TIM5_AutomaticOutput);
|
||||
void TIM5_CtrlPWMOutputs(FunctionalState NewState);
|
||||
void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode);
|
||||
void TIM5_SetCompare1(uint16_t Compare);
|
||||
void TIM5_SetCompare2(uint16_t Compare);
|
||||
void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);
|
||||
void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction);
|
||||
void TIM5_OC1PreloadConfig(FunctionalState NewState);
|
||||
void TIM5_OC2PreloadConfig(FunctionalState NewState);
|
||||
void TIM5_OC1FastConfig(FunctionalState NewState);
|
||||
void TIM5_OC2FastConfig(FunctionalState NewState);
|
||||
void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
|
||||
void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity);
|
||||
void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState);
|
||||
|
||||
/* Input Capture management ***************************************************/
|
||||
void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel,
|
||||
TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
|
||||
TIM5_ICSelection_TypeDef TIM5_ICSelection,
|
||||
TIM5_ICPSC_TypeDef TIM5_ICPrescaler,
|
||||
uint8_t TIM5_ICFilter);
|
||||
void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel,
|
||||
TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
|
||||
TIM5_ICSelection_TypeDef TIM5_ICSelection,
|
||||
TIM5_ICPSC_TypeDef TIM5_ICPrescaler,
|
||||
uint8_t TIM5_ICFilter);
|
||||
uint16_t TIM5_GetCapture1(void);
|
||||
uint16_t TIM5_GetCapture2(void);
|
||||
void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler);
|
||||
void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler);
|
||||
|
||||
/* Interrupts, DMA and flags management ***************************************/
|
||||
void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState);
|
||||
void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource);
|
||||
FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG);
|
||||
void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG);
|
||||
ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT);
|
||||
void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT);
|
||||
void TIM5_DMACmd(TIM5_DMASource_TypeDef TIM5_DMASource, FunctionalState NewState);
|
||||
void TIM5_SelectCCDMA(FunctionalState NewState);
|
||||
|
||||
/* Clocks management **********************************************************/
|
||||
void TIM5_InternalClockConfig(void);
|
||||
void TIM5_TIxExternalClockConfig(TIM5_TIxExternalCLK1Source_TypeDef TIM5_TIxExternalCLKSource,
|
||||
TIM5_ICPolarity_TypeDef TIM5_ICPolarity,
|
||||
uint8_t ICFilter);
|
||||
void TIM5_ETRClockMode1Config(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler,
|
||||
TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity,
|
||||
uint8_t ExtTRGFilter);
|
||||
void TIM5_ETRClockMode2Config(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler,
|
||||
TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity,
|
||||
uint8_t ExtTRGFilter);
|
||||
|
||||
/* Synchronization management *************************************************/
|
||||
void TIM5_SelectInputTrigger(TIM5_TRGSelection_TypeDef TIM5_InputTriggerSource);
|
||||
void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource);
|
||||
void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode);
|
||||
void TIM5_SelectMasterSlaveMode(FunctionalState NewState);
|
||||
void TIM5_ETRConfig(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler,
|
||||
TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity,
|
||||
uint8_t ExtTRGFilter);
|
||||
|
||||
/* Specific interface management **********************************************/
|
||||
void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode,
|
||||
TIM5_ICPolarity_TypeDef TIM5_IC1Polarity,
|
||||
TIM5_ICPolarity_TypeDef TIM5_IC2Polarity);
|
||||
void TIM5_SelectHallSensor(FunctionalState NewState);
|
||||
|
||||
#endif /* __STM8L15x_TIM5_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
393
firmware/inc/stm8l151x/inc/stm8l15x_usart.h
Normal file
393
firmware/inc/stm8l151x/inc/stm8l15x_usart.h
Normal file
@@ -0,0 +1,393 @@
|
||||
/**
|
||||
********************************************************************************
|
||||
* @file stm8l15x_usart.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the USART firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_USART_H
|
||||
#define __STM8L15x_USART_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
#include "stm8l15x_clk.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup USART_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_FLAG_TXE = (uint16_t)0x0080, /*!< Transmit Data Register Empty flag */
|
||||
USART_FLAG_TC = (uint16_t)0x0040, /*!< Transmission Complete flag */
|
||||
USART_FLAG_RXNE = (uint16_t)0x0020, /*!< Read Data Register Not Empty flag */
|
||||
USART_FLAG_IDLE = (uint16_t)0x0010, /*!< Idle line detected flag */
|
||||
USART_FLAG_OR = (uint16_t)0x0008, /*!< OverRun error flag */
|
||||
USART_FLAG_NF = (uint16_t)0x0004, /*!< Noise error flag */
|
||||
USART_FLAG_FE = (uint16_t)0x0002, /*!< Framing Error flag */
|
||||
USART_FLAG_PE = (uint16_t)0x0001, /*!< Parity Error flag */
|
||||
USART_FLAG_SBK = (uint16_t)0x0101 /*!< Send Break characters Flag */
|
||||
} USART_FLAG_TypeDef;
|
||||
|
||||
#define IS_USART_FLAG(Flag) \
|
||||
(((Flag) == USART_FLAG_TXE) || \
|
||||
((Flag) == USART_FLAG_TC) || \
|
||||
((Flag) == USART_FLAG_RXNE) || \
|
||||
((Flag) == USART_FLAG_IDLE) || \
|
||||
((Flag) == USART_FLAG_OR) || \
|
||||
((Flag) == USART_FLAG_NF) || \
|
||||
((Flag) == USART_FLAG_FE) || \
|
||||
((Flag) == USART_FLAG_PE) || \
|
||||
((Flag) == USART_FLAG_SBK))
|
||||
|
||||
#define IS_USART_CLEAR_FLAG(Flag) (((Flag) == USART_FLAG_TC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief USART Interrupt definition
|
||||
* USART_IT possible values
|
||||
* Elements values convention: 0x0ZYX
|
||||
* X: Position of the corresponding Interrupt
|
||||
* Y: Flag position
|
||||
* Z: Register index
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_IT_TXE = (uint16_t)0x0277, /*!< Transmit interrupt */
|
||||
USART_IT_TC = (uint16_t)0x0266, /*!< Transmission Complete interrupt */
|
||||
USART_IT_RXNE = (uint16_t)0x0255, /*!< Receive interrupt */
|
||||
USART_IT_IDLE = (uint16_t)0x0244, /*!< IDLE line interrupt */
|
||||
USART_IT_OR = (uint16_t)0x0235, /*!< Overrun Error interrupt */
|
||||
USART_IT_PE = (uint16_t)0x0100, /*!< Parity Error interrupt */
|
||||
USART_IT_ERR = (uint16_t)0x0500, /*!< Error interrupt */
|
||||
USART_IT_NF = (uint16_t)0x0102, /*!< Noise Error interrupt */
|
||||
USART_IT_FE = (uint16_t)0x0101 /*!< Frame Error interrupt */
|
||||
} USART_IT_TypeDef;
|
||||
|
||||
#define IS_USART_CONFIG_IT(Interrupt) \
|
||||
(((Interrupt) == USART_IT_PE) || \
|
||||
((Interrupt) == USART_IT_TXE) || \
|
||||
((Interrupt) == USART_IT_TC) || \
|
||||
((Interrupt) == USART_IT_RXNE) || \
|
||||
((Interrupt) == USART_IT_OR) || \
|
||||
((Interrupt) == USART_IT_ERR) || \
|
||||
((Interrupt) == USART_IT_IDLE))
|
||||
|
||||
#define IS_USART_GET_IT(ITPendingBit) \
|
||||
(((ITPendingBit) == USART_IT_TXE) || \
|
||||
((ITPendingBit) == USART_IT_TC) || \
|
||||
((ITPendingBit) == USART_IT_RXNE) || \
|
||||
((ITPendingBit) == USART_IT_IDLE) || \
|
||||
((ITPendingBit) == USART_IT_OR) || \
|
||||
((ITPendingBit) == USART_IT_PE))
|
||||
|
||||
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Wakeup_Modes
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_WakeUp_IdleLine = (uint8_t)0x00, /*!< 0x01 Idle Line wake up */
|
||||
USART_WakeUp_AddressMark = (uint8_t)0x08 /*!< 0x02 Address Mark wake up */
|
||||
} USART_WakeUp_TypeDef;
|
||||
|
||||
#define IS_USART_WAKEUP(WakeUpMode)(((WakeUpMode) == USART_WakeUp_IdleLine) || \
|
||||
((WakeUpMode) == USART_WakeUp_AddressMark))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_StopBits_1 = (uint8_t)0x00, /*!< One stop bit is transmitted at the end of frame*/
|
||||
USART_StopBits_2 = (uint8_t)0x20, /*!< Two stop bits are transmitted at the end of frame*/
|
||||
USART_StopBits_1_5 = (uint8_t)0x30 /*!< One and half stop bits*/
|
||||
} USART_StopBits_TypeDef;
|
||||
|
||||
#define IS_USART_STOPBITS(StopBit)(((StopBit) == USART_StopBits_1) || \
|
||||
((StopBit) == USART_StopBits_1_5) || \
|
||||
((StopBit) == USART_StopBits_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_Parity_No = (uint8_t)0x00, /*!< No Parity*/
|
||||
USART_Parity_Even = (uint8_t)0x04, /*!< Even Parity*/
|
||||
USART_Parity_Odd = (uint8_t)0x06 /*!< Odd Parity*/
|
||||
} USART_Parity_TypeDef;
|
||||
|
||||
#define IS_USART_PARITY(Parity)(((Parity) == USART_Parity_No) || \
|
||||
((Parity) == USART_Parity_Even) || \
|
||||
((Parity) == USART_Parity_Odd ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Lin_Break_Detection_Length
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_LINBreakDetectionLength_10BITS = (uint8_t)0x00, /*!< 10 bits Lin Break detection */
|
||||
USART_LINBreakDetectionLength_11BITS = (uint8_t)0x01 /*!< 11 bits Lin Break detection */
|
||||
} USART_LINBreakDetectionLength_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Word_Length
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_WordLength_8b = (uint8_t)0x00, /*!< 8 bits Data */
|
||||
USART_WordLength_9b = (uint8_t)0x10 /*!< 9 bits Data */
|
||||
} USART_WordLength_TypeDef;
|
||||
|
||||
#define IS_USART_WORDLENGTH(WordLength) (((WordLength) == USART_WordLength_8b) || \
|
||||
((WordLength) == USART_WordLength_9b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_Mode_Rx = (uint8_t)0x04, /*!< Receive Enable */
|
||||
USART_Mode_Tx = (uint8_t)0x08 /*!< Transmit Enable */
|
||||
} USART_Mode_TypeDef;
|
||||
|
||||
#define IS_USART_MODE(MODE) ((((MODE) & (uint8_t)0xF3) == 0x00) && ((MODE) != (uint16_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DMA_Requests
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_DMAReq_TX = (uint8_t)0x80, /*!< Receive DMA request Enable */
|
||||
USART_DMAReq_RX = (uint8_t)0x40 /*!< Transmit DMA request Enable */
|
||||
} USART_DMAReq_TypeDef;
|
||||
|
||||
#define IS_USART_DMAREQ(DMAReq) ((((DMAReq) & (uint8_t)0x3F) == 0x00) && ((DMAReq) != (uint8_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_IrDA_Mode
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_IrDAMode_Normal = (uint8_t)0x00, /*!< IrDA Normal Mode */
|
||||
USART_IrDAMode_LowPower = (uint8_t)0x01 /*!< IrDA Low Power Mode */
|
||||
} USART_IrDAMode_TypeDef;
|
||||
|
||||
#define IS_USART_IRDAMODE(IrDAMode) (((IrDAMode) == USART_IrDAMode_LowPower) || \
|
||||
((IrDAMode) == USART_IrDAMode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_Clock_Disable = (uint8_t)0x00, /*!< CK pin disabled */
|
||||
USART_Clock_Enable = (uint8_t)0x08 /*!< CK pin enabled */
|
||||
} USART_Clock_TypeDef;
|
||||
|
||||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) ||((CLOCK) == USART_Clock_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CPOL_Low = (uint8_t)0x00, /*!< CK to 0 when idle */
|
||||
USART_CPOL_High = (uint8_t)0x04 /*!< CK to 1 when idle.*/
|
||||
} USART_CPOL_TypeDef;
|
||||
|
||||
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CPHA_1Edge = (uint8_t)0x00, /*!< The first clock transition is the first data capture edge*/
|
||||
USART_CPHA_2Edge = (uint8_t)0x02 /*!< The second clock transition is the first data capture edge*/
|
||||
} USART_CPHA_TypeDef;
|
||||
|
||||
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_LastBit
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_LastBit_Disable = (uint8_t)0x00, /*!< The clock pulse of the last data bit is not output to the SCLK pin.*/
|
||||
USART_LastBit_Enable = (uint8_t)0x01 /*!< The clock pulse of the last data bit is output to the SCLK pin.*/
|
||||
} USART_LastBit_TypeDef;
|
||||
|
||||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
|
||||
((LASTBIT) == USART_LastBit_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroupUSART_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/* BaudRate value should be < 625000 bps */
|
||||
#define IS_USART_BAUDRATE(NUM) ((NUM) <= (uint32_t)625000)
|
||||
|
||||
#define USART_ADDRESS_MAX ((uint8_t)16)
|
||||
#define IS_USART_ADDRESS(address) ((address) < USART_ADDRESS_MAX)
|
||||
|
||||
#define USART_DATA_9BITS_MAX ((uint16_t)0x1FF)
|
||||
#define IS_USART_DATA_9BITS(DATA) ((DATA) < USART_DATA_9BITS_MAX)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the USART configuration to the default reset state ***/
|
||||
void USART_DeInit(USART_TypeDef* USARTx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void USART_Init(USART_TypeDef* USARTx, uint32_t BaudRate, USART_WordLength_TypeDef
|
||||
USART_WordLength, USART_StopBits_TypeDef USART_StopBits,
|
||||
USART_Parity_TypeDef USART_Parity, USART_Mode_TypeDef USART_Mode);
|
||||
void USART_ClockInit(USART_TypeDef* USARTx, USART_Clock_TypeDef USART_Clock,
|
||||
USART_CPOL_TypeDef USART_CPOL, USART_CPHA_TypeDef USART_CPHA,
|
||||
USART_LastBit_TypeDef USART_LastBit);
|
||||
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||
void USART_SendBreak(USART_TypeDef* USARTx);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void USART_SendData8(USART_TypeDef* USARTx, uint8_t Data);
|
||||
void USART_SendData9(USART_TypeDef* USARTx, uint16_t Data);
|
||||
uint8_t USART_ReceiveData8(USART_TypeDef* USARTx);
|
||||
uint16_t USART_ReceiveData9(USART_TypeDef* USARTx);
|
||||
|
||||
/* Multi-Processor Communication functions ************************************/
|
||||
void USART_WakeUpConfig(USART_TypeDef* USARTx, USART_WakeUp_TypeDef USART_WakeUp);
|
||||
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||
|
||||
/* Half-duplex mode function **************************************************/
|
||||
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Smartcard mode functions ***************************************************/
|
||||
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||
|
||||
/* IrDA mode functions ********************************************************/
|
||||
void USART_IrDAConfig(USART_TypeDef* USARTx, USART_IrDAMode_TypeDef USART_IrDAMode);
|
||||
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void USART_DMACmd(USART_TypeDef* USARTx, USART_DMAReq_TypeDef USART_DMAReq,
|
||||
FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void USART_ITConfig(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT,
|
||||
FunctionalState NewState);
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG);
|
||||
void USART_ClearFlag(USART_TypeDef* USARTx, USART_FLAG_TypeDef USART_FLAG);
|
||||
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT);
|
||||
void USART_ClearITPendingBit(USART_TypeDef* USARTx, USART_IT_TypeDef USART_IT);
|
||||
|
||||
|
||||
|
||||
#endif /* __STM8L15x_USART_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
154
firmware/inc/stm8l151x/inc/stm8l15x_wfe.h
Normal file
154
firmware/inc/stm8l151x/inc/stm8l15x_wfe.h
Normal file
@@ -0,0 +1,154 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_wfe.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the WFE firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_WFE_H
|
||||
#define __STM8L15x_WFE_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WFE
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WFE_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup WFE_Sources
|
||||
* @brief Signal Sources to generate wake_up events
|
||||
@verbatim
|
||||
Elements values convention: 0xXXYY
|
||||
X = SRx registers index
|
||||
XX = 01 : CR1
|
||||
XX = 02 : CR2
|
||||
XX = 03 : CR3
|
||||
XX = 04 : CR4
|
||||
YY = flag mask in the dedicated register(XX register)
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
typedef enum {
|
||||
WFE_Source_TIM2_EV0 = (uint16_t)0x0101, /*!< TIM2 Update/Trigger and Break interrupt */
|
||||
WFE_Source_TIM2_EV1 = (uint16_t)0x0102, /*!< TIM2 Capture/Compare interrupt */
|
||||
WFE_Source_TIM1_EV0 = (uint16_t)0x0104, /*!< TIM1 Update/Trigger and Break interrupt */
|
||||
WFE_Source_TIM1_EV1 = (uint16_t)0x0108, /*!< TIM1 Capture/Compare interrupt */
|
||||
WFE_Source_EXTI_EV0 = (uint16_t)0x0110, /*!< I/O port interrupt from Pins 0 */
|
||||
WFE_Source_EXTI_EV1 = (uint16_t)0x0120, /*!< I/O port interrupt from Pins 1 */
|
||||
WFE_Source_EXTI_EV2 = (uint16_t)0x0140, /*!< I/O port interrupt from Pins 2 */
|
||||
WFE_Source_EXTI_EV3 = (uint16_t)0x0180, /*!< I/O port interrupt from Pins 3 */
|
||||
WFE_Source_EXTI_EV4 = (uint16_t)0x0201, /*!< I/O port interrupt from Pins 4 */
|
||||
WFE_Source_EXTI_EV5 = (uint16_t)0x0202, /*!< I/O port interrupt from Pins 5 */
|
||||
WFE_Source_EXTI_EV6 = (uint16_t)0x0204, /*!< I/O port interrupt from Pins 6 */
|
||||
WFE_Source_EXTI_EV7 = (uint16_t)0x0208, /*!< I/O port interrupt from Pins 7 */
|
||||
WFE_Source_EXTI_EVB_G = (uint16_t)0x0210, /*!< I/O port interrupt from port B and G */
|
||||
WFE_Source_EXTI_EVD_H = (uint16_t)0x0220, /*!< I/O port interrupt from Port D and H */
|
||||
WFE_Source_EXTI_EVE_F = (uint16_t)0x0240, /*!< I/O port interrupt from Port E and F */
|
||||
WFE_Source_ADC1_COMP_EV = (uint16_t)0x0280, /*!< ADC1, COMP1 and COMP2 interrupts */
|
||||
WFE_Source_TIM3_EV0 = (uint16_t)0x0301, /*!< TIM3 Update/Trigger and Break interrupt */
|
||||
WFE_Source_TIM3_EV1 = (uint16_t)0x0302, /*!< TIM3 Capture/Compare interrupt */
|
||||
WFE_Source_TIM4_EV = (uint16_t)0x0304, /*!< TIM4 Update and Trigger interrupt */
|
||||
WFE_Source_SPI1_EV = (uint16_t)0x0308, /*!< SPI1 Rx and Tx interrupt */
|
||||
WFE_Source_I2C1_EV = (uint16_t)0x0310, /*!< I2C1 Rx and Tx interrupt */
|
||||
WFE_Source_USART1_EV = (uint16_t)0x0320, /*!< USART1 Rx and Tx interrupt */
|
||||
WFE_Source_DMA1CH01_EV = (uint16_t)0x0340, /*!< DMA1 channel 0 and 1 interrupt */
|
||||
WFE_Source_DMA1CH23_EV = (uint16_t)0x0380, /*!< DMA1 channel 2 and 3 interrupt */
|
||||
WFE_Source_RTC_CSS_EV = (uint16_t)0x0401, /*!< RTC or CSS on LSE event */
|
||||
WFE_Source_SPI2_EV = (uint16_t)0x0402, /*!< SPI2 Rx and Tx interrupt */
|
||||
WFE_Source_USART2_EV = (uint16_t)0x0404, /*!< USART2 Rx and Tx interrupt */
|
||||
WFE_Source_USART3_EV = (uint16_t)0x0408, /*!< USART3 Rx and Tx interrupt */
|
||||
WFE_Source_TIM5_EV0 = (uint16_t)0x0410, /*!< TIM5 Update/Trigger and Break interrupt */
|
||||
WFE_Source_TIM5_EV1 = (uint16_t)0x0420, /*!< TIM5 Capture/Compare interrupt */
|
||||
WFE_Source_AES_EV = (uint16_t)0x0440 /*!< AES interrupt */
|
||||
} WFE_Source_TypeDef;
|
||||
|
||||
#define IS_WFE_SOURCE(Source) (((Source) == WFE_Source_TIM2_EV0) || \
|
||||
((Source) == WFE_Source_TIM2_EV1) || \
|
||||
((Source) == WFE_Source_TIM1_EV0) || \
|
||||
((Source) == WFE_Source_TIM1_EV1) || \
|
||||
((Source) == WFE_Source_EXTI_EV0) || \
|
||||
((Source) == WFE_Source_EXTI_EV1) || \
|
||||
((Source) == WFE_Source_EXTI_EV2) || \
|
||||
((Source) == WFE_Source_EXTI_EV3) || \
|
||||
((Source) == WFE_Source_EXTI_EV4) || \
|
||||
((Source) == WFE_Source_EXTI_EV5) || \
|
||||
((Source) == WFE_Source_EXTI_EV6) || \
|
||||
((Source) == WFE_Source_EXTI_EV7) || \
|
||||
((Source) == WFE_Source_EXTI_EVB_G) || \
|
||||
((Source) == WFE_Source_EXTI_EVD_H) || \
|
||||
((Source) == WFE_Source_EXTI_EVE_F) || \
|
||||
((Source) == WFE_Source_ADC1_COMP_EV) || \
|
||||
((Source) == WFE_Source_TIM3_EV0) || \
|
||||
((Source) == WFE_Source_TIM3_EV1) || \
|
||||
((Source) == WFE_Source_TIM4_EV) || \
|
||||
((Source) == WFE_Source_SPI1_EV) || \
|
||||
((Source) == WFE_Source_I2C1_EV) || \
|
||||
((Source) == WFE_Source_USART1_EV) || \
|
||||
((Source) == WFE_Source_DMA1CH01_EV) || \
|
||||
((Source) == WFE_Source_AES_EV) || \
|
||||
((Source) == WFE_Source_TIM5_EV1) || \
|
||||
((Source) == WFE_Source_TIM5_EV0) || \
|
||||
((Source) == WFE_Source_USART3_EV) || \
|
||||
((Source) == WFE_Source_USART2_EV) || \
|
||||
((Source) == WFE_Source_SPI2_EV) || \
|
||||
((Source) == WFE_Source_RTC_CSS_EV) || \
|
||||
((Source) == WFE_Source_DMA1CH23_EV))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the WFE configuration to the default reset state ******/
|
||||
void WFE_DeInit(void);
|
||||
|
||||
/* WFE Source configuration and management functions **************************/
|
||||
void WFE_WakeUpSourceEventCmd(WFE_Source_TypeDef WFE_Source, FunctionalState NewState);
|
||||
FunctionalState WFE_GetWakeUpSourceEventStatus(WFE_Source_TypeDef WFE_Source);
|
||||
|
||||
#endif /* __STM8L15x_WFE_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
96
firmware/inc/stm8l151x/inc/stm8l15x_wwdg.h
Normal file
96
firmware/inc/stm8l151x/inc/stm8l15x_wwdg.h
Normal file
@@ -0,0 +1,96 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file contains all the functions prototypes for the WWDG firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM8L15x_WWDG_H
|
||||
#define __STM8L15x_WWDG_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_WindowLimitValue
|
||||
* @{
|
||||
*/
|
||||
#define IS_WWDG_WINDOW_LIMIT_VALUE(WindowLimitValue) ((WindowLimitValue) <= 0x7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_CounterValue
|
||||
* @{
|
||||
*/
|
||||
#define IS_WWDG_COUNTER_VALUE(CounterValue) ((CounterValue) <= 0x7F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Refresh window and Counter configuration functions *************************/
|
||||
void WWDG_Init(uint8_t Counter, uint8_t WindowValue);
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||
void WWDG_SetCounter(uint8_t Counter);
|
||||
|
||||
/* WWDG activation function ***************************************************/
|
||||
void WWDG_Enable(uint8_t Counter);
|
||||
|
||||
/* WWDG counter and software reset management **********************************/
|
||||
uint8_t WWDG_GetCounter(void);
|
||||
void WWDG_SWReset(void);
|
||||
|
||||
|
||||
#endif /* __STM8L15x_WWDG_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
988
firmware/inc/stm8l151x/src/stm8l15x_adc.c
Normal file
988
firmware/inc/stm8l151x/src/stm8l15x_adc.c
Normal file
@@ -0,0 +1,988 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_adc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
|
||||
* - Initialization and Configuration
|
||||
* - Power saving
|
||||
* - Analog Watchdog configuration
|
||||
* - Temperature Sensor & Vrefint (Voltage Reference internal) management
|
||||
* - Regular Channels Configuration
|
||||
* - Regular Channels DMA Configuration
|
||||
* - Injected channels Configuration
|
||||
* - Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* 1. Enable The ADC controller clock using CLK_PeripheralClockConfig()
|
||||
* function : CLK_PeripheralClockConfig(CLK_Peripheral_ADC1, ENABLE).
|
||||
*
|
||||
* 2. Configure the ADC Prescaler, conversion resolution and data
|
||||
* alignment using the ADC_Init() function.
|
||||
*
|
||||
* 3. Activate the ADC peripheral using ADC_Cmd() function.
|
||||
*
|
||||
* Regular channels group configuration
|
||||
* ====================================
|
||||
* - To configure the ADC regular channels group features, use
|
||||
* ADC_Init() and ADC_RegularChannelConfig() functions.
|
||||
* - To activate the continuous mode, use the ADC_continuousModeCmd()
|
||||
* function.
|
||||
* - To configure and activate the Discontinuous mode, use the
|
||||
* ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
|
||||
* - To read the ADC converted values, use the ADC_GetConversionValue()
|
||||
* function.
|
||||
*
|
||||
* DMA for Regular channels group features configuration
|
||||
* ======================================================
|
||||
* - To enable the DMA mode for regular channels group, use the
|
||||
* ADC_DMACmd() function.
|
||||
* - To enable the generation of DMA requests continuously at the end
|
||||
* of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
|
||||
* function.
|
||||
|
||||
* Injected channels group configuration
|
||||
* =====================================
|
||||
* - To configure the ADC Injected channels group features, use
|
||||
* ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()
|
||||
* functions.
|
||||
* - To activate the continuous mode, use the ADC_continuousModeCmd()
|
||||
* function.
|
||||
* - To activate the Injected Discontinuous mode, use the
|
||||
* ADC_InjectedDiscModeCmd() function.
|
||||
* - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
|
||||
* function.
|
||||
* - To read the ADC converted values, use the ADC_GetInjectedConversionValue()
|
||||
* function.
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_adc.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC
|
||||
* @brief ADC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Initialization and Configuration functions
|
||||
===============================================================================
|
||||
This section provides functions allowing to:
|
||||
- Enable or disable the ADC peripheral,
|
||||
- Initialize and configure the ADC Prescaler, ADC Conversion Resolution
|
||||
(12bit..6bit), ADC Continuous Conversion Mode (Continuous or Single
|
||||
conversion),
|
||||
- Configure External trigger Sensitivity and source,
|
||||
- Start ADC conversion, by software trigger.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Deinitializes the ADC peripheral registers to their default reset
|
||||
* values.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_DeInit(ADC_TypeDef* ADCx)
|
||||
{
|
||||
/* Set the Configuration registers to their reset values */
|
||||
ADCx->CR1 = ADC_CR1_RESET_VALUE;
|
||||
ADCx->CR2 = ADC_CR2_RESET_VALUE;
|
||||
ADCx->CR3 = ADC_CR3_RESET_VALUE;
|
||||
|
||||
/* Set the status registers to their reset values */
|
||||
ADCx->SR = (uint8_t)~ADC_SR_RESET_VALUE;
|
||||
|
||||
/* Set the High threshold registers to their reset values */
|
||||
ADCx->HTRH = ADC_HTRH_RESET_VALUE;
|
||||
ADCx->HTRL = ADC_HTRL_RESET_VALUE;
|
||||
|
||||
/* Set the low threshold registers to their reset values */
|
||||
ADCx->LTRH = ADC_LTRH_RESET_VALUE;
|
||||
ADCx->LTRL = ADC_LTRL_RESET_VALUE;
|
||||
|
||||
/* Set the channels sequence registers to their reset values */
|
||||
ADCx->SQR[0] = ADC_SQR1_RESET_VALUE;
|
||||
ADCx->SQR[1] = ADC_SQR2_RESET_VALUE;
|
||||
ADCx->SQR[2] = ADC_SQR3_RESET_VALUE;
|
||||
ADCx->SQR[3] = ADC_SQR4_RESET_VALUE;
|
||||
|
||||
/* Set the channels Trigger registers to their reset values */
|
||||
ADCx->TRIGR[0] = ADC_TRIGR1_RESET_VALUE;
|
||||
ADCx->TRIGR[1] = ADC_TRIGR2_RESET_VALUE;
|
||||
ADCx->TRIGR[2] = ADC_TRIGR3_RESET_VALUE;
|
||||
ADCx->TRIGR[3] = ADC_TRIGR4_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the specified ADC peripheral according to the specified
|
||||
* parameters.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param ADC_ConversionMode : specifies the ADC conversion mode,
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_ConversionMode_Single: Single Conversion Mode
|
||||
* @arg ADC_ConversionMode_Continuous: Continuous Conversion Mode
|
||||
* @param ADC_Resolution : specifies the ADC Data resolution,
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_Resolution_12Bit: 12 bit resolution
|
||||
* @arg ADC_Resolution_10Bit: 10 bit resolution
|
||||
* @arg ADC_Resolution_8Bit: 8 bit resolution
|
||||
* @arg ADC_Resolution_6Bit: 6 bit resolution
|
||||
* @param ADC_Prescaler : specifies the ADC Prescaler,
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_Prescaler_1: ADC Clock frequency is divided by 1
|
||||
* @arg ADC_Prescaler_2: ADC Clock frequency is divided by 2
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_Init(ADC_TypeDef* ADCx,
|
||||
ADC_ConversionMode_TypeDef ADC_ConversionMode,
|
||||
ADC_Resolution_TypeDef ADC_Resolution,
|
||||
ADC_Prescaler_TypeDef ADC_Prescaler)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_CONVERSION_MODE(ADC_ConversionMode));
|
||||
assert_param(IS_ADC_RESOLUTION(ADC_Resolution));
|
||||
assert_param(IS_ADC_PRESCALER(ADC_Prescaler));
|
||||
|
||||
/*clear CR1 register */
|
||||
ADCx->CR1 &= (uint8_t)~(ADC_CR1_CONT | ADC_CR1_RES);
|
||||
|
||||
/* set the resolution and the conversion mode */
|
||||
ADCx->CR1 |= (uint8_t)((uint8_t)ADC_ConversionMode | (uint8_t)ADC_Resolution);
|
||||
|
||||
/*clear CR2 register */
|
||||
ADCx->CR2 &= (uint8_t)~(ADC_CR2_PRESC);
|
||||
|
||||
/* set the Prescaler */
|
||||
ADCx->CR2 |= (uint8_t) ADC_Prescaler;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected ADC peripheral.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param NewState : new state of the specified ADC peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Set the ADON bit to wake up the specified ADC from power down mode */
|
||||
ADCx->CR1 |= ADC_CR1_ADON;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected ADC peripheral */
|
||||
ADCx->CR1 &= (uint8_t)~ADC_CR1_ADON;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts ADC conversion, by software trigger.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
|
||||
{
|
||||
/* Start the ADC software conversion */
|
||||
ADCx->CR1 |= ADC_CR1_START;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the ADC conversion through external trigger.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param ADC_ExtEventSelection : Specifies the external trigger.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_ExtEventSelection_None: Conversion starts only by software start
|
||||
* @arg ADC_ExtEventSelection_Trigger1: Trigger 1 Enables conversion
|
||||
* @arg ADC_ExtEventSelection_Trigger2: Trigger 2 Enables conversion
|
||||
* @arg ADC_ExtEventSelection_Trigger3: Trigger 3 Enables conversion
|
||||
* @param ADC_ExtTRGSensitivity : Specifies the external trigger sensitivity.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_ExtTRGSensitivity_Rising: External Trigger Sensitivity is Rising Edge
|
||||
* @arg ADC_ExtTRGSensitivity_Falling: External Trigger Sensitivity is Falling Edge
|
||||
* @arg ADC_ExtTRGSensitivity_All: External Trigger Sensitivity is Falling and Rising Edge
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_ExternalTrigConfig(ADC_TypeDef* ADCx,
|
||||
ADC_ExtEventSelection_TypeDef ADC_ExtEventSelection,
|
||||
ADC_ExtTRGSensitivity_TypeDef ADC_ExtTRGSensitivity)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_EXT_EVENT_SELECTION(ADC_ExtEventSelection));
|
||||
assert_param(IS_ADC_EXT_TRG_SENSITIVITY(ADC_ExtTRGSensitivity));
|
||||
|
||||
/*clear old configuration of CR2 register */
|
||||
ADCx->CR2 &= (uint8_t)~(ADC_CR2_TRIGEDGE | ADC_CR2_EXTSEL);
|
||||
|
||||
/* set the External Trigger Edge Sensitivity and the external event
|
||||
selection */
|
||||
ADCx->CR2 |= (uint8_t)( (uint8_t)ADC_ExtTRGSensitivity | \
|
||||
(uint8_t)ADC_ExtEventSelection);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group2 Analog Watchdog configuration functions
|
||||
* @brief Analog Watchdog configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Analog Watchdog configuration functions
|
||||
===============================================================================
|
||||
|
||||
This section provides functions allowing to configure the Analog Watchdog
|
||||
(AWD) feature in the ADC.
|
||||
|
||||
A typical configuration Analog Watchdog is done following these steps :
|
||||
1. the ADC guarded channel is selected using the
|
||||
ADC_AnalogWatchdogChannelSelect() function.
|
||||
2. The Analog watchdog lower and higher threshold are configured using the
|
||||
ADC_AnalogWatchdogThresholdsConfig() function.
|
||||
|
||||
Note : Both AWD selection and thresholds can be configured with one unique
|
||||
function ADC_AnalogWatchdogConfig(), which is kept for firmware
|
||||
compatibility reason.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Configures the channel to be checked by the Analog watchdog.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param ADC_AnalogWatchdogSelection : Specifies the channel to be checked
|
||||
* by the Analog watchdog.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel0: AWD affected to Channel 0
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel1: AWD affected to Channel 1
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel2: AWD affected to Channel 2
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel3: AWD affected to Channel 3
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel4: AWD affected to Channel 4
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel5: AWD affected to Channel 5
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel6: AWD affected to Channel 6
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel7: AWD affected to Channel 7
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel8: AWD affected to Channel 8
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel9: AWD affected to Channel 9
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel10: AWD affected to Channel 10
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel11: AWD affected to Channel 11
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel12: AWD affected to Channel 12
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel13: AWD affected to Channel 13
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel14: AWD affected to Channel 14
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel15: AWD affected to Channel 15
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel16: AWD affected to Channel 16
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel17: AWD affected to Channel 17
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel18: AWD affected to Channel 18
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel19: AWD affected to Channel 19
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel20: AWD affected to Channel 20
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel21: AWD affected to Channel 21
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel22: AWD affected to Channel 22
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel23: AWD affected to Channel 23
|
||||
* @ref ADC_AnalogWatchdogSelection_TypeDef enumeration.
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_AnalogWatchdogChannelSelect(ADC_TypeDef* ADCx,
|
||||
ADC_AnalogWatchdogSelection_TypeDef ADC_AnalogWatchdogSelection)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ANALOGWATCHDOG_SELECTION(ADC_AnalogWatchdogSelection));
|
||||
|
||||
/* Reset the CHSEL bits */
|
||||
ADCx->CR3 &= ((uint8_t)~ADC_CR3_CHSEL);
|
||||
|
||||
/* Select the channel to be checked by the Analog watchdog */
|
||||
ADCx->CR3 |= (uint8_t)ADC_AnalogWatchdogSelection;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the high and low thresholds of the Analog watchdog.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param HighThreshold: Analog watchdog High threshold value.
|
||||
* This parameter must be a 12bit value.
|
||||
* @param LowThreshold: Analog watchdog Low threshold value.
|
||||
* This parameter must be a 12bit value.
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_THRESHOLD(HighThreshold));
|
||||
assert_param(IS_ADC_THRESHOLD(LowThreshold));
|
||||
|
||||
/* Set the ADC high threshold */
|
||||
ADCx->HTRH = (uint8_t)(HighThreshold >> 8);
|
||||
ADCx->HTRL = (uint8_t)(HighThreshold);
|
||||
|
||||
/* Set the ADC low threshold */
|
||||
ADCx->LTRH = (uint8_t)(LowThreshold >> 8);
|
||||
ADCx->LTRL = (uint8_t)(LowThreshold);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the Analog watchdog.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param ADC_AnalogWatchdogSelection : Specifies the channel to be checked
|
||||
* by the Analog watchdog.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel0: AWD affected to Channel 0
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel1: AWD affected to Channel 1
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel2: AWD affected to Channel 2
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel3: AWD affected to Channel 3
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel4: AWD affected to Channel 4
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel5: AWD affected to Channel 5
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel6: AWD affected to Channel 6
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel7: AWD affected to Channel 7
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel8: AWD affected to Channel 8
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel9: AWD affected to Channel 9
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel10: AWD affected to Channel 10
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel11: AWD affected to Channel 11
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel12: AWD affected to Channel 12
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel13: AWD affected to Channel 13
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel14: AWD affected to Channel 14
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel15: AWD affected to Channel 15
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel16: AWD affected to Channel 16
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel17: AWD affected to Channel 17
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel18: AWD affected to Channel 18
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel19: AWD affected to Channel 19
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel20: AWD affected to Channel 20
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel21: AWD affected to Channel 21
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel22: AWD affected to Channel 22
|
||||
* @arg ADC_AnalogWatchdogSelection_Channel23: AWD affected to Channel 23
|
||||
* @param HighThreshold: Analog watchdog High threshold value.
|
||||
* This parameter must be a 12bit value.
|
||||
* @param LowThreshold: Analog watchdog Low threshold value.
|
||||
* This parameter must be a 12bit value.
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_AnalogWatchdogConfig(ADC_TypeDef* ADCx,
|
||||
ADC_AnalogWatchdogSelection_TypeDef ADC_AnalogWatchdogSelection,
|
||||
uint16_t HighThreshold,
|
||||
uint16_t LowThreshold)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_ANALOGWATCHDOG_SELECTION(ADC_AnalogWatchdogSelection));
|
||||
assert_param(IS_ADC_THRESHOLD(HighThreshold));
|
||||
assert_param(IS_ADC_THRESHOLD(LowThreshold));
|
||||
|
||||
/*Reset the CHSEL bits */
|
||||
ADCx->CR3 &= ((uint8_t)~ADC_CR3_CHSEL);
|
||||
|
||||
/* Select the channel to be checked by the Analog watchdog.*/
|
||||
ADCx->CR3 |= (uint8_t)ADC_AnalogWatchdogSelection;
|
||||
|
||||
/* Set the ADC high threshold */
|
||||
ADCx->HTRH = (uint8_t)(HighThreshold >> 8);
|
||||
ADCx->HTRL = (uint8_t)(HighThreshold);
|
||||
|
||||
/* Set the ADC low threshold */
|
||||
ADCx->LTRH = (uint8_t)(LowThreshold >> 8);
|
||||
ADCx->LTRL = (uint8_t)LowThreshold;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group3 Temperature Sensor & Vrefint (Voltage Reference
|
||||
* internal) management functions
|
||||
* @brief Temperature Sensor & Vrefint (Voltage Reference internal)
|
||||
* management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Temperature Sensor & Vrefint (Voltage Reference internal) management functions
|
||||
===============================================================================
|
||||
|
||||
This section provides functions allowing to enable/ disable the internal
|
||||
connections between the ADC and the Temperature Sensor and the Vrefint source.
|
||||
|
||||
A typical configuration to get the Temperature sensor or/and Vrefint channels
|
||||
voltages is done following these steps :
|
||||
1. Enable the internal connection of Temperature sensor or/and Vrefint sources
|
||||
with the ADC channels:
|
||||
- for the Temperature sensor using ADC_TempSensorCmd() function.
|
||||
- for the Internal Voltage reference using ADC_VrefintCmd() function.
|
||||
2. Enable the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint channels
|
||||
using ADC_ChannelCmd()function.
|
||||
3. Get the voltage values, using ADC_GetConversionValue().
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Temperature sensor internal reference.
|
||||
* @param NewState : new state of the Temperature sensor internal reference.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_TempSensorCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/*Enable the Temperature sensor internal reference.*/
|
||||
ADC1->TRIGR[0] |= (uint8_t)(ADC_TRIGR1_TSON);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Disable the Temperature sensor internal reference.*/
|
||||
ADC1->TRIGR[0] &= (uint8_t)(~ADC_TRIGR1_TSON);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Internal Voltage reference.
|
||||
* @param NewState : new state of the Internal Voltage reference.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_VrefintCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the Internal Voltage reference.*/
|
||||
ADC1->TRIGR[0] |= (uint8_t)(ADC_TRIGR1_VREFINTON);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Internal Voltage reference.*/
|
||||
ADC1->TRIGR[0] &= (uint8_t)(~ADC_TRIGR1_VREFINTON);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup ADC_Group4 Channels Configuration functions
|
||||
* @brief Channels Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Channels Configuration functions
|
||||
===============================================================================
|
||||
This section provides functions allowing to:
|
||||
- Enable or disable the ADC channel using ADC_ChannelCmd() function,
|
||||
- Configure the channels sampling times using ADC_SamplingTimeConfig()
|
||||
function.
|
||||
Note: there are 2 sampling times configuration values :
|
||||
- 1st Group value : for channels 0..23
|
||||
- 2nd Group value : for channels 24..27 (depending on the MCU
|
||||
package density) and Temperature Sensor and Vrefint channels.
|
||||
- Configure the channels Schmitt Trigger for each channel using
|
||||
ADC_SchmittTriggerConfig() function.
|
||||
- Get the current ADC conversion value.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected ADC channel(s).
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param ADC_Channels: specifies the ADC channels to be initialized
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_Channel_0: Channel 0
|
||||
* @arg ADC_Channel_1: Channel 1
|
||||
* @arg ADC_Channel_2: Channel 2
|
||||
* @arg ADC_Channel_3: Channel 3
|
||||
* @arg ADC_Channel_4: Channel 4
|
||||
* @arg ADC_Channel_5: Channel 5
|
||||
* @arg ADC_Channel_6: Channel 6
|
||||
* @arg ADC_Channel_7: Channel 7
|
||||
* @arg ADC_Channel_8: Channel 8
|
||||
* @arg ADC_Channel_9: Channel 9
|
||||
* @arg ADC_Channel_10: Channel 10
|
||||
* @arg ADC_Channel_11: Channel 11
|
||||
* @arg ADC_Channel_12: Channel 12
|
||||
* @arg ADC_Channel_13: Channel 13
|
||||
* @arg ADC_Channel_14: Channel 14
|
||||
* @arg ADC_Channel_15: Channel 15
|
||||
* @arg ADC_Channel_16: Channel 16
|
||||
* @arg ADC_Channel_17: Channel 17
|
||||
* @arg ADC_Channel_18: Channel 18
|
||||
* @arg ADC_Channel_19: Channel 19
|
||||
* @arg ADC_Channel_20: Channel 20
|
||||
* @arg ADC_Channel_21: Channel 21
|
||||
* @arg ADC_Channel_22: Channel 22
|
||||
* @arg ADC_Channel_23: Channel 23
|
||||
* @arg ADC_Channel_24: Channel 24
|
||||
* @arg ADC_Channel_25: Channel 25
|
||||
* @arg ADC_Channel_26: Channel 26
|
||||
* @arg ADC_Channel_27: Channel 27
|
||||
* @arg ADC_Channel_Vrefint: Vrefint Channel
|
||||
* @arg ADC_Channel_TempSensor: Temperature sensor Channel
|
||||
* @arg ADC_Channel_00To07: select from channel00 to channel07
|
||||
* @arg ADC_Channel_08To15: select from channel08 to channel15
|
||||
* @arg ADC_Channel_16To23: select from channel16 to channel23
|
||||
* @arg ADC_Channel_24To27: select from channel24 to channel27
|
||||
* @param NewState : new state of the specified ADC channel(s).
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_ChannelCmd(ADC_TypeDef* ADCx, ADC_Channel_TypeDef ADC_Channels, FunctionalState NewState)
|
||||
{
|
||||
uint8_t regindex = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
regindex = (uint8_t)((uint16_t)ADC_Channels >> 8);
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected ADC channel(s). */
|
||||
ADCx->SQR[regindex] |= (uint8_t)(ADC_Channels);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected ADC channel(s). */
|
||||
ADCx->SQR[regindex] &= (uint8_t)(~(uint8_t)(ADC_Channels));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the sampling time for the selected ADC channel group.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param ADC_GroupChannels : ADC channel group to configure.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_Group_SlowChannels: Slow Channels group
|
||||
* @arg ADC_Group_FastChannels: Fast Channels group
|
||||
* @note The channels of 1st ADC Group can be channels 0..23
|
||||
* @note The channels of 2nd ADC Group can be channels 24..27 (depending on the MCU
|
||||
* package density) and Temperature Sensor and Vrefint channels.
|
||||
* @param ADC_SamplingTime : Specifies the sample time value
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_SamplingTime_4Cycles: Sampling Time Cycles is 4
|
||||
* @arg ADC_SamplingTime_9Cycles: Sampling Time Cycles is 9
|
||||
* @arg ADC_SamplingTime_16Cycles: Sampling Time Cycles is 16
|
||||
* @arg ADC_SamplingTime_24Cycles: Sampling Time Cycles is 24
|
||||
* @arg ADC_SamplingTime_48Cycles: Sampling Time Cycles is 48
|
||||
* @arg ADC_SamplingTime_96Cycles: Sampling Time Cycles is 96
|
||||
* @arg ADC_SamplingTime_192Cycles: Sampling Time Cycles is 192
|
||||
* @arg ADC_SamplingTime_384Cycles: Sampling Time Cycles is 384
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_SamplingTimeConfig(ADC_TypeDef* ADCx,
|
||||
ADC_Group_TypeDef ADC_GroupChannels,
|
||||
ADC_SamplingTime_TypeDef ADC_SamplingTime)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_GROUP(ADC_GroupChannels));
|
||||
assert_param(IS_ADC_SAMPLING_TIME_CYCLES(ADC_SamplingTime));
|
||||
|
||||
if ( ADC_GroupChannels != ADC_Group_SlowChannels)
|
||||
{
|
||||
/* Configures the sampling time for the Fast ADC channel group. */
|
||||
ADCx->CR3 &= (uint8_t)~ADC_CR3_SMPT2;
|
||||
ADCx->CR3 |= (uint8_t)(ADC_SamplingTime << 5);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Configures the sampling time for the Slow ADC channel group. */
|
||||
ADCx->CR2 &= (uint8_t)~ADC_CR2_SMPT1;
|
||||
ADCx->CR2 |= (uint8_t)ADC_SamplingTime;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the status of the Schmitt Trigger for the selected ADC
|
||||
* channel(s).
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param ADC_Channels: specifies the ADC channels to be initialized,
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_Channel_0: Channel 0
|
||||
* @arg ADC_Channel_1: Channel 1
|
||||
* @arg ADC_Channel_2: Channel 2
|
||||
* @arg ADC_Channel_3: Channel 3
|
||||
* @arg ADC_Channel_4: Channel 4
|
||||
* @arg ADC_Channel_5: Channel 5
|
||||
* @arg ADC_Channel_6: Channel 6
|
||||
* @arg ADC_Channel_7: Channel 7
|
||||
* @arg ADC_Channel_8: Channel 8
|
||||
* @arg ADC_Channel_9: Channel 9
|
||||
* @arg ADC_Channel_10: Channel 10
|
||||
* @arg ADC_Channel_11: Channel 11
|
||||
* @arg ADC_Channel_12: Channel 12
|
||||
* @arg ADC_Channel_13: Channel 13
|
||||
* @arg ADC_Channel_14: Channel 14
|
||||
* @arg ADC_Channel_15: Channel 15
|
||||
* @arg ADC_Channel_16: Channel 16
|
||||
* @arg ADC_Channel_17: Channel 17
|
||||
* @arg ADC_Channel_18: Channel 18
|
||||
* @arg ADC_Channel_19: Channel 19
|
||||
* @arg ADC_Channel_20: Channel 20
|
||||
* @arg ADC_Channel_21: Channel 21
|
||||
* @arg ADC_Channel_22: Channel 22
|
||||
* @arg ADC_Channel_23: Channel 23
|
||||
* @arg ADC_Channel_24: Channel 24
|
||||
* @arg ADC_Channel_25: Channel 25
|
||||
* @arg ADC_Channel_26: Channel 26
|
||||
* @arg ADC_Channel_27: Channel 27
|
||||
* @arg ADC_Channel_Vrefint: Vrefint Channel
|
||||
* @arg ADC_Channel_TempSensor: Temperature sensor Channel
|
||||
* @arg ADC_Channel_00To07: select from channel00 to channel07
|
||||
* @arg ADC_Channel_08To15: select from channel08 to channel15
|
||||
* @arg ADC_Channel_16To23: select from channel16 to channel23
|
||||
* @arg ADC_Channel_24To27: select from channel24 to channel27
|
||||
* @param NewState : new state of the Schmitt Trigger
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_SchmittTriggerConfig(ADC_TypeDef* ADCx, ADC_Channel_TypeDef ADC_Channels,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
uint8_t regindex = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
regindex = (uint8_t)((uint16_t)ADC_Channels >> 8);
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the Schmitt Trigger for the selected ADC channel(s).*/
|
||||
ADCx->TRIGR[regindex] &= (uint8_t)(~(uint8_t)ADC_Channels);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Schmitt Trigger for the selected ADC channel(s).*/
|
||||
ADCx->TRIGR[regindex] |= (uint8_t)(ADC_Channels);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last ADC converted data.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @retval The Data conversion value.
|
||||
*/
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
|
||||
/* Get last ADC converted data.*/
|
||||
tmpreg = (uint16_t)(ADCx->DRH);
|
||||
tmpreg = (uint16_t)((uint16_t)((uint16_t)tmpreg << 8) | ADCx->DRL);
|
||||
|
||||
/* Return the selected ADC conversion value */
|
||||
return (uint16_t)(tmpreg) ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group5 ADC Channels DMA Configuration function
|
||||
* @brief ADC Channels DMA Configuration function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
ADC Channels DMA Configuration function
|
||||
===============================================================================
|
||||
|
||||
This section provides a function allowing to configure the DMA for ADC
|
||||
channel.
|
||||
Since converted channel values are stored into a unique data register,
|
||||
it is useful to use DMA for conversion of more than one channel. This
|
||||
avoids the loss of the data already stored in the ADC Data register.
|
||||
|
||||
When the DMA mode is enabled (using the ADC_DMACmd() function), after each
|
||||
conversion of a channel, a DMA request is generated.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables or disables the specified ADC DMA request.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param NewState : new state of the specified ADC DMA transfer.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the specified ADC DMA request */
|
||||
ADCx->SQR[0] &= (uint8_t)~ADC_SQR1_DMAOFF;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the specified ADC DMA request */
|
||||
ADCx->SQR[0] |= ADC_SQR1_DMAOFF;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Group6 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Interrupts and flags management functions
|
||||
===============================================================================
|
||||
|
||||
This section provides functions allowing to configure the ADC Interrupts and
|
||||
get the status and clear flags and Interrupts pending bits.
|
||||
|
||||
The ADC provides 3 Interrupt sources and 3 Flags:
|
||||
|
||||
Flags :
|
||||
----------
|
||||
1. ADC_FLAG_OVR : Overrun detection when ADC channel converted data is lost
|
||||
|
||||
2. ADC_FLAG_EOC : End of conversion<6F>- to indicate the end of a regular
|
||||
CHANNEL conversion or a GROUP conversions, depending of the
|
||||
ADC Continuous Conversion Mode (Continuous or Single
|
||||
conversion) and of the DMA usage.
|
||||
Note : if DMA is used, EOC occurs at the end of the sequence
|
||||
conversion, else it occurs after each conversion
|
||||
3. ADC_FLAG_AWD: to indicate if the converted voltage crosses the
|
||||
programmed Analog watchdog thresholds values.
|
||||
|
||||
|
||||
Interrupts :
|
||||
------------
|
||||
1. ADC_IT_OVR : specifies the interrupt source for the Overrun detection event.
|
||||
2. ADC_IT_EOC : specifies the interrupt source for the End of conversion event.
|
||||
3. ADC_IT_AWD : specifies the interrupt source for the Analog watchdog event.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified ADC interrupts.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param ADC_IT : specifies the ADC interrupt sources to be enabled or
|
||||
* disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_IT_EOC: End of Conversion Interrupt
|
||||
* @arg ADC_IT_AWD: Analog Watchdog Interrupt
|
||||
* @arg ADC_IT_OVER: Over Run Interrupt
|
||||
* @param NewState : new state of the specified ADC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, ADC_IT_TypeDef ADC_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_ADC_IT(ADC_IT));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected ADC interrupts */
|
||||
ADCx->CR1 |= (uint8_t) ADC_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected ADC interrupts */
|
||||
ADCx->CR1 &= (uint8_t)(~ADC_IT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified ADC flag is set or not.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param ADC_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_FLAG_EOC: End of Conversion flag
|
||||
* @arg ADC_FLAG_AWD: Analog Watchdog flag
|
||||
* @arg ADC_FLAG_OVER: Over Run flag
|
||||
* @retval The new state of ADC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, ADC_FLAG_TypeDef ADC_FLAG)
|
||||
{
|
||||
FlagStatus flagstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
|
||||
|
||||
/* Check the status of the specified ADC flag */
|
||||
if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
|
||||
{
|
||||
/* ADC_FLAG is set */
|
||||
flagstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* ADC_FLAG is reset */
|
||||
flagstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the ADC_FLAG status */
|
||||
return flagstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the ADC's pending flags.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param ADC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_FLAG_EOC: End of Conversion flag
|
||||
* @arg ADC_FLAG_AWD: Analog Watchdog flag
|
||||
* @arg ADC_FLAG_OVER: Over Run flag
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx,
|
||||
ADC_FLAG_TypeDef ADC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
|
||||
|
||||
/* Clear the selected ADC flags */
|
||||
ADCx->SR = (uint8_t)~ADC_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified ADC interrupt has occurred or not.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param ADC_IT: specifies the ADC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_IT_EOC: End of Conversion Interrupt
|
||||
* @arg ADC_IT_AWD: Analog Watchdog Interrupt
|
||||
* @arg ADC_IT_OVER: Over Run Interrupt
|
||||
* @retval Status of ADC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx,
|
||||
ADC_IT_TypeDef ADC_IT)
|
||||
{
|
||||
ITStatus itstatus = RESET;
|
||||
uint8_t itmask = 0, enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_GET_IT(ADC_IT));
|
||||
|
||||
/* Get the ADC IT index */
|
||||
itmask = (uint8_t)(ADC_IT >> 3);
|
||||
itmask = (uint8_t)((uint8_t)((uint8_t)(itmask & (uint8_t)0x10) >> 2) | \
|
||||
(uint8_t)(itmask & (uint8_t)0x03));
|
||||
|
||||
/* Get the ADC_IT enable bit status */
|
||||
enablestatus = (uint8_t)(ADCx->CR1 & (uint8_t)ADC_IT) ;
|
||||
|
||||
/* Check the status of the specified ADC interrupt */
|
||||
if (((ADCx->SR & itmask) != (uint8_t)RESET) && enablestatus)
|
||||
{
|
||||
/* ADC_IT is set */
|
||||
itstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* ADC_IT is reset */
|
||||
itstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the ADC_IT status */
|
||||
return itstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the ADC<44>s interrupt pending bits.
|
||||
* @param ADCx where x can be 1 to select the specified ADC peripheral.
|
||||
* @param ADC_IT: specifies the ADC interrupt pending bit to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ADC_IT_EOC: End of Conversion Interrupt
|
||||
* @arg ADC_IT_AWD: Analog Watchdog Interrupt
|
||||
* @arg ADC_IT_OVER: Over Run Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx,
|
||||
ADC_IT_TypeDef ADC_IT)
|
||||
{
|
||||
uint8_t itmask = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_ADC_IT(ADC_IT));
|
||||
|
||||
/* Get the ADC IT index */
|
||||
itmask = (uint8_t)(ADC_IT >> 3);
|
||||
itmask = (uint8_t)((uint8_t)(((uint8_t)(itmask & (uint8_t)0x10)) >> 2) | \
|
||||
(uint8_t)(itmask & (uint8_t)0x03));
|
||||
|
||||
/* Clear the selected ADC interrupt pending bits */
|
||||
ADCx->SR = (uint8_t)~itmask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
488
firmware/inc/stm8l151x/src/stm8l15x_aes.c
Normal file
488
firmware/inc/stm8l151x/src/stm8l15x_aes.c
Normal file
@@ -0,0 +1,488 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_aes.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Advanced Encryption Standard (AES) peripheral:
|
||||
* - Configuration
|
||||
* - Read/Write operations
|
||||
* - DMA transfers management
|
||||
* - Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* 1- Enable AES clock to get write access to AES registers
|
||||
* using CLK_PeripheralClockConfig(CLK_Peripheral_AES, ENABLE);
|
||||
*
|
||||
* 2- Configure the AES operation mode using AES_OperationModeConfig()
|
||||
*
|
||||
* 3- If required, enable interrupt source using AES_ITConfig()
|
||||
*
|
||||
* 4- If required, when using the DMA mode
|
||||
* - Configure the DMA using DMA_Init()
|
||||
* - Enable DMA requests using AES_DMAConfig()
|
||||
*
|
||||
* 5- Enable the AES peripheral using AES_Cmd()
|
||||
*
|
||||
* 6- Write data/key using AES_WriteSubData() / AES_WriteSubKey()
|
||||
*
|
||||
* @endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_aes.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AES
|
||||
* @brief AES driver modules
|
||||
* @{
|
||||
*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup AES_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Group1 Configuration
|
||||
* @brief Configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Configuration
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the AES peripheral.
|
||||
* @param None.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_DeInit(void)
|
||||
{
|
||||
/* Set AES_CR to reset value 0x00, AES_SR is reset by setting ERRC and CCFC bits in CR */
|
||||
AES->CR = AES_CR_ERRC | AES_CR_CCFC;
|
||||
AES->DINR = AES_DINR_RESET_VALUE; /* Set AES_DINR to reset value 0x00 */
|
||||
AES->DOUTR = AES_DOUTR_RESET_VALUE; /* Set AES_DOUTR to reset value 0x00 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the AES operation mode.
|
||||
* @param AES_Operation : the selected AES operation mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg AES_Operation_Encryp: AES in Encryption mode
|
||||
* @arg AES_Operation_KeyDeriv: AES in Key Derivation mode
|
||||
* @arg AES_Operation_Decryp: AES in Decryption mode
|
||||
* @arg AES_Operation_KeyDerivAndDecryp: AES in Key Derivation and Decryption mode
|
||||
* @note The operation mode must be configured when AES peripheral is disabled.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_OperationModeConfig(AES_Operation_TypeDef AES_Operation)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_AES_MODE(AES_Operation));
|
||||
|
||||
/* Reset the operation mode bits in CR register */
|
||||
AES->CR &= (uint8_t) (~AES_CR_MODE);
|
||||
|
||||
/* Set the new operation mode bits in CR register */
|
||||
AES->CR |= (uint8_t) (AES_Operation);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the AES peripheral.
|
||||
* @param NewState : The new state of the AES peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note AES peripheral can be enabled once operation mode is configured using
|
||||
* AES_OperationModeConfig()
|
||||
* @retval None
|
||||
*/
|
||||
void AES_Cmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
AES->CR |= (uint8_t) AES_CR_EN; /**< AES Enable */
|
||||
}
|
||||
else
|
||||
{
|
||||
AES->CR &= (uint8_t)(~AES_CR_EN); /**< AES Disable */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Group2 AES Read and Write
|
||||
* @brief AES Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
AES Read and Write operations
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write data in DINR register to be processed by AES peripheral.
|
||||
* @param Data: The data to be processed.
|
||||
* @note When an unexpected write to DINR register is detected, WRERR flag is
|
||||
* set.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_WriteSubData(uint8_t Data)
|
||||
{
|
||||
/* Write Data */
|
||||
AES->DINR = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write key in DINR register.
|
||||
* @param Key: The key to be used for encryption/decryption.
|
||||
* @note When an unexpected write to DINR register is detected, WRERR flag is
|
||||
* set.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_WriteSubKey(uint8_t Key)
|
||||
{
|
||||
/* Write key */
|
||||
AES->DINR = Key;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the data in DOUTR register processed by AES peripheral.
|
||||
* @note When an unexpected read of DOUTR register is detected, RDERR flag is
|
||||
* set
|
||||
* @retval The processed data.
|
||||
*/
|
||||
uint8_t AES_ReadSubData(void)
|
||||
{
|
||||
return AES->DOUTR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the DOUTR register content.
|
||||
* @retval The derivation key.
|
||||
* @note When an unexpected read of DOUTR register is detected, RDERR flag is
|
||||
* set.
|
||||
*/
|
||||
uint8_t AES_ReadSubKey(void)
|
||||
{
|
||||
return AES->DOUTR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Group3 DMA transfers management functions
|
||||
* @brief DMA transfers management function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
DMA transfers management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the AES DMA interface.
|
||||
* @param AES_DMATransfer: Specifies the AES DMA transfer.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg AES_DMATransfer_InOut: DMA requests enabled for input/Output transfer phase
|
||||
* @param NewState Indicates the new state of the AES DMA interface.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
* @note CCF bit has no meaning when DMA requests are enabled (DMAEN = 1).
|
||||
*/
|
||||
void AES_DMAConfig(AES_DMATransfer_TypeDef AES_DMATransfer, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_AES_DMATRANSFER(AES_DMATransfer));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the DMA transfer */
|
||||
AES->CR |= (uint8_t) AES_DMATransfer;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the DMA transfer */
|
||||
AES->CR &= (uint8_t)(~AES_DMATransfer);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Group4 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
Interrupts and flags management functions
|
||||
===============================================================================
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified AES interrupt.
|
||||
* @param AES_IT: Specifies the AES interrupt source to enable/disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg AES_IT_CCIE: Computation Complete interrupt enable
|
||||
* @arg AES_IT_ERRIE: Error interrupt enable
|
||||
* @param NewState : The new state of the AES peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_ITConfig(AES_IT_TypeDef AES_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_AES_IT(AES_IT));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
AES->CR |= (uint8_t) AES_IT; /**< AES_IT Enable */
|
||||
}
|
||||
else
|
||||
{
|
||||
AES->CR &= (uint8_t)(~AES_IT); /**< AES_IT Disable */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified AES flag is set or not.
|
||||
* @param AES_FLAG specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg AES_FLAG_CCF: Computation Complete Flag
|
||||
* @arg AES_FLAG_RDERR: Read Error Flag
|
||||
* @arg AES_FLAG_WRERR: Write Error Flag
|
||||
* @retval FlagStatus (SET or RESET)
|
||||
* @note CCF bit has a meaning only when DMA requests are disabled (DMAEN bit = 0).
|
||||
*/
|
||||
FlagStatus AES_GetFlagStatus(AES_FLAG_TypeDef AES_FLAG)
|
||||
{
|
||||
FlagStatus status = RESET;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_AES_FLAG(AES_FLAG));
|
||||
|
||||
if (AES_FLAG == AES_FLAG_CCF)
|
||||
{
|
||||
if ((AES->SR & (uint8_t)AES_FLAG_CCF) != (uint8_t)0x00)
|
||||
{
|
||||
/* Computation Complete Flag CCF is set */
|
||||
status = (FlagStatus) SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Computation Complete Flag CCF is reset */
|
||||
status = (FlagStatus) RESET;
|
||||
}
|
||||
}
|
||||
else if (AES_FLAG == AES_FLAG_RDERR)
|
||||
{
|
||||
if ((AES->SR & (uint8_t)AES_FLAG_RDERR) != (uint8_t)0x00)
|
||||
{
|
||||
/* Read Error Flag RDERR is set */
|
||||
status = (FlagStatus) SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Read Error Flag RDERR is reset */
|
||||
status = (FlagStatus) RESET;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((AES->SR & (uint8_t)AES_FLAG_WRERR) != (uint8_t)0x00)
|
||||
{
|
||||
/* Write Error Flag WRERR is set */
|
||||
status = (FlagStatus) SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Write Error Flag WRERR is reset */
|
||||
status = (FlagStatus) RESET;
|
||||
}
|
||||
}
|
||||
/* Return the AES_FLAG status */
|
||||
return ((FlagStatus) status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the AES flags.
|
||||
* @param AES_FLAG: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg AES_FLAG_CCF: Computation Complete Flag
|
||||
* @arg AES_FLAG_RDERR: Read Error Flag
|
||||
* @arg AES_FLAG_WRERR: Write Error Flag
|
||||
* @retval None
|
||||
*/
|
||||
void AES_ClearFlag(AES_FLAG_TypeDef AES_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_AES_FLAG(AES_FLAG));
|
||||
|
||||
/* Check if AES_FLAG is AES_FLAG_CCF */
|
||||
if (AES_FLAG == AES_FLAG_CCF)
|
||||
{
|
||||
/* Clear CCF flag by setting CCFC bit */
|
||||
AES->CR |= (uint8_t) AES_CR_CCFC;
|
||||
}
|
||||
else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */
|
||||
{
|
||||
/* Clear RDERR and WRERR flags by setting ERRC bit */
|
||||
AES->CR |= (uint8_t) AES_CR_ERRC;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified AES interrupt has occurred or not.
|
||||
* @param AES_IT: Specifies the AES interrupt pending bit to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg AES_IT_CCIE: Computation Complete interrupt enable
|
||||
* @arg AES_IT_ERRIE: Error interrupt enable
|
||||
* @retval ITStatus The new state of AES_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus AES_GetITStatus(AES_IT_TypeDef AES_IT)
|
||||
{
|
||||
ITStatus itstatus = RESET;
|
||||
BitStatus cciebitstatus, ccfbitstatus = RESET;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_AES_IT(AES_IT));
|
||||
|
||||
cciebitstatus = (BitStatus) (AES->CR & AES_CR_CCIE);
|
||||
ccfbitstatus = (BitStatus) (AES->SR & AES_SR_CCF);
|
||||
|
||||
/* Check if AES_IT is AES_IT_CCIE */
|
||||
if (AES_IT == AES_IT_CCIE)
|
||||
{
|
||||
/* Check the status of the specified AES interrupt */
|
||||
if (((cciebitstatus) != RESET) && ((ccfbitstatus) != RESET))
|
||||
{
|
||||
/* Interrupt occurred */
|
||||
itstatus = (ITStatus) SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Interrupt not occurred */
|
||||
itstatus = (ITStatus) RESET;
|
||||
}
|
||||
}
|
||||
else /* AES_IT is AES_IT_ERRIE */
|
||||
{
|
||||
/* Check the status of the specified AES interrupt */
|
||||
if ((AES->CR & AES_CR_ERRIE) != RESET)
|
||||
{
|
||||
/* Check if WRERR or RDERR flags are set */
|
||||
if ((AES->SR & (uint8_t)(AES_SR_WRERR | AES_SR_RDERR)) != RESET)
|
||||
{
|
||||
/* Interrupt occurred */
|
||||
itstatus = (ITStatus) SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Interrupt not occurred */
|
||||
itstatus = (ITStatus) RESET;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Interrupt not occurred */
|
||||
itstatus = (ITStatus) RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the AES_IT status */
|
||||
return ((ITStatus)itstatus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the AES's interrupt pending bits.
|
||||
* @param AES_IT: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg AES_IT_CCIE: Computation Complete interrupt enable
|
||||
* @arg AES_IT_ERRIE: Error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
void AES_ClearITPendingBit(AES_IT_TypeDef AES_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_AES_IT(AES_IT));
|
||||
|
||||
/* Check if AES_IT is AES_IT_CCIE */
|
||||
if (AES_IT == AES_IT_CCIE)
|
||||
{
|
||||
/* Clear CCF flag by setting CCFC bit */
|
||||
AES->CR |= (uint8_t) AES_CR_CCFC;
|
||||
}
|
||||
else /* AES_IT is AES_IT_ERRIE */
|
||||
{
|
||||
/* Clear RDERR and WRERR flags by setting ERRC bit */
|
||||
AES->CR |= (uint8_t) AES_CR_ERRC;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
247
firmware/inc/stm8l151x/src/stm8l15x_beep.c
Normal file
247
firmware/inc/stm8l151x/src/stm8l15x_beep.c
Normal file
@@ -0,0 +1,247 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_beep.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the BEEPER (BEEP) peripheral:
|
||||
* - Initialization and Configuration
|
||||
* - Low Speed Internal Clock(LSI) Calibration
|
||||
*
|
||||
* @verbatim
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* 1- Make sure that the LS RC clock calibration is performed by the following
|
||||
* steps:
|
||||
* - Connect internally the LS clock source to TIM2 channel 1 input
|
||||
* capture for measurement using BEEP_LSClockToTIMConnectCmd() function
|
||||
* - Update the BEEP_CSR register by the measured LSI frequency
|
||||
* --> During this phase the BEEPER must be disabled to avoid
|
||||
* unwanted interrupts
|
||||
*
|
||||
* 2- Configure the output beeper frequency using the BEEP_Init() function
|
||||
*
|
||||
* 3- Enable the beeper using the BEEP_Cmd() function
|
||||
*
|
||||
* @endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_beep.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup BEEP
|
||||
* @brief BEEP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup BEEP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BEEP_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Initialization and Configuration functions
|
||||
===============================================================================
|
||||
This section provides functions allowing to:
|
||||
- Initialize and configure the Beeper frequency
|
||||
- Enable and Disable the Beeper output
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the BEEP peripheral registers to their default
|
||||
* reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BEEP_DeInit(void)
|
||||
{
|
||||
BEEP->CSR1 = BEEP_CSR1_RESET_VALUE;
|
||||
BEEP->CSR2 = BEEP_CSR2_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the BEEP function according to the specified parameters.
|
||||
* @note The LS RC calibration must be performed before calling this function.
|
||||
* @param BEEP_Frequency Frequency selection.
|
||||
* This parameter can be one of the values of @ref BEEP_Frequency_TypeDef.
|
||||
* @retval None
|
||||
*/
|
||||
void BEEP_Init(BEEP_Frequency_TypeDef BEEP_Frequency)
|
||||
{
|
||||
|
||||
/* Check parameter */
|
||||
assert_param(IS_BEEP_FREQUENCY(BEEP_Frequency));
|
||||
|
||||
/* Set a default calibration value if no calibration is done */
|
||||
if ((BEEP->CSR2 & BEEP_CSR2_BEEPDIV) == BEEP_CSR2_BEEPDIV)
|
||||
{
|
||||
BEEP->CSR2 &= (uint8_t)(~BEEP_CSR2_BEEPDIV); /* Clear bits */
|
||||
BEEP->CSR2 |= BEEP_CALIBRATION_DEFAULT;
|
||||
}
|
||||
|
||||
/* Select the output frequency */
|
||||
BEEP->CSR2 &= (uint8_t)(~BEEP_CSR2_BEEPSEL);
|
||||
BEEP->CSR2 |= (uint8_t)(BEEP_Frequency);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the BEEP function.
|
||||
* @note Initialisation of BEEP and LS RC calibration must be done before.
|
||||
* @param NewState Indicates the new state of the BEEP function.
|
||||
* @retval None
|
||||
*/
|
||||
void BEEP_Cmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the BEEP peripheral */
|
||||
BEEP->CSR2 |= BEEP_CSR2_BEEPEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the BEEP peripheral */
|
||||
BEEP->CSR2 &= (uint8_t)(~BEEP_CSR2_BEEPEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BEEP_Group2 Low Speed Internal Clock(LSI) Calibration functions
|
||||
* @brief Low Speed Internal Clock(LSI) Calibration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Low Speed Internal Clock(LSI) Calibration functions
|
||||
===============================================================================
|
||||
|
||||
This section provides functions allowing to measure and calibrate the internal
|
||||
low speed clock source to ensure better BEEPER output frequency .
|
||||
|
||||
A typical configuration for LSI calibration is done following these steps :
|
||||
1. Disable the Beeper to avoid any unwanted interrupt using BEEP_Cmd() function
|
||||
2. Measure the LSI clock frequency by connecting it internally to TIM2 input capture
|
||||
using BEEP_LSClockToTIMConnectCmd() function.
|
||||
3. Calibrate the beeper frequency with the measured LSI clock frequency using
|
||||
BEEP_LSICalibrationConfig() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the LS clock source connection to TIM for measurement.
|
||||
* @param NewState Indicates the new state of the LS clock to TIM connection
|
||||
* @retval None
|
||||
*/
|
||||
void BEEP_LSClockToTIMConnectCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Connect LS clock to TIM for measurement */
|
||||
BEEP->CSR1 |= BEEP_CSR1_MSR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disconnect LS clock to TIM */
|
||||
BEEP->CSR1 &= (uint8_t)(~BEEP_CSR1_MSR);
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief Update CSR register with the measured LSI frequency.
|
||||
* @note BEEP must be disabled to avoid unwanted interrupts.
|
||||
* @note Prescaler calculation:
|
||||
* A is the integer part of LSIFreqkHz/4 and x the decimal part.
|
||||
* x <= A/(1+2A) is equivalent to A >= x(1+2A)
|
||||
* and also to 4A >= 4x(1+2A) [F1]
|
||||
* but we know that A + x = LSIFreqkHz/4 ==> 4x = LSIFreqkHz-4A
|
||||
* so [F1] can be written :
|
||||
* 4A >= (LSIFreqkHz-4A)(1+2A)
|
||||
* @param LSIFreqHz Low Speed RC frequency measured by timer (in Hz).
|
||||
* @retval None
|
||||
*/
|
||||
void BEEP_LSICalibrationConfig(uint32_t LSIFreqHz)
|
||||
{
|
||||
uint16_t lsifreqkhz;
|
||||
uint16_t A;
|
||||
|
||||
/* Check parameter */
|
||||
assert_param(IS_LSI_FREQUENCY(LSIFreqHz));
|
||||
|
||||
lsifreqkhz = (uint16_t)(LSIFreqHz / 1000); /* Converts value in kHz */
|
||||
|
||||
/* Calculation of BEEPER calibration value */
|
||||
|
||||
BEEP->CSR2 &= (uint8_t)(~BEEP_CSR2_BEEPDIV); /* Clear bits */
|
||||
|
||||
A = (uint16_t)(lsifreqkhz >> 3U); /* Division by 8, keep integer part only */
|
||||
|
||||
if ((8U * A) >= ((lsifreqkhz - (8U * A)) * (1U + (2U * A))))
|
||||
{
|
||||
BEEP->CSR2 |= (uint8_t)(A - 2U);
|
||||
}
|
||||
else
|
||||
{
|
||||
BEEP->CSR2 |= (uint8_t)(A - 1U);
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
1123
firmware/inc/stm8l151x/src/stm8l15x_clk.c
Normal file
1123
firmware/inc/stm8l151x/src/stm8l15x_clk.c
Normal file
File diff suppressed because it is too large
Load Diff
728
firmware/inc/stm8l151x/src/stm8l15x_comp.c
Normal file
728
firmware/inc/stm8l151x/src/stm8l15x_comp.c
Normal file
@@ -0,0 +1,728 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_comp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the comparators (COMP1 and COMP2) peripheral:
|
||||
* - Comparators configuration
|
||||
* - Window mode control
|
||||
* - Internal Reference Voltage (VREFINT) output
|
||||
* - Comparator channels trigger configuration
|
||||
* - Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* 1- Enable comparators clock using CLK_PeripheralClockConfig(CLK_Peripheral_COMP, ENABLE);
|
||||
*
|
||||
* When using COMP1:
|
||||
* 2- Connect internal reference voltage to COMP1 inverting input
|
||||
* using COMP_VrefintToCOMP1Connect()
|
||||
* 3- Close the analog switch number 14 using SYSCFG_RIAnalogSwitchConfig()
|
||||
* 4- Close the analog switch that corresponds to the pin to be used as
|
||||
* non inverting input using SYSCFG_RIAnalogSwitchConfig()
|
||||
* 5- Close the I/O switch of the pin to be used as non inverting input
|
||||
* using SYSCFG_RIIOSwitchConfig()
|
||||
* 6- Configure the event detection using COMP_EdgeConfig()
|
||||
*
|
||||
* When using COMP2:
|
||||
* 2- Select the COMP2 inverting input, configure the speed and COMP2
|
||||
* output redirection using COMP_Init()
|
||||
* If the inverting input is an external pin, close the I/O channel
|
||||
* switch using SYSCFG_RIIOSwitchConfig()
|
||||
* 3- Close I/O Switch that corresponds to the selected pin as
|
||||
* comparator 2 non inverting input using SYSCFG_RIIOSwitchConfig()
|
||||
* 4- Configure the event detection using COMP_EdgeConfig()
|
||||
*
|
||||
* @note
|
||||
* 1- COMP1 comparator and ADC can't be used at the same time since
|
||||
* they share the same ADC switch matrix (analog switches).
|
||||
*
|
||||
* 2- When an I/O is used as comparator input, the corresponding GPIO
|
||||
* registers should be configured in input floating.
|
||||
*
|
||||
* 3- Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on
|
||||
* GPIO pin. They are only internal.
|
||||
* To get the comparator output level, use COMP_GetOutputLevel() function
|
||||
* @endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_comp.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP
|
||||
* @brief COMP driver modules
|
||||
* @{
|
||||
*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Initialization and Configuration functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the COMPx peripheral registers to their default reset values.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void COMP_DeInit(void)
|
||||
{
|
||||
/* Set COMP->CSR1 to reset value 0x00 */
|
||||
COMP->CSR1 = (uint8_t) COMP_CSR1_RESET_VALUE;
|
||||
|
||||
/* Set COMP->CSR2 to reset value 0x00 */
|
||||
COMP->CSR2 = (uint8_t) COMP_CSR2_RESET_VALUE;
|
||||
|
||||
/* Set COMP->CSR3 to reset value 0xC0 */
|
||||
COMP->CSR3 = (uint8_t) COMP_CSR3_RESET_VALUE;
|
||||
|
||||
/* Set COMP->CSR4 to reset value 0x00 */
|
||||
COMP->CSR4 = (uint8_t) COMP_CSR4_RESET_VALUE;
|
||||
|
||||
/* Set COMP->CSR5 to reset value 0x00 */
|
||||
COMP->CSR5 = (uint8_t) COMP_CSR5_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the comparator inverting input, output and speed.
|
||||
* @note This function configures only COMP2.
|
||||
* @param COMP_InvertingInput : selects the comparator inverting input.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_InvertingInput_IO: Input/Output on comparator inverting input enable
|
||||
* @arg COMP_InvertingInput_VREFINT: VREFINT on comparator inverting input enable
|
||||
* @arg COMP_InvertingInput_3_4VREFINT: 3/4 VREFINT on comparator inverting input enable
|
||||
* @arg COMP_InvertingInput_1_2VREFINT: 1/2 VREFINT on comparator inverting input enable
|
||||
* @arg COMP_InvertingInput_1_4VREFINT: 1/4 VREFINT on comparator inverting input enable
|
||||
* @arg COMP_InvertingInput_DAC1: DAC1 output on comparator inverting input enable
|
||||
* @arg COMP_InvertingInput_DAC2: DAC2 output on comparator inverting input enable
|
||||
* @param COMP_OutputSelect : selects the comparator output
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_OutputSelect_TIM2IC2: COMP2 output connected to TIM2 Input Capture 2
|
||||
* @arg COMP_OutputSelect_TIM3IC2: COMP2 output connected to TIM3 Input Capture 2
|
||||
* @arg COMP_OutputSelect_TIM1BRK: COMP2 output connected to TIM1 Break Input
|
||||
* @arg COMP_OutputSelect_TIM1OCREFCLR: COMP2 output connected to TIM1 OCREF Clear
|
||||
* @param COMP_Speed selects the comparator speed
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_Speed_Slow: Comparator speed: slow
|
||||
* @arg COMP_Speed_Fast: Comparator speed: fast
|
||||
* @retval None.
|
||||
*/
|
||||
void COMP_Init(COMP_InvertingInput_Typedef COMP_InvertingInput,
|
||||
COMP_OutputSelect_Typedef COMP_OutputSelect, COMP_Speed_TypeDef COMP_Speed)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_INVERTING_INPUT(COMP_InvertingInput));
|
||||
assert_param(IS_COMP_OUTPUT(COMP_OutputSelect));
|
||||
assert_param(IS_COMP_SPEED(COMP_Speed));
|
||||
|
||||
/* Reset the INSEL[2:0] bits in CSR3 register */
|
||||
COMP->CSR3 &= (uint8_t) (~COMP_CSR3_INSEL);
|
||||
/* Select the comparator inverting input */
|
||||
COMP->CSR3 |= (uint8_t) COMP_InvertingInput;
|
||||
|
||||
/* Reset the OUTSEL[1:0] bits in CSR3 register */
|
||||
COMP->CSR3 &= (uint8_t) (~COMP_CSR3_OUTSEL);
|
||||
/* Redirect the comparator output */
|
||||
COMP->CSR3 |= (uint8_t) COMP_OutputSelect;
|
||||
|
||||
/* Reset the comparator speed bit */
|
||||
COMP->CSR2 &= (uint8_t) (~COMP_CSR2_SPEED);
|
||||
/* Select the comparator speed */
|
||||
COMP->CSR2 |= (uint8_t) COMP_Speed;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables connection between VREFINT and COMP1 inverting input.
|
||||
* @param NewState new state of the VREFINT connection to COMP1 inverting input.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_VrefintToCOMP1Connect(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the comparator */
|
||||
COMP->CSR3 |= COMP_CSR3_VREFEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the comparator */
|
||||
COMP->CSR3 &= (uint8_t)(~COMP_CSR3_VREFEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the COMP edge detection.
|
||||
* @param COMP_Selection: selects the comparator.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_Selection_COMP1: Selection of Comparator 1
|
||||
* @arg COMP_Selection_COMP2: Selection of Comparator 2
|
||||
* @param COMP_Edge: This parameter can be one of the following values:
|
||||
* @arg COMP_Edge_Falling: Falling edge selection
|
||||
* @arg COMP_Edge_Rising: Rising edge selection
|
||||
* @arg COMP_Edge_Rising_Falling: Rising and Falling edge selection
|
||||
* @retval None.
|
||||
*/
|
||||
void COMP_EdgeConfig(COMP_Selection_TypeDef COMP_Selection, COMP_Edge_TypeDef COMP_Edge)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
assert_param(IS_COMP_EDGE(COMP_Edge));
|
||||
|
||||
/* Check if comparator 1 is selected */
|
||||
if (COMP_Selection == COMP_Selection_COMP1)
|
||||
{
|
||||
/* Reset the comparator 1 edge control bits */
|
||||
COMP->CSR1 &= (uint8_t) (~COMP_CSR1_CMP1);
|
||||
|
||||
/* Select the edge detection of comparator 1 output */
|
||||
COMP->CSR1 |= (uint8_t) COMP_Edge;
|
||||
}
|
||||
/* The comparator 2 is selected */
|
||||
else
|
||||
{
|
||||
/* Reset the comparator 2 edge control bits */
|
||||
COMP->CSR2 &= (uint8_t) (~COMP_CSR2_CMP2);
|
||||
|
||||
/* Select the edge detection of comparator 2 output */
|
||||
COMP->CSR2 |= (uint8_t) COMP_Edge;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the output level of the comparator.
|
||||
* @note Comparators outputs aren't available on GPIO (outputs levels are
|
||||
* only internal).
|
||||
* @param COMP_Selection: selects the comparator.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_Selection_COMP1: Selection of Comparator 1
|
||||
* @arg COMP_Selection_COMP2: Selection of Comparator 2
|
||||
* @retval Returns the comparator output level
|
||||
* This value can be one of the following:
|
||||
* - COMP_OutputLevel_Low: Comparator output level is low
|
||||
* - COMP_OutputLevel_High: Comparator output level is high
|
||||
*/
|
||||
COMP_OutputLevel_TypeDef COMP_GetOutputLevel(COMP_Selection_TypeDef COMP_Selection)
|
||||
{
|
||||
uint8_t compout;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
|
||||
/* Check if Comparator 1 is selected */
|
||||
if (COMP_Selection == COMP_Selection_COMP1)
|
||||
{
|
||||
/* Check if comparator 1 output level is high */
|
||||
if ((COMP->CSR1 & COMP_CSR1_CMP1OUT) != (uint8_t) RESET)
|
||||
{
|
||||
/* Get Comparator 1 output level */
|
||||
compout = (COMP_OutputLevel_TypeDef) COMP_OutputLevel_High;
|
||||
}
|
||||
/* comparator 1 output level is low */
|
||||
else
|
||||
{
|
||||
/* Get Comparator 1 output level */
|
||||
compout = (COMP_OutputLevel_TypeDef) COMP_OutputLevel_Low;
|
||||
}
|
||||
}
|
||||
/* Comparator 2 is selected */
|
||||
else
|
||||
{
|
||||
/* Check if comparator 2 output level is high */
|
||||
if ((COMP->CSR2 & COMP_CSR2_CMP2OUT) != (uint8_t) RESET)
|
||||
{
|
||||
/* Get Comparator output level */
|
||||
compout = (COMP_OutputLevel_TypeDef) COMP_OutputLevel_High;
|
||||
}
|
||||
/* comparator 2 output level is low */
|
||||
else
|
||||
{
|
||||
/* Get Comparator 2 output level */
|
||||
compout = (COMP_OutputLevel_TypeDef) COMP_OutputLevel_Low;
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the comparator output level */
|
||||
return (COMP_OutputLevel_TypeDef)(compout);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group2 Window mode control function
|
||||
* @brief Window mode control function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Window mode control function
|
||||
===============================================================================
|
||||
|
||||
In window mode:
|
||||
- COMP1 inverting input is fixed to VREFINT defining the first
|
||||
threshold
|
||||
- COMP2 inverting input is configurable (DAC_OUT1, VREFINT sub-multiples, ...)
|
||||
defining the second threshold
|
||||
- COMP1 and COMP2 non inverting inputs are connected together.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the window mode.
|
||||
* @param NewState new state of the window mode.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_WindowCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the window mode */
|
||||
COMP->CSR3 |= (uint8_t) COMP_CSR3_WNDWE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the window mode */
|
||||
COMP->CSR3 &= (uint8_t)(~COMP_CSR3_WNDWE);
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group3 Internal Reference Voltage output function
|
||||
* @brief Internal Reference Voltage (VREFINT) output function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Internal Reference Voltage (VREFINT) output function
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the output of the internal reference voltage.
|
||||
* @param NewState : new state of the Vrefint output.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_VrefintOutputCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the output of internal reference voltage */
|
||||
COMP->CSR3 |= (uint8_t) COMP_CSR3_VREFOUTEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the output of internal reference voltage */
|
||||
COMP->CSR3 &= (uint8_t) (~COMP_CSR3_VREFOUTEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group4 Comparator channels trigger configuration
|
||||
* @brief Comparator channels trigger configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Comparator channels trigger configuration
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the schmitt trigger.
|
||||
* @param NewState : new state of the schmitt trigger.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_SchmittTriggerCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable Schmitt trigger on Input Output switches Channels */
|
||||
COMP->CSR1 |= (uint8_t) COMP_CSR1_STE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable Schmitt trigger on Input Output switches Channels */
|
||||
COMP->CSR1 &= (uint8_t) (~COMP_CSR1_STE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables trigger on the specified input/output group.
|
||||
* @param COMP_TriggerGroup : specifies the input/output group
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_TriggerGroup_InvertingInput: Trigger on comparator 2 inverting input
|
||||
* @arg COMP_TriggerGroup_NonInvertingInput: Trigger on comparator 2 non inverting input
|
||||
* @arg COMP_TriggerGroup_VREFINTOutput: Trigger on VREFINT output
|
||||
* @arg COMP_TriggerGroup_DACOutput: Trigger on DAC output
|
||||
* @param COMP_TriggerPin : specifies the pin(s) within the input/output group
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_TriggerPin_0: Trigger Pin 0
|
||||
* @arg COMP_TriggerPin_0: Trigger Pin 1
|
||||
* @arg COMP_TriggerPin_0: Trigger Pin 2
|
||||
* @param NewState : enable or disable the trigger on the selected pin(s)
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_TriggerConfig(COMP_TriggerGroup_TypeDef COMP_TriggerGroup,
|
||||
COMP_TriggerPin_TypeDef COMP_TriggerPin,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_TRIGGERGROUP(COMP_TriggerGroup));
|
||||
assert_param(IS_COMP_TRIGGERPIN(COMP_TriggerPin));
|
||||
|
||||
switch (COMP_TriggerGroup)
|
||||
{
|
||||
case COMP_TriggerGroup_InvertingInput:
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
COMP->CSR4 &= (uint8_t) ~COMP_TriggerPin;
|
||||
}
|
||||
else
|
||||
{
|
||||
COMP->CSR4 |= (uint8_t) COMP_TriggerPin;
|
||||
}
|
||||
break;
|
||||
|
||||
case COMP_TriggerGroup_NonInvertingInput:
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
COMP->CSR4 &= (uint8_t) ~((uint8_t)(COMP_TriggerPin << 3));
|
||||
}
|
||||
else
|
||||
{
|
||||
COMP->CSR4 |= (uint8_t) (COMP_TriggerPin << 3);
|
||||
}
|
||||
break;
|
||||
|
||||
case COMP_TriggerGroup_VREFINTOutput:
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
COMP->CSR5 &= (uint8_t) ~COMP_TriggerPin;
|
||||
}
|
||||
else
|
||||
{
|
||||
COMP->CSR5 |= (uint8_t) COMP_TriggerPin;
|
||||
}
|
||||
break;
|
||||
|
||||
case COMP_TriggerGroup_DACOutput:
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
COMP->CSR5 &= (uint8_t) ~((uint8_t)(COMP_TriggerPin << 3));
|
||||
}
|
||||
else
|
||||
{
|
||||
COMP->CSR5 |= (uint8_t) (COMP_TriggerPin << 3);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group5 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Interrupts and flags management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the interrupt generation when an event is detected.
|
||||
* @param COMP_Selection : selects the comparator
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_Selection_COMP1: Selection of Comparator 1
|
||||
* @arg COMP_Selection_COMP2: Selection of Comparator 2
|
||||
* @param NewState : new state of the COMPx interrupt.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_ITConfig(COMP_Selection_TypeDef COMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Check if Comparator 1 is selected */
|
||||
if (COMP_Selection == COMP_Selection_COMP1)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the COMP1 Interrupt source */
|
||||
COMP->CSR1 |= (uint8_t) COMP_CSR1_IE1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the COMP1 Interrupt source */
|
||||
COMP->CSR1 &= (uint8_t)(~COMP_CSR1_IE1);
|
||||
}
|
||||
}
|
||||
else /* Comparator 2 is selected */
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the COMP2 Interrupt source */
|
||||
COMP->CSR2 |= (uint8_t) COMP_CSR2_IE2;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the COMP2 Interrupt source */
|
||||
COMP->CSR2 &= (uint8_t)(~COMP_CSR2_IE2);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the comparator flag is set or not.
|
||||
* @param COMP_Selection : selects the comparator
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_Selection_COMP1: Selection of Comparator 1
|
||||
* @arg COMP_Selection_COMP2: Selection of Comparator 2
|
||||
* @retval The new state of COMPx event flag (SET or RESET).
|
||||
*/
|
||||
FlagStatus COMP_GetFlagStatus(COMP_Selection_TypeDef COMP_Selection)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
|
||||
/* Check if COMP1 is selected */
|
||||
if (COMP_Selection == COMP_Selection_COMP1)
|
||||
{
|
||||
if ((COMP->CSR1 & COMP_CSR1_EF1) != (uint8_t) RESET)
|
||||
{
|
||||
/* The comparator 1 event flag is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The comparator 1 event flag is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
else /* COMP2 is selected */
|
||||
{
|
||||
if ((COMP->CSR2 & COMP_CSR2_EF2) != (uint8_t) RESET)
|
||||
{
|
||||
/* The comparator 2 event flag is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The comparator 2 event flag is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/* return the comparator event flag status */
|
||||
return (FlagStatus)(bitstatus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the comparator<6F>s pending flag.
|
||||
* @param COMP_Selection : selects the comparator
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_Selection_COMP1: Selection of Comparator 1
|
||||
* @arg COMP_Selection_COMP2: Selection of Comparator 2
|
||||
* @retval None.
|
||||
*/
|
||||
void COMP_ClearFlag(COMP_Selection_TypeDef COMP_Selection)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
|
||||
if (COMP_Selection == COMP_Selection_COMP1)
|
||||
{
|
||||
/* Clear the flag EF1 (rc_w0) clear this bit by writing 0. */
|
||||
COMP->CSR1 &= (uint8_t) (~COMP_CSR1_EF1);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the flag EF2 (rc_w0) clear this bit by writing 0. */
|
||||
COMP->CSR2 &= (uint8_t) (~COMP_CSR2_EF2);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the comparator interrupt has occurred or not.
|
||||
* @param COMP_Selection : selects the comparator
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_Selection_COMP1: Selection of Comparator 1
|
||||
* @arg COMP_Selection_COMP2: Selection of Comparator 2
|
||||
* @retval ITStatus : The state of the COMPx event flag (SET or RESET).
|
||||
*/
|
||||
ITStatus COMP_GetITStatus(COMP_Selection_TypeDef COMP_Selection)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint8_t itstatus = 0x00, itenable = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
|
||||
if (COMP_Selection == COMP_Selection_COMP1)
|
||||
{
|
||||
/* Get the EF1 comparator event flag status */
|
||||
itstatus = (uint8_t) (COMP->CSR1 & COMP_CSR1_EF1);
|
||||
|
||||
/* Get the IE1 interrupt enable bit status */
|
||||
itenable = (uint8_t) (COMP->CSR1 & COMP_CSR1_IE1);
|
||||
|
||||
if ((itstatus != (uint8_t) RESET) && (itenable != (uint8_t) RESET))
|
||||
{
|
||||
/* the EF1 and IE1 are set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* the EF1 or IE1 is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get the EF2 comparator event flag value */
|
||||
itstatus = (uint8_t) (COMP->CSR2 & COMP_CSR2_EF2);
|
||||
|
||||
/* Get the IE2 interrupt enable bit value */
|
||||
itenable = (uint8_t) (COMP->CSR2 & COMP_CSR2_IE2);
|
||||
|
||||
if ((itstatus != (uint8_t)RESET) && (itenable != (uint8_t)RESET))
|
||||
{
|
||||
/* The EF2 and IE2 are set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The EF2 or IE2 is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the COMP interrupt status */
|
||||
return (ITStatus) bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the interrupt pending bits of the comparator.
|
||||
* @param COMP_Selection : selects the comparator
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_Selection_COMP1: Selection of Comparator 1
|
||||
* @arg COMP_Selection_COMP2: Selection of Comparator 2
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_ClearITPendingBit(COMP_Selection_TypeDef COMP_Selection)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
|
||||
if (COMP_Selection == COMP_Selection_COMP1)
|
||||
{
|
||||
/* Clear the flag EF1 (rc_w0) clear this bit by writing 0. */
|
||||
COMP->CSR1 &= (uint8_t) (~COMP_CSR1_EF1);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the flag EF2 (rc_w0) clear this bit by writing 0. */
|
||||
COMP->CSR2 &= (uint8_t) (~COMP_CSR2_EF2);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
839
firmware/inc/stm8l151x/src/stm8l15x_dac.c
Normal file
839
firmware/inc/stm8l151x/src/stm8l15x_dac.c
Normal file
@@ -0,0 +1,839 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
|
||||
* - DAC channels configuration: trigger, output buffer, data format
|
||||
* - DMA management
|
||||
* - Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* DAC Peripheral features
|
||||
* ===================================================================
|
||||
* The device integrates two 12-bit Digital Analog Converters that can
|
||||
* be used independently or simultaneously (dual mode):
|
||||
* 1- DAC channel1 with DAC_OUT1 (PF0) as output
|
||||
* 1- DAC channel2 with DAC_OUT2 (PF1) as output
|
||||
*
|
||||
* Digital to Analog conversion can be non-triggered using DAC_Trigger_None
|
||||
* and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
|
||||
* DAC_SetChannel1Data()/DAC_SetChannel2Data.
|
||||
*
|
||||
* Digital to Analog conversion can be triggered by:
|
||||
* 1- External event: PE4 using DAC_Trigger_Ext.
|
||||
* This pin (PE4) must be configured in input mode.
|
||||
*
|
||||
* 2- Timers TRGO: TIM4, TIM5
|
||||
* (DAC_Trigger_T4_TRGO, DAC_Trigger_T5_TRGO)
|
||||
* The timer TRGO event should be selected using TIMx_SelectOutputTrigger()
|
||||
*
|
||||
* 3- Software using DAC_Trigger_Software
|
||||
*
|
||||
* Each DAC channel integrates an output buffer that can be used to
|
||||
* reduce the output impedance, and to drive external loads directly
|
||||
* without having to add an external operational amplifier.
|
||||
*
|
||||
* Refer to the device datasheet for more details about output impedance
|
||||
* value with and without output buffer.
|
||||
*
|
||||
* Both DAC channels can be used to generate
|
||||
* 1- Noise wave using DAC_Wave_Noise
|
||||
* 2- Triangle wave using DAC_Wave_Triangle
|
||||
*
|
||||
*
|
||||
* The DAC data format can be:
|
||||
* 1- 8-bit right alignment using DAC_Align_8b_R
|
||||
* 2- 12-bit left alignment using DAC_Align_12b_L
|
||||
* 3- 12-bit right alignment using DAC_Align_12b_R
|
||||
*
|
||||
* The analog output voltage on each DAC channel pin is determined
|
||||
* by the following equation: DAC_OUTx = VREF+ * DOR / 4095
|
||||
* with DOR is the Data Output Register
|
||||
* VEF+ is the input voltage reference (refer to the device datasheet)
|
||||
* e.g. To set DAC_OUT1 to 0.7V, use
|
||||
* DAC_SetChannel1Data(DAC_Align_12b_R, 868);
|
||||
* Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
|
||||
*
|
||||
* A DMA1 request can be generated when an external trigger (but not
|
||||
* a software trigger) occurs if DMA1 requests are enabled using
|
||||
* DAC_DMACmd()
|
||||
* DMA1 requests are mapped as following:
|
||||
* 1- DAC channel1 is mapped on DMA1 channel3 which must be already
|
||||
* configured
|
||||
* 2- DAC channel2 is mapped on DMA1 channel1 which must be already
|
||||
* configured
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* - DAC clock must be enabled to get write access to DAC registers using
|
||||
* CLK_PeripheralClockConfig(CLK_Peripheral_DAC, ENABLE)
|
||||
* - Configure DAC_OUTx (DAC_OUT1: PF0, DAC_OUT2: PF1) in analog mode.
|
||||
* - Configure the DAC channel using DAC_Init()
|
||||
* - Enable the DAC channel using DAC_Cmd()
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_dac.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group1 DAC channels configuration
|
||||
* @brief DAC channels configuration: trigger, output buffer, data format
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
DAC channels configuration: trigger, output buffer, data format
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DeInit(void)
|
||||
{
|
||||
/* Set Channel1 the Configuration registers to their reset values */
|
||||
DAC->CH1CR1 = DAC_CR1_RESET_VALUE;
|
||||
DAC->CH1CR2 = DAC_CR2_RESET_VALUE;
|
||||
|
||||
/* Set Channel2 the Configuration registers to their reset values */
|
||||
DAC->CH2CR1 = DAC_CR1_RESET_VALUE;
|
||||
DAC->CH2CR2 = DAC_CR2_RESET_VALUE;
|
||||
|
||||
/* Set the Software Trigger configuration registers to their reset values */
|
||||
DAC->SWTRIGR = DAC_SWTRIGR_RESET_VALUE;
|
||||
|
||||
/* Set the Status registers to their reset values */
|
||||
DAC->SR = (uint8_t)~DAC_SR_RESET_VALUE;
|
||||
|
||||
/* Set the Channel1 Data holding registers to their reset values */
|
||||
DAC->CH1RDHRH = DAC_RDHRH_RESET_VALUE;
|
||||
DAC->CH1RDHRL = DAC_RDHRL_RESET_VALUE;
|
||||
DAC->CH1LDHRH = DAC_LDHRH_RESET_VALUE;
|
||||
DAC->CH1LDHRL = DAC_LDHRL_RESET_VALUE;
|
||||
DAC->CH1DHR8 = DAC_DHR8_RESET_VALUE;
|
||||
|
||||
/* Set the Channel2 Data holding registers to their reset values */
|
||||
DAC->CH2RDHRH = DAC_RDHRH_RESET_VALUE;
|
||||
DAC->CH2RDHRL = DAC_RDHRL_RESET_VALUE;
|
||||
DAC->CH2LDHRH = DAC_LDHRH_RESET_VALUE;
|
||||
DAC->CH2LDHRL = DAC_LDHRL_RESET_VALUE;
|
||||
DAC->CH2DHR8 = DAC_DHR8_RESET_VALUE;
|
||||
|
||||
/* Set the Dual mode 12bit Right Data holding registers to their reset values */
|
||||
DAC->DCH1RDHRH = DAC_RDHRH_RESET_VALUE;
|
||||
DAC->DCH1RDHRL = DAC_RDHRL_RESET_VALUE;
|
||||
DAC->DCH2RDHRH = DAC_RDHRH_RESET_VALUE;
|
||||
DAC->DCH2RDHRL = DAC_RDHRL_RESET_VALUE;
|
||||
|
||||
/* Set the Dual mode 12bit Left Data holding registers to their reset values */
|
||||
DAC->DCH1LDHRH = DAC_LDHRH_RESET_VALUE;
|
||||
DAC->DCH1LDHRL = DAC_LDHRL_RESET_VALUE;
|
||||
DAC->DCH2LDHRH = DAC_LDHRH_RESET_VALUE;
|
||||
DAC->DCH2LDHRL = DAC_LDHRL_RESET_VALUE;
|
||||
|
||||
/* Set the Dual mode 8bit Data holding registers to their reset values */
|
||||
DAC->DCH1DHR8 = DAC_DHR8_RESET_VALUE;
|
||||
DAC->DCH2DHR8 = DAC_DHR8_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC according to the specified parameters.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_Trigger : the selected DAC trigger.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Trigger_None: DAC trigger None
|
||||
* @arg DAC_Trigger_T4_TRGO: DAC trigger TIM4 TRGO
|
||||
* @arg DAC_Trigger_T5_TRGO: DAC trigger TIM5 TRGO
|
||||
* @arg DAC_Trigger_Ext: DAC trigger External Trigger (PE4)
|
||||
* @arg DAC_Trigger_Software: DAC trigger software
|
||||
* @param DAC_OutputBuffer : the status of DAC load Buffer
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_OutputBuffer_Enable: DAC output buffer Enabled
|
||||
* @arg DAC_OutputBuffer_Disable: DAC output buffer Disabled
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Init(DAC_Channel_TypeDef DAC_Channel,
|
||||
DAC_Trigger_TypeDef DAC_Trigger,
|
||||
DAC_OutputBuffer_TypeDef DAC_OutputBuffer)
|
||||
{
|
||||
uint8_t tmpreg = 0;
|
||||
uint16_t tmpreg2 = 0;
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_TRIGGER(DAC_Trigger));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_OutputBuffer));
|
||||
|
||||
/* Get the DAC CHxCR1 value */
|
||||
tmpreg2 = (uint16_t)((uint8_t)((uint8_t)DAC_Channel << 1));
|
||||
tmpreg = *(uint8_t*)((uint16_t)(DAC_BASE + CR1_Offset + tmpreg2));
|
||||
|
||||
/* Clear BOFFx, TENx, TSELx bits */
|
||||
tmpreg &= (uint8_t)~(DAC_CR1_BOFF | DAC_CR1_TEN | DAC_CR1_TSEL );
|
||||
|
||||
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||
tmpreg |= (uint8_t)(DAC_OutputBuffer);
|
||||
|
||||
|
||||
/* Configure for the selected DAC channel trigger*/
|
||||
if (DAC_Trigger != DAC_Trigger_None)
|
||||
{
|
||||
/* Set TSELx and TEN bits according to DAC_Trigger value */
|
||||
tmpreg |= (uint8_t)(DAC_CR1_TEN | DAC_Trigger) ;
|
||||
}
|
||||
|
||||
/* Write to DAC CHxCR1 */
|
||||
*(uint8_t*)((uint16_t)(DAC_BASE + CR1_Offset + tmpreg2)) = (uint8_t)tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the DAC channel.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note When the DAC channel is enabled the trigger source can no more
|
||||
* be modified.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Cmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
uint16_t cr1addr = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Find CHxCR1 register Address */
|
||||
cr1addr = DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1);
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel */
|
||||
(*(uint8_t*)(cr1addr)) |= DAC_CR1_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel */
|
||||
(*(uint8_t*)(cr1addr)) &= (uint8_t) ~(DAC_CR1_EN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel software trigger.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel software trigger.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void DAC_SoftwareTriggerCmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR |= (uint8_t)(DAC_SWTRIGR_SWTRIG1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR &= (uint8_t)~((uint8_t)(DAC_SWTRIGR_SWTRIG1 << DAC_Channel));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables simultaneously the two DAC channels software
|
||||
* triggers.
|
||||
* @param NewState: new state of the DAC channels software triggers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for both DAC channels */
|
||||
DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2) ;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for both DAC channels */
|
||||
DAC->SWTRIGR &= (uint8_t)~(DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_Wave: Specifies the wave type to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Wave_Noise: noise wave generation
|
||||
* @arg DAC_Wave_Triangle: triangle wave generation
|
||||
* @param NewState: new state of the selected DAC channel wave generation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_WaveGenerationCmd(DAC_Channel_TypeDef DAC_Channel,
|
||||
DAC_Wave_TypeDef DAC_Wave,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
uint8_t tmpreg = 0;
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_WAVE(DAC_Wave));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Get the DAC CHxCR1 value & Clear WAVEN bits */
|
||||
tmpreg = (uint8_t)((*(uint8_t*)(uint16_t)(DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1))) & (uint8_t)~(DAC_CR1_WAVEN));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
tmpreg |= (uint8_t)(DAC_Wave);
|
||||
}
|
||||
|
||||
/* Write to DAC CHxCR1 */
|
||||
(*(uint8_t*) (uint16_t)(DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1))) = tmpreg;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select DAC Noise Wave Generation LFSR according to the specified parameters.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_LFSRUnmask : the selected unmasked bit.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_LFSRUnmask_Bit0: Noise LFSR Unmask 1 LSB
|
||||
* @arg DAC_LFSRUnmask_Bits1_0: Noise LFSR Unmask 2 LSB
|
||||
* @arg DAC_LFSRUnmask_Bit2_0: Noise LFSR Unmask 3 LSB
|
||||
* @arg DAC_LFSRUnmask_Bit3_0: Noise LFSR Unmask 4 LSB
|
||||
* @arg DAC_LFSRUnmask_Bit4_0: Noise LFSR Unmask 5 LSB
|
||||
* @arg DAC_LFSRUnmask_Bit5_0: Noise LFSR Unmask 6 LSB
|
||||
* @arg DAC_LFSRUnmask_Bit6_0: Noise LFSR Unmask 7 LSB
|
||||
* @arg DAC_LFSRUnmask_Bit7_0: Noise LFSR Unmask 8 LSB
|
||||
* @arg DAC_LFSRUnmask_Bit8_0: Noise LFSR Unmask 9 LSB
|
||||
* @arg DAC_LFSRUnmask_Bit9_0: Noise LFSR Unmask 10 LSB
|
||||
* @arg DAC_LFSRUnmask_Bit10_0: Noise LFSR Unmask 11 LSB
|
||||
* @arg DAC_LFSRUnmask_Bit11_0: Noise LFSR Unmask 12 LSB
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetNoiseWaveLFSR(DAC_Channel_TypeDef DAC_Channel, DAC_LFSRUnmask_TypeDef DAC_LFSRUnmask)
|
||||
{
|
||||
uint8_t tmpreg = 0;
|
||||
uint16_t cr2addr = 0;
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_LFSRUnmask));
|
||||
|
||||
/* Get the DAC CHxCR2 value & Clear MAMPx bits */
|
||||
cr2addr = (uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1));
|
||||
tmpreg = (uint8_t)((*(uint8_t*)(cr2addr)) & (uint8_t)~(DAC_CR2_MAMPx));
|
||||
|
||||
/* Write to DAC CHxCR2 */
|
||||
(*(uint8_t*)(cr2addr)) = (uint8_t)( tmpreg | DAC_LFSRUnmask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select DAC Triangle Wave Generation Amplitude according to the specified parameters.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_TriangleAmplitude : the selected Amplitude
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_TriangleAmplitude_1: Triangle Amplitude = Vref.(1/4096)
|
||||
* @arg DAC_TriangleAmplitude_3: Triangle Amplitude = Vref.(3/4096)
|
||||
* @arg DAC_TriangleAmplitude_7: Triangle Amplitude = Vref.(7/4096)
|
||||
* @arg DAC_TriangleAmplitude_15: Triangle Amplitude = Vref.(15/4096)
|
||||
* @arg DAC_TriangleAmplitude_31: Triangle Amplitude = Vref.(31/4096)
|
||||
* @arg DAC_TriangleAmplitude_63: Triangle Amplitude = Vref.(63/4096)
|
||||
* @arg DAC_TriangleAmplitude_127: Triangle Amplitude = Vref.(127/4096)
|
||||
* @arg DAC_TriangleAmplitude_255: Triangle Amplitude = Vref.(255/4096)
|
||||
* @arg DAC_TriangleAmplitude_511: Triangle Amplitude = Vref.(511/4096)
|
||||
* @arg DAC_TriangleAmplitude_1023: Triangle Amplitude = Vref.(1023/4096)
|
||||
* @arg DAC_TriangleAmplitude_2047: Triangle Amplitude = Vref.(2047/4096)
|
||||
* @arg DAC_TriangleAmplitude_4095: Triangle Amplitude = Vref.(4095/4096)
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetTriangleWaveAmplitude(DAC_Channel_TypeDef DAC_Channel, DAC_TriangleAmplitude_TypeDef DAC_TriangleAmplitude)
|
||||
{
|
||||
uint8_t tmpreg = 0;
|
||||
uint16_t cr2addr = 0;
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_TriangleAmplitude));
|
||||
|
||||
|
||||
/* Get the DAC CHxCR2 value & Clear MAMPx bits */
|
||||
cr2addr = (uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1));
|
||||
tmpreg = (uint8_t)((*(uint8_t*)(cr2addr)) & (uint8_t)~(DAC_CR2_MAMPx));
|
||||
|
||||
/* Write to DAC CHxCR2 */
|
||||
(*(uint8_t*)(cr2addr)) = (uint8_t)( tmpreg | DAC_TriangleAmplitude);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel1.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel1.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data : Data to be loaded in the selected data holding register.
|
||||
* @retval None.
|
||||
*/
|
||||
void DAC_SetChannel1Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
|
||||
if (DAC_Align != DAC_Align_8b_R)
|
||||
{
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(uint8_t*)((uint16_t)(DAC_BASE + CH1RDHRH_Offset + DAC_Align )) = (uint8_t)(((uint16_t)DAC_Data) >> 8);
|
||||
*(uint8_t*)((uint16_t)(DAC_BASE + CH1RDHRH_Offset + 1 + DAC_Align )) = (uint8_t)DAC_Data;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_DAC_DATA_08R(DAC_Data));
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
DAC->CH1DHR8 = (uint8_t)(DAC_Data);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel2.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data : Data to be loaded in the selected data holding register.
|
||||
* @retval None.
|
||||
*/
|
||||
void DAC_SetChannel2Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
|
||||
if (DAC_Align != DAC_Align_8b_R)
|
||||
{
|
||||
/* Set the DAC channel2 selected data holding register */
|
||||
*(uint8_t*)((uint16_t)(DAC_BASE + CH2RDHRH_Offset + DAC_Align )) = (uint8_t)(((uint16_t)DAC_Data) >> 8);
|
||||
*(uint8_t*)((uint16_t)(DAC_BASE + CH2RDHRH_Offset + 1 + DAC_Align )) = (uint8_t)DAC_Data;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_DAC_DATA_08R(DAC_Data));
|
||||
|
||||
/* Set the DAC channel2 selected data holding register */
|
||||
DAC->CH2DHR8 = (uint8_t)(DAC_Data);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual channel DAC.
|
||||
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @note In dual mode, a unique register access is required to write in both
|
||||
* DAC channels at the same time.
|
||||
* @retval None.
|
||||
*/
|
||||
void DAC_SetDualChannelData(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data2, uint16_t DAC_Data1)
|
||||
{
|
||||
uint16_t dchxrdhrhaddr = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
|
||||
if (DAC_Align != DAC_Align_8b_R)
|
||||
{
|
||||
/* Identify the DCHxRDHRH address*/
|
||||
dchxrdhrhaddr = (uint16_t)(DAC_BASE + DCH1RDHRH_Offset + DAC_Align);
|
||||
|
||||
/* Set the DAC channels Dual data holding registers */
|
||||
*(uint8_t*)(uint16_t)dchxrdhrhaddr = (uint8_t)(((uint16_t)DAC_Data1) >> 8);
|
||||
*(uint8_t*)(uint16_t)(dchxrdhrhaddr + 1) = (uint8_t)DAC_Data1;
|
||||
*(uint8_t*)(uint16_t)(dchxrdhrhaddr + 2) = (uint8_t)(((uint16_t)DAC_Data2) >> 8);
|
||||
*(uint8_t*)(uint16_t)(dchxrdhrhaddr + 3) = (uint8_t)DAC_Data2;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_DAC_DATA_08R(DAC_Data1 | DAC_Data2));
|
||||
|
||||
/* Set the DAC channels Dual data holding registers */
|
||||
DAC->DCH1DHR8 = (uint8_t)(DAC_Data1);
|
||||
DAC->DCH2DHR8 = (uint8_t)(DAC_Data2);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint16_t DAC_GetDataOutputValue(DAC_Channel_TypeDef DAC_Channel)
|
||||
{
|
||||
uint16_t outputdata = 0;
|
||||
uint16_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
|
||||
if ( DAC_Channel == DAC_Channel_1)
|
||||
{
|
||||
/* Returns the DAC channel data output register value */
|
||||
tmp = (uint16_t)((uint16_t)DAC->CH1DORH << 8);
|
||||
outputdata = (uint16_t)(tmp | (DAC->CH1DORL));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Returns the DAC channel data output register value */
|
||||
tmp = (uint16_t)((uint16_t)DAC->CH2DORH << 8);
|
||||
outputdata = (uint16_t)(tmp | (DAC->CH2DORL));
|
||||
}
|
||||
|
||||
/* return the selected DAC channel data output value.*/
|
||||
return (uint16_t)outputdata;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group2 DMA management functions
|
||||
* @brief DMA management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
DMA management function
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel DMA request.
|
||||
* When enabled DMA1 is generated when an external trigger occurs
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel1) which
|
||||
* must be already configured.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMACmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
uint16_t cr2addr = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Find CHxCR2 register Address */
|
||||
cr2addr = DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1);
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel DMA request */
|
||||
(*(uint8_t*)(cr2addr)) |= DAC_CR2_DMAEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
(*(uint8_t*)(cr2addr)) &= (uint8_t)~(DAC_CR2_DMAEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Interrupts and flags management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC interrupts.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
||||
* the acknowledgement for the first external trigger is received (first request).
|
||||
* @param NewState: new state of the specified DAC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ITConfig(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT, FunctionalState NewState)
|
||||
{
|
||||
uint16_t cr2addr = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Find CHxCR2 register Address */
|
||||
cr2addr = DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1);
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC interrupts */
|
||||
(*(uint8_t*)(cr2addr)) |= (uint8_t)(DAC_IT);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC interrupts */
|
||||
(*(uint8_t*)(cr2addr)) &= (uint8_t)(~(DAC_IT));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC flag is set or not.
|
||||
* @param DAC_Channel: thee selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to check.
|
||||
* This parameter can be only of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
||||
* the acknowledgement for the first external trigger is received (first request).
|
||||
* @retval The new state of DAC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DAC_GetFlagStatus(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG)
|
||||
{
|
||||
FlagStatus flagstatus = RESET;
|
||||
uint8_t flag = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
flag = (uint8_t)(DAC_FLAG << DAC_Channel);
|
||||
|
||||
/* Check the status of the specified DAC flag */
|
||||
if ((DAC->SR & flag ) != (uint8_t)RESET)
|
||||
{
|
||||
/* DAC FLAG is set */
|
||||
flagstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC FLAG is reset */
|
||||
flagstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the DAC FLAG status */
|
||||
return flagstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channel's pending flags.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearFlag(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG)
|
||||
{
|
||||
uint8_t flag = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* identify the selected flag*/
|
||||
flag = (uint8_t)(DAC_FLAG << DAC_Channel);
|
||||
|
||||
/* Clear the selected DAC flag */
|
||||
DAC->SR = (uint8_t)(~flag);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC interrupt has occurred or not.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt source to check.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
||||
* the acknowledgement for the first external trigger is received (first request).
|
||||
* @retval The new state of DAC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DAC_GetITStatus(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT)
|
||||
{
|
||||
ITStatus itstatus = RESET;
|
||||
uint8_t enablestatus = 0;
|
||||
uint8_t flagstatus = 0;
|
||||
uint8_t tempreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* identify the status of the IT and its correspondent flag*/
|
||||
tempreg = *(uint8_t*)(uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 2));
|
||||
enablestatus = (uint8_t)( tempreg & (uint8_t)((uint8_t)DAC_IT << DAC_Channel));
|
||||
flagstatus = (uint8_t)(DAC->SR & (uint8_t)(DAC_IT >> ((uint8_t)0x05 - DAC_Channel)));
|
||||
|
||||
/* Check the status of the specified DAC interrupt */
|
||||
if (((flagstatus) != (uint8_t)RESET) && enablestatus)
|
||||
{
|
||||
/* DAC IT is set */
|
||||
itstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC IT is reset */
|
||||
itstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the DAC IT status */
|
||||
return itstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channel's interrupt pending bits.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearITPendingBit(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Clear the selected DAC interrupt pending bits */
|
||||
DAC->SR = (uint8_t)~(uint8_t)((uint8_t)DAC_IT >> (0x05 - DAC_Channel));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
753
firmware/inc/stm8l151x/src/stm8l15x_dma.c
Normal file
753
firmware/inc/stm8l151x/src/stm8l15x_dma.c
Normal file
@@ -0,0 +1,753 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides all the DMA firmware functions.
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access controller (DMA):
|
||||
* - Initialization and Configuration
|
||||
* - Data Counter
|
||||
* - Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* 1. Enable The DMA controller clock using CLK_PeripheralClockConfig()
|
||||
* function: CLK_PeripheralClockConfig(CLK_Peripheral_DMA1, ENABLE).
|
||||
*
|
||||
* 2. Enable and configure the peripheral to be connected to the DMA
|
||||
* channel (except for internal SRAM / FLASH memories: no
|
||||
* initialization is necessary).
|
||||
*
|
||||
* 3. For a given Channel, program the Source and Destination
|
||||
* addresses, the transfer Direction, the Buffer Size, the
|
||||
* Peripheral and Memory Incrementation mode and Data Size,
|
||||
* the Circular or Normal mode, the channel transfer Priority
|
||||
* and the Memory-to-Memory transfer mode (for channel 3 only,
|
||||
* if needed) using the DMA_Init() function.
|
||||
*
|
||||
* 4. Enable the corresponding interrupt(s) using the function
|
||||
* DMA_ITConfig() if you need to use DMA interrupts.
|
||||
*
|
||||
* 5. Enable the DMA channel using the DMA_Cmd() function.
|
||||
*
|
||||
* 6. Activate the needed channel Request using PPP_DMACmd() function
|
||||
* for any PPP peripheral except internal SRAM and FLASH (ie. TIM4,
|
||||
* USART ...). The function allowing this operation is provided in
|
||||
* each PPP peripheral driver (ie. TIM4_DMACmd for TIM4 peripheral).
|
||||
*
|
||||
* 7. Optionally, you can configure the number of data to be
|
||||
* transferred when the channel is disabled (ie. after each
|
||||
* Transfer Complete event or when a Transfer Error occurs) using
|
||||
* the function DMA_SetCurrDataCounter().
|
||||
* And you can get the number of remaining data to be transferred
|
||||
* using the function DMA_GetCurrDataCounter() at run time (when
|
||||
* the DMA channel is enabled and running).
|
||||
*
|
||||
* 8. To control DMA events you can use one of the following
|
||||
* two methods:
|
||||
* a- Check on DMA channel flags using the function
|
||||
* DMA_GetFlagStatus().
|
||||
* b- Use DMA interrupts through the function DMA_ITConfig()
|
||||
* at initialization phase and DMA_GetITStatus() function
|
||||
* into interrupt routines in communication phase.
|
||||
* After checking on a flag you should clear it using
|
||||
* DMA_ClearFlag() function. And after checking on an interrupt
|
||||
* event you should clear it using DMA_ClearITPendingBit()
|
||||
* function.
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_dma.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA
|
||||
* @brief DMA driver modules
|
||||
* @{
|
||||
*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Initialization and Configuration functions
|
||||
===============================================================================
|
||||
|
||||
This subsection provides functions allowing to initialize the DMA channel
|
||||
source and destination addresses, incrementation and data sizes, transfer
|
||||
direction, buffer size, circular/normal mode selection, memory-to-memory mode
|
||||
selection and channel priority value.
|
||||
|
||||
- The DMA_Init() function follows the DMA configuration procedures.
|
||||
- All DMA channels can be enabled and disabled in the same time using
|
||||
DMA_GlobalCmd() function.
|
||||
- The DMA has 4 channels, User can enable or disable channels using
|
||||
DMA_Cmd() function.
|
||||
- The timeout duration (number of wait cycles starting from the latest
|
||||
request) is configured using DMA_SetTimeOut() function. The DMA then waits
|
||||
until this timeout has elapsed before requesting from the core a high
|
||||
priority access to the bus.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DMA Global Status register to its default reset
|
||||
* values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_GlobalDeInit(void)
|
||||
{
|
||||
/* Disable the DMA */
|
||||
DMA1->GCSR &= (uint8_t)~(DMA_GCSR_GE);
|
||||
|
||||
/* Reset DMA Channelx control register */
|
||||
DMA1->GCSR = (uint8_t)DMA_GCSR_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DMA Channelx registers to their default reset
|
||||
* values.
|
||||
* @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CHANNEL(DMA_Channelx));
|
||||
|
||||
/* Disable the selected DMA Channelx */
|
||||
DMA_Channelx->CCR &= (uint8_t)~(DMA_CCR_CE);
|
||||
|
||||
/* Reset DMA Channelx control register */
|
||||
DMA_Channelx->CCR = DMA_CCR_RESET_VALUE;
|
||||
|
||||
/* Reset DMA Channelx remaining bytes register */
|
||||
DMA_Channelx->CNBTR = DMA_CNBTR_RESET_VALUE;
|
||||
|
||||
/* Reset DMA Channelx peripheral address register */
|
||||
if (DMA_Channelx == DMA1_Channel3)
|
||||
{
|
||||
DMA_Channelx->CPARH = DMA_C3PARH_RESET_VALUE;
|
||||
DMA_Channelx->CM0EAR = DMA_C3M0EAR_RESET_VALUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_Channelx->CPARH = DMA_CPARH_RESET_VALUE;
|
||||
}
|
||||
DMA_Channelx->CPARL = DMA_CPARL_RESET_VALUE;
|
||||
|
||||
/* Reset DMA Channelx memory address register */
|
||||
DMA_Channelx->CM0ARH = DMA_CM0ARH_RESET_VALUE;
|
||||
DMA_Channelx->CM0ARL = DMA_CM0ARL_RESET_VALUE;
|
||||
|
||||
/* Reset interrupt pending bits for DMA Channel */
|
||||
DMA_Channelx->CSPR = DMA_CSPR_RESET_VALUE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMA Channelx according to the specified parameters.
|
||||
* @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
|
||||
* @param DMA_Memory0BaseAddr: Specifies Memory 0 Base Address
|
||||
* @param DMA_PeripheralMemory1BaseAddr: Specifies DMA channelx Peripheral
|
||||
* Base Address (if data is from/to peripheral) or DMA channelx
|
||||
* Memory1 Base Address (if data is from Memory0 to Memory1).
|
||||
* @param DMA_BufferSize: Specifies the size of the DMA channelx Buffer.
|
||||
* This parameter must be a value greater than 0.
|
||||
* @param DMA_DIR: Specifies the DMA Channelx transfer direction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_DIR_PeripheralToMemory: Data transfer direction is Peripheral To Memory
|
||||
* @arg DMA_DIR_MemoryToPeripheral: Data transfer direction is Memory To Peripheral
|
||||
* @arg DMA_DIR_Memory0ToMemory1: Data transfer direction is Memory0 To Memory 1
|
||||
* @param DMA_Mode: Specifies the DMA channelx mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_Mode_Normal: DMA normal buffer mode
|
||||
* @arg DMA_Mode_Circular: DMA circular buffer mode
|
||||
* @param DMA_MemoryIncMode: Specifies the DMA channelx memory Incremental/Decremental mode
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_MemoryIncMode_Dec: DMA memory incremented mode is decremental
|
||||
* @arg DMA_MemoryIncMode_Inc: DMA memory incremented mode is incremental
|
||||
* @param DMA_Priority: Specifies the DMA channelx priority.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_Priority_Low: Software Priority is Low
|
||||
* @arg DMA_Priority_Medium: Software Priority is Medium
|
||||
* @arg DMA_Priority_High: Software Priority is High
|
||||
* @arg DMA_Priority_VeryHigh: Software Priority is Very High
|
||||
* @param DMA_MemoryDataSize: Specifies the DMA channelx transfer Data size
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_MemoryDataSize_Byte: Memory Data Size is 1 Byte
|
||||
* @arg DMA_MemoryDataSize_HalfWord: Memory Data Size is 2 Bytes
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx,
|
||||
uint32_t DMA_Memory0BaseAddr,
|
||||
uint16_t DMA_PeripheralMemory1BaseAddr,
|
||||
uint8_t DMA_BufferSize,
|
||||
DMA_DIR_TypeDef DMA_DIR,
|
||||
DMA_Mode_TypeDef DMA_Mode,
|
||||
DMA_MemoryIncMode_TypeDef DMA_MemoryIncMode,
|
||||
DMA_Priority_TypeDef DMA_Priority,
|
||||
DMA_MemoryDataSize_TypeDef DMA_MemoryDataSize )
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CHANNEL(DMA_Channelx));
|
||||
assert_param(IS_DMA_DIR(DMA_DIR));
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DMA_BufferSize));
|
||||
assert_param(IS_DMA_MODE(DMA_Mode));
|
||||
assert_param(IS_DMA_MEMORY_INC_MODE(DMA_MemoryIncMode));
|
||||
assert_param(IS_DMA_PRIORITY(DMA_Priority));
|
||||
|
||||
/*--------------------------- DMA Channelx CCR Configuration ---------------*/
|
||||
/* Disable the selected DMA Channelx */
|
||||
DMA_Channelx->CCR &= (uint8_t)~(DMA_CCR_CE);
|
||||
|
||||
/* Reset DMA Channelx control register */
|
||||
DMA_Channelx->CCR = DMA_CCR_RESET_VALUE;
|
||||
|
||||
/* Set DMA direction & Mode & Incremental Memory mode */
|
||||
DMA_Channelx->CCR |= (uint8_t)((uint8_t)((uint8_t)DMA_DIR | \
|
||||
(uint8_t)DMA_Mode) | \
|
||||
(uint8_t)DMA_MemoryIncMode);
|
||||
|
||||
/*Clear old priority and memory data size option */
|
||||
DMA_Channelx->CSPR &= (uint8_t)(~(uint8_t)(DMA_CSPR_PL | DMA_CSPR_16BM));
|
||||
|
||||
/* Set old priority and memory data size option */
|
||||
DMA_Channelx->CSPR |= (uint8_t)((uint8_t)DMA_Priority | \
|
||||
(uint8_t)DMA_MemoryDataSize);
|
||||
|
||||
/*--------------------------- DMA Channelx CNDTR Configuration -------------*/
|
||||
/* Write to DMA Channelx CNDTR */
|
||||
DMA_Channelx->CNBTR = (uint8_t)DMA_BufferSize;
|
||||
|
||||
/*--------------------------- DMA Channelx CPAR Configuration --------------*/
|
||||
/* Write to DMA Channelx (0, 1 or 2) Peripheral address or Write to
|
||||
DMA Channel 3 Memory 1 address */
|
||||
DMA_Channelx->CPARH = (uint8_t)(DMA_PeripheralMemory1BaseAddr >> (uint8_t)8);
|
||||
DMA_Channelx->CPARL = (uint8_t)(DMA_PeripheralMemory1BaseAddr);
|
||||
|
||||
/*--------------------------- DMA Channelx CMAR Configuration --------------*/
|
||||
/* Write to DMA Channelx Memory address */
|
||||
if (DMA_Channelx == DMA1_Channel3)
|
||||
{
|
||||
DMA_Channelx->CM0EAR = (uint8_t)(DMA_Memory0BaseAddr >> (uint8_t)16);
|
||||
}
|
||||
DMA_Channelx->CM0ARH = (uint8_t)(DMA_Memory0BaseAddr >> (uint8_t)8);
|
||||
DMA_Channelx->CM0ARL = (uint8_t)(DMA_Memory0BaseAddr);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables All the DMA.
|
||||
* @param NewState: new state of the DMA. This parameter can be: ENABLE
|
||||
* or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_GlobalCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the DMA */
|
||||
DMA1->GCSR |= (uint8_t)DMA_GCSR_GE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the DMA */
|
||||
DMA1->GCSR &= (uint8_t)(~DMA_GCSR_GE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMA Channelx.
|
||||
* @note DMA_GlobalCmd function must be called first to enable or disable
|
||||
* the global DMA.
|
||||
* @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
|
||||
* @param NewState: new state of the DMA Channelx.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CHANNEL(DMA_Channelx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMA Channelx */
|
||||
DMA_Channelx->CCR |= DMA_CCR_CE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMA Channelx */
|
||||
DMA_Channelx->CCR &= (uint8_t)(~DMA_CCR_CE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the Time out Value.
|
||||
* @param DMA_TimeOut: an integer from 0 to 63
|
||||
* @note If timeout duration >0 (number of wait cycles starting from the
|
||||
* latest request), the DMA waits until this timeout has elapsed before
|
||||
* requesting from the core a high priority access to the bus.
|
||||
* @note If timeout duration =0, there is no timeout and once a request is served,
|
||||
* the DMA immediately asks to the CPU a high priority access to the bus.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_SetTimeOut(uint8_t DMA_TimeOut)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_TIMEOUT(DMA_TimeOut));
|
||||
|
||||
/* set the time out, GB and GE must be = 0 */
|
||||
DMA1->GCSR = 0;
|
||||
DMA1->GCSR = (uint8_t)(DMA_TimeOut << (uint8_t)2);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group2 Data Counter functions
|
||||
* @brief Data Counter functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Data Counter functions
|
||||
===============================================================================
|
||||
|
||||
This subsection provides functions allowing to configure and read the buffer
|
||||
size (number of data to be transferred).
|
||||
|
||||
The DMA data counter can be written only when the DMA channel is disabled
|
||||
(ie. after transfer complete event).
|
||||
|
||||
The DMA_SetCurrDataCounter() function can be used to write the Channel data
|
||||
counter value.
|
||||
|
||||
|
||||
Note: It is advised to use this function rather than DMA_Init() (DMA_BufferSize
|
||||
parameter) in situations where only the Data buffer needs to be reloaded.
|
||||
|
||||
The DMA data counter can be read to indicate the number of remaining transfers
|
||||
for the relative DMA channel. This counter is decremented at the end of each
|
||||
data transfer and when the transfer is complete:
|
||||
- If Normal mode is selected: the counter is set to 0.
|
||||
- If Circular mode is selected: the counter is reloaded with the initial value
|
||||
(configured before enabling the DMA channel)
|
||||
|
||||
The DMA_GetCurrDataCounter() function can be used to read the Channel current
|
||||
data counter value.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the number of data units to transfer for DMA Channelx.
|
||||
* @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
|
||||
* @param DataNumber: The number of data units to transfer, it can be any value
|
||||
* from 0 to 255
|
||||
* @note It is advised to use this function rather than DMA_Init() in situations
|
||||
* where only the Data buffer needs to be reloaded.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx, uint8_t DataNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CHANNEL(DMA_Channelx));
|
||||
|
||||
/*Set the number of data units for DMA Channelx */
|
||||
DMA_Channelx->CNBTR = DataNumber;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current DMA Channelx transfer.
|
||||
* @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
|
||||
* @retval The number of remaining data units in the current DMA Channelx
|
||||
*/
|
||||
uint8_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CHANNEL(DMA_Channelx));
|
||||
|
||||
/* Return the number of remaining data units for DMA Channelx */
|
||||
return ((uint8_t)(DMA_Channelx->CNBTR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Interrupts and flags management functions
|
||||
===============================================================================
|
||||
|
||||
This subsection provides functions allowing to configure the DMA Interrupts
|
||||
sources and check or clear the flags or pending bits status.
|
||||
The user should identify which mode will be used in his application to manage
|
||||
the DMA controller events: Polling mode or Interrupt mode.
|
||||
|
||||
Polling Mode
|
||||
=============
|
||||
Each DMA channel can be managed through 2 event Flags:
|
||||
(x: DMA channel number )
|
||||
1. DMA1_FLAG_TCx: to indicate that a Transfer Complete event occurred
|
||||
2. DMA1_FLAG_HTx: to indicate that a Half-Transfer Complete event
|
||||
occurred
|
||||
|
||||
In this Mode it is advised to use DMA_GetFlagStatus() and DMA_ClearFlag()
|
||||
functions.
|
||||
|
||||
|
||||
Interrupt Mode
|
||||
===============
|
||||
Each DMA channel can be managed through 2 Interrupts:
|
||||
|
||||
Interrupt Source
|
||||
----------------
|
||||
1. DMA_IT_TC: specifies the interrupt source for the Transfer Complete
|
||||
event.
|
||||
2. DMA_IT_HT: specifies the interrupt source for the Half-transfer
|
||||
Complete event.
|
||||
|
||||
In this Mode it is advised to use DMA_ITConfig(), DMA_GetITStatus() and
|
||||
DMA_ClearITPendingBit() functions.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMA Channelx interrupts.
|
||||
* @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3
|
||||
* @param DMA_ITx: specifies the DMA interrupts sources to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_ITx_TC: Transaction Complete Interrupt
|
||||
* @arg DMA_ITx_HT: Half Transaction Interrupt
|
||||
* @param NewState: new state of the specified DMA interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx,
|
||||
DMA_ITx_TypeDef DMA_ITx,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CHANNEL(DMA_Channelx));
|
||||
assert_param(IS_DMA_CONFIG_ITX(DMA_ITx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMA interrupts */
|
||||
DMA_Channelx->CCR |= (uint8_t)(DMA_ITx);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMA interrupts */
|
||||
DMA_Channelx->CCR &= (uint8_t)~(DMA_ITx);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMA Channelx flag is set or not.
|
||||
* @param DMA_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_FLAG_GB: Global Busy Flag
|
||||
* @arg DMA1_FLAG_IFC0: Global Interrupt Flag Channel 0
|
||||
* @arg DMA1_FLAG_IFC1: Global Interrupt Flag Channel 1
|
||||
* @arg DMA1_FLAG_IFC2: Global Interrupt Flag Channel 2
|
||||
* @arg DMA1_FLAG_IFC3: Global Interrupt Flag Channel 3
|
||||
* @arg DMA1_FLAG_TC0: Transaction Complete Interrupt Flag Channel 0
|
||||
* @arg DMA1_FLAG_TC1: Transaction Complete Interrupt Flag Channel 1
|
||||
* @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 2
|
||||
* @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 3
|
||||
* @arg DMA1_FLAG_HT0: Half Transaction Interrupt Flag Channel 0
|
||||
* @arg DMA1_FLAG_HT1: Half Transaction Interrupt Flag Channel 1
|
||||
* @arg DMA1_FLAG_HT2: Half Transaction Interrupt Flag Channel 2
|
||||
* @arg DMA1_FLAG_HT3: Half Transaction Interrupt Flag Channel 3
|
||||
* @arg DMA1_FLAG_PEND0: DMA Request pending on Channel 0
|
||||
* @arg DMA1_FLAG_PEND1: DMA Request pending on Channel 1
|
||||
* @arg DMA1_FLAG_PEND2: DMA Request pending on Channel 2
|
||||
* @arg DMA1_FLAG_PEND3: DMA Request pending on Channel 3
|
||||
* @arg DMA1_FLAG_BUSY0: No DMA transfer on going in Channel 0
|
||||
* @arg DMA1_FLAG_BUSY1: No DMA transfer on going in Channel 1
|
||||
* @arg DMA1_FLAG_BUSY2: No DMA transfer on going in Channel 2
|
||||
* @arg DMA1_FLAG_BUSY3: No DMA transfer on going in Channel 3
|
||||
* @retval The status of DMA_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DMA_GetFlagStatus(DMA_FLAG_TypeDef DMA_FLAG)
|
||||
{
|
||||
FlagStatus flagstatus = RESET;
|
||||
DMA_Channel_TypeDef* DMA_Channelx = DMA1_Channel0;
|
||||
uint8_t tmpgir1 = 0;
|
||||
uint8_t tmpgcsr = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
|
||||
|
||||
/* Get flags registers values*/
|
||||
tmpgcsr = DMA1->GCSR;
|
||||
tmpgir1 = DMA1->GIR1;
|
||||
|
||||
if (((uint16_t)DMA_FLAG & (uint16_t)0x0F00) != (uint16_t)RESET)
|
||||
{
|
||||
/* find the used DMA channel */
|
||||
if (((uint16_t)DMA_FLAG & 0x0100) != (uint16_t)RESET)
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel0;
|
||||
}
|
||||
else if (((uint16_t)DMA_FLAG & 0x0200) != (uint16_t)RESET)
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel1;
|
||||
}
|
||||
else if (((uint16_t)DMA_FLAG & 0x0400) != (uint16_t)RESET)
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel2;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel3;
|
||||
}
|
||||
|
||||
/* Get the specified DMA Channelx flag status. */
|
||||
flagstatus = (FlagStatus)((uint8_t)(DMA_Channelx->CSPR) & (uint8_t)DMA_FLAG);
|
||||
}
|
||||
else if (((uint16_t)DMA_FLAG & 0x1000) != (uint16_t)RESET)
|
||||
{
|
||||
/* Get the specified DMA Channelx flag status. */
|
||||
flagstatus = (FlagStatus)(tmpgir1 & (uint8_t)DMA_FLAG);
|
||||
}
|
||||
else /*if ((DMA_FLAG & DMA_FLAG_GB) != (uint16_t)RESET)*/
|
||||
{
|
||||
/* Get the specified DMA Channelx flag status. */
|
||||
flagstatus = (FlagStatus)(tmpgcsr & DMA_GCSR_GB);
|
||||
}
|
||||
|
||||
/* Return the specified DMA Channelx flag status. */
|
||||
return (flagstatus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channels selected flags.
|
||||
* @param DMA_FLAG: specifies the flag to clear.
|
||||
* This parameter can be one or a combination (for the same channel)of
|
||||
* the following values:
|
||||
* @arg DMA1_FLAG_TC0: Transaction Complete Interrupt Flag Channel 0
|
||||
* @arg DMA1_FLAG_TC1: Transaction Complete Interrupt Flag Channel 1
|
||||
* @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 2
|
||||
* @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 3
|
||||
* @arg DMA1_FLAG_HT0: Half Transaction Interrupt Flag Channel 0
|
||||
* @arg DMA1_FLAG_HT1: Half Transaction Interrupt Flag Channel 1
|
||||
* @arg DMA1_FLAG_HT2: Half Transaction Interrupt Flag Channel 2
|
||||
* @arg DMA1_FLAG_HT3: Half Transaction Interrupt Flag Channel 3
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearFlag(DMA_FLAG_TypeDef DMA_FLAG)
|
||||
{
|
||||
DMA_Channel_TypeDef* DMA_Channelx = DMA1_Channel0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
|
||||
|
||||
/* Identify the used DMA channel */
|
||||
if (((uint16_t)DMA_FLAG & (uint16_t)0x0100) != (uint16_t)RESET)
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel0;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (((uint16_t)DMA_FLAG & (uint16_t)0x0200) != (uint16_t)RESET)
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel1;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (((uint16_t)DMA_FLAG & (uint16_t)0x0400) != (uint16_t)RESET)
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel2;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel3;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*Clears the DMA flags.*/
|
||||
DMA_Channelx->CSPR &= (uint8_t)~(uint8_t)((uint8_t)DMA_FLAG & (uint8_t)0x06);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMA Channelx interrupt has occurred or not.
|
||||
* @param DMA_IT: specifies the DMA interrupt source to check.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg DMA1_IT_TC0: Transaction Complete Interrupt Channel 0
|
||||
* @arg DMA1_IT_TC1: Transaction Complete Interrupt Channel 1
|
||||
* @arg DMA1_IT_TC2: Transaction Complete Interrupt Channel 2
|
||||
* @arg DMA1_IT_TC3: Transaction Complete Interrupt Channel 3
|
||||
* @arg DMA1_IT_HT0: Half Transaction Interrupt Channel 0
|
||||
* @arg DMA1_IT_HT1: Half Transaction Interrupt Channel 1
|
||||
* @arg DMA1_IT_HT2: Half Transaction Interrupt Channel 2
|
||||
* @arg DMA1_IT_HT3: Half Transaction Interrupt Channel 3
|
||||
* @retval ITStatus: The status of DMA_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DMA_GetITStatus(DMA_IT_TypeDef DMA_IT)
|
||||
{
|
||||
ITStatus itstatus = RESET;
|
||||
uint8_t tmpreg = 0;
|
||||
uint8_t tmp2 = 0;
|
||||
DMA_Channel_TypeDef* DMA_Channelx = DMA1_Channel0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_IT(DMA_IT));
|
||||
|
||||
/* Identify the used DMA channel */
|
||||
if ((DMA_IT & 0x10) != (uint8_t)RESET)
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel0;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((DMA_IT & 0x20) != (uint8_t)RESET)
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel1;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((DMA_IT & 0x40) != (uint8_t)RESET)
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel2;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel3;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Get the specified DMA Channelx interrupt status. */
|
||||
tmpreg = DMA_Channelx->CSPR ;
|
||||
tmpreg &= DMA_Channelx->CCR ;
|
||||
tmp2 = (uint8_t)(DMA_IT & (uint8_t)(DMA_CCR_TCIE | DMA_CCR_HTIE));
|
||||
itstatus = (ITStatus)((uint8_t)tmpreg & (uint8_t)tmp2);
|
||||
|
||||
/* Return the specified DMA Channelx interrupt status. */
|
||||
return (itstatus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMA Channelx<6C>s interrupt pending bits.
|
||||
* @param DMA_IT: specifies the DMA interrupt pending bit to clear.
|
||||
* This parameter can be one or a combination(for the same channel)of
|
||||
* the following values:
|
||||
* @arg DMA1_IT_TC0: Transaction Complete Interrupt Channel 0
|
||||
* @arg DMA1_IT_TC1: Transaction Complete Interrupt Channel 1
|
||||
* @arg DMA1_IT_TC2: Transaction Complete Interrupt Channel 2
|
||||
* @arg DMA1_IT_TC3: Transaction Complete Interrupt Channel 3
|
||||
* @arg DMA1_IT_HT0: Half Transaction Interrupt Channel 0
|
||||
* @arg DMA1_IT_HT1: Half Transaction Interrupt Channel 1
|
||||
* @arg DMA1_IT_HT2: Half Transaction Interrupt Channel 2
|
||||
* @arg DMA1_IT_HT3: Half Transaction Interrupt Channel 3
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearITPendingBit(DMA_IT_TypeDef DMA_IT)
|
||||
{
|
||||
DMA_Channel_TypeDef* DMA_Channelx = DMA1_Channel0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_IT(DMA_IT));
|
||||
/* Identify the used DMA channel */
|
||||
if ((DMA_IT & 0x10) != (uint8_t)RESET)
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel0;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((DMA_IT & 0x20) != (uint8_t)RESET)
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel1;
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((DMA_IT & 0x40) != (uint8_t)RESET)
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel2;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_Channelx = DMA1_Channel3;
|
||||
}
|
||||
}
|
||||
}
|
||||
/*Clears the DMA Channelx<6C>s interrupt pending bits*/
|
||||
DMA_Channelx->CSPR &= (uint8_t)~(uint8_t)(DMA_IT & (uint8_t)0x06);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
559
firmware/inc/stm8l151x/src/stm8l15x_exti.c
Normal file
559
firmware/inc/stm8l151x/src/stm8l15x_exti.c
Normal file
@@ -0,0 +1,559 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_exti.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the EXTI peripheral:
|
||||
* - Interrupt sensitivity of GPIO ports/pins configuration
|
||||
* - Interrupt status management
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* This driver provides functions to configure and initialize the EXTI
|
||||
* peripheral
|
||||
* These functions are split in 2 groups:
|
||||
*
|
||||
* 1. EXTI configuration: this group includes all needed functions
|
||||
* to configure the EXTI GPIO ports and pins:
|
||||
* - Set GPIO pins sensitivity
|
||||
* - Select GPIO port, GPIO half port and set the GPIO port sensitivity
|
||||
*
|
||||
* 2. EXTI interrupt status management
|
||||
* - Get the interrupt status: set/reset
|
||||
* - Clear interrupt pending bits
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_exti.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI
|
||||
* @brief EXTI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Group1 Interrupt sensitivity of GPIO ports/pins configuration
|
||||
* @brief Interrupt sensitivity of GPIO ports/pins configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
EXTI configuration functions
|
||||
===============================================================================
|
||||
|
||||
===================================================================
|
||||
EXTI Driver: how to configure EXTI
|
||||
===================================================================
|
||||
To use a GPIO pin as an interrupt source, follow theses steps:
|
||||
|
||||
1. Configure the GPIO pin in input mode with interrupt enabled using
|
||||
GPIO_Init()
|
||||
|
||||
2. Configure the GPIO pin sensitivity (falling, rising...) using
|
||||
EXTI_SetPinSensitivity()
|
||||
|
||||
3. Enable global interrupts using enableInterrupts()
|
||||
|
||||
4. In the IRQ handler corresponding to the GPIO pin, clear the interrupt
|
||||
pending bit using EXTI_ClearITPendingBit()
|
||||
|
||||
To use a GPIO port as an interrupt source, follows theses steps:
|
||||
|
||||
1. Configure the GPIO pins of the same port in input mode with interrupt
|
||||
enabled using GPIO_Init()
|
||||
|
||||
2. Configure the GPIO port sensitivity (falling, rising...) using
|
||||
EXTI_SetPortSensitivity()
|
||||
|
||||
3. Select the GPIO port and the corresponding half port using
|
||||
EXTI_SelectPort() then EXTI_SetHalfPortSelection()
|
||||
|
||||
4. Enable global interrupts using enableInterrupts()
|
||||
|
||||
5. In the IRQ handler corresponding to the GPIO port, clear the interrupt
|
||||
pending bit using EXTI_ClearITPendingBit()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the EXTI registers to their default reset value.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
EXTI->CR1 = EXTI_CR1_RESET_VALUE;
|
||||
EXTI->CR2 = EXTI_CR2_RESET_VALUE;
|
||||
EXTI->CR3 = EXTI_CR3_RESET_VALUE;
|
||||
EXTI->CR4 = EXTI_CR4_RESET_VALUE;
|
||||
EXTI->SR1 = 0xFF; /* Setting SR1 bits in order to clear flags */
|
||||
EXTI->SR2 = 0xFF; /* Setting SR2 bits in order to clear flags */
|
||||
EXTI->CONF1 = EXTI_CONF1_RESET_VALUE;
|
||||
EXTI->CONF2 = EXTI_CONF2_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the external interrupt sensitivity of the selected pin.
|
||||
* @note Global interrupts must be disabled before calling this function.
|
||||
* @note The modification of external interrupt sensitivity is only possible
|
||||
* when he interrupts are disabled.
|
||||
* @note The normal behavior is to disable the interrupts before calling this
|
||||
* function, and re-enable them after.
|
||||
* @param EXTI_Pin : The pin to configure.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg EXTI_Pin_0: GPIO Pin 0
|
||||
* @arg EXTI_Pin_1: GPIO Pin 1
|
||||
* @arg EXTI_Pin_2: GPIO Pin 2
|
||||
* @arg EXTI_Pin_3: GPIO Pin 3
|
||||
* @arg EXTI_Pin_4: GPIO Pin 4
|
||||
* @arg EXTI_Pin_5: GPIO Pin 5
|
||||
* @arg EXTI_Pin_6: GPIO Pin 6
|
||||
* @arg EXTI_Pin_7: GPIO Pin 7
|
||||
* @param EXTI_Trigger : The external interrupt sensitivity value to set.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg EXTI_Trigger_Falling_Low: Interrupt on Falling edge and Low level
|
||||
* @arg EXTI_Trigger_Rising: Interrupt on Rising edge only
|
||||
* @arg EXTI_Trigger_Falling: Interrupt on Falling edge only
|
||||
* @arg EXTI_Trigger_Rising_Falling: Interrupt on Rising and Falling edges
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_SetPinSensitivity(EXTI_Pin_TypeDef EXTI_Pin, EXTI_Trigger_TypeDef EXTI_Trigger)
|
||||
{
|
||||
|
||||
/* Check function parameters */
|
||||
assert_param(IS_EXTI_PINNUM(EXTI_Pin));
|
||||
assert_param(IS_EXTI_TRIGGER(EXTI_Trigger));
|
||||
|
||||
/* Clear port sensitivity bits */
|
||||
switch (EXTI_Pin)
|
||||
{
|
||||
case EXTI_Pin_0:
|
||||
EXTI->CR1 &= (uint8_t)(~EXTI_CR1_P0IS);
|
||||
EXTI->CR1 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Pin);
|
||||
break;
|
||||
case EXTI_Pin_1:
|
||||
EXTI->CR1 &= (uint8_t)(~EXTI_CR1_P1IS);
|
||||
EXTI->CR1 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Pin);
|
||||
break;
|
||||
case EXTI_Pin_2:
|
||||
EXTI->CR1 &= (uint8_t)(~EXTI_CR1_P2IS);
|
||||
EXTI->CR1 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Pin);
|
||||
break;
|
||||
case EXTI_Pin_3:
|
||||
EXTI->CR1 &= (uint8_t)(~EXTI_CR1_P3IS);
|
||||
EXTI->CR1 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Pin);
|
||||
break;
|
||||
case EXTI_Pin_4:
|
||||
EXTI->CR2 &= (uint8_t)(~EXTI_CR2_P4IS);
|
||||
EXTI->CR2 |= (uint8_t)((uint8_t)(EXTI_Trigger) << ((uint8_t)EXTI_Pin & (uint8_t)0xEF));
|
||||
break;
|
||||
case EXTI_Pin_5:
|
||||
EXTI->CR2 &= (uint8_t)(~EXTI_CR2_P5IS);
|
||||
EXTI->CR2 |= (uint8_t)((uint8_t)(EXTI_Trigger) << ((uint8_t)EXTI_Pin & (uint8_t)0xEF));
|
||||
break;
|
||||
case EXTI_Pin_6:
|
||||
EXTI->CR2 &= (uint8_t)(~EXTI_CR2_P6IS);
|
||||
EXTI->CR2 |= (uint8_t)((uint8_t)(EXTI_Trigger) << ((uint8_t)EXTI_Pin & (uint8_t)0xEF));
|
||||
break;
|
||||
case EXTI_Pin_7:
|
||||
EXTI->CR2 &= (uint8_t)(~EXTI_CR2_P7IS);
|
||||
EXTI->CR2 |= (uint8_t)((uint8_t)(EXTI_Trigger) << ((uint8_t)EXTI_Pin & (uint8_t)0xEF));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the port interrupt selection.
|
||||
* @param EXTI_Port : The port number to access.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg EXTI_Port_B: GPIO Port B
|
||||
* @arg EXTI_Port_D: GPIO Port D
|
||||
* @arg EXTI_Port_E: GPIO Port E
|
||||
* @arg EXTI_Port_F: GPIO Port F
|
||||
* @arg EXTI_Port_G: GPIO Port G
|
||||
* @arg EXTI_Port_H: GPIO Port H
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_SelectPort(EXTI_Port_TypeDef EXTI_Port)
|
||||
{
|
||||
/* Check function parameter */
|
||||
assert_param(IS_EXTI_PORT(EXTI_Port));
|
||||
|
||||
if (EXTI_Port == EXTI_Port_B)
|
||||
{
|
||||
/* Select Port B by resetting PGBS bit in CONF2 register */
|
||||
EXTI->CONF2 &= (uint8_t) (~EXTI_CONF2_PGBS);
|
||||
}
|
||||
else if (EXTI_Port == EXTI_Port_D)
|
||||
{
|
||||
/* Select Port D by resetting PHDS bit in CONF2 register */
|
||||
EXTI->CONF2 &= (uint8_t) (~EXTI_CONF2_PHDS);
|
||||
}
|
||||
else if (EXTI_Port == EXTI_Port_E)
|
||||
{
|
||||
/* Select Port E by resetting PFES bit in CONF1 register */
|
||||
EXTI->CONF1 &= (uint8_t) (~EXTI_CONF1_PFES);
|
||||
}
|
||||
else if (EXTI_Port == EXTI_Port_F)
|
||||
{
|
||||
/* Select Port F by setting PFES bit in CONF1 register */
|
||||
EXTI->CONF1 |= (uint8_t) (EXTI_CONF1_PFES);
|
||||
}
|
||||
else if (EXTI_Port == EXTI_Port_G)
|
||||
{
|
||||
/* Select Port G by setting PGBS bit in CONF2 register */
|
||||
EXTI->CONF2 |= (uint8_t) (EXTI_CONF2_PGBS);
|
||||
}
|
||||
else /* EXTI_Port is EXTI_Port_H */
|
||||
{
|
||||
/* Select Port H by setting PHDS bit in CONF2 register */
|
||||
EXTI->CONF2 |= (uint8_t) (EXTI_CONF2_PHDS);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the half port interrupt selection.
|
||||
* @note This function should be called once the port sensitivity configured,
|
||||
* otherwise it will not have any effect on the port external interrupt.
|
||||
* @note This function should be called after EXTI_SelectPort() function which
|
||||
* selects the port to be used otherwise ports are selected by default
|
||||
* @param EXTI_HalfPort : The port part to access (MSB or LSB).
|
||||
* This parameter can be one of the following values:
|
||||
* @arg EXTI_HalfPort_B_LSB: Interrupt selector PB(3:0)
|
||||
* @arg EXTI_HalfPort_B_MSB: Interrupt selector PB(7:4)
|
||||
* @arg EXTI_HalfPort_D_LSB: Interrupt selector PD(3:0)
|
||||
* @arg EXTI_HalfPort_D_MSB: Interrupt selector PD(7:4)
|
||||
* @arg EXTI_HalfPort_E_LSB: Interrupt selector PE(3:0)
|
||||
* @arg EXTI_HalfPort_E_MSB: Interrupt selector PE(7:4)
|
||||
* @arg EXTI_HalfPort_F_LSB: Interrupt selector PF(3:0)
|
||||
* @arg EXTI_HalfPort_F_MSB: Interrupt selector PF(7:4)
|
||||
* @arg EXTI_HalfPort_G_LSB: Interrupt selector PG(3:0)
|
||||
* @arg EXTI_HalfPort_G_MSB: Interrupt selector PG(7:4)
|
||||
* @arg EXTI_HalfPort_H_LSB: Interrupt selector PH(3:0)
|
||||
* @arg EXTI_HalfPort_H_MSB: Interrupt selector PH(7:4)
|
||||
* @param NewState : The external interrupt new state.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_SetHalfPortSelection(EXTI_HalfPort_TypeDef EXTI_HalfPort,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_EXTI_HALFPORT(EXTI_HalfPort));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if ((EXTI_HalfPort & 0x80) == 0x00)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable port interrupt selector */
|
||||
EXTI->CONF1 |= (uint8_t)EXTI_HalfPort;
|
||||
}
|
||||
else /*NewState == DISABLE */
|
||||
{
|
||||
/* Disable port interrupt selector */
|
||||
EXTI->CONF1 &= (uint8_t)(~(uint8_t)EXTI_HalfPort);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable port interrupt selector */
|
||||
EXTI->CONF2 |= (uint8_t)(EXTI_HalfPort & (uint8_t)0x7F);
|
||||
}
|
||||
else /*NewState == DISABLE */
|
||||
{
|
||||
/* Disable port interrupt selector */
|
||||
EXTI->CONF2 &= (uint8_t)(~(uint8_t) (EXTI_HalfPort & (uint8_t)0x7F));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the external interrupt sensitivity of the selected port.
|
||||
* @note Global interrupts must be disabled before calling this function.
|
||||
* @note The modification of external interrupt sensitivity is only possible
|
||||
* when the interrupts are disabled.
|
||||
* @note The normal behavior is to disable the interrupts before calling this
|
||||
* function, and re-enable them after.
|
||||
* @param EXTI_Port : The port number to access.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg EXTI_Port_B: GPIO Port B
|
||||
* @arg EXTI_Port_D: GPIO Port D
|
||||
* @arg EXTI_Port_E: GPIO Port E
|
||||
* @arg EXTI_Port_F: GPIO Port F
|
||||
* @arg EXTI_Port_G: GPIO Port G
|
||||
* @arg EXTI_Port_H: GPIO Port H
|
||||
* @param EXTI_Trigger : The external interrupt sensitivity value to set.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg EXTI_Trigger_Falling_Low: Interrupt on Falling edge and Low level
|
||||
* @arg EXTI_Trigger_Rising: Interrupt on Rising edge only
|
||||
* @arg EXTI_Trigger_Falling: Interrupt on Falling edge only
|
||||
* @arg EXTI_Trigger_Rising_Falling: Interrupt on Rising and Falling edges
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_SetPortSensitivity(EXTI_Port_TypeDef EXTI_Port,
|
||||
EXTI_Trigger_TypeDef EXTI_Trigger)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_EXTI_PORT(EXTI_Port));
|
||||
assert_param(IS_EXTI_TRIGGER(EXTI_Trigger));
|
||||
|
||||
/* Ceck if selected port is in EXTI_CR3 register */
|
||||
if ((EXTI_Port & 0xF0) == 0x00)
|
||||
{
|
||||
/* Reset the trigger bits corresponding to EXTI_Port */
|
||||
EXTI->CR3 &= (uint8_t) (~(uint8_t)((uint8_t)0x03 << EXTI_Port));
|
||||
/* Write EXTI port trigger */
|
||||
EXTI->CR3 |= (uint8_t)((uint8_t)(EXTI_Trigger) << EXTI_Port);
|
||||
}
|
||||
else /* selected port is in EXTI_CR4 register */
|
||||
{
|
||||
/* Reset the trigger bits corresponding to EXTI_Port */
|
||||
EXTI->CR4 &= (uint8_t) (~(uint8_t)((uint8_t)0x03 << (EXTI_Port & 0x0F)));
|
||||
/* Write EXTI port trigger */
|
||||
EXTI->CR4 |= (uint8_t)(EXTI_Trigger << (EXTI_Port & 0x0F));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the external interrupt sensitivity of the selected pin.
|
||||
* @param EXTI_Pin : The pin number to access.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg EXTI_Pin_0: GPIO Pin 0
|
||||
* @arg EXTI_Pin_1: GPIO Pin 1
|
||||
* @arg EXTI_Pin_2: GPIO Pin 2
|
||||
* @arg EXTI_Pin_3: GPIO Pin 3
|
||||
* @arg EXTI_Pin_4: GPIO Pin 4
|
||||
* @arg EXTI_Pin_5: GPIO Pin 5
|
||||
* @arg EXTI_Pin_6: GPIO Pin 6
|
||||
* @arg EXTI_Pin_7: GPIO Pin 7
|
||||
* @retval The external interrupt sensitivity of the selected port.
|
||||
*/
|
||||
EXTI_Trigger_TypeDef EXTI_GetPinSensitivity(EXTI_Pin_TypeDef EXTI_Pin)
|
||||
{
|
||||
uint8_t value = 0;
|
||||
|
||||
/* Check function parameters */
|
||||
assert_param(IS_EXTI_PINNUM(EXTI_Pin));
|
||||
|
||||
switch (EXTI_Pin)
|
||||
{
|
||||
case EXTI_Pin_0:
|
||||
value = (uint8_t)(EXTI->CR1 & EXTI_CR1_P0IS);
|
||||
break;
|
||||
case EXTI_Pin_1:
|
||||
value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_P1IS) >> EXTI_Pin_1);
|
||||
break;
|
||||
case EXTI_Pin_2:
|
||||
value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_P2IS) >> EXTI_Pin_2);
|
||||
break;
|
||||
case EXTI_Pin_3:
|
||||
value = (uint8_t)((uint8_t)(EXTI->CR1 & EXTI_CR1_P3IS) >> EXTI_Pin_3);
|
||||
break;
|
||||
case EXTI_Pin_4:
|
||||
value = (uint8_t)(EXTI->CR2 & EXTI_CR2_P4IS);
|
||||
break;
|
||||
case EXTI_Pin_5:
|
||||
value = (uint8_t)((uint8_t)(EXTI->CR2 & EXTI_CR2_P5IS) >> ((uint8_t)EXTI_Pin_5 & (uint8_t)0x0F));
|
||||
break;
|
||||
case EXTI_Pin_6:
|
||||
value = (uint8_t)((uint8_t)(EXTI->CR2 & EXTI_CR2_P6IS) >> ((uint8_t)EXTI_Pin_6 & (uint8_t)0x0F));
|
||||
break;
|
||||
case EXTI_Pin_7:
|
||||
value = (uint8_t)((uint8_t)(EXTI->CR2 & EXTI_CR2_P7IS) >> ((uint8_t)EXTI_Pin_7 & (uint8_t)0x0F));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return((EXTI_Trigger_TypeDef)value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the external interrupt sensitivity of the selected port.
|
||||
* @param EXTI_Port : The port number to access.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg EXTI_Port_B: GPIO Port B
|
||||
* @arg EXTI_Port_D: GPIO Port D
|
||||
* @arg EXTI_Port_E: GPIO Port E
|
||||
* @arg EXTI_Port_F: GPIO Port F
|
||||
* @arg EXTI_Port_G: GPIO Port G
|
||||
* @arg EXTI_Port_H: GPIO Port H
|
||||
* @retval The external interrupt sensitivity of the selected port.
|
||||
*/
|
||||
EXTI_Trigger_TypeDef EXTI_GetPortSensitivity(EXTI_Port_TypeDef EXTI_Port)
|
||||
{
|
||||
uint8_t portsensitivity = 0;
|
||||
|
||||
/* Check function parameters */
|
||||
assert_param(IS_EXTI_PORT(EXTI_Port));
|
||||
|
||||
/* Check if selected port is in EXTI_CR3 */
|
||||
if ((EXTI_Port & 0xF0) == 0x00)
|
||||
{
|
||||
/* Get port sensitivity */
|
||||
portsensitivity = (uint8_t)((uint8_t)0x03 & (uint8_t)(EXTI->CR3 >> EXTI_Port));
|
||||
}
|
||||
/* selected port is in EXTI_CR4 */
|
||||
else
|
||||
{
|
||||
/* Get port sensitivity */
|
||||
portsensitivity = (uint8_t)((uint8_t)0x03 & (uint8_t)(EXTI->CR4 >> (EXTI_Port & 0x0F)));
|
||||
}
|
||||
|
||||
return((EXTI_Trigger_TypeDef)portsensitivity);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Group2 EXTI Interrupt status management functions
|
||||
* @brief EXTI Interrupt status management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
EXTI Interrupt status management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Gets the external interrupt status.
|
||||
* @param EXTI_IT : Specifies the interrupt to read.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg EXTI_IT_Pin0: GPIO Pin 0
|
||||
* @arg EXTI_IT_Pin1: GPIO Pin 1
|
||||
* @arg EXTI_IT_Pin2: GPIO Pin 2
|
||||
* @arg EXTI_IT_Pin3: GPIO Pin 3
|
||||
* @arg EXTI_IT_Pin4: GPIO Pin 4
|
||||
* @arg EXTI_IT_Pin5: GPIO Pin 5
|
||||
* @arg EXTI_IT_Pin6: GPIO Pin 6
|
||||
* @arg EXTI_IT_Pin7: GPIO Pin 7
|
||||
* @arg EXTI_IT_PortB: GPIO Port B
|
||||
* @arg EXTI_IT_PortD: GPIO Port D
|
||||
* @arg EXTI_IT_PortE: GPIO Port E
|
||||
* @arg EXTI_IT_PortF: GPIO Port F
|
||||
* @arg EXTI_IT_PortG: GPIO Port G
|
||||
* @arg EXTI_IT_PortH: GPIO Port H
|
||||
* @retval The status of the specified interrupt.
|
||||
* This parameter can be a SET or RESET
|
||||
*/
|
||||
ITStatus EXTI_GetITStatus(EXTI_IT_TypeDef EXTI_IT)
|
||||
{
|
||||
ITStatus status = RESET;
|
||||
/* Check function parameters */
|
||||
assert_param(IS_EXTI_ITPENDINGBIT(EXTI_IT));
|
||||
|
||||
if (((uint16_t)EXTI_IT & (uint16_t)0xFF00) == 0x0100)
|
||||
{
|
||||
status = (ITStatus)(EXTI->SR2 & (uint8_t)((uint16_t)EXTI_IT & (uint16_t)0x00FF));
|
||||
}
|
||||
else
|
||||
{
|
||||
status = (ITStatus)(EXTI->SR1 & ((uint8_t)((uint16_t)EXTI_IT & (uint16_t)0x00FF)));
|
||||
}
|
||||
return((ITStatus)status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the specified interrupt pending bit
|
||||
* @param EXTI_IT : Specifies the interrupt to clear
|
||||
* This parameter can be one of the following values:
|
||||
* @arg EXTI_IT_Pin0: GPIO Pin 0
|
||||
* @arg EXTI_IT_Pin1: GPIO Pin 1
|
||||
* @arg EXTI_IT_Pin2: GPIO Pin 2
|
||||
* @arg EXTI_IT_Pin3: GPIO Pin 3
|
||||
* @arg EXTI_IT_Pin4: GPIO Pin 4
|
||||
* @arg EXTI_IT_Pin5: GPIO Pin 5
|
||||
* @arg EXTI_IT_Pin6: GPIO Pin 6
|
||||
* @arg EXTI_IT_Pin7: GPIO Pin 7
|
||||
* @arg EXTI_IT_PortB: GPIO Port B
|
||||
* @arg EXTI_IT_PortD: GPIO Port D
|
||||
* @arg EXTI_IT_PortE: GPIO Port E
|
||||
* @arg EXTI_IT_PortF: GPIO Port F
|
||||
* @arg EXTI_IT_PortG: GPIO Port G
|
||||
* @arg EXTI_IT_PortH: GPIO Port H
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearITPendingBit(EXTI_IT_TypeDef EXTI_IT)
|
||||
{
|
||||
uint16_t tempvalue = 0;
|
||||
|
||||
/* Check function parameters */
|
||||
assert_param(IS_EXTI_ITPENDINGBIT(EXTI_IT));
|
||||
|
||||
tempvalue = ((uint16_t)EXTI_IT & (uint16_t)0xFF00);
|
||||
|
||||
if ( tempvalue == 0x0100)
|
||||
{
|
||||
EXTI->SR2 = (uint8_t)((uint16_t)EXTI_IT & (uint16_t)0x00FF);
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->SR1 = (uint8_t) (EXTI_IT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
1045
firmware/inc/stm8l151x/src/stm8l15x_flash.c
Normal file
1045
firmware/inc/stm8l151x/src/stm8l15x_flash.c
Normal file
File diff suppressed because it is too large
Load Diff
410
firmware/inc/stm8l151x/src/stm8l15x_gpio.c
Normal file
410
firmware/inc/stm8l151x/src/stm8l15x_gpio.c
Normal file
@@ -0,0 +1,410 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the GPIO peripheral:
|
||||
* - Initialization and Configuration
|
||||
* - GPIO Read and Write
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* 1. Configure the GPIO pin(s) using GPIO_Init()
|
||||
* Two main configuration are available for each pin:
|
||||
* - Input: Floating
|
||||
* Pull-up.
|
||||
* In Input mode, external interrupt can be enabled or disabled
|
||||
* - Output: Push-Pull
|
||||
* Open Drain.
|
||||
* In output mode, the GPIO pin speed is configurable:
|
||||
* Slow (2 MHz) or Fast (10MHz).
|
||||
*
|
||||
* 2. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
|
||||
*
|
||||
* 3. To set/reset GPIO pins sharing the same GPIO port use
|
||||
* GPIO_SetBits() / GPIO_ResetBits()
|
||||
*
|
||||
* 4. To enable external interrupt, the GPIO pin must be configured
|
||||
* in input mode with interrupt enabled. Interrupt sensitivity
|
||||
* (rising, falling...) is configurable using
|
||||
* EXTI_SetPinSensitivity() in the EXTI peripheral driver "stm8l15x_exti.c"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_gpio.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CLK
|
||||
* @brief CLK driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup GPIO_Group1 Initialization and Configuration
|
||||
* @brief Initialization and Configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Initialization and Configuration
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx: Select the GPIO peripheral number (x = A to I).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
GPIOx->CR2 = GPIO_CR2_RESET_VALUE; /* Reset Control Register 2 */
|
||||
GPIOx->ODR = GPIO_ODR_RESET_VALUE; /* Reset Output Data Register */
|
||||
GPIOx->DDR = GPIO_DDR_RESET_VALUE; /* Reset Data Direction Register */
|
||||
GPIOx->CR1 = GPIO_CR1_RESET_VALUE; /* Reset Control Register 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx according to the specified parameters.
|
||||
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
|
||||
* @param GPIO_Pin : This parameter contains the pin number
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_Pin_0: Pin 0
|
||||
* @arg GPIO_Pin_1: Pin 1
|
||||
* @arg GPIO_Pin_2: Pin 2
|
||||
* @arg GPIO_Pin_3: Pin 3
|
||||
* @arg GPIO_Pin_4: Pin 4
|
||||
* @arg GPIO_Pin_5: Pin 5
|
||||
* @arg GPIO_Pin_6: Pin 6
|
||||
* @arg GPIO_Pin_7: Pin 7
|
||||
* @param GPIO_Mode : This parameter can be a value of the
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_Mode_In_FL_No_IT: Input floating, no external interrupt
|
||||
* @arg GPIO_Mode_In_PU_No_IT: Input pull-up, no external interrupt
|
||||
* @arg GPIO_Mode_In_FL_IT: Input pull-up, external interrupt
|
||||
* @arg GPIO_Mode_Out_OD_Low_Fast: Output open-drain, low level, 10MHz
|
||||
* @arg GPIO_Mode_Out_PP_Low_Fast: Output push-pull, low level, 10MHz
|
||||
* @arg GPIO_Mode_Out_OD_Low_Slow: Output open-drain, low level, 2MHz
|
||||
* @arg GPIO_Mode_Out_PP_Low_Slow: Output push-pull, low level, 2MHz
|
||||
* @arg GPIO_Mode_Out_OD_HiZ_Fast: Output open-drain, high-impedance level, 10MHz
|
||||
* @arg GPIO_Mode_Out_PP_High_Fast: Output push-pull, high level, 10MHz
|
||||
* @arg GPIO_Mode_Out_OD_HiZ_Slow: Output open-drain, high-impedance level, 2MHz
|
||||
* @arg GPIO_Mode_Out_PP_High_Slow: Output push-pull, high level, 2MHz
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, GPIO_Mode_TypeDef GPIO_Mode)
|
||||
{
|
||||
/*----------------------*/
|
||||
/* Check the parameters */
|
||||
/*----------------------*/
|
||||
|
||||
assert_param(IS_GPIO_MODE(GPIO_Mode));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Reset corresponding bit to GPIO_Pin in CR2 register */
|
||||
GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
|
||||
|
||||
/*-----------------------------*/
|
||||
/* Input/Output mode selection */
|
||||
/*-----------------------------*/
|
||||
|
||||
if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x80) != (uint8_t)0x00) /* Output mode */
|
||||
{
|
||||
if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x10) != (uint8_t)0x00) /* High level */
|
||||
{
|
||||
GPIOx->ODR |= GPIO_Pin;
|
||||
} else /* Low level */
|
||||
{
|
||||
GPIOx->ODR &= (uint8_t)(~(GPIO_Pin));
|
||||
}
|
||||
/* Set Output mode */
|
||||
GPIOx->DDR |= GPIO_Pin;
|
||||
} else /* Input mode */
|
||||
{
|
||||
/* Set Input mode */
|
||||
GPIOx->DDR &= (uint8_t)(~(GPIO_Pin));
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Pull-Up/Float (Input) or Push-Pull/Open-Drain (Output) modes selection */
|
||||
/*------------------------------------------------------------------------*/
|
||||
|
||||
if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x40) != (uint8_t)0x00) /* Pull-Up or Push-Pull */
|
||||
{
|
||||
GPIOx->CR1 |= GPIO_Pin;
|
||||
} else /* Float or Open-Drain */
|
||||
{
|
||||
GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------*/
|
||||
/* Interrupt (Input) or Slope (Output) modes selection */
|
||||
/*-----------------------------------------------------*/
|
||||
|
||||
if ((((uint8_t)(GPIO_Mode)) & (uint8_t)0x20) != (uint8_t)0x00) /* Interrupt or Slow slope */
|
||||
{
|
||||
GPIOx->CR2 |= GPIO_Pin;
|
||||
} else /* No external interrupt or No slope control */
|
||||
{
|
||||
GPIOx->CR2 &= (uint8_t)(~(GPIO_Pin));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the external pull-up on GPIOx pins.
|
||||
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
|
||||
* @param GPIO_Pin : Specifies the pin number
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_Pin_0: Pin 0
|
||||
* @arg GPIO_Pin_1: Pin 1
|
||||
* @arg GPIO_Pin_2: Pin 2
|
||||
* @arg GPIO_Pin_3: Pin 3
|
||||
* @arg GPIO_Pin_4: Pin 4
|
||||
* @arg GPIO_Pin_5: Pin 5
|
||||
* @arg GPIO_Pin_6: Pin 6
|
||||
* @arg GPIO_Pin_7: Pin 7
|
||||
* @param NewState : The new state of the pull up pin.
|
||||
* Can be ENABLE or DISABLE
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ExternalPullUpConfig(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE) /* External Pull-Up Set*/
|
||||
{
|
||||
GPIOx->CR1 |= GPIO_Pin;
|
||||
} else /* External Pull-Up Reset*/
|
||||
{
|
||||
GPIOx->CR1 &= (uint8_t)(~(GPIO_Pin));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group2 GPIO Read and Write
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
GPIO Read and Write
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @note The port must be configured in output mode.
|
||||
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
|
||||
* @param GPIO_PortVal : Specifies the value to be written to the port output
|
||||
* data register.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint8_t GPIO_PortVal)
|
||||
{
|
||||
GPIOx->ODR = GPIO_PortVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
|
||||
* @param GPIO_Pin: Specifies the port bit to be written.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_Pin_0: Pin 0
|
||||
* @arg GPIO_Pin_1: Pin 1
|
||||
* @arg GPIO_Pin_2: Pin 2
|
||||
* @arg GPIO_Pin_3: Pin 3
|
||||
* @arg GPIO_Pin_4: Pin 4
|
||||
* @arg GPIO_Pin_5: Pin 5
|
||||
* @arg GPIO_Pin_6: Pin 6
|
||||
* @arg GPIO_Pin_7: Pin 7
|
||||
* @param GPIO_BitVal: specifies the desired status to be written.
|
||||
* This parameter can be SET or RESET
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin, BitAction GPIO_BitVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_STATE_VALUE(GPIO_BitVal));
|
||||
|
||||
if (GPIO_BitVal != RESET)
|
||||
{
|
||||
GPIOx->ODR |= GPIO_Pin;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->ODR &= (uint8_t)(~GPIO_Pin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes high level to the specified GPIO pins.
|
||||
* @note The port must be configured in output mode.
|
||||
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
|
||||
* @param GPIO_Pin : Specifies the pins to be turned high.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_Pin_0: Pin 0
|
||||
* @arg GPIO_Pin_1: Pin 1
|
||||
* @arg GPIO_Pin_2: Pin 2
|
||||
* @arg GPIO_Pin_3: Pin 3
|
||||
* @arg GPIO_Pin_4: Pin 4
|
||||
* @arg GPIO_Pin_5: Pin 5
|
||||
* @arg GPIO_Pin_6: Pin 6
|
||||
* @arg GPIO_Pin_7: Pin 7
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
|
||||
{
|
||||
GPIOx->ODR |= GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes low level to the specified GPIO pins.
|
||||
* @note The port must be configured in output mode.
|
||||
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
|
||||
* @param GPIO_Pin : Specifies the pins to be turned low
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_Pin_0: Pin 0
|
||||
* @arg GPIO_Pin_1: Pin 1
|
||||
* @arg GPIO_Pin_2: Pin 2
|
||||
* @arg GPIO_Pin_3: Pin 3
|
||||
* @arg GPIO_Pin_4: Pin 4
|
||||
* @arg GPIO_Pin_5: Pin 5
|
||||
* @arg GPIO_Pin_6: Pin 6
|
||||
* @arg GPIO_Pin_7: Pin 7
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
|
||||
{
|
||||
GPIOx->ODR &= (uint8_t)(~GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pins.
|
||||
* @note The port must be configured in output mode.
|
||||
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
|
||||
* @param GPIO_Pin : Specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint8_t GPIO_Pin)
|
||||
{
|
||||
GPIOx->ODR ^= GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
* @note The port must be configured in input mode.
|
||||
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
|
||||
* @retval The GPIOx input data port value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
return ((uint8_t)GPIOx->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
* @note The port must be configured in input mode.
|
||||
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
|
||||
* @retval The GPIOx output data port value.
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
return ((uint8_t)GPIOx->ODR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO input data pin.
|
||||
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
|
||||
* @param GPIO_Pin : Specifies the pin number.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_Pin_0: Pin 0
|
||||
* @arg GPIO_Pin_1: Pin 1
|
||||
* @arg GPIO_Pin_2: Pin 2
|
||||
* @arg GPIO_Pin_3: Pin 3
|
||||
* @arg GPIO_Pin_4: Pin 4
|
||||
* @arg GPIO_Pin_5: Pin 5
|
||||
* @arg GPIO_Pin_6: Pin 6
|
||||
* @arg GPIO_Pin_7: Pin 7
|
||||
* @retval BitStatus : GPIO input pin status.
|
||||
*/
|
||||
BitStatus GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
|
||||
{
|
||||
return ((BitStatus)(GPIOx->IDR & (uint8_t)GPIO_Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO Output data pin.
|
||||
* @param GPIOx : Select the GPIO peripheral number (x = A to I).
|
||||
* @param GPIO_Pin : Specifies the pin number
|
||||
* @retval BitStatus : GPIO output pin status.
|
||||
*/
|
||||
BitStatus GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, GPIO_Pin_TypeDef GPIO_Pin)
|
||||
{
|
||||
return ((BitStatus)(GPIOx->ODR & (uint8_t)GPIO_Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
1369
firmware/inc/stm8l151x/src/stm8l15x_i2c.c
Normal file
1369
firmware/inc/stm8l151x/src/stm8l15x_i2c.c
Normal file
File diff suppressed because it is too large
Load Diff
199
firmware/inc/stm8l151x/src/stm8l15x_irtim.c
Normal file
199
firmware/inc/stm8l151x/src/stm8l15x_irtim.c
Normal file
@@ -0,0 +1,199 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_irtim.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to configure the IRTIM peripheral.
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* This driver provides functions to:
|
||||
* 1. Enable the IRTIM peripheral
|
||||
* 2. Enable the high sink mode on the IRTIM pin
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_irtim.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRTIM
|
||||
* @brief IRTIM driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/** @defgroup IRTIM_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRTIM_Group1 IRTIM configuration functions
|
||||
* @brief IRTIM configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
IRTIM configuration functions
|
||||
===============================================================================
|
||||
|
||||
===================================================================
|
||||
IRTIM Driver: how to use it
|
||||
===================================================================
|
||||
To generate the infrared remote control signal, perform the following steps:
|
||||
1. Use TIM2 channel 1 to generate the high frequency carrier signal
|
||||
by calling TIM2_OC1Init()
|
||||
2. Use TIM3 channel 1 to generate the modulation envelope by
|
||||
calling TIM3_OC1Init()
|
||||
3. Enable the IRTIM peripheral using IRTIM_Cmd()
|
||||
|
||||
Note1: When IRTIM peripheral is enabled, TIM2 channel 1 and TIM3 channel 1
|
||||
become inactive (no signal on output) and can be used as GPIO.
|
||||
|
||||
Note2: The high sink LED driver capability (only available on the IRTIM pin)
|
||||
can be activated using IRTIM_HighSinkODCmd() to sink the high
|
||||
current needed to directly control an infrared LED
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the IRTIM peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void IRTIM_DeInit(void)
|
||||
{
|
||||
IRTIM->CR = IRTIM_CR_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the IRTIM peripheral.
|
||||
* @param NewState : The new state of the IRTIM peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void IRTIM_Cmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* set or Reset the EN Bit */
|
||||
if (NewState == DISABLE)
|
||||
{
|
||||
IRTIM->CR &= (uint8_t)(~IRTIM_CR_EN) ;
|
||||
}
|
||||
else
|
||||
{
|
||||
IRTIM->CR |= IRTIM_CR_EN ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the High sink open drain buffer of the IRTIM peripheral.
|
||||
* @param NewState : The new state of the High sink open drain buffer.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void IRTIM_HighSinkODCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* set or Reset the EN Bit */
|
||||
if (NewState == DISABLE)
|
||||
{
|
||||
IRTIM->CR &= (uint8_t)(~IRTIM_CR_HSEN) ;
|
||||
}
|
||||
else
|
||||
{
|
||||
IRTIM->CR |= IRTIM_CR_HSEN ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRTIM_Group2 IRITM status management functions
|
||||
* @brief IRITM status management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
IRITM status management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the IRTIM device is enabled or not.
|
||||
* @param None
|
||||
* @retval state of the IRTIM device.
|
||||
*/
|
||||
|
||||
FunctionalState IRTIM_GetStatus(void)
|
||||
{
|
||||
return ((FunctionalState) (IRTIM->CR & IRTIM_CR_EN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the IRTIM High Sink Open Drain buffer is Enabled or not.
|
||||
* @param None
|
||||
* @retval state of High Sink Open Drain buffer.
|
||||
*/
|
||||
FunctionalState IRTIM_GetHighSinkODStatus(void)
|
||||
{
|
||||
return ((FunctionalState)(IRTIM->CR & IRTIM_CR_HSEN));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
396
firmware/inc/stm8l151x/src/stm8l15x_itc.c
Normal file
396
firmware/inc/stm8l151x/src/stm8l15x_itc.c
Normal file
@@ -0,0 +1,396 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_itc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionality of the Interrupt controller (ITC) peripheral:
|
||||
* - Configuration and management
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_itc.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ITC
|
||||
* @brief ITC driver modules
|
||||
* @{
|
||||
*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ITC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Utility function used to read CC register.
|
||||
* @param None
|
||||
* @retval CPU CC register value
|
||||
*/
|
||||
uint8_t ITC_GetCPUCC(void)
|
||||
{
|
||||
#ifdef _COSMIC_
|
||||
_asm("push cc");
|
||||
_asm("pop a");
|
||||
return; /* Ignore compiler warning, the returned value is in A register */
|
||||
#elif defined _RAISONANCE_ /* _RAISONANCE_ */
|
||||
return _getCC_();
|
||||
#elif defined(_SDCC_) /* SDCC patch: do same as IAR */
|
||||
__asm__("push cc");
|
||||
__asm__("pop a");
|
||||
#else /* _IAR_ */
|
||||
asm("push cc");
|
||||
asm("pop a"); /* Ignore compiler warning, the returned value is in A register */
|
||||
#endif /* _COSMIC_*/
|
||||
}
|
||||
|
||||
/** @defgroup ITC_Group1 ITC configuration and management functions
|
||||
* @brief ITC configuration and management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
ITC configuration and management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the ITC registers to their default reset value.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void ITC_DeInit(void)
|
||||
{
|
||||
ITC->ISPR1 = ITC_SPRX_RESET_VALUE;
|
||||
ITC->ISPR2 = ITC_SPRX_RESET_VALUE;
|
||||
ITC->ISPR3 = ITC_SPRX_RESET_VALUE;
|
||||
ITC->ISPR4 = ITC_SPRX_RESET_VALUE;
|
||||
ITC->ISPR5 = ITC_SPRX_RESET_VALUE;
|
||||
ITC->ISPR6 = ITC_SPRX_RESET_VALUE;
|
||||
ITC->ISPR7 = ITC_SPRX_RESET_VALUE;
|
||||
ITC->ISPR8 = ITC_SPRX_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the interrupt software priority bits (I1, I0) value from CPU CC register.
|
||||
* @param None
|
||||
* @retval The interrupt software priority bits value.
|
||||
*/
|
||||
uint8_t ITC_GetSoftIntStatus(void)
|
||||
{
|
||||
return ((uint8_t)(ITC_GetCPUCC() & CPU_SOFT_INT_DISABLED));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the software priority of the specified interrupt source.
|
||||
* @param IRQn : Specifies the peripheral interrupt source.
|
||||
* @retval Specifies the software priority of the interrupt source.
|
||||
*/
|
||||
ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(IRQn_TypeDef IRQn)
|
||||
{
|
||||
uint8_t Value = 0;
|
||||
uint8_t Mask = 0;
|
||||
|
||||
/* Check function parameters */
|
||||
assert_param(IS_ITC_IRQ(IRQn));
|
||||
|
||||
/* Define the mask corresponding to the bits position in the SPR register */
|
||||
Mask = (uint8_t)(0x03U << ((IRQn % 4U) * 2U));
|
||||
|
||||
switch (IRQn)
|
||||
{
|
||||
case FLASH_IRQn:
|
||||
case DMA1_CHANNEL0_1_IRQn:
|
||||
case DMA1_CHANNEL2_3_IRQn:
|
||||
Value = (uint8_t)(ITC->ISPR1 & Mask); /* Read software priority */
|
||||
break;
|
||||
|
||||
case EXTIE_F_PVD_IRQn:
|
||||
#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
|
||||
case RTC_IRQn:
|
||||
case EXTIB_IRQn:
|
||||
case EXTID_IRQn:
|
||||
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
|
||||
case RTC_CSSLSE_IRQn:
|
||||
case EXTIB_IRQn:
|
||||
case EXTID_IRQn:
|
||||
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
|
||||
case RTC_CSSLSE_IRQn:
|
||||
case EXTIB_G_IRQn:
|
||||
case EXTID_H_IRQn:
|
||||
#endif /* STM8L15X_MD */
|
||||
Value = (uint8_t)(ITC->ISPR2 & Mask); /* Read software priority */
|
||||
break;
|
||||
|
||||
case EXTI0_IRQn:
|
||||
case EXTI1_IRQn:
|
||||
case EXTI2_IRQn:
|
||||
case EXTI3_IRQn:
|
||||
Value = (uint8_t)(ITC->ISPR3 & Mask); /* Read software priority */
|
||||
break;
|
||||
|
||||
case EXTI4_IRQn:
|
||||
case EXTI5_IRQn:
|
||||
case EXTI6_IRQn:
|
||||
case EXTI7_IRQn:
|
||||
Value = (uint8_t)(ITC->ISPR4 & Mask); /* Read software priority */
|
||||
break;
|
||||
|
||||
#if defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
|
||||
case SWITCH_CSS_IRQn:
|
||||
#else
|
||||
case SWITCH_CSS_BREAK_DAC_IRQn:
|
||||
#endif /* STM8L15X_LD */
|
||||
case ADC1_COMP_IRQn:
|
||||
#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
|
||||
case LCD_IRQn:
|
||||
case TIM2_UPD_OVF_TRG_BRK_IRQn:
|
||||
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
|
||||
case TIM2_UPD_OVF_TRG_BRK_IRQn:
|
||||
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
|
||||
case LCD_AES_IRQn:
|
||||
case TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn:
|
||||
#endif /* STM8L15X_MD */
|
||||
Value = (uint8_t)(ITC->ISPR5 & Mask); /* Read software priority */
|
||||
break;
|
||||
|
||||
#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
|
||||
case TIM1_UPD_OVF_TRG_IRQn:
|
||||
#endif /* STM8L15X_LD */
|
||||
#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
|
||||
defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
|
||||
case TIM2_CC_IRQn:
|
||||
case TIM3_UPD_OVF_TRG_BRK_IRQn :
|
||||
case TIM3_CC_IRQn:
|
||||
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
|
||||
case TIM2_CC_USART2_RX_IRQn:
|
||||
case TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn :
|
||||
case TIM3_CC_USART3_RX_IRQn:
|
||||
#endif /* STM8L15X_MD */
|
||||
Value = (uint8_t)(ITC->ISPR6 & Mask); /* Read software priority */
|
||||
break;
|
||||
|
||||
#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
|
||||
case TIM1_CC_IRQn:
|
||||
#endif /* STM8L15X_LD */
|
||||
case TIM4_UPD_OVF_TRG_IRQn:
|
||||
case SPI1_IRQn:
|
||||
#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
|
||||
defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
|
||||
case USART1_TX_IRQn:
|
||||
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
|
||||
case USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn:
|
||||
#endif /* STM8L15X_MD || STM8L15X_LD */
|
||||
Value = (uint8_t)(ITC->ISPR7 & Mask); /* Read software priority */
|
||||
break;
|
||||
|
||||
#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
|
||||
defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
|
||||
case USART1_RX_IRQn:
|
||||
case I2C1_IRQn:
|
||||
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
|
||||
case USART1_RX_TIM5_CC_IRQn:
|
||||
case I2C1_SPI2_IRQn:
|
||||
#endif /* STM8L15X_MD || STM8L15X_LD*/
|
||||
Value = (uint8_t)(ITC->ISPR8 & Mask); /* Read software priority */
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
Value >>= (uint8_t)((IRQn % 4u) * 2u);
|
||||
|
||||
return((ITC_PriorityLevel_TypeDef)Value);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the software priority of the specified interrupt source.
|
||||
* @note The modification of the software priority is only possible when
|
||||
* the interrupts are disabled.
|
||||
* @note The normal behavior is to disable the interrupt before calling
|
||||
* this function, and re-enable it after.
|
||||
* @note The priority level 0 cannot be set (see product specification
|
||||
* for more details).
|
||||
* @param IRQn : Specifies the peripheral interrupt source.
|
||||
* @param ITC_PriorityLevel : Specifies the software priority value to set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg ITC_PriorityLevel_0: Software priority level 0 (cannot be written)
|
||||
* @arg ITC_PriorityLevel_1: Software priority level 1
|
||||
* @arg ITC_PriorityLevel_2: Software priority level 2
|
||||
* @arg ITC_PriorityLevel_3: Software priority level 3
|
||||
* @retval None
|
||||
*/
|
||||
void ITC_SetSoftwarePriority(IRQn_TypeDef IRQn, ITC_PriorityLevel_TypeDef ITC_PriorityLevel)
|
||||
{
|
||||
uint8_t Mask = 0;
|
||||
uint8_t NewPriority = 0;
|
||||
|
||||
/* Check function parameters */
|
||||
assert_param(IS_ITC_IRQ(IRQn));
|
||||
assert_param(IS_ITC_PRIORITY(ITC_PriorityLevel));
|
||||
|
||||
/* Check if interrupts are disabled */
|
||||
assert_param(IS_ITC_INTERRUPTS_DISABLED);
|
||||
|
||||
/* Define the mask corresponding to the bits position in the SPR register */
|
||||
/* The mask is reversed in order to clear the 2 bits after more easily */
|
||||
Mask = (uint8_t)(~(uint8_t)(0x03U << ((IRQn % 4U) * 2U)));
|
||||
/* Define the new priority to write */
|
||||
NewPriority = (uint8_t)((uint8_t)(ITC_PriorityLevel) << ((IRQn % 4U) * 2U));
|
||||
|
||||
switch (IRQn)
|
||||
{
|
||||
case FLASH_IRQn:
|
||||
case DMA1_CHANNEL0_1_IRQn:
|
||||
case DMA1_CHANNEL2_3_IRQn:
|
||||
ITC->ISPR1 &= Mask;
|
||||
ITC->ISPR1 |= NewPriority;
|
||||
break;
|
||||
|
||||
case EXTIE_F_PVD_IRQn:
|
||||
#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
|
||||
case RTC_IRQn:
|
||||
case EXTIB_IRQn:
|
||||
case EXTID_IRQn:
|
||||
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
|
||||
case RTC_CSSLSE_IRQn:
|
||||
case EXTIB_IRQn:
|
||||
case EXTID_IRQn:
|
||||
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
|
||||
case RTC_CSSLSE_IRQn:
|
||||
case EXTIB_G_IRQn:
|
||||
case EXTID_H_IRQn:
|
||||
#endif /* STM8L15X_MD */
|
||||
ITC->ISPR2 &= Mask;
|
||||
ITC->ISPR2 |= NewPriority;
|
||||
break;
|
||||
|
||||
case EXTI0_IRQn:
|
||||
case EXTI1_IRQn:
|
||||
case EXTI2_IRQn:
|
||||
case EXTI3_IRQn:
|
||||
ITC->ISPR3 &= Mask;
|
||||
ITC->ISPR3 |= NewPriority;
|
||||
break;
|
||||
|
||||
case EXTI4_IRQn:
|
||||
case EXTI5_IRQn:
|
||||
case EXTI6_IRQn:
|
||||
case EXTI7_IRQn:
|
||||
ITC->ISPR4 &= Mask;
|
||||
ITC->ISPR4 |= NewPriority;
|
||||
break;
|
||||
#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
|
||||
case SWITCH_CSS_BREAK_DAC_IRQn:
|
||||
#else
|
||||
case SWITCH_CSS_IRQn:
|
||||
#endif /* STM8L15X_LD */
|
||||
case ADC1_COMP_IRQn:
|
||||
#if defined (STM8L15X_MD) || defined (STM8L05X_MD_VL) || defined (STM8AL31_L_MD)
|
||||
case LCD_IRQn:
|
||||
case TIM2_UPD_OVF_TRG_BRK_IRQn:
|
||||
#elif defined (STM8L15X_LD) || defined (STM8L05X_LD_VL)
|
||||
case TIM2_UPD_OVF_TRG_BRK_IRQn:
|
||||
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
|
||||
case LCD_AES_IRQn:
|
||||
case TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn:
|
||||
#endif /* STM8L15X_MD */
|
||||
ITC->ISPR5 &= Mask;
|
||||
ITC->ISPR5 |= NewPriority;
|
||||
break;
|
||||
#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
|
||||
case TIM1_UPD_OVF_TRG_IRQn:
|
||||
#endif /* STM8L15X_LD */
|
||||
#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
|
||||
defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
|
||||
case TIM2_CC_IRQn:
|
||||
case TIM3_UPD_OVF_TRG_BRK_IRQn :
|
||||
case TIM3_CC_IRQn:
|
||||
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
|
||||
case TIM2_CC_USART2_RX_IRQn:
|
||||
case TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn :
|
||||
case TIM3_CC_USART3_RX_IRQn:
|
||||
#endif /* STM8L15X_MD */
|
||||
ITC->ISPR6 &= Mask;
|
||||
ITC->ISPR6 |= NewPriority;
|
||||
break;
|
||||
|
||||
#if !defined (STM8L15X_LD) && !defined (STM8L05X_LD_VL)
|
||||
case TIM1_CC_IRQn:
|
||||
#endif /* STM8L15X_LD */
|
||||
case TIM4_UPD_OVF_TRG_IRQn:
|
||||
case SPI1_IRQn:
|
||||
#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
|
||||
defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
|
||||
case USART1_TX_IRQn:
|
||||
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
|
||||
case USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn:
|
||||
#endif /* STM8L15X_MD */
|
||||
ITC->ISPR7 &= Mask;
|
||||
ITC->ISPR7 |= NewPriority;
|
||||
break;
|
||||
|
||||
#if defined (STM8L15X_MD) || defined (STM8L15X_LD) || defined (STM8L05X_MD_VL) ||\
|
||||
defined (STM8AL31_L_MD) || defined (STM8L05X_LD_VL)
|
||||
case USART1_RX_IRQn:
|
||||
case I2C1_IRQn:
|
||||
#elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) || defined (STM8L05X_HD_VL)
|
||||
case USART1_RX_TIM5_CC_IRQn:
|
||||
case I2C1_SPI2_IRQn:
|
||||
#endif /* STM8L15X_MD */
|
||||
ITC->ISPR8 &= Mask;
|
||||
ITC->ISPR8 |= NewPriority;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
220
firmware/inc/stm8l151x/src/stm8l15x_iwdg.c
Normal file
220
firmware/inc/stm8l151x/src/stm8l15x_iwdg.c
Normal file
@@ -0,0 +1,220 @@
|
||||
/**
|
||||
********************************************************************************
|
||||
* @file stm8l15x_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent watchdog (IWDG) peripheral:
|
||||
* - Prescaler and Counter configuration
|
||||
* - IWDG activation
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* IWDG features
|
||||
* ===================================================================
|
||||
*
|
||||
* The IWDG can be started by either software or hardware (configurable
|
||||
* through option byte).
|
||||
*
|
||||
* The IWDG is clocked by its own dedicated low-speed clock (LSI) and
|
||||
* thus stays active even if the main clock fails.
|
||||
* Once the IWDG is started, the LSI is forced ON and cannot be disabled
|
||||
* (LSI cannot be disabled too), and the counter starts counting down from
|
||||
* the reset value of 0xFF. When it reaches the end of count value (0x00)
|
||||
* a system reset is generated.
|
||||
* The IWDG counter should be reloaded at regular intervals to prevent
|
||||
* an MCU reset.
|
||||
*
|
||||
* The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
* in Halt and Active Halt mode depending on the configuration of the IWDG_HALT
|
||||
* option byte. (IWDG reset can wake-up from Halt).
|
||||
*
|
||||
* IWDGF flag in RST_SR register can be used to inform when a IWDG
|
||||
* reset occurs.
|
||||
*
|
||||
* Min-max timeout value @38KHz (LSI): 0.10 ms / ~1.724s
|
||||
* The IWDG timeout may vary due to LSI frequency dispersion. STM8L15x
|
||||
* devices provide the capability to measure the LSI frequency (LSI clock
|
||||
* connected internally to TIM2 CH1 input capture). The measured value
|
||||
* can be used to have an IWDG timeout with an acceptable accuracy.
|
||||
* For more information, please refer to the STM8L15x Reference manual
|
||||
*
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* 1. Enable write access to IWDG_PR and IWDG_RLR registers using
|
||||
* IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
|
||||
*
|
||||
* 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function
|
||||
*
|
||||
* 3. Configure the IWDG counter value using IWDG_SetReload() function.
|
||||
* This value will be loaded in the IWDG counter each time the counter
|
||||
* is reloaded, then the IWDG will start counting down from this value.
|
||||
*
|
||||
* 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used
|
||||
* in software mode (no need to enable the LSI, it will be enabled
|
||||
* by hardware)
|
||||
*
|
||||
* 5. Then the application program must reload the IWDG counter at regular
|
||||
* intervals during normal operation to prevent an MCU reset, using
|
||||
* IWDG_ReloadCounter() function.
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_iwdg.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG
|
||||
* @brief IWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
|
||||
* @brief Prescaler and Counter configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Prescaler and Counter configuration functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
|
||||
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_WRITE_ACCESS_MODE(IWDG_WriteAccess));
|
||||
IWDG->KR = IWDG_WriteAccess; /* Write Access */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Prescaler value.
|
||||
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
|
||||
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
|
||||
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
|
||||
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
|
||||
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
|
||||
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
|
||||
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_PRESCALER_VALUE(IWDG_Prescaler));
|
||||
IWDG->PR = IWDG_Prescaler;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Reload value.
|
||||
* @note Write access should be enabled
|
||||
* @param IWDG_Reload : Reload register value.
|
||||
* This parameter must be a number between 0 and 0xFF.
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetReload(uint8_t IWDG_Reload)
|
||||
{
|
||||
IWDG->RLR = IWDG_Reload;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reloads IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_ReloadCounter(void)
|
||||
{
|
||||
IWDG->KR = IWDG_KEY_REFRESH;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group2 IWDG activation function
|
||||
* @brief IWDG activation function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
IWDG activation function
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_Enable(void)
|
||||
{
|
||||
IWDG->KR = IWDG_KEY_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
632
firmware/inc/stm8l151x/src/stm8l15x_lcd.c
Normal file
632
firmware/inc/stm8l151x/src/stm8l15x_lcd.c
Normal file
@@ -0,0 +1,632 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_lcd.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the LCD controller (LCD) peripheral:
|
||||
* - Initialization and configuration
|
||||
* - LCD RAM memory write
|
||||
* - Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* LCD Clock
|
||||
* ===================================================================
|
||||
* LCD has tow clock sources:
|
||||
* - RTCCLK divided by 2 used to generate LCD frame rate
|
||||
* - LCDCLK to used for LCD registers read/write access
|
||||
*
|
||||
* To configure the RTCCLK/LCDCLK, proceed as follows:
|
||||
* - Enable RTC clock using CLK_PeripheralClockConfig(CLK_Peripheral_RTC, ENABLE)
|
||||
* function
|
||||
* - Enable LCD clock using CLK_PeripheralClockConfig(CLK_Peripheral_LCD, ENABLE)
|
||||
* function
|
||||
* - Select the RTC clock source using the CLK_RTCClockConfig() function.
|
||||
*
|
||||
* ===================================================================
|
||||
* LCD and low power modes
|
||||
* ===================================================================
|
||||
* The LCD remains active during Active-halt, Wait, Low power run and
|
||||
* Low power wait modes unless disabled
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* 1. Enable RTC clock using CLK_PeripheralClockConfig(CLK_Peripheral_RTC, ENABLE) function
|
||||
*
|
||||
* 2. Enable LCD clock using CLK_PeripheralClockConfig(CLK_Peripheral_LCD, ENABLE) function
|
||||
*
|
||||
* 3. Select the RTC clock source using the CLK_RTCClockConfig() function.
|
||||
*
|
||||
* 4. Configure the LCD prescaler, divider, duty, bias and voltage source
|
||||
* using LCD_Init() function
|
||||
*
|
||||
* 5. Call the LCD_PortMaskConfig() function to assign the unused SEGx
|
||||
* (segment) and COMx (common) pins as standard general purpose IOs
|
||||
*
|
||||
* 6. Optionally you can enable/configure:
|
||||
* - LCD High Drive using the LCD_HighDriveCmd() function
|
||||
* - LCD Pulse ON Duration using the LCD_PulseOnDurationConfig() function
|
||||
* - LCD Dead Time using the LCD_DeadTimeConfig() function
|
||||
* - The LCD Blink mode and frequency using the LCD_BlinkConfig() function
|
||||
* - The LCD Contrast using the LCD_ContrastConfig() function
|
||||
*
|
||||
* 7. Call the LCD_Cmd() to enable the LCD controller
|
||||
*
|
||||
* 8. Write to the LCD RAM memory using the LCD_WriteRAM() function.
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_lcd.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LCD
|
||||
* @brief LCD driver modules
|
||||
* @{
|
||||
*/
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup LCD_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Initialization and Configuration functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the LCD Controller registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_DeInit(void)
|
||||
{
|
||||
uint8_t counter = 0;
|
||||
|
||||
LCD->CR1 = LCD_CR1_RESET_VALUE;
|
||||
LCD->CR2 = LCD_CR2_RESET_VALUE;
|
||||
LCD->CR3 = LCD_CR3_RESET_VALUE;
|
||||
LCD->FRQ = LCD_FRQ_RESET_VALUE;
|
||||
|
||||
for (counter = 0;counter < 0x05; counter++)
|
||||
{
|
||||
LCD->PM[counter] = LCD_PM_RESET_VALUE;
|
||||
}
|
||||
|
||||
for (counter = 0;counter < 0x16; counter++)
|
||||
{
|
||||
LCD->RAM[counter] = LCD_RAM_RESET_VALUE;
|
||||
}
|
||||
|
||||
LCD->CR4 = LCD_CR4_RESET_VALUE;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the LCD according to the specified parameters.
|
||||
* @param LCD_CLKPrescalerDiv : LCD clock prescaler
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_Prescaler_1: CLKprescaler = ClKinput
|
||||
* @arg LCD_Prescaler_2: CLKprescaler = ClKinput/2
|
||||
* @arg LCD_Prescaler_4: CLKprescaler = ClKinput/4
|
||||
* @arg LCD_Prescaler_8: CLKprescaler = ClKinput/8
|
||||
* @arg LCD_Prescaler_16: CLKprescaler = ClKinput/16
|
||||
* @arg LCD_Prescaler_32: CLKprescaler = ClKinput/32
|
||||
* @arg LCD_Prescaler_64: CLKprescaler = ClKinput/64
|
||||
* @arg LCD_Prescaler_128: CLKprescaler = ClKinput/128
|
||||
* @arg LCD_Prescaler_256: CLKprescaler = ClKinput/256
|
||||
* @arg LCD_Prescaler_512: CLKprescaler = ClKinput/512
|
||||
* @arg LCD_Prescaler_1024: CLKprescaler = ClKinput/1024
|
||||
* @arg LCD_Prescaler_2048: CLKprescaler = ClKinput/2048
|
||||
* @arg LCD_Prescaler_4096: CLKprescaler = ClKinput/4096
|
||||
* @arg LCD_Prescaler_8192: CLKprescaler = ClKinput/8192
|
||||
* @arg LCD_Prescaler_16384: CLKprescaler = ClKinput/16384
|
||||
* @arg LCD_Prescaler_32768: CLKprescaler = ClKinput/32768
|
||||
* @param LCD_Divider : LCD clock divider
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_Divider_16: LCD frequency = CLKprescaler/16
|
||||
* @arg LCD_Divider_17: LCD frequency = CLKprescaler/17
|
||||
* @arg LCD_Divider_18: LCD frequency = CLKprescaler/18
|
||||
* @arg LCD_Divider_19: LCD frequency = CLKprescaler/19
|
||||
* @arg LCD_Divider_20: LCD frequency = CLKprescaler/20
|
||||
* @arg LCD_Divider_21: LCD frequency = CLKprescaler/21
|
||||
* @arg LCD_Divider_22: LCD frequency = CLKprescaler/22
|
||||
* @arg LCD_Divider_23: LCD frequency = CLKprescaler/23
|
||||
* @arg LCD_Divider_24: LCD frequency = CLKprescaler/24
|
||||
* @arg LCD_Divider_25: LCD frequency = CLKprescaler/25
|
||||
* @arg LCD_Divider_26: LCD frequency = CLKprescaler/26
|
||||
* @arg LCD_Divider_27: LCD frequency = CLKprescaler/27
|
||||
* @arg LCD_Divider_28: LCD frequency = CLKprescaler/28
|
||||
* @arg LCD_Divider_29: LCD frequency = CLKprescaler/29
|
||||
* @arg LCD_Divider_30: LCD frequency = CLKprescaler/30
|
||||
* @arg LCD_Divider_31: LCD frequency = CLKprescaler/31
|
||||
* @param LCD_Duty : LCD duty
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_Duty_Static: Static duty
|
||||
* @arg LCD_Duty_1_2: 1/2 duty
|
||||
* @arg LCD_Duty_1_3: 1/3 duty
|
||||
* @arg LCD_Duty_1_4: 1/4 duty
|
||||
* @arg LCD_Duty_1_8: 1/8 duty
|
||||
* @param LCD_Bias : LCD bias
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_Bias_1_4: 1/4 bias
|
||||
* @arg LCD_Bias_1_3: 1/3 bias
|
||||
* @arg LCD_Bias_1_2: 1/2 bias
|
||||
* @param LCD_VoltageSource : LCD voltage source
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_VoltageSource_Internal: Internal voltage source
|
||||
* @arg LCD_VoltageSource_External: External voltage source
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_Init(LCD_Prescaler_TypeDef LCD_Prescaler, LCD_Divider_TypeDef LCD_Divider,
|
||||
LCD_Duty_TypeDef LCD_Duty, LCD_Bias_TypeDef LCD_Bias,
|
||||
LCD_VoltageSource_TypeDef LCD_VoltageSource)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_LCD_CLOCK_PRESCALER(LCD_Prescaler));
|
||||
assert_param(IS_LCD_CLOCK_DIVIDER(LCD_Divider));
|
||||
assert_param(IS_LCD_DUTY(LCD_Duty));
|
||||
assert_param(IS_LCD_BIAS(LCD_Bias));
|
||||
assert_param(IS_LCD_VOLTAGE_SOURCE(LCD_VoltageSource));
|
||||
|
||||
LCD->FRQ &= (uint8_t)(~LCD_FRQ_PS); /* Clear the prescaler bits */
|
||||
LCD->FRQ |= LCD_Prescaler;
|
||||
|
||||
LCD->FRQ &= (uint8_t)(~LCD_FRQ_DIV); /* Clear the divider bits */
|
||||
LCD->FRQ |= LCD_Divider;
|
||||
|
||||
/* Configure the Duty cycle */
|
||||
LCD->CR1 &= (uint8_t)(~LCD_CR1_DUTY); /* Clear the duty bits */
|
||||
LCD->CR4 &= (uint8_t)(~LCD_CR4_DUTY8); /* Clear the DUTY8 bit */
|
||||
|
||||
if (LCD_Duty == LCD_Duty_1_8)
|
||||
{
|
||||
LCD->CR4 |= (uint8_t)((uint8_t)((uint8_t)LCD_Duty & (uint8_t)0xF0) >> 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
LCD->CR1 |= (uint8_t)((uint8_t)LCD_Duty & (uint8_t)0x0F);
|
||||
}
|
||||
|
||||
/* Configure the Bias */
|
||||
LCD->CR1 &= (uint8_t)(~LCD_CR1_B2); /* Clear the B2 bit */
|
||||
LCD->CR4 &= (uint8_t)(~LCD_CR4_B4); /* Clear the B4 bit */
|
||||
|
||||
if (LCD_Bias == LCD_Bias_1_4)
|
||||
{
|
||||
LCD->CR1 |= (uint8_t)((uint8_t)LCD_Bias & (uint8_t)0x0F);
|
||||
LCD->CR4 |= (uint8_t)((uint8_t)((uint8_t)LCD_Bias & (uint8_t)0xF0) >> 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
LCD->CR1 |= (uint8_t)((uint8_t)LCD_Bias & (uint8_t)0x0F);
|
||||
}
|
||||
|
||||
LCD->CR2 &= (uint8_t)(~LCD_CR2_VSEL); /* Clear the voltage source bit */
|
||||
LCD->CR2 |= LCD_VoltageSource;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the LCD Port Mask.
|
||||
* @param LCD_PortMaskRegister: The LCD register index in the port mask matrix.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_PortMaskRegister_0: PortMask Register 0
|
||||
* @arg LCD_PortMaskRegister_1: PortMask Register 1
|
||||
* @arg LCD_PortMaskRegister_2: PortMask Register 2
|
||||
* @arg LCD_PortMaskRegister_3: PortMask Register 3
|
||||
* @arg LCD_PortMaskRegister_4: PortMask Register 4
|
||||
* @arg LCD_PortMaskRegister_5: PortMask Register 5
|
||||
* @param LCD_Mask : Value to be written
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_PortMaskConfig(LCD_PortMaskRegister_TypeDef LCD_PortMaskRegister, uint8_t LCD_Mask)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_LCD_PORT_MASK(LCD_PortMaskRegister));
|
||||
|
||||
/* Copy data bytes to Port mask register */
|
||||
LCD->PM[LCD_PortMaskRegister] = LCD_Mask;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the LCD Controller.
|
||||
* @param NewState: new state of the LCD peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_Cmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
LCD->CR3 |= LCD_CR3_LCDEN; /* Enable the LCD peripheral*/
|
||||
}
|
||||
else
|
||||
{
|
||||
LCD->CR3 &= (uint8_t)(~LCD_CR3_LCDEN); /* Disable the LCD peripheral*/
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the low resistance divider. Displays with high
|
||||
* internal resistance may need a longer drive time to achieve
|
||||
* satisfactory contrast. This function is useful in this case if some
|
||||
* additional power consumption can be tolerated.
|
||||
* @note When this mode is enabled, the PulseOn Duration (PON) have to be
|
||||
* programmed to 1/CK_PS (LCD_PulseOnDuration_1).
|
||||
* @param NewState: new state of the low resistance divider.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_HighDriveCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
LCD->CR2 |= LCD_CR2_HD; /* Permanently enable low resistance divider */
|
||||
}
|
||||
else
|
||||
{
|
||||
LCD->CR2 &= (uint8_t)(~LCD_CR2_HD); /* Permanently disable low resistance divider */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the LCD pulses on duration.
|
||||
* @param LCD_PulseOnDuration: specifies the LCD pulse on duration in terms of
|
||||
* CLKprescaler (prescaled LCD clock period) pulses.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_PulseOnDuration_0: 0 pulse
|
||||
* @arg LCD_PulseOnDuration_1: Pulse ON duration = 1/CLKprescaler
|
||||
* @arg LCD_PulseOnDuration_2: Pulse ON duration = 2/CLKprescaler
|
||||
* @arg LCD_PulseOnDuration_3: Pulse ON duration = 3/CLKprescaler
|
||||
* @arg LCD_PulseOnDuration_4: Pulse ON duration = 4/CLKprescaler
|
||||
* @arg LCD_PulseOnDuration_5: Pulse ON duration = 5/CLKprescaler
|
||||
* @arg LCD_PulseOnDuration_6: Pulse ON duration = 6/CLKprescaler
|
||||
* @arg LCD_PulseOnDuration_7: Pulse ON duration = 7/CLKprescaler
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_PulseOnDurationConfig(LCD_PulseOnDuration_TypeDef LCD_PulseOnDuration)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_LCD_PULSE_DURATION(LCD_PulseOnDuration));
|
||||
|
||||
LCD->CR2 &= (uint8_t)(~LCD_CR2_PON); /* Clear the pulses on duration bits */
|
||||
LCD->CR2 |= LCD_PulseOnDuration;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the LCD dead time.
|
||||
* @param LCD_DeadTime: specifies the LCD dead time.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_DeadTime_0: No dead Time
|
||||
* @arg LCD_DeadTime_1: One Phase between different couple of Frame
|
||||
* @arg LCD_DeadTime_2: Two Phase between different couple of Frame
|
||||
* @arg LCD_DeadTime_3: Three Phase between different couple of Frame
|
||||
* @arg LCD_DeadTime_4: Four Phase between different couple of Frame
|
||||
* @arg LCD_DeadTime_5: Five Phase between different couple of Frame
|
||||
* @arg LCD_DeadTime_6: Six Phase between different couple of Frame
|
||||
* @arg LCD_DeadTime_7: Seven Phase between different couple of Frame
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_DeadTimeConfig(LCD_DeadTime_TypeDef LCD_DeadTime)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_LCD_DEAD_TIME(LCD_DeadTime));
|
||||
|
||||
LCD->CR3 &= (uint8_t)(~LCD_CR3_DEAD); /* Clear the dead time bits */
|
||||
|
||||
LCD->CR3 |= LCD_DeadTime;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the LCD Blink mode and Blink frequency.
|
||||
* @param LCD_BlinkMode: specifies the LCD blink mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_BlinkMode_Off: Blink disabled
|
||||
* @arg LCD_BlinkMode_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
|
||||
* @arg LCD_BlinkMode_SEG0_AllCOM: Blink enabled on SEG[0], all COM (up to 8
|
||||
* pixels according to the programmed duty)
|
||||
* @arg LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM
|
||||
* (all pixels)
|
||||
* @param LCD_BlinkFrequency: specifies the LCD blink frequency.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_BlinkFrequency_Div8: The Blink frequency = fLcd/8
|
||||
* @arg LCD_BlinkFrequency_Div16: The Blink frequency = fLcd/16
|
||||
* @arg LCD_BlinkFrequency_Div32: The Blink frequency = fLcd/32
|
||||
* @arg LCD_BlinkFrequency_Div64: The Blink frequency = fLcd/64
|
||||
* @arg LCD_BlinkFrequency_Div128: The Blink frequency = fLcd/128
|
||||
* @arg LCD_BlinkFrequency_Div256: The Blink frequency = fLcd/256
|
||||
* @arg LCD_BlinkFrequency_Div512: The Blink frequency = fLcd/512
|
||||
* @arg LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_BlinkConfig(LCD_BlinkMode_TypeDef LCD_BlinkMode, LCD_BlinkFrequency_TypeDef LCD_BlinkFrequency)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_LCD_BLINK_MODE(LCD_BlinkMode));
|
||||
assert_param(IS_LCD_BLINK_FREQUENCY(LCD_BlinkFrequency));
|
||||
|
||||
LCD->CR1 &= (uint8_t)(~LCD_CR1_BLINK); /* Clear the blink mode bits */
|
||||
LCD->CR1 |= LCD_BlinkMode; /* Config the LCD Blink Mode */
|
||||
|
||||
LCD->CR1 &= (uint8_t)(~LCD_CR1_BLINKF); /* Clear the blink frequency bits */
|
||||
LCD->CR1 |= LCD_BlinkFrequency; /* Config the LCD Blink Frequency */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the LCD Contrast.
|
||||
* @param LCD_Contrast: specifies the LCD Contrast.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_Contrast_Level_0: Medium Density / High Density Maximum Voltage = 2.60V / 2.60V
|
||||
* @arg LCD_Contrast_Level_1: Medium Density / High Density Maximum Voltage = 2.70V / 2.73V
|
||||
* @arg LCD_Contrast_Level_2: Medium Density / High Density Maximum Voltage = 2.80V / 2.86V
|
||||
* @arg LCD_Contrast_Level_3: Medium Density / High Density Maximum Voltage = 2.90V / 2.99V
|
||||
* @arg LCD_Contrast_Level_4: Medium Density / High Density Maximum Voltage = 3.00V / 3.12V
|
||||
* @arg LCD_Contrast_Level_5: Medium Density / High Density Maximum Voltage = 3.10V / 3.25V
|
||||
* @arg LCD_Contrast_Level_6: Medium Density / High Density Maximum Voltage = 3.20V / 3.38V
|
||||
* @arg LCD_Contrast_Level_7: Medium Density / High Density Maximum Voltage = 3.30V / 3.51V
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_ContrastConfig(LCD_Contrast_TypeDef LCD_Contrast)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_LCD_CONTRAST(LCD_Contrast));
|
||||
|
||||
LCD->CR2 &= (uint8_t)(~LCD_CR2_CC); /* Clear the contrast bits */
|
||||
LCD->CR2 |= LCD_Contrast; /* Select the maximum voltage value Vlcd */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Group2 LCD RAM memory write functions
|
||||
* @brief LCD RAM memory write functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
LCD RAM memory write functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Writes a word in the specific LCD RAM.
|
||||
* @param LCD_RAMRegister: specifies the LCD Contrast.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_RAMRegister_0: LCD RAM Register 0
|
||||
* @arg LCD_RAMRegister_1: LCD RAM Register 1
|
||||
* @arg LCD_RAMRegister_2: LCD RAM Register 2
|
||||
* @arg LCD_RAMRegister_3: LCD RAM Register 3
|
||||
* @arg LCD_RAMRegister_4: LCD RAM Register 4
|
||||
* @arg LCD_RAMRegister_5: LCD RAM Register 5
|
||||
* @arg LCD_RAMRegister_6: LCD RAM Register 6
|
||||
* @arg LCD_RAMRegister_7: LCD RAM Register 7
|
||||
* @arg LCD_RAMRegister_8: LCD RAM Register 8
|
||||
* @arg LCD_RAMRegister_9: LCD RAM Register 9
|
||||
* @arg LCD_RAMRegister_10: LCD RAM Register 10
|
||||
* @arg LCD_RAMRegister_11: LCD RAM Register 11
|
||||
* @arg LCD_RAMRegister_12: LCD RAM Register 12
|
||||
* @arg LCD_RAMRegister_13: LCD RAM Register 13
|
||||
* @arg LCD_RAMRegister_14: LCD RAM Register 14
|
||||
* @arg LCD_RAMRegister_15: LCD RAM Register 15
|
||||
* @arg LCD_RAMRegister_15: LCD RAM Register 16
|
||||
* @arg LCD_RAMRegister_15: LCD RAM Register 17
|
||||
* @arg LCD_RAMRegister_15: LCD RAM Register 18
|
||||
* @arg LCD_RAMRegister_15: LCD RAM Register 19
|
||||
* @arg LCD_RAMRegister_15: LCD RAM Register 20
|
||||
* @arg LCD_RAMRegister_15: LCD RAM Register 21
|
||||
* @param LCD_Data: specifies LCD Data Value to be written.
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_WriteRAM(LCD_RAMRegister_TypeDef LCD_RAMRegister, uint8_t LCD_Data)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_LCD_RAM_REGISTER(LCD_RAMRegister));
|
||||
|
||||
/* Copy data bytes to RAM register */
|
||||
LCD->RAM[LCD_RAMRegister] = LCD_Data;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the LCD page where the data will be written.
|
||||
* @param LCD_Page: The accessed LCD page.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_PageSelection_FirstPage: The LCD RAM is selected as the first page
|
||||
* @arg LCD_PageSelection_SecondPage: The LCD RAM is selected as the second page
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_PageSelect(LCD_PageSelection_TypeDef LCD_PageSelection)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_LCD_PAGE_SELECT(LCD_PageSelection));
|
||||
|
||||
LCD->CR4 &= (uint8_t)(~LCD_CR4_PAGECOM); /* Clear the PAGE COM bit */
|
||||
LCD->CR4 |= LCD_PageSelection; /* Select the LCD page */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Interrupts and flags management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the start of frame interrupt.
|
||||
* @param NewState: new state of the specified LCD interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_ITConfig(FunctionalState NewState)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
LCD->CR3 |= LCD_CR3_SOFIE; /* Enable interrupt*/
|
||||
}
|
||||
else
|
||||
{
|
||||
LCD->CR3 &= (uint8_t)(~LCD_CR3_SOFIE); /* Disable interrupt*/
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the LCD start of new frame flag is set or not.
|
||||
* @retval The new state of the start of new frame flag.
|
||||
* This returned value can be: SET or RESET.
|
||||
*/
|
||||
FlagStatus LCD_GetFlagStatus(void)
|
||||
{
|
||||
FlagStatus status = RESET;
|
||||
|
||||
/* Check the status of the start of new frame LCD flag */
|
||||
if ((LCD->CR3 & (uint8_t)LCD_CR3_SOF) != (uint8_t)RESET)
|
||||
{
|
||||
status = SET; /* Flag is set */
|
||||
}
|
||||
else
|
||||
{
|
||||
status = RESET; /* Flag is reset*/
|
||||
}
|
||||
/* Return the FLAG status */
|
||||
return status;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the start of frame LCD flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_ClearFlag(void)
|
||||
{
|
||||
/* Clear the flag bit */
|
||||
LCD->CR3 |= (uint8_t)(LCD_CR3_SOFC);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the start of frame interrupt has occurred or not.
|
||||
* @param None
|
||||
* @retval The new state of the start of new frame interrupt.
|
||||
* This returned value can be: SET or RESET.
|
||||
*/
|
||||
ITStatus LCD_GetITStatus(void)
|
||||
{
|
||||
ITStatus pendingbitstatus = RESET;
|
||||
uint8_t enablestatus = 0;
|
||||
|
||||
enablestatus = (uint8_t)((uint8_t)LCD->CR3 & LCD_CR3_SOFIE);
|
||||
/* Check the status of the start of frame interrupt */
|
||||
if (((LCD->CR3 & LCD_CR3_SOF) != RESET) && enablestatus)
|
||||
{
|
||||
/* ITPENDINGBIT is set */
|
||||
pendingbitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* ITPENDINGBIT is reset */
|
||||
pendingbitstatus = RESET;
|
||||
}
|
||||
/* Return the ITPENDINGBIT status */
|
||||
return pendingbitstatus;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the start of frame interrupt pending bits.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_ClearITPendingBit(void)
|
||||
{
|
||||
/* Clear the flag bit */
|
||||
LCD->CR3 |= (uint8_t)(LCD_CR3_SOFC);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
358
firmware/inc/stm8l151x/src/stm8l15x_pwr.c
Normal file
358
firmware/inc/stm8l151x/src/stm8l15x_pwr.c
Normal file
@@ -0,0 +1,358 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* - PVD configuration
|
||||
* - Ultra Low Power mode configuration
|
||||
* - Interrupts and flags management
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_pwr.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR
|
||||
* @brief PWR driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group1 PVD configuration functions
|
||||
* @brief PVD configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
PVD configuration functions
|
||||
===============================================================================
|
||||
|
||||
- The PVD is used to monitor the VDD power supply by comparing it to a threshold
|
||||
selected by the PVD Level (PLS[2:0] bits in the PWR_CSR1).
|
||||
- The PVD can use an external input analog voltage (PVD_IN) which is compared
|
||||
internally to VREFINT. The PVD_IN (PE6) has to be configured in Analog mode
|
||||
when PWR_PVDLevel_PVDIn is selected (PLS[2:0] = 111).
|
||||
- A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
|
||||
PVD threshold. An interrupt is generated in case enabled for PVD.
|
||||
- The PVD interrup event has the capability to wake up the CPU from Halt/Active Halt modes.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_DeInit(void)
|
||||
{
|
||||
PWR->CSR1 = PWR_CSR1_PVDIF;
|
||||
PWR->CSR2 = PWR_CSR2_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param PWR_PVDLevel: specifies the PVD detection level
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_PVDLevel_1V85: PVD detection level set to 1.85V
|
||||
* @arg PWR_PVDLevel_2V05: PVD detection level set to 2.05V
|
||||
* @arg PWR_PVDLevel_2V26: PVD detection level set to 2.26V
|
||||
* @arg PWR_PVDLevel_2V45: PVD detection level set to 2.45V
|
||||
* @arg PWR_PVDLevel_2V65: PVD detection level set to 2.65V
|
||||
* @arg PWR_PVDLevel_2V85: PVD detection level set to 2.85V
|
||||
* @arg PWR_PVDLevel_3V05: PVD detection level set to 3.05V
|
||||
* @arg PWR_PVDLevel_PVDIn: External input analog voltage (Compare internally to VREFINT)
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDLevelConfig(PWR_PVDLevel_TypeDef PWR_PVDLevel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
|
||||
|
||||
/* Clear the PVD level */
|
||||
PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PLS);
|
||||
|
||||
/* Configure the PVD level */
|
||||
PWR->CSR1 |= PWR_PVDLevel;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Power Voltage Detector(PVD).
|
||||
* @param NewState: new state of the PVD.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the PWR PVD */
|
||||
PWR->CSR1 |= PWR_CSR1_PVDE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the PWR PVD */
|
||||
PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PVDE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group2 Ultra Low Power mode configuration functions
|
||||
* @brief Ultra Low Power mode configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Ultra Low Power mode configuration functions
|
||||
===============================================================================
|
||||
|
||||
- The internal voltage reference consumption is not negligible, in particular
|
||||
in Halt and Active Halt modes. To reduce power consumption, use the PWR_UltraLowPowerCmd()
|
||||
function (ULP bit (Ultra low power) in the PWR_CSR2 register) to disable the
|
||||
internal voltage reference. However, in this case, when exiting from the
|
||||
Halt/Active Halt modes, the functions managed through the internal voltage reference
|
||||
are not reliable during the internal voltage reference startup time (up to 3 ms).
|
||||
To reduce the wakeup time, the device can exit from Halt/Active Halt modes without
|
||||
waiting for the internal voltage reference startup time. This is performed
|
||||
by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast
|
||||
wakeup) in the PWR_CSR2 register) before entering Halt/Active Halt mode.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Fast WakeUp from Ultra Low Power mode.
|
||||
* @param NewState: new state of the Fast WakeUp functionality.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_FastWakeUpCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the PWR FWU */
|
||||
PWR->CSR2 |= PWR_CSR2_FWU;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the PWR FWU */
|
||||
PWR->CSR2 &= (uint8_t)(~PWR_CSR2_FWU);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Ultra Low Power mode.
|
||||
* @param NewState: new state of the Ultra Low Power mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_UltraLowPowerCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the PWR ULP */
|
||||
PWR->CSR2 |= PWR_CSR2_ULP;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the PWR ULP */
|
||||
PWR->CSR2 &= (uint8_t)(~PWR_CSR2_ULP);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group3 Interrupts and Flags management functions
|
||||
* @brief Interrupts and Flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Interrupts and Flags management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the Programmable Voltage Detector (PVD) Interrupt .
|
||||
* @param NewState : Indicates the new state of the PVD interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDITConfig(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the PVD interrupt */
|
||||
PWR->CSR1 |= PWR_CSR1_PVDIEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the PVD interrupt */
|
||||
PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PVDIEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified PWR flag is set or not.
|
||||
* @param PWR_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_PVDOF: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the PWR_PVDCmd() function.
|
||||
* @arg PWR_FLAG_VREFINTF: Internal Voltage Reference Ready flag. This
|
||||
* flag indicates the state of the internal voltage reference, VREFINT.
|
||||
* @arg PWR_FLAG_PVDIF: PVD Interrupt Flag, it's set by hardware when a PVD
|
||||
* event occurs
|
||||
* @retval The new state of PWR_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus PWR_GetFlagStatus(PWR_FLAG_TypeDef PWR_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_FLAG(PWR_FLAG));
|
||||
|
||||
if ((PWR_FLAG & PWR_FLAG_VREFINTF) != 0)
|
||||
{
|
||||
if ((PWR->CSR2 & PWR_CR2_VREFINTF) != (uint8_t)RESET )
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((PWR->CSR1 & PWR_FLAG) != (uint8_t)RESET )
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the flag status */
|
||||
return((FlagStatus)bitstatus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the PWR PVDIF Flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDClearFlag(void)
|
||||
{
|
||||
/* Set the PVDIF to clear it */
|
||||
PWR->CSR1 |= PWR_CSR1_PVDIF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the PVD interrupt has occurred or not.
|
||||
* @param None
|
||||
* @retval The new state of the PVD Interrupt (SET or RESET).
|
||||
*/
|
||||
ITStatus PWR_PVDGetITStatus(void)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
uint8_t PVD_itStatus = 0x0, PVD_itEnable = 0x0;
|
||||
|
||||
PVD_itStatus = (uint8_t)(PWR->CSR1 & (uint8_t)PWR_CSR1_PVDIF);
|
||||
PVD_itEnable = (uint8_t)(PWR->CSR1 & (uint8_t)PWR_CSR1_PVDIEN);
|
||||
|
||||
if ((PVD_itStatus != (uint8_t)RESET ) && (PVD_itEnable != (uint8_t)RESET))
|
||||
{
|
||||
bitstatus = (ITStatus)SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (ITStatus)RESET;
|
||||
}
|
||||
return ((ITStatus)bitstatus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the PWR interrupt pending bit.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDClearITPendingBit(void)
|
||||
{
|
||||
/* Set the PVDIF to clear it */
|
||||
PWR->CSR1 |= PWR_CSR1_PVDIF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
171
firmware/inc/stm8l151x/src/stm8l15x_rst.c
Normal file
171
firmware/inc/stm8l151x/src/stm8l15x_rst.c
Normal file
@@ -0,0 +1,171 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_rst.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the RST peripheral:
|
||||
* - Flag management
|
||||
* - NRST Pin configuration
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* RST specific features
|
||||
* ===================================================================
|
||||
*
|
||||
* When a reset occurs, there is a reset phase from the external pin
|
||||
* pull-down to the internal reset signal release. During this phase,
|
||||
* the microcontroller sets some hardware configurations before going
|
||||
* to the reset vector.
|
||||
* At the end of this phase, most of the registers are configured with
|
||||
* their <20>reset state<74> values.
|
||||
* During the reset phase, some pin configurations may be different from
|
||||
* their <20>reset state<74> configuration.
|
||||
*
|
||||
* The NRST pin is an input and can be configured as open-drain output
|
||||
* using the RST_GPOutputEnable() function
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
||||
#include "stm8l15x_rst.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RST
|
||||
* @brief RST driver modules
|
||||
* @{
|
||||
*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define RST_CR_MASK 0xD0 /*!< Enable the GPIO */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RST_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RST_Group1 Flag management functions
|
||||
* @brief Flag management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Flag management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified RST flag is set or not.
|
||||
* @param RST_Flag : specify the reset flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RST_FLAG_PORF: POR reset flag
|
||||
* @arg RST_FLAG_SWIMF: SWIM reset flag
|
||||
* @arg RST_FLAG_ILLOPF: Illegal opcode reset flag
|
||||
* @arg RST_FLAG_IWDGF: Independent watchdog reset flag
|
||||
* @arg RST_FLAG_WWDGF: Window watchdog reset flag
|
||||
* @arg RST_FLAG_BORF: BOR reset flag
|
||||
* @retval The new state of RST_Flag (SET or RESET).
|
||||
*/
|
||||
FlagStatus RST_GetFlagStatus(RST_FLAG_TypeDef RST_Flag)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RST_FLAG(RST_Flag));
|
||||
|
||||
/* Get flag status */
|
||||
return((FlagStatus)(((uint8_t)(RST->SR & RST_Flag) == (uint8_t)0x00) ? RESET : SET));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the specified RST flag.
|
||||
* @param RST_Flag : specify the reset flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RST_FLAG_PORF: POR reset flag
|
||||
* @arg RST_FLAG_SWIMF: SWIM reset flag
|
||||
* @arg RST_FLAG_ILLOPF: Illegal opcode reset flag
|
||||
* @arg RST_FLAG_IWDGF: Independent watchdog reset flag
|
||||
* @arg RST_FLAG_WWDGF: Window watchdog reset flag
|
||||
* @arg RST_FLAG_BORF: BOR reset flag
|
||||
* @retval None
|
||||
*/
|
||||
void RST_ClearFlag(RST_FLAG_TypeDef RST_Flag)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RST_FLAG(RST_Flag));
|
||||
|
||||
RST->SR = (uint8_t)RST_Flag;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RST_Group2 NRST Pin configuration function
|
||||
* @brief NRST Pin configuration function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
NRST Pin configuration function
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the reset pad as GP output.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void RST_GPOutputEnable(void)
|
||||
{
|
||||
|
||||
RST->CR = RST_CR_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
2245
firmware/inc/stm8l151x/src/stm8l15x_rtc.c
Normal file
2245
firmware/inc/stm8l151x/src/stm8l15x_rtc.c
Normal file
File diff suppressed because it is too large
Load Diff
794
firmware/inc/stm8l151x/src/stm8l15x_spi.c
Normal file
794
firmware/inc/stm8l151x/src/stm8l15x_spi.c
Normal file
@@ -0,0 +1,794 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_spi.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Serial peripheral interface (SPI):
|
||||
* - Initialization and Configuration
|
||||
* - Data transfers functions
|
||||
* - Hardware CRC Calculation
|
||||
* - DMA transfers management
|
||||
* - Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* 1. Enable peripheral clock using CLK_PeripheralClockConfig(CLK_Peripheral_SPIx,
|
||||
* ENABLE) function (Refer to the product datasheet for the available SPI
|
||||
* peripherals)
|
||||
*
|
||||
* 2. Enable the external Pull-up on the used SPI Pins using the
|
||||
* GPIO_ExternalPullUpConfig() function or an eternal pull-up equivalent resistor
|
||||
* (RPU = 45 KOhm typical value).
|
||||
*
|
||||
*
|
||||
* 3. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
|
||||
* Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
|
||||
* function.
|
||||
*
|
||||
* 4. Enable the corresponding interrupt using the function SPI_ITConfig() if you
|
||||
* need to use interrupt mode.
|
||||
*
|
||||
* 5. When using the DMA mode
|
||||
* - Configure the DMA using DMA_Init() function
|
||||
* - Active the needed channel Request using SPI_DMACmd() function
|
||||
*
|
||||
* 6. Enable the SPI using the SPI_Cmd() function.
|
||||
*
|
||||
* 7. Enable the DMA using the DMA_Cmd() function when using DMA mode.
|
||||
*
|
||||
* 8. Optionally you can enable/configure the following parameters without
|
||||
* re-initialization (i.e there is no need to call again SPI_Init() function):
|
||||
* - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
|
||||
* is programmed as Data direction parameter using the SPI_Init() function
|
||||
* it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
|
||||
* using the SPI_BiDirectionalLineConfig() function.
|
||||
* - When SPI_NSS_Soft is selected as Slave Select Management parameter
|
||||
* using the SPI_Init() function it can be possible to manage the
|
||||
* NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
|
||||
*
|
||||
* 9. To use the CRC Hardware calculation feature refer to the Peripheral
|
||||
* CRC hardware Calculation subsection.
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_spi.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI
|
||||
* @brief SPI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SPI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Initialization and Configuration functions
|
||||
===============================================================================
|
||||
|
||||
This section provides a set of functions allowing to initialize the SPI Direction,
|
||||
SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
|
||||
Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
|
||||
|
||||
The SPI_Init() function follows the SPI configuration procedures for Master mode
|
||||
and Slave mode (details for these procedures are available in reference manual
|
||||
(RM0031)).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the SPI peripheral registers to their default reset values.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_DeInit(SPI_TypeDef* SPIx)
|
||||
{
|
||||
SPIx->CR1 = SPI_CR1_RESET_VALUE;
|
||||
SPIx->CR2 = SPI_CR2_RESET_VALUE;
|
||||
SPIx->CR3 = SPI_CR3_RESET_VALUE;
|
||||
SPIx->SR = SPI_SR_RESET_VALUE;
|
||||
SPIx->CRCPR = SPI_CRCPR_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SPI according to the specified parameters.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param SPI_FirstBit: This parameter can be any of the
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FirstBit_MSB: MSB bit will be transmitted first
|
||||
* @arg SPI_FirstBit_LSB: LSB bit will be transmitted first
|
||||
* @param SPI_BaudRatePrescaler: This parameter can be any of the
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_BaudRatePrescaler_2: SPI frequency = frequency(CPU)/2
|
||||
* @arg SPI_BaudRatePrescaler_4: SPI frequency = frequency(CPU)/4
|
||||
* @arg SPI_BaudRatePrescaler_8: SPI frequency = frequency(CPU)/8
|
||||
* @arg SPI_BaudRatePrescaler_16: SPI frequency = frequency(CPU)/16
|
||||
* @arg SPI_BaudRatePrescaler_32: SPI frequency = frequency(CPU)/32
|
||||
* @arg SPI_BaudRatePrescaler_64: SPI frequency = frequency(CPU)/64
|
||||
* @arg SPI_BaudRatePrescaler_128: SPI frequency = frequency(CPU)/128
|
||||
* @arg SPI_BaudRatePrescaler_256: SPI frequency = frequency(CPU)/256
|
||||
* @param SPI_Mode: Mode
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_Mode_Master: SPI Master configuration
|
||||
* @arg SPI_Mode_Slave: SPI Slave configuration
|
||||
* @param SPI_CPOL: Clock Polarity
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_CPOL_Low: Clock to 0 when idle
|
||||
* @arg SPI_CPOL_High: Clock to 1 when idle
|
||||
* @param SPI_CPHA: Clock Phase
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_CPHA_1Edge: The first clock transition is the first data capture edge
|
||||
* @arg SPI_CPHA_2Edge: The second clock transition is the first data capture edge
|
||||
* @param SPI_Data_Direction: Data direction
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_Direction_Rx: Select Rx receive direction in bi-directional mode
|
||||
* @arg SPI_Direction_Tx: Select Tx transmission direction in bi-directional mode
|
||||
* @param SPI_Slave_Management: Slave management
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_NSS_Soft: Software slave management disabled
|
||||
* @arg SPI_NSS_Hard: Software slave management enabled
|
||||
* @param CRCPolynomial: Configures the CRC polynomial.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_Init(SPI_TypeDef* SPIx, SPI_FirstBit_TypeDef SPI_FirstBit,
|
||||
SPI_BaudRatePrescaler_TypeDef SPI_BaudRatePrescaler,
|
||||
SPI_Mode_TypeDef SPI_Mode, SPI_CPOL_TypeDef SPI_CPOL,
|
||||
SPI_CPHA_TypeDef SPI_CPHA, SPI_DirectionMode_TypeDef SPI_Data_Direction,
|
||||
SPI_NSS_TypeDef SPI_Slave_Management, uint8_t CRCPolynomial)
|
||||
{
|
||||
/* Check structure elements */
|
||||
assert_param(IS_SPI_FIRSTBIT(SPI_FirstBit));
|
||||
assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_BaudRatePrescaler));
|
||||
assert_param(IS_SPI_MODE(SPI_Mode));
|
||||
assert_param(IS_SPI_POLARITY(SPI_CPOL));
|
||||
assert_param(IS_SPI_PHASE(SPI_CPHA));
|
||||
assert_param(IS_SPI_DATA_DIRECTION(SPI_Data_Direction));
|
||||
assert_param(IS_SPI_SLAVEMANAGEMENT(SPI_Slave_Management));
|
||||
assert_param(IS_SPI_CRC_POLYNOMIAL(CRCPolynomial));
|
||||
|
||||
/* Frame Format, BaudRate, Clock Polarity and Phase configuration */
|
||||
SPIx->CR1 = (uint8_t)((uint8_t)((uint8_t)SPI_FirstBit |
|
||||
(uint8_t)SPI_BaudRatePrescaler) |
|
||||
(uint8_t)((uint8_t)SPI_CPOL |
|
||||
SPI_CPHA));
|
||||
|
||||
/* Data direction configuration: BDM, BDOE and RXONLY bits */
|
||||
SPIx->CR2 = (uint8_t)((uint8_t)(SPI_Data_Direction) | (uint8_t)(SPI_Slave_Management));
|
||||
|
||||
if (SPI_Mode == SPI_Mode_Master)
|
||||
{
|
||||
SPIx->CR2 |= (uint8_t)SPI_CR2_SSI;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CR2 &= (uint8_t)~(SPI_CR2_SSI);
|
||||
}
|
||||
|
||||
/* Master/Slave mode configuration */
|
||||
SPIx->CR1 |= (uint8_t)(SPI_Mode);
|
||||
|
||||
/* CRC configuration */
|
||||
SPIx->CRCPR = (uint8_t)CRCPolynomial;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SPI peripheral.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param NewState New state of the SPI peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SPIx->CR1 |= SPI_CR1_SPE; /* Enable the SPI peripheral*/
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CR1 &= (uint8_t)(~SPI_CR1_SPE); /* Disable the SPI peripheral*/
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures internally by software the NSS pin.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param NewState Indicates the new state of the SPI Software slave management.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_NSSInternalSoftwareCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SPIx->CR2 |= SPI_CR2_SSI; /* Set NSS pin internally by software*/
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CR2 &= (uint8_t)(~SPI_CR2_SSI); /* Reset NSS pin internally by software*/
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the data transfer direction in Bi-directional mode.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param SPI_Direction Specifies the data transfer direction in Bi-directional mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_Direction_Rx: Select Rx receive direction in bi-directional mode
|
||||
* @arg SPI_Direction_Tx: Select Tx transmission direction in bi-directional mode
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, SPI_Direction_TypeDef SPI_Direction)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_SPI_DIRECTION(SPI_Direction));
|
||||
|
||||
if (SPI_Direction != SPI_Direction_Rx)
|
||||
{
|
||||
SPIx->CR2 |= SPI_CR2_BDOE; /* Set the Tx only mode*/
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CR2 &= (uint8_t)(~SPI_CR2_BDOE); /* Set the Rx only mode*/
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Group2 Data transfers functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Data transfers functions
|
||||
===============================================================================
|
||||
|
||||
This section provides a set of functions allowing to manage the SPI data transfers
|
||||
|
||||
In reception, data are received and then stored into an internal Rx buffer while
|
||||
In transmission, data are first stored into an internal Tx buffer before being
|
||||
transmitted.
|
||||
|
||||
The read access of the SPI_DR register can be done using the SPI_ReceiveData()
|
||||
function and returns the Rx buffered value. Whereas a write access to the SPI_DR
|
||||
can be done using SPI_SendData() function and stores the written data into
|
||||
Tx buffer.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Transmits a Data through the SPI peripheral.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param Data: Byte to be transmitted.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_SendData(SPI_TypeDef* SPIx, uint8_t Data)
|
||||
{
|
||||
SPIx->DR = Data; /* Write in the DR register the data to be sent*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the most recent received data by the SPI peripheral.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @retval The value of the received data.
|
||||
*/
|
||||
uint8_t SPI_ReceiveData(SPI_TypeDef* SPIx)
|
||||
{
|
||||
return ((uint8_t)SPIx->DR); /* Return the data in the DR register*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Group3 Hardware CRC Calculation functions
|
||||
* @brief Hardware CRC Calculation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Hardware CRC Calculation functions
|
||||
===============================================================================
|
||||
|
||||
This section provides a set of functions allowing to manage the SPI CRC hardware
|
||||
calculation
|
||||
|
||||
SPI communication using CRC is possible through the following procedure:
|
||||
1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
|
||||
Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
|
||||
function.
|
||||
2. Enable the CRC calculation using the SPI_CalculateCRC() function.
|
||||
3. Enable the SPI using the SPI_Cmd() function
|
||||
4. Before writing the last data to the TX buffer, set the CRCNext bit using the
|
||||
SPI_TransmitCRC() function to indicate that after transmission of the last
|
||||
data, the CRC should be transmitted.
|
||||
5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR2_CRCNEXT
|
||||
bit is reset. The CRC is also received and compared against the SPI_RXCRCR
|
||||
value.
|
||||
If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
|
||||
can be generated when the SPI_IT_ERR interrupt is enabled.
|
||||
|
||||
Note:
|
||||
-----
|
||||
- It is advised to don't read the calculate CRC values during the communication.
|
||||
|
||||
- When the SPI is in slave mode, be careful to enable CRC calculation only
|
||||
when the clock is stable, that is, when the clock is in the steady state.
|
||||
If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
|
||||
to the SCK slave input clock as soon as CRCEN is set, and this, whatever
|
||||
the value of the SPE bit.
|
||||
|
||||
- With high bitrate frequencies, be careful when transmitting the CRC.
|
||||
As the number of used CPU cycles has to be as low as possible in the CRC
|
||||
transfer phase, it is forbidden to call software functions in the CRC
|
||||
transmission sequence to avoid errors in the last data and CRC reception.
|
||||
In fact, CRCNEXT bit has to be written before the end of the transmission/reception
|
||||
of the last data.
|
||||
|
||||
- For high bit rate frequencies, it is advised to use the DMA mode to avoid the
|
||||
degradation of the SPI speed performance due to CPU accesses impacting the
|
||||
SPI bandwidth.
|
||||
|
||||
- When the STM8L15x are configured as slaves and the NSS hardware mode is
|
||||
used, the NSS pin needs to be kept low between the data phase and the CRC
|
||||
phase.
|
||||
|
||||
- When the SPI is configured in slave mode with the CRC feature enabled, CRC
|
||||
calculation takes place even if a high level is applied on the NSS pin.
|
||||
This may happen for example in case of a multislave environment where the
|
||||
communication master addresses slaves alternately.
|
||||
|
||||
- Between a slave de-selection (high level on NSS) and a new slave selection
|
||||
(low level on NSS), the CRC value should be cleared on both master and slave
|
||||
sides in order to resynchronize the master and slave for their respective
|
||||
CRC calculation.
|
||||
|
||||
To clear the CRC, follow the procedure below:
|
||||
1. Disable SPI using the SPI_Cmd() function
|
||||
2. Disable the CRC calculation using the SPI_CalculateCRC() function.
|
||||
3. Enable the CRC calculation using the SPI_CalculateCRC() function.
|
||||
4. Enable SPI using the SPI_Cmd() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables the transmit of the CRC value.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_TransmitCRC(SPI_TypeDef* SPIx)
|
||||
{
|
||||
SPIx->CR2 |= SPI_CR2_CRCNEXT; /* Enable the CRC transmission*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CRC value calculation of the transferred bytes.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param NewState Indicates the new state of the SPI CRC value calculation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_CalculateCRCCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* SPI must be disabled for correct operation od Hardware CRC calculation */
|
||||
SPI_Cmd(SPI1, DISABLE);
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SPIx->CR2 |= SPI_CR2_CRCEN; /* Enable the CRC calculation*/
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CR2 &= (uint8_t)(~SPI_CR2_CRCEN); /* Disable the CRC calculation*/
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the transmit or the receive CRC register value.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param SPI_CRC: Specifies the CRC register to be read.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_CRC_RX: Select Tx CRC register
|
||||
* @arg SPI_CRC_TX: Select Rx CRC register
|
||||
* @retval The selected CRC register value.
|
||||
*/
|
||||
uint8_t SPI_GetCRC(SPI_TypeDef* SPIx, SPI_CRC_TypeDef SPI_CRC)
|
||||
{
|
||||
uint8_t crcreg = 0;
|
||||
|
||||
/* Check function parameters */
|
||||
assert_param(IS_SPI_CRC(SPI_CRC));
|
||||
|
||||
if (SPI_CRC != SPI_CRC_RX)
|
||||
{
|
||||
crcreg = SPIx->TXCRCR; /* Get the Tx CRC register*/
|
||||
}
|
||||
else
|
||||
{
|
||||
crcreg = SPIx->RXCRCR; /* Get the Rx CRC register*/
|
||||
}
|
||||
|
||||
/* Return the selected CRC register status*/
|
||||
return crcreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset the Rx CRCR and Tx CRCR registers.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_ResetCRC(SPI_TypeDef* SPIx)
|
||||
{
|
||||
/* Rx CRCR & Tx CRCR registers are reset when CRCEN (hardware calculation)
|
||||
bit in SPI_CR2 is written to 1 (enable) */
|
||||
SPI_CalculateCRCCmd(SPIx, ENABLE);
|
||||
|
||||
/* Previous function disable the SPI */
|
||||
SPI_Cmd(SPIx, ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the CRC Polynomial register value.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @retval uint8_t The CRC Polynomial register value.
|
||||
*/
|
||||
uint8_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
|
||||
{
|
||||
return SPIx->CRCPR; /* Return the CRC polynomial register */
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Group4 DMA transfers management functions
|
||||
* @brief DMA transfers management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
DMA transfers management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SPI DMA interface.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param SPI_DMAReq Specifies the SPI DMA transfer request to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_DMAReq_RX: SPI DMA Rx transfer requests
|
||||
* @arg SPI_DMAReq_TX: SPI DMA Tx transfer requests
|
||||
* @param NewState Indicates the new state of the SPI DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_DMACmd(SPI_TypeDef* SPIx, SPI_DMAReq_TypeDef SPI_DMAReq, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_SPI_DMAREQ(SPI_DMAReq));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI DMA requests */
|
||||
SPIx->CR3 |= (uint8_t) SPI_DMAReq;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI DMA requests */
|
||||
SPIx->CR3 &= (uint8_t)~SPI_DMAReq;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Group5 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Interrupts and flags management functions
|
||||
===============================================================================
|
||||
|
||||
This section provides a set of functions allowing to configure the SPI Interrupts
|
||||
sources and check or clear the flags or pending bits status.
|
||||
The user should identify which mode will be used in his application to manage
|
||||
the communication: Polling mode, Interrupt mode or DMA mode.
|
||||
|
||||
Polling Mode
|
||||
=============
|
||||
In Polling Mode, the SPI communication can be managed by 6 flags:
|
||||
1. SPI_FLAG_TXE: to indicate the status of the transmit buffer register
|
||||
2. SPI_FLAG_RXNE: to indicate the status of the receive buffer register
|
||||
3. SPI_FLAG_WKUP: to indicate the state of the Wakeup event.
|
||||
4. SPI_FLAG_CRCERR: to indicate if a CRC Calculation error occurs
|
||||
5. SPI_FLAG_MODF: to indicate if a Mode Fault error occurs
|
||||
6. SPI_FLAG_OVR: to indicate if an Overrun error occurs
|
||||
|
||||
In this Mode it is advised to use the following functions:
|
||||
- FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG);
|
||||
- void SPI_ClearFlag(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG);
|
||||
|
||||
Interrupt Mode
|
||||
===============
|
||||
In Interrupt Mode, the SPI communication can be managed by 4 interrupt sources
|
||||
and 6 pending bits:
|
||||
Pending Bits:
|
||||
-------------
|
||||
1. SPI_IT_TXE: to indicate the status of the transmit buffer register
|
||||
2. SPI_IT_RXNE: to indicate the status of the receive buffer register
|
||||
3. SPI_IT_CRCERR: to indicate if a CRC Calculation error occurs
|
||||
4. SPI_IT_MODF: to indicate if a Mode Fault error occurs
|
||||
5. SPI_IT_OVR: to indicate if an Overrun error occurs
|
||||
6. SPI_IT_WKUP: to indicate if an Wake_up event occurs
|
||||
Interrupt Source:
|
||||
-----------------
|
||||
1. SPI_IT_TXE: specifies the interrupt source for the Tx buffer empty
|
||||
interrupt.
|
||||
2. SPI_IT_RXNE: specifies the interrupt source for the Rx buffer not
|
||||
empty interrupt.
|
||||
3. SPI_IT_ERR: specifies the interrupt source for the errors interrupt.
|
||||
4. SPI_IT_WKUP: specifies the interrupt source for the Wake-up interrupt.
|
||||
|
||||
In this Mode it is advised to use the following functions:
|
||||
- void SPI_ITConfig(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT, FunctionalState NewState);
|
||||
- ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT);
|
||||
- void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT);
|
||||
|
||||
DMA Mode
|
||||
========
|
||||
In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
|
||||
1. SPI_DMAReq_Tx: specifies the Tx buffer DMA transfer request
|
||||
2. SPI_DMAReq_Rx: specifies the Rx buffer DMA transfer request
|
||||
|
||||
In this Mode it is advised to use the following function:
|
||||
- void SPI_DMACmd(SPI_TypeDef* SPIx, SPI_DMAReq_TypeDef SPI_DMAReq, FunctionalState NewState);
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified interrupts.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param SPI_IT Specifies the SPI interrupts sources to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_TXE: Transmit buffer empty
|
||||
* @arg SPI_IT_RXNE: Receive buffer not empty
|
||||
* @arg SPI_IT_ERR: Error
|
||||
* @arg SPI_IT_WKUP: Wake-up
|
||||
* @param NewState: The new state of the specified SPI interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_ITConfig(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT, FunctionalState NewState)
|
||||
{
|
||||
uint8_t itpos = 0;
|
||||
/* Check function parameters */
|
||||
assert_param(IS_SPI_CONFIG_IT(SPI_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Get the SPI IT index */
|
||||
itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)SPI_IT & (uint8_t)0x0F));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SPIx->CR3 |= itpos; /* Enable interrupt*/
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CR3 &= (uint8_t)(~itpos); /* Disable interrupt*/
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SPI flag is set or not.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param SPI_FLAG: Specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_BSY: Busy
|
||||
* @arg SPI_FLAG_OVR: Overrun
|
||||
* @arg SPI_FLAG_MODF: Mode fault
|
||||
* @arg SPI_FLAG_CRCERR: CRC error
|
||||
* @arg SPI_FLAG_WKUP: Wake-up
|
||||
* @arg SPI_FLAG_TXE: Transmit buffer empty
|
||||
* @arg SPI_FLAG_RXNE: Receive buffer empty
|
||||
* @retval Indicates the state of SPI_FLAG.
|
||||
* This parameter can be SET or RESET.
|
||||
*/
|
||||
FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG)
|
||||
{
|
||||
FlagStatus status = RESET;
|
||||
/* Check parameters */
|
||||
assert_param(IS_SPI_FLAG(SPI_FLAG));
|
||||
|
||||
/* Check the status of the specified SPI flag */
|
||||
if ((SPIx->SR & (uint8_t)SPI_FLAG) != (uint8_t)RESET)
|
||||
{
|
||||
status = SET; /* SPI_FLAG is set */
|
||||
}
|
||||
else
|
||||
{
|
||||
status = RESET; /* SPI_FLAG is reset*/
|
||||
}
|
||||
|
||||
/* Return the SPI_FLAG status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SPI flags.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param SPI_FLAG: Specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_FLAG_CRCERR
|
||||
* @arg SPI_FLAG_WKUP
|
||||
* @note OVR (OverRun Error) interrupt pending bit is cleared by software
|
||||
* sequence: a read operation to SPI_DR register (SPI_ReceiveData()) followed by
|
||||
* a read operation to SPI_SR register (SPI_GetFlagStatus()).
|
||||
* @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
|
||||
* a read/write operation to SPI_SR register (SPI_GetFlagStatus()) followed by
|
||||
* a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_ClearFlag(SPI_TypeDef* SPIx, SPI_FLAG_TypeDef SPI_FLAG)
|
||||
{
|
||||
assert_param(IS_SPI_CLEAR_FLAG(SPI_FLAG));
|
||||
/* Clear the flag bit */
|
||||
SPIx->SR = (uint8_t)(~SPI_FLAG);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified interrupt has occurred or not.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param SPI_IT: Specifies the SPI interrupt pending bit to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_CRCERR
|
||||
* @arg SPI_IT_WKUP
|
||||
* @arg SPI_IT_OVR
|
||||
* @arg SPI_IT_MODF
|
||||
* @arg SPI_IT_RXNE
|
||||
* @arg SPI_IT_TXE
|
||||
* @retval Indicates the state of the SPI_IT.
|
||||
|
||||
*/
|
||||
ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT)
|
||||
{
|
||||
ITStatus pendingbitstatus = RESET;
|
||||
uint8_t itpos = 0;
|
||||
uint8_t itmask1 = 0;
|
||||
uint8_t itmask2 = 0;
|
||||
__IO uint8_t enablestatus = 0;
|
||||
assert_param(IS_SPI_GET_IT(SPI_IT));
|
||||
/* Get the SPI IT index */
|
||||
itpos = (uint8_t)((uint8_t)1 << ((uint8_t)SPI_IT & (uint8_t)0x0F));
|
||||
|
||||
/* Get the SPI IT mask */
|
||||
itmask1 = (uint8_t)((uint8_t)SPI_IT >> (uint8_t)4);
|
||||
/* Set the IT mask */
|
||||
itmask2 = (uint8_t)((uint8_t)1 << itmask1);
|
||||
/* Get the SPI_IT enable bit status */
|
||||
enablestatus = (uint8_t)((uint8_t)SPIx->SR & itmask2);
|
||||
/* Check the status of the specified SPI interrupt */
|
||||
if (((SPIx->CR3 & itpos) != RESET) && enablestatus)
|
||||
{
|
||||
/* SPI_IT is set */
|
||||
pendingbitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* SPI_IT is reset */
|
||||
pendingbitstatus = RESET;
|
||||
}
|
||||
/* Return the SPI_IT status */
|
||||
return pendingbitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the interrupt pending bits.
|
||||
* @param SPIx: where x can be 1 to select the specified SPI peripheral.
|
||||
* @param SPI_IT: Specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_IT_CRCERR
|
||||
* @arg SPI_IT_WKUP
|
||||
* @note OVR (OverRun Error) interrupt pending bit is cleared by software sequence:
|
||||
* a read operation to SPI_DR register (SPI_ReceiveData()) followed by
|
||||
* a read operation to SPI_SR register (SPI_GetITStatus()).
|
||||
* @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
|
||||
* a read/write operation to SPI_SR register (SPI_GetITStatus()) followed by
|
||||
* a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
|
||||
* @retval None
|
||||
*/
|
||||
void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, SPI_IT_TypeDef SPI_IT)
|
||||
{
|
||||
uint8_t itpos = 0;
|
||||
assert_param(IS_SPI_CLEAR_IT(SPI_IT));
|
||||
|
||||
/* Clear SPI_IT_CRCERR or SPI_IT_WKUP interrupt pending bits */
|
||||
|
||||
/* Get the SPI pending bit index */
|
||||
itpos = (uint8_t)((uint8_t)1 << (uint8_t)((uint8_t)(SPI_IT & (uint8_t)0xF0) >> 4));
|
||||
/* Clear the pending bit */
|
||||
SPIx->SR = (uint8_t)(~itpos);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
507
firmware/inc/stm8l151x/src/stm8l15x_syscfg.c
Normal file
507
firmware/inc/stm8l151x/src/stm8l15x_syscfg.c
Normal file
@@ -0,0 +1,507 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_syscfg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the RI and SYSCFG:
|
||||
* - RI configuration
|
||||
* - SYSCFG configuration
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* This driver provides functions to configure the RI and SYSCFG
|
||||
* These functions are split in 2 groups:
|
||||
*
|
||||
* 1. RI configuration: this group includes all needed functions
|
||||
* to configure the RI:
|
||||
* - Routing the TIM1 Input capture channels
|
||||
* - Close and Open the I/O switches
|
||||
* - Close and Open the analog switches
|
||||
* - Configure the internal Pull-up and Pull-down resistors
|
||||
*
|
||||
* 2. SYSCFG configuration: this group includes all needed functions
|
||||
* to configure the SYSCFG:
|
||||
* - Configure the alternate function remapping of some peripherals
|
||||
* such as: USART, SPI, TIMs...
|
||||
* Remapping possibilities depends on the device (low-density,
|
||||
* medium-density or high density) so it is recommended to
|
||||
* refer to the product reference manual.
|
||||
* - Configure the DMA channels remapping of ADC1 and TIM4
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_syscfg.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG
|
||||
* @brief SYSCFG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Group1 RI configuration
|
||||
* @brief RI configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
RI configuration functions
|
||||
===============================================================================
|
||||
|
||||
===================================================================
|
||||
SYSCFG Driver: how to configure RI
|
||||
===================================================================
|
||||
|
||||
1. By default, TIM1 Input Capture channels 2 and 3 are connected to the
|
||||
I/O port assigned in the datasheet pinout (default routing).
|
||||
TIM1 Input Capture channels 2 and 3 can be routed by calling
|
||||
SYSCFG_RITIMInputCaptureConfig()
|
||||
Refer to the device reference manual for more details about
|
||||
TIM1 input capture routing
|
||||
|
||||
2. For more details about using SYSCFG_RIIOSwitchConfig()
|
||||
and SYSCFG_RIAnalogSwitchConfig() with COMP1 and COMP2, refer to
|
||||
comparators driver
|
||||
|
||||
3. To output the Internal reference voltage VREFINT, configure corresponding
|
||||
GPIO pin in input mode using GPIO_Init() then use SYSCFG_RIIOSwitchConfig()
|
||||
|
||||
4. To use the internal Pull-up and Pull-down resistors call
|
||||
SYSCFG_RIResistorConfig()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the RI registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_RIDeInit(void)
|
||||
{
|
||||
RI->ICR1 = RI_ICR1_RESET_VALUE; /*!< Set RI->ICR1 to reset value */
|
||||
RI->ICR2 = RI_ICR2_RESET_VALUE; /*!< Set RI->ICR2 to reset value */
|
||||
RI->IOSR1 = RI_IOSR1_RESET_VALUE; /*!< Set RI->IOSR1 to reset value */
|
||||
RI->IOSR2 = RI_IOSR2_RESET_VALUE; /*!< Set RI->IOSR2 to reset value */
|
||||
RI->IOSR3 = RI_IOSR3_RESET_VALUE; /*!< Set RI->IOSR3 to reset value */
|
||||
RI->IOSR4 = RI_IOSR4_RESET_VALUE; /*!< Set RI->IOSR3 to reset value */
|
||||
RI->ASCR1 = RI_ASCR1_RESET_VALUE; /*!< Set RI->ASCR1 to reset value */
|
||||
RI->ASCR2 = RI_ASCR2_RESET_VALUE; /*!< Set RI->ASCR2 to reset value */
|
||||
RI->RCR = RI_RCR_RESET_VALUE; /*!< Set RI->RCR to reset value */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the routing interface to select which Input Output pin
|
||||
* to be routed to TIM1 Input Capture.
|
||||
* @param RI_InputCapture: selects the TIM1 input capture2 RI_InputCapture_IC2
|
||||
* or the TIM1 input capture3 RI_InputCapture_IC3
|
||||
* @param RI_InputCaptureRouting: selects the value to set in TIM1 Input Capture
|
||||
* routing register ICRx and can be from RI_InputCaptureRouting_0 to
|
||||
* RI_InputCaptureRouting_22.
|
||||
* @retval None.
|
||||
*/
|
||||
void SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_TypeDef RI_InputCapture,
|
||||
RI_InputCaptureRouting_TypeDef RI_InputCaptureRouting)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));
|
||||
assert_param(IS_RI_INPUTCAPTUREROUTING(RI_InputCaptureRouting));
|
||||
|
||||
/* Check whether Input Capture 2 is selected */
|
||||
if (RI_InputCapture == RI_InputCapture_IC2)
|
||||
{
|
||||
/* Set the value in ICR1 register to route TIM input Capture 2 */
|
||||
RI->ICR1 = (uint8_t) RI_InputCaptureRouting;
|
||||
}
|
||||
|
||||
else /* The Input Capture 3 is selected */
|
||||
{
|
||||
/* Set the value in ICR2 register to route TIM input capture 3 */
|
||||
RI->ICR2 = (uint8_t) RI_InputCaptureRouting;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Routing Interface Analog switch.
|
||||
* @param RI_AnalogSwitch: Analog Switch
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RI_AnalogSwitch_0: Analog switch 0
|
||||
* @arg RI_AnalogSwitch_1: Analog switch 1
|
||||
* @arg RI_AnalogSwitch_2: Analog switch 2
|
||||
* @arg RI_AnalogSwitch_3: Analog switch 3
|
||||
* @arg RI_AnalogSwitch_4: Analog switch 4
|
||||
* @arg RI_AnalogSwitch_5: Analog switch 5
|
||||
* @arg RI_AnalogSwitch_6: Analog switch 6
|
||||
* @arg RI_AnalogSwitch_7: Analog switch 7
|
||||
* @arg RI_AnalogSwitch_8: Analog switch 8
|
||||
* @arg RI_AnalogSwitch_9: Analog switch 9
|
||||
* @arg RI_AnalogSwitch_10: Analog switch 10
|
||||
* @arg RI_AnalogSwitch_11: Analog switch 11
|
||||
* @arg RI_AnalogSwitch_12: Analog switch 14
|
||||
* @param NewState: new state of the analog switch.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_RIAnalogSwitchConfig(RI_AnalogSwitch_TypeDef RI_AnalogSwitch,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
uint8_t AnalogSwitchRegister, AnalogSwitchIndex = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RI_ANALOGSWITCH(RI_AnalogSwitch));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Get the analog switch register ASCR1 or ASCR2 */
|
||||
AnalogSwitchRegister = (uint8_t) (RI_AnalogSwitch & (uint8_t) 0xF0);
|
||||
|
||||
/* Get the analog switch bit index in ASCRx register */
|
||||
AnalogSwitchIndex = (uint8_t) (RI_AnalogSwitch & (uint8_t) 0x0F);
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
if (AnalogSwitchRegister == (uint8_t) 0x10)
|
||||
{
|
||||
/* Enable the analog switch */
|
||||
RI->ASCR1 |= (uint8_t) ((uint8_t)1 << (uint8_t) AnalogSwitchIndex);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enable the analog switch */
|
||||
RI->ASCR2 |= (uint8_t) ((uint8_t)1 << (uint8_t) AnalogSwitchIndex);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (AnalogSwitchRegister == (uint8_t) 0x10)
|
||||
{
|
||||
/* Disable the analog switch */
|
||||
RI->ASCR1 &= (uint8_t) (~(uint8_t)((uint8_t)1 << AnalogSwitchIndex));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the analog switch */
|
||||
RI->ASCR2 &= (uint8_t) (~ (uint8_t)((uint8_t)1 << AnalogSwitchIndex));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Closes or Opens the routing interface Input Output switches.
|
||||
* @param RI_IOSwitch: can be one of RI_IOSwitch_1..RI_IOSwitch_24
|
||||
* @param NewState: new state of the Input Output Switch.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None.
|
||||
*/
|
||||
void SYSCFG_RIIOSwitchConfig(RI_IOSwitch_TypeDef RI_IOSwitch,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
uint8_t IOSwitchRegister, IOSwitchIndex = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RI_IOSWITCH(RI_IOSwitch));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Get the Input Output switch bit index in IOSRx register */
|
||||
IOSwitchIndex = (uint8_t) (RI_IOSwitch & (uint8_t) 0x0F);
|
||||
|
||||
/* Get the Input Output switch register IOSR1, IOSR2 or IOSR3 */
|
||||
IOSwitchRegister = (uint8_t) (RI_IOSwitch & (uint8_t) 0xF0);
|
||||
|
||||
/* Check whether the Input Output switch control bit is in the IOSR1 register */
|
||||
if (IOSwitchRegister == (uint8_t) 0x10)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Close the Input Output switch */
|
||||
RI->IOSR1 |= (uint8_t) ((uint8_t)1 << IOSwitchIndex);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Open the Input Output switch */
|
||||
RI->IOSR1 &= (uint8_t) (~ (uint8_t)((uint8_t)1 << IOSwitchIndex));
|
||||
}
|
||||
}
|
||||
|
||||
/* Check whether the Input Output switch control bit is in the IOSR2 register */
|
||||
else if (IOSwitchRegister == (uint8_t) 0x20)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Close the Input Output switch */
|
||||
RI->IOSR2 |= (uint8_t) ((uint8_t)1 << IOSwitchIndex);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Open the Input Output switch */
|
||||
RI->IOSR2 &= (uint8_t) (~(uint8_t)((uint8_t)1 << IOSwitchIndex));
|
||||
}
|
||||
}
|
||||
|
||||
/* The Input Output switch control bit is in the IOSR3 register */
|
||||
else if (IOSwitchRegister == (uint8_t) 0x30)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Close the Input Output switch */
|
||||
RI->IOSR3 |= (uint8_t) ((uint8_t)1 << IOSwitchIndex);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Open the Input Output switch */
|
||||
RI->IOSR3 &= (uint8_t) (~ (uint8_t) ((uint8_t) 1 << IOSwitchIndex));
|
||||
}
|
||||
}
|
||||
|
||||
/* The Input Output switch control bit is in the IOSR4 register */
|
||||
else
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Close the Input Output switch */
|
||||
RI->IOSR4 |= (uint8_t) ((uint8_t)1 << IOSwitchIndex);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Open the Input Output switch */
|
||||
RI->IOSR4 &= (uint8_t) (~ (uint8_t) ((uint8_t) 1 << IOSwitchIndex));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the Pull-up and Pull-down Resistors
|
||||
* @param RI_Resistor: selects the resistor to connect,
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RI_Resistor_10KPU: 10K pull up
|
||||
* @arg RI_Resistor_400KPU: 400K pull up
|
||||
* @arg RI_Resistor_10KPD: 10K pull down
|
||||
* @arg RI_Resistor_400KPD: 400K pull down
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_RIResistorConfig(RI_Resistor_TypeDef RI_Resistor, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RI_RESISTOR(RI_Resistor));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the resistor */
|
||||
RI->RCR |= (uint8_t) RI_Resistor;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Resistor */
|
||||
RI->RCR &= (uint8_t) (~RI_Resistor);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Group2 SYSCFG configuration
|
||||
* @brief SYSCFG configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
SYSCFG configuration functions
|
||||
===============================================================================
|
||||
|
||||
===================================================================
|
||||
SYSCFG Driver: how to use it for remapping
|
||||
===================================================================
|
||||
|
||||
1. To remap the alternate function of some peripherals (such as: USART,
|
||||
SPI, TIMs...), use SYSCFG_REMAPPinConfig()
|
||||
|
||||
2. To remap the DMA channels of ADC1 and TIM4, use SYSCFG_REMAPDMAChannelConfig()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the Remapping registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_REMAPDeInit(void)
|
||||
{
|
||||
/*!< Set RMPCR1 to reset value */
|
||||
SYSCFG->RMPCR1 = SYSCFG_RMPCR1_RESET_VALUE;
|
||||
|
||||
/*!< Set RMPCR2 to reset value */
|
||||
SYSCFG->RMPCR2 = SYSCFG_RMPCR2_RESET_VALUE;
|
||||
|
||||
/*!< Set RMPCR3 to reset value */
|
||||
SYSCFG->RMPCR3 = SYSCFG_RMPCR3_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Changes the mapping of the specified pins.
|
||||
* @param REMAP_Pin: selects the pin to remap.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg REMAP_Pin_USART1TxRxPortA: USART1 Tx- Rx (PC3- PC2) remapping to PA2- PA3
|
||||
* @arg REMAP_Pin_USART1TxRxPortC: USART1 Tx- Rx (PC3- PC2) remapping to PC5- PC6
|
||||
* @arg REMAP_Pin_USART1Clk: USART1 CK (PC4) remapping to PA0
|
||||
* @arg REMAP_Pin_SPI1Full: SPI1 MISO- MOSI- SCK- NSS(PB7- PB6- PB5- PB4)
|
||||
* remapping to PA2- PA3- PC6- PC5
|
||||
* @arg REMAP_Pin_ADC1ExtTRIG1: ADC1 External Trigger 1 (PA6) remapping to PD0
|
||||
* @arg REMAP_Pin_TIM2TRIGPortA: TIM2 Trigger (PB3) remapping to PA4
|
||||
* @arg REMAP_Pin_TIM3TRIGPortA: TIM3 Trigger (PD1) remapping to PA5
|
||||
* @arg REMAP_Pin_TIM2TRIGLSE: TIM2 Trigger remapping to LSE
|
||||
* @arg REMAP_Pin_TIM3TRIGLSE: TIM3 Trigger remapping to LSE
|
||||
* @arg REMAP_Pin_SPI2Full: SPI2 MISO- MOSI- SCK- NSS(PG7- PG6- PG5- PG4)
|
||||
* remapping to PI3- PI2- PI1- PI0
|
||||
* @arg REMAP_Pin_TIM3TRIGPortG: TIM3 Trigger (PD1) remapping to PG3
|
||||
* @arg REMAP_Pin_TIM23BKIN: TIM2 Break Input (PA4) remapping to PG0
|
||||
* and TIM3 Break Input (PA5) remapping to PG1
|
||||
* @arg REMAP_Pin_SPI1PortF: SPI1 MISO- MOSI- SCK- NSS(PB7- PB6- PB5- PB4)
|
||||
* remapping to PF0- PF1- PF2- PF3
|
||||
* @arg REMAP_Pin_USART3TxRxPortF: USART3 Tx- Rx (PG1- PG0) remapping to PF0- PF1
|
||||
* @arg REMAP_Pin_USART3Clk: USART3 CK (PG2) remapping to PF2
|
||||
* @arg REMAP_Pin_TIM3Channel1: TIM3 Channel 1 (PB1) remapping to PI0
|
||||
* @arg REMAP_Pin_TIM3Channel2: TIM3 Channel 2 (PD0) remapping to PI3
|
||||
* @arg REMAP_Pin_CCO: CCO (PC4) remapping to PE2
|
||||
* @arg REMAP_Pin_TIM2Channel1: TIM2 Channel 1 (PB0) remapping to PC5
|
||||
* @arg REMAP_Pin_TIM2Channel2: TIM2 Channel 2 (PB2) remapping to PC6
|
||||
* @param NewState: This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_REMAPPinConfig(REMAP_Pin_TypeDef REMAP_Pin, FunctionalState NewState)
|
||||
{
|
||||
uint8_t regindex = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_REMAP_PIN(REMAP_Pin));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Read register index */
|
||||
regindex = (uint8_t) ((uint16_t) REMAP_Pin >> 8);
|
||||
|
||||
/* Check if REMAP_Pin is in RMPCR1 register */
|
||||
if (regindex == 0x01)
|
||||
{
|
||||
SYSCFG->RMPCR1 &= (uint8_t)((uint8_t)((uint8_t)REMAP_Pin << 4) | (uint8_t)0x0F);
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SYSCFG->RMPCR1 |= (uint8_t)((uint16_t)REMAP_Pin & (uint16_t)0x00F0);
|
||||
}
|
||||
}
|
||||
/* Check if REMAP_Pin is in RMPCR2 register */
|
||||
else if (regindex == 0x02)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SYSCFG->RMPCR2 |= (uint8_t) REMAP_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
SYSCFG->RMPCR2 &= (uint8_t)((uint16_t)(~(uint16_t)REMAP_Pin));
|
||||
}
|
||||
}
|
||||
/* REMAP_Pin is in RMPCR3 register */
|
||||
else
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SYSCFG->RMPCR3 |= (uint8_t) REMAP_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
SYSCFG->RMPCR3 &= (uint8_t)((uint16_t)(~(uint16_t)REMAP_Pin));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Remaps the DMA Channel to the specific peripheral (ADC or TIM4)
|
||||
* @param REMAP_DMAChannel: specifies the DMA Channel to remap.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg REMAP_DMA1Channel_ADC1ToChannel0: ADC1 DMA1 req/ack mapped on DMA1 channel 0
|
||||
* @arg REMAP_DMA1Channel_ADC1ToChannel1: ADC1 DMA1 req/ack mapped on DMA1 channel 1
|
||||
* @arg REMAP_DMA1Channel_ADC1ToChannel2: ADC1 DMA1 req/ack mapped on DMA1 channel 2
|
||||
* @arg REMAP_DMA1Channel_ADC1ToChannel3: ADC1 DMA1 req/ack mapped on DMA1 channel 3
|
||||
* @arg REMAP_DMA1Channel_TIM4ToChannel0: TIM4 DMA1 req/ack mapped on DMA1 channel 0
|
||||
* @arg REMAP_DMA1Channel_TIM4ToChannel1: TIM4 DMA1 req/ack mapped on DMA1 channel 1
|
||||
* @arg REMAP_DMA1Channel_TIM4ToChannel2: TIM4 DMA1 req/ack mapped on DMA1 channel 2
|
||||
* @arg REMAP_DMA1Channel_TIM4ToChannel3: TIM4 DMA1 req/ack mapped on DMA1 channel 3
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_REMAPDMAChannelConfig(REMAP_DMAChannel_TypeDef REMAP_DMAChannel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_REMAP_DMACHANNEL(REMAP_DMAChannel));
|
||||
|
||||
/* Check if the TIM4 DMA channel is selected: bits 4 --> 7 are set */
|
||||
if ((REMAP_DMAChannel & 0xF0) != RESET)
|
||||
{
|
||||
/* Reset the TIM4 DMA channels */
|
||||
SYSCFG->RMPCR1 &= (uint8_t) (~SYSCFG_RMPCR1_TIM4DMA_REMAP);
|
||||
}
|
||||
/* ADC DMA channel is selected: bits 4 --> 7 are reset */
|
||||
else
|
||||
{
|
||||
/* Reset the ADC DMA channels */
|
||||
SYSCFG->RMPCR1 &= (uint8_t) (~SYSCFG_RMPCR1_ADC1DMA_REMAP);
|
||||
}
|
||||
/* Set the DMA Channels remapping */
|
||||
SYSCFG->RMPCR1 |= (uint8_t) ((uint8_t)0x0F & REMAP_DMAChannel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
2774
firmware/inc/stm8l151x/src/stm8l15x_tim1.c
Normal file
2774
firmware/inc/stm8l151x/src/stm8l15x_tim1.c
Normal file
File diff suppressed because it is too large
Load Diff
2154
firmware/inc/stm8l151x/src/stm8l15x_tim2.c
Normal file
2154
firmware/inc/stm8l151x/src/stm8l15x_tim2.c
Normal file
File diff suppressed because it is too large
Load Diff
2154
firmware/inc/stm8l151x/src/stm8l15x_tim3.c
Normal file
2154
firmware/inc/stm8l151x/src/stm8l15x_tim3.c
Normal file
File diff suppressed because it is too large
Load Diff
762
firmware/inc/stm8l151x/src/stm8l15x_tim4.c
Normal file
762
firmware/inc/stm8l151x/src/stm8l15x_tim4.c
Normal file
@@ -0,0 +1,762 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_tim4.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the TIM4 peripheral:
|
||||
* - TimeBase management
|
||||
* - Interrupts, DMA and flags management
|
||||
* - Clocks management
|
||||
* - Synchronization management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* This driver provides functions to configure and initialize the TIM4
|
||||
* peripheral
|
||||
* These functions are split in 4 groups:
|
||||
*
|
||||
* 1. TIM4 TimeBase management: this group includes all needed functions
|
||||
* to configure the TIM Timebase unit:
|
||||
* - Set/Get Prescaler
|
||||
* - Set/Get Autoreload
|
||||
* - Select the One Pulse mode
|
||||
* - Update Request Configuration
|
||||
* - Update Disable Configuration
|
||||
* - Auto-Preload Configuration
|
||||
* - Enable/Disable the counter
|
||||
*
|
||||
* 2. TIM4 interrupts, DMA and flags management
|
||||
* - Enable/Disable interrupt sources
|
||||
* - Get flags status
|
||||
* - Clear flags/ Pending bits
|
||||
* - Enable/Disable DMA requests
|
||||
*
|
||||
* 3. TIM4 clocks management: this group includes all needed functions
|
||||
* to configure the clock controller unit:
|
||||
* - Select internal clock
|
||||
*
|
||||
* 4. TIM4 synchronization management: this group includes all needed
|
||||
* functions to configure the Synchronization unit:
|
||||
* - Select Input Trigger
|
||||
* - Select Output Trigger
|
||||
* - Select Master Slave Mode
|
||||
*
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_tim4.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4
|
||||
* @brief TIM4 driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup TIM4_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_Group1 TimeBase management functions
|
||||
* @brief TimeBase management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
TimeBase management functions
|
||||
===============================================================================
|
||||
|
||||
===================================================================
|
||||
TIM4 Driver: how to use it in Timing(Time base) Mode
|
||||
===================================================================
|
||||
To use the Timer in Timing(Time base) mode, the following steps are mandatory:
|
||||
|
||||
1. Enable TIM4 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM4, ENABLE) function.
|
||||
|
||||
2. Call TIM4_TimeBaseInit() to configure the Time Base unit with the
|
||||
corresponding configuration.
|
||||
|
||||
3. Enable global interrupts if you need to generate the update interrupt.
|
||||
|
||||
4. Enable the corresponding interrupt using the function TIM4_ITConfig(TIM4_IT_Update)
|
||||
|
||||
5. Call the TIM4_Cmd(ENABLE) function to enable the TIM4 counter.
|
||||
|
||||
Note1: All other functions can be used separately to modify, if needed,
|
||||
a specific feature of the Timer.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the TIM4 peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_DeInit(void)
|
||||
{
|
||||
TIM4->CR1 = TIM4_CR1_RESET_VALUE;
|
||||
TIM4->CR2 = TIM4_CR2_RESET_VALUE;
|
||||
TIM4->SMCR = TIM4_SMCR_RESET_VALUE;
|
||||
TIM4->IER = TIM4_IER_RESET_VALUE;
|
||||
TIM4->CNTR = TIM4_CNTR_RESET_VALUE;
|
||||
TIM4->PSCR = TIM4_PSCR_RESET_VALUE;
|
||||
TIM4->ARR = TIM4_ARR_RESET_VALUE;
|
||||
TIM4->SR1 = TIM4_SR1_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the TIM4 Time Base Unit according to the specified parameters.
|
||||
* @param TIM4_Prescaler: Prescaler
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_Prescaler_1: Time base Prescaler = 1 (No effect)
|
||||
* @arg TIM4_Prescaler_2: Time base Prescaler = 2
|
||||
* @arg TIM4_Prescaler_4: Time base Prescaler = 4
|
||||
* @arg TIM4_Prescaler_8: Time base Prescaler = 8
|
||||
* @arg TIM4_Prescaler_16: Time base Prescaler = 16
|
||||
* @arg TIM4_Prescaler_32: Time base Prescaler = 32
|
||||
* @arg TIM4_Prescaler_64: Time base Prescaler = 64
|
||||
* @arg TIM4_Prescaler_128: Time base Prescaler = 128
|
||||
* @arg TIM4_Prescaler_256: Time base Prescaler = 256
|
||||
* @arg TIM4_Prescaler_512: Time base Prescaler = 512
|
||||
* @arg TIM4_Prescaler_1024: Time base Prescaler = 1024
|
||||
* @arg TIM4_Prescaler_2048: Time base Prescaler = 2048
|
||||
* @arg TIM4_Prescaler_4096: Time base Prescaler = 4096
|
||||
* @arg TIM4_Prescaler_8192: Time base Prescaler = 8192
|
||||
* @arg TIM4_Prescaler_16384: Time base Prescaler = 16384
|
||||
* @arg TIM4_Prescaler_32768: Time base Prescaler = 32768
|
||||
* @param TIM4_Period: This parameter must be a value between 0x00 and 0xFF.
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_TimeBaseInit(TIM4_Prescaler_TypeDef TIM4_Prescaler,
|
||||
uint8_t TIM4_Period)
|
||||
{
|
||||
/* Check TIM4 prescaler value */
|
||||
assert_param(IS_TIM4_Prescaler(TIM4_Prescaler));
|
||||
/* Set the Autoreload value */
|
||||
TIM4->ARR = (uint8_t)(TIM4_Period);
|
||||
/* Set the Prescaler value */
|
||||
TIM4->PSCR = (uint8_t)(TIM4_Prescaler);
|
||||
|
||||
/* Generate an update event to reload the Prescaler value immediately */
|
||||
TIM4->EGR = TIM4_EventSource_Update;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the TIM4 Prescaler.
|
||||
* @param Prescaler: Specifies the Prescaler Register value
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_Prescaler_1: Time base Prescaler = 1 (No effect)
|
||||
* @arg TIM4_Prescaler_2: Time base Prescaler = 2
|
||||
* @arg TIM4_Prescaler_4: Time base Prescaler = 4
|
||||
* @arg TIM4_Prescaler_8: Time base Prescaler = 8
|
||||
* @arg TIM4_Prescaler_16: Time base Prescaler = 16
|
||||
* @arg TIM4_Prescaler_32: Time base Prescaler = 32
|
||||
* @arg TIM4_Prescaler_64: Time base Prescaler = 64
|
||||
* @arg TIM4_Prescaler_128: Time base Prescaler = 128
|
||||
* @arg TIM4_Prescaler_256: Time base Prescaler = 256
|
||||
* @arg TIM4_Prescaler_512: Time base Prescaler = 512
|
||||
* @arg TIM4_Prescaler_1024: Time base Prescaler = 1024
|
||||
* @arg TIM4_Prescaler_2048: Time base Prescaler = 2048
|
||||
* @arg TIM4_Prescaler_4096: Time base Prescaler = 4096
|
||||
* @arg TIM4_Prescaler_8192: Time base Prescaler = 8192
|
||||
* @arg TIM4_Prescaler_16384: Time base Prescaler = 16384
|
||||
* @arg TIM4_Prescaler_32768: Time base Prescaler = 32768
|
||||
* @param TIM4_PSCReloadMode: Specifies the TIM4 Prescaler Reload mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_PSCReloadMode_Update: Prescaler value is reloaded at every update
|
||||
* @arg TIM4_PSCReloadMode_Immediate: Prescaler value is reloaded immediately
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_PrescalerConfig(TIM4_Prescaler_TypeDef Prescaler,
|
||||
TIM4_PSCReloadMode_TypeDef TIM4_PSCReloadMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM4_Prescaler_RELOAD(TIM4_PSCReloadMode));
|
||||
assert_param(IS_TIM4_Prescaler(Prescaler));
|
||||
|
||||
/* Set the Prescaler value */
|
||||
TIM4->PSCR = (uint8_t) Prescaler;
|
||||
|
||||
/* Set or reset the UG Bit */
|
||||
if (TIM4_PSCReloadMode == TIM4_PSCReloadMode_Immediate)
|
||||
{
|
||||
TIM4->EGR |= TIM4_EGR_UG ;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIM4->EGR &= (uint8_t)(~TIM4_EGR_UG) ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the TIM4 Counter Register value.
|
||||
* @param Counter: Specifies the Counter register new value.
|
||||
* This parameter is between 0x00 and 0xFF.
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_SetCounter(uint8_t Counter)
|
||||
{
|
||||
/* Set the Counter Register value */
|
||||
TIM4->CNTR = (uint8_t)(Counter);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the TIM4 Autoreload Register value.
|
||||
* @param Autoreload: Specifies the Autoreload register new value.
|
||||
* This parameter is between 0x00 and 0xFF.
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_SetAutoreload(uint8_t Autoreload)
|
||||
{
|
||||
/* Set the Autoreload Register value */
|
||||
TIM4->ARR = (uint8_t)(Autoreload);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the TIM4 Counter value.
|
||||
* @param None
|
||||
* @retval Counter Register value.
|
||||
*/
|
||||
uint8_t TIM4_GetCounter(void)
|
||||
{
|
||||
uint8_t tmpcntr = 0;
|
||||
tmpcntr = TIM4->CNTR;
|
||||
/* Get the Counter Register value */
|
||||
return ((uint8_t)tmpcntr);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the TIM4 Prescaler value.
|
||||
* @param None
|
||||
* @retval TIM4 Prescaler can be one of the following values:
|
||||
* - TIM4_Prescaler_1: Time base Prescaler = 1 (No effect)
|
||||
* - TIM4_Prescaler_2: Time base Prescaler = 2
|
||||
* - TIM4_Prescaler_4: Time base Prescaler = 4
|
||||
* - TIM4_Prescaler_8: Time base Prescaler = 8
|
||||
* - TIM4_Prescaler_16: Time base Prescaler = 16
|
||||
* - TIM4_Prescaler_32: Time base Prescaler = 32
|
||||
* - TIM4_Prescaler_64: Time base Prescaler = 64
|
||||
* - TIM4_Prescaler_128: Time base Prescaler = 128
|
||||
* - TIM4_Prescaler_256: Time base Prescaler = 256
|
||||
* - TIM4_Prescaler_512: Time base Prescaler = 512
|
||||
* - TIM4_Prescaler_1024: Time base Prescaler = 1024
|
||||
* - TIM4_Prescaler_2048: Time base Prescaler = 2048
|
||||
* - TIM4_Prescaler_4096: Time base Prescaler = 4096
|
||||
* - TIM4_Prescaler_8192: Time base Prescaler = 8192
|
||||
* - TIM4_Prescaler_16384: Time base Prescaler = 16384
|
||||
* - TIM4_Prescaler_32768: Time base Prescaler = 32768
|
||||
*/
|
||||
TIM4_Prescaler_TypeDef TIM4_GetPrescaler(void)
|
||||
{
|
||||
/* Get the Prescaler Register value */
|
||||
return ((TIM4_Prescaler_TypeDef)TIM4->PSCR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or Disables the TIM4 Update event.
|
||||
* @param NewState: The new state of the TIM4 peripheral Preload register.
|
||||
* This parameter can be ENABLE or DISABLE
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_UpdateDisableConfig(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Set or Reset the UDIS Bit */
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
TIM4->CR1 |= TIM4_CR1_UDIS ;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIM4->CR1 &= (uint8_t)(~TIM4_CR1_UDIS) ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the TIM4 Update Request Interrupt source.
|
||||
* @param TIM4_UpdateSource: Specifies the Update source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_UpdateSource_Global: Global Update request source
|
||||
* @arg TIM4_UpdateSource_Regular: Regular Update request source
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_UpdateRequestConfig(TIM4_UpdateSource_TypeDef TIM4_UpdateSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM4_UPDATE_SOURCE(TIM4_UpdateSource));
|
||||
|
||||
/* Set or Reset the URS Bit */
|
||||
if (TIM4_UpdateSource == TIM4_UpdateSource_Regular)
|
||||
{
|
||||
TIM4->CR1 |= TIM4_CR1_URS ;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIM4->CR1 &= (uint8_t)(~TIM4_CR1_URS) ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables TIM4 peripheral Preload register on ARR.
|
||||
* @param NewState: The new state of the TIM4 peripheral Preload register.
|
||||
* This parameter can be ENABLE or DISABLE
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_ARRPreloadConfig(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Set or Reset the ARPE Bit */
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
TIM4->CR1 |= TIM4_CR1_ARPE ;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIM4->CR1 &= (uint8_t)(~TIM4_CR1_ARPE) ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the TIM4's One Pulse Mode.
|
||||
* @param TIM4_OPMode: Specifies the OPM Mode to be used.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_OPMode_Single: Single one Pulse mode (OPM Active)
|
||||
* @arg TIM4_OPMode_Repetitive: Repetitive Pulse mode (OPM inactive)
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_SelectOnePulseMode(TIM4_OPMode_TypeDef TIM4_OPMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM4_OPM_MODE(TIM4_OPMode));
|
||||
|
||||
/* Set or Reset the OPM Bit */
|
||||
if (TIM4_OPMode == TIM4_OPMode_Single)
|
||||
{
|
||||
TIM4->CR1 |= TIM4_CR1_OPM ;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIM4->CR1 &= (uint8_t)(~TIM4_CR1_OPM) ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the TIM4 peripheral.
|
||||
* @param NewState: The new state of the TIM4 peripheral.
|
||||
* This parameter can be ENABLE or DISABLE
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_Cmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* set or Reset the CEN Bit */
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
TIM4->CR1 |= TIM4_CR1_CEN ;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIM4->CR1 &= (uint8_t)(~TIM4_CR1_CEN) ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_Group2 Interrupts DMA and flags management functions
|
||||
* @brief Interrupts, DMA and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Interrupts, DMA and flags management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified TIM4 interrupts.
|
||||
* @param TIM4_IT: Specifies the TIM4 interrupts sources to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_IT_Update: Update
|
||||
* @arg TIM4_IT_Trigger: Trigger
|
||||
* @param NewState: The new state of the TIM4 peripheral.
|
||||
* This parameter can be ENABLE or DISABLE
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_ITConfig(TIM4_IT_TypeDef TIM4_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM4_IT(TIM4_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the Interrupt sources */
|
||||
TIM4->IER |= (uint8_t)TIM4_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Interrupt sources */
|
||||
TIM4->IER &= (uint8_t)(~(uint8_t)TIM4_IT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the TIM4 event to be generated by software.
|
||||
* @param TIM4_EventSource: Specifies the event source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_EventSource_Update: Update
|
||||
* @arg TIM4_EventSource_Trigger: Trigger
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_GenerateEvent(TIM4_EventSource_TypeDef TIM4_EventSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM4_EVENT_SOURCE((uint8_t)TIM4_EventSource));
|
||||
|
||||
/* Set the event sources */
|
||||
TIM4->EGR |= (uint8_t)TIM4_EventSource;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified TIM4 flag is set or not.
|
||||
* @param TIM4_FLAG: Specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_FLAG_Update: Update
|
||||
* @arg TIM4_FLAG_Trigger: Trigger
|
||||
* @retval FlagStatus: The new state of TIM4_FLAG.
|
||||
* This parameter can be SET or RESET.
|
||||
*/
|
||||
FlagStatus TIM4_GetFlagStatus(TIM4_FLAG_TypeDef TIM4_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM4_GET_FLAG(TIM4_FLAG));
|
||||
|
||||
if ((TIM4->SR1 & (uint8_t)TIM4_FLAG) != 0)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return ((FlagStatus)bitstatus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the TIM's pending flags.
|
||||
* @param TIM4_FLAG: Specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_FLAG_Update: Update
|
||||
* @arg TIM4_FLAG_Trigger: Trigger
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_ClearFlag(TIM4_FLAG_TypeDef TIM4_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM4_CLEAR_FLAG((uint8_t)TIM4_FLAG));
|
||||
/* Clear the flags (rc_w0) clear this bit by writing 0. Writing '1' has no effect*/
|
||||
TIM4->SR1 = (uint8_t)(~((uint8_t)TIM4_FLAG));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the TIM4 interrupt has occurred or not.
|
||||
* @param TIM4_IT: Specifies the TIM4 interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_IT_Update: Update
|
||||
* @arg TIM4_IT_Trigger: Trigger
|
||||
* @retval ITStatus: The new state of the TIM4_IT.
|
||||
* This parameter can be SET or RESET
|
||||
*/
|
||||
|
||||
ITStatus TIM4_GetITStatus(TIM4_IT_TypeDef TIM4_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
uint8_t itStatus = 0x0, itEnable = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM4_GET_IT(TIM4_IT));
|
||||
|
||||
itStatus = (uint8_t)(TIM4->SR1 & (uint8_t)TIM4_IT);
|
||||
|
||||
itEnable = (uint8_t)(TIM4->IER & (uint8_t)TIM4_IT);
|
||||
|
||||
if ((itStatus != (uint8_t)RESET ) && (itEnable != (uint8_t)RESET ))
|
||||
{
|
||||
bitstatus = (ITStatus)SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (ITStatus)RESET;
|
||||
}
|
||||
return ((ITStatus)bitstatus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the TIM4's interrupt pending bits.
|
||||
* @param TIM4_IT: Specifies the pending bit to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_IT_Update: Update
|
||||
* @arg TIM4_IT_Trigger: Trigger
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_ClearITPendingBit(TIM4_IT_TypeDef TIM4_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM4_IT(TIM4_IT));
|
||||
|
||||
/* Clear the IT pending Bit */
|
||||
TIM4->SR1 = (uint8_t)(~(uint8_t)TIM4_IT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the TIMx's DMA Requests.
|
||||
* @param TIM4_DMASources: specifies the DMA Request sources.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_DMASource_Update: Update
|
||||
* @param NewState: new state of the DMA Request sources.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_DMACmd( TIM4_DMASource_TypeDef TIM4_DMASource, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_TIM4_DMA_SOURCE(TIM4_DMASource));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the DMA sources */
|
||||
TIM4->DER |= (uint8_t)TIM4_DMASource;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the DMA sources */
|
||||
TIM4->DER &= (uint8_t)~TIM4_DMASource;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_Group3 Clocks management functions
|
||||
* @brief Clocks management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Clocks management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables the TIM4 internal Clock.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_InternalClockConfig(void)
|
||||
{
|
||||
/* Disable slave mode to clock the prescaler directly with the internal clock */
|
||||
TIM4->SMCR &= (uint8_t)(~TIM4_SMCR_SMS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM4_Group4 Synchronization management functions
|
||||
* @brief Synchronization management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Synchronization management functions
|
||||
===============================================================================
|
||||
|
||||
===================================================================
|
||||
TIM4 Driver: how to use it in synchronization Mode
|
||||
===================================================================
|
||||
Case of two/several Timers
|
||||
**************************
|
||||
1. If TIM4 is used as master to other timers use the following functions:
|
||||
- TIM4_SelectOutputTrigger()
|
||||
- TIM4_SelectMasterSlaveMode()
|
||||
2. If TIM4 is used as slave to other timers use the following functions:
|
||||
- TIM4_SelectInputTrigger()
|
||||
- TIM4_SelectSlaveMode()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Selects the TIM4 Input Trigger source.
|
||||
* @param TIM4_InputTriggerSource: Specifies Input Trigger source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_TRGSelection_TIM5: TRIG Input source = TIM5 TRIG Output
|
||||
* @arg TIM4_TRGSelection_TIM1: TRIG Input source = TIM1 TRIG Output
|
||||
* @arg TIM4_TRGSelection_TIM3: TRIG Input source = TIM3 TRIG Output
|
||||
* @arg TIM4_TRGSelection_TIM2: TRIG Input source = TIM2 TRIG Output
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_SelectInputTrigger(TIM4_TRGSelection_TypeDef TIM4_InputTriggerSource)
|
||||
{
|
||||
uint8_t tmpsmcr = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM4_TRIGGER_SELECTION(TIM4_InputTriggerSource));
|
||||
|
||||
tmpsmcr = TIM4->SMCR;
|
||||
|
||||
/* Select the Trigger Source */
|
||||
tmpsmcr &= (uint8_t)(~TIM4_SMCR_TS);
|
||||
tmpsmcr |= (uint8_t)TIM4_InputTriggerSource;
|
||||
|
||||
TIM4->SMCR = (uint8_t)tmpsmcr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the TIM4 Trigger Output Mode.
|
||||
* @param TIM4_TRGOSource: Specifies the Trigger Output source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_TRGOSource_Reset: Trigger Output source = Reset
|
||||
* @arg TIM4_TRGOSource_Enable: Trigger Output source = TIM4 is enabled
|
||||
* @arg TIM4_TRGOSource_Update: Trigger Output source = Update event
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_SelectOutputTrigger(TIM4_TRGOSource_TypeDef TIM4_TRGOSource)
|
||||
{
|
||||
uint8_t tmpcr2 = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM4_TRGO_SOURCE(TIM4_TRGOSource));
|
||||
|
||||
tmpcr2 = TIM4->CR2;
|
||||
|
||||
/* Reset the MMS Bits */
|
||||
tmpcr2 &= (uint8_t)(~TIM4_CR2_MMS);
|
||||
|
||||
/* Select the TRGO source */
|
||||
tmpcr2 |= (uint8_t)TIM4_TRGOSource;
|
||||
|
||||
TIM4->CR2 = tmpcr2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the TIM4 Slave Mode.
|
||||
* @param TIM4_SlaveMode: Specifies the TIM4 Slave Mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM4_SlaveMode_Disable: Disable slave mode to clock the prescaler
|
||||
directly with the internal clock
|
||||
* @arg TIM4_SlaveMode_Reset: Slave Mode Selection = Reset
|
||||
* @arg TIM4_SlaveMode_Gated: Slave Mode Selection = Gated
|
||||
* @arg TIM4_SlaveMode_Trigger: Slave Mode Selection = Trigger
|
||||
* @arg TIM4_SlaveMode_External1: Slave Mode Selection = External 1
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_SelectSlaveMode(TIM4_SlaveMode_TypeDef TIM4_SlaveMode)
|
||||
{
|
||||
uint8_t tmpsmcr = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM4_SLAVE_MODE(TIM4_SlaveMode));
|
||||
|
||||
tmpsmcr = TIM4->SMCR;
|
||||
|
||||
/* Reset the SMS Bits */
|
||||
tmpsmcr &= (uint8_t)(~TIM4_SMCR_SMS);
|
||||
|
||||
/* Select the Slave Mode */
|
||||
tmpsmcr |= (uint8_t)TIM4_SlaveMode;
|
||||
|
||||
TIM4->SMCR = tmpsmcr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or Resets the TIM4 Master/Slave Mode.
|
||||
* @param NewState: The new state of the synchronization between TIM4 and its slaves (through TRGO).
|
||||
* This parameter can be ENABLE or DISABLE
|
||||
* @retval None
|
||||
*/
|
||||
void TIM4_SelectMasterSlaveMode(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Set or Reset the MSM Bit */
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
TIM4->SMCR |= TIM4_SMCR_MSM;
|
||||
}
|
||||
else
|
||||
{
|
||||
TIM4->SMCR &= (uint8_t)(~TIM4_SMCR_MSM);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
2154
firmware/inc/stm8l151x/src/stm8l15x_tim5.c
Normal file
2154
firmware/inc/stm8l151x/src/stm8l15x_tim5.c
Normal file
File diff suppressed because it is too large
Load Diff
1208
firmware/inc/stm8l151x/src/stm8l15x_usart.c
Normal file
1208
firmware/inc/stm8l151x/src/stm8l15x_usart.c
Normal file
File diff suppressed because it is too large
Load Diff
348
firmware/inc/stm8l151x/src/stm8l15x_wfe.c
Normal file
348
firmware/inc/stm8l151x/src/stm8l15x_wfe.c
Normal file
@@ -0,0 +1,348 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm8l15x_wfe.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Wait for Event (WFE) peripheral:
|
||||
* - WFE Source configuration and management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* WFE specific features
|
||||
* ===================================================================
|
||||
*
|
||||
* Wait for event mode (WFE) stops the CPU but allows the other peripherals
|
||||
* and interrupt controller to continue running.
|
||||
* This mode is entered from Run mode by executing a WFE instruction.
|
||||
* Peripheral events can be generated by the timers, serial interfaces,
|
||||
* DMA controller, comparators and I/O ports.
|
||||
* These are enabled by using the WFE_WakeUpSourceEventCmd() function.
|
||||
*
|
||||
* When a peripheral event is enabled, the corresponding interrupts are
|
||||
* not served and you have to clear the corresponding flag status.
|
||||
*
|
||||
* There are two ways to wake up the CPU from WFE mode:
|
||||
* - Interrupts: When an interrupt occurs, the CPU wakes up from WFE mode
|
||||
* serves the interrupt then goes back to WFE mode.
|
||||
* - Wake up event: when a wake up event occurs, the CPU wakes up and
|
||||
* resumes processing, in this case and to save time and power consumption
|
||||
* there is no context save/restore activity.
|
||||
*
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_wfe.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WFE
|
||||
* @brief WFE driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup WFE_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WFE_Group1 WFE Source configuration and management functions
|
||||
* @brief WFE Source configuration and management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
WFE Source configuration and management functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the WFE registers to their default reset value.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WFE_DeInit(void)
|
||||
{
|
||||
WFE->CR1 = WFE_CRX_RESET_VALUE;
|
||||
WFE->CR2 = WFE_CRX_RESET_VALUE;
|
||||
WFE->CR3 = WFE_CRX_RESET_VALUE;
|
||||
WFE->CR4 = WFE_CRX_RESET_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the source that can generate the wake-up event.
|
||||
* @param WFE_Source: The wake-up event source .
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WFE_Source_TIM2_EV0: TIM2 Update/Trigger and Break interrupt
|
||||
* @arg WFE_Source_TIM2_EV1: TIM2 Capture/Compare interrupt
|
||||
* @arg WFE_Source_TIM1_EV0: TIM1 Update/Trigger and Break interrupt
|
||||
* @arg WFE_Source_TIM1_EV1: TIM1 Capture/Compare interrupt
|
||||
* @arg WFE_Source_EXTI_EV0: I/O port interrupt from Pins 0
|
||||
* @arg WFE_Source_EXTI_EV1: I/O port interrupt from Pins 1
|
||||
* @arg WFE_Source_EXTI_EV2: I/O port interrupt from Pins 2
|
||||
* @arg WFE_Source_EXTI_EV3: I/O port interrupt from Pins 3
|
||||
* @arg WFE_Source_EXTI_EV4: I/O port interrupt from Pins 4
|
||||
* @arg WFE_Source_EXTI_EV5: I/O port interrupt from Pins 5
|
||||
* @arg WFE_Source_EXTI_EV6: I/O port interrupt from Pins 6
|
||||
* @arg WFE_Source_EXTI_EV7: I/O port interrupt from Pins 7
|
||||
* @arg WFE_Source_EXTI_EVB_G: I/O port interrupt from port B and G
|
||||
* @arg WFE_Source_EXTI_EVD_H: I/O port interrupt from Port D and H
|
||||
* @arg WFE_Source_EXTI_EVE_F: I/O port interrupt from Port E and F
|
||||
* @arg WFE_Source_ADC1_COMP_EV: ADC1, COMP1 and COMP2 interrupts
|
||||
* @arg WFE_Source_TIM3_EV0: TIM3 Update/Trigger and Break interrupt
|
||||
* @arg WFE_Source_TIM3_EV1: TIM3 Capture/Compare interrupt
|
||||
* @arg WFE_Source_TIM4_EV: TIM4 Update and Trigger interrupt
|
||||
* @arg WFE_Source_SPI1_EV: SPI1 Rx and Tx interrupt
|
||||
* @arg WFE_Source_I2C1_EV: I2C1 Rx and Tx interrupt
|
||||
* @arg WFE_Source_USART1_EV: USART1 Rx and Tx interrupt
|
||||
* @arg WFE_Source_DMA1CH01_EV: DMA1 channel 0 and 1 interrupt
|
||||
* @arg WFE_Source_DMA1CH23_EV: DMA1 channel 2 and 3 interrupt
|
||||
* @arg WFE_Source_RTC_CSS_EV: RTC or CSS on LSE event
|
||||
* @arg WFE_Source_SPI2_EV: SPI2 Rx and Tx interrupt
|
||||
* @arg WFE_Source_USART2_EV: USART2 Rx and Tx interrupt
|
||||
* @arg WFE_Source_USART3_EV: USART3 Rx and Tx interrupt
|
||||
* @arg WFE_Source_TIM5_EV0: TIM5 Update/Trigger and Break interrupt
|
||||
* @arg WFE_Source_TIM5_EV1: TIM5 Capture/Compare interrupt
|
||||
* @param NewState : The wake-up new state.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void WFE_WakeUpSourceEventCmd(WFE_Source_TypeDef WFE_Source, FunctionalState NewState)
|
||||
{
|
||||
uint8_t register_index = 0;
|
||||
/* Check function parameters */
|
||||
assert_param(IS_WFE_SOURCE(WFE_Source));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* The mask is reversed in order to */
|
||||
register_index = (uint8_t)((uint16_t)WFE_Source >> 0x08);
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
switch (register_index)
|
||||
{
|
||||
case 1:
|
||||
WFE->CR1 |= (uint8_t)WFE_Source;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
WFE->CR2 |= (uint8_t)WFE_Source;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
WFE->CR3 |= (uint8_t)WFE_Source;
|
||||
break;
|
||||
|
||||
case 4:
|
||||
WFE->CR4 |= (uint8_t)WFE_Source;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (register_index)
|
||||
{
|
||||
case 1:
|
||||
WFE->CR1 &= (uint8_t)(~(uint8_t)WFE_Source);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
WFE->CR2 &= (uint8_t)(~ (uint8_t)WFE_Source);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
WFE->CR3 &= (uint8_t)(~(uint8_t)WFE_Source);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
WFE->CR4 &= (uint8_t)(~(uint8_t)WFE_Source);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the status of the specified source event.
|
||||
* @param WFE_Source: The wake-up event source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WFE_Source_TIM2_EV0: TIM2 Update/Trigger and Break interrupt
|
||||
* @arg WFE_Source_TIM2_EV1: TIM2 Capture/Compare interrupt
|
||||
* @arg WFE_Source_TIM1_EV0: TIM1 Update/Trigger and Break interrupt
|
||||
* @arg WFE_Source_TIM1_EV1: TIM1 Capture/Compare interrupt
|
||||
* @arg WFE_Source_EXTI_EV0: I/O port interrupt from Pins 0
|
||||
* @arg WFE_Source_EXTI_EV1: I/O port interrupt from Pins 1
|
||||
* @arg WFE_Source_EXTI_EV2: I/O port interrupt from Pins 2
|
||||
* @arg WFE_Source_EXTI_EV3: I/O port interrupt from Pins 3
|
||||
* @arg WFE_Source_EXTI_EV4: I/O port interrupt from Pins 4
|
||||
* @arg WFE_Source_EXTI_EV5: I/O port interrupt from Pins 5
|
||||
* @arg WFE_Source_EXTI_EV6: I/O port interrupt from Pins 6
|
||||
* @arg WFE_Source_EXTI_EV7: I/O port interrupt from Pins 7
|
||||
* @arg WFE_Source_EXTI_EVB_G: I/O port interrupt from port B and G
|
||||
* @arg WFE_Source_EXTI_EVD_H: I/O port interrupt from Port D and H
|
||||
* @arg WFE_Source_EXTI_EVE_F: I/O port interrupt from Port E and F
|
||||
* @arg WFE_Source_ADC1_COMP_EV: ADC1, COMP1 and COMP2 interrupts
|
||||
* @arg WFE_Source_TIM3_EV0: TIM3 Update/Trigger and Break interrupt
|
||||
* @arg WFE_Source_TIM3_EV1: TIM3 Capture/Compare interrupt
|
||||
* @arg WFE_Source_TIM4_EV: TIM4 Update and Trigger interrupt
|
||||
* @arg WFE_Source_SPI1_EV: SPI1 Rx and Tx interrupt
|
||||
* @arg WFE_Source_I2C1_EV: I2C1 Rx and Tx interrupt
|
||||
* @arg WFE_Source_USART1_EV: USART1 Rx and Tx interrupt
|
||||
* @arg WFE_Source_DMA1CH01_EV: DMA1 channel 0 and 1 interrupt
|
||||
* @arg WFE_Source_DMA1CH23_EV: DMA1 channel 2 and 3 interrupt
|
||||
* @arg WFE_Source_RTC_CSS_EV: RTC or CSS on LSE event
|
||||
* @arg WFE_Source_SPI2_EV: SPI2 Rx and Tx interrupt
|
||||
* @arg WFE_Source_USART2_EV: USART2 Rx and Tx interrupt
|
||||
* @arg WFE_Source_USART3_EV: USART3 Rx and Tx interrupt
|
||||
* @arg WFE_Source_TIM5_EV0: TIM5 Update/Trigger and Break interrupt
|
||||
* @arg WFE_Source_TIM5_EV1: TIM5 Capture/Compare interrupt
|
||||
* @retval Source Event state, ENABLE or DISABLE
|
||||
*/
|
||||
FunctionalState WFE_GetWakeUpSourceEventStatus(WFE_Source_TypeDef WFE_Source)
|
||||
{
|
||||
FunctionalState status = DISABLE;
|
||||
/* Check function parameters */
|
||||
assert_param(IS_WFE_SOURCE(WFE_Source));
|
||||
|
||||
switch (WFE_Source)
|
||||
{
|
||||
case WFE_Source_TIM2_EV0:
|
||||
case WFE_Source_TIM2_EV1:
|
||||
case WFE_Source_TIM1_EV0:
|
||||
case WFE_Source_TIM1_EV1:
|
||||
case WFE_Source_EXTI_EV0:
|
||||
case WFE_Source_EXTI_EV1:
|
||||
case WFE_Source_EXTI_EV2:
|
||||
case WFE_Source_EXTI_EV3:
|
||||
|
||||
if ((WFE->CR1 & (uint8_t)WFE_Source) != (uint8_t)0x00)
|
||||
{
|
||||
/* The wake-up event source is enabled*/
|
||||
status = ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The wake-up event source is disabled*/
|
||||
status = DISABLE;
|
||||
}
|
||||
break;
|
||||
|
||||
case WFE_Source_EXTI_EV4:
|
||||
case WFE_Source_EXTI_EV5:
|
||||
case WFE_Source_EXTI_EV6:
|
||||
case WFE_Source_EXTI_EV7:
|
||||
case WFE_Source_EXTI_EVB_G:
|
||||
case WFE_Source_EXTI_EVD_H:
|
||||
case WFE_Source_EXTI_EVE_F:
|
||||
case WFE_Source_ADC1_COMP_EV:
|
||||
|
||||
if ((WFE->CR2 & (uint8_t)WFE_Source) != (uint8_t)0x00)
|
||||
{
|
||||
/* The wake-up event source is enabled*/
|
||||
status = ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The wake-up event source is disabled*/
|
||||
status = DISABLE;
|
||||
}
|
||||
break;
|
||||
case WFE_Source_TIM3_EV0:
|
||||
case WFE_Source_TIM3_EV1:
|
||||
case WFE_Source_TIM4_EV:
|
||||
case WFE_Source_SPI1_EV:
|
||||
case WFE_Source_I2C1_EV:
|
||||
case WFE_Source_USART1_EV:
|
||||
case WFE_Source_DMA1CH01_EV:
|
||||
case WFE_Source_DMA1CH23_EV:
|
||||
|
||||
if ((WFE->CR3 & (uint8_t)WFE_Source) != (uint8_t)0x00)
|
||||
{
|
||||
/* The wake-up event source is enabled*/
|
||||
status = ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The wake-up event source is disabled*/
|
||||
status = DISABLE;
|
||||
}
|
||||
break;
|
||||
|
||||
case WFE_Source_TIM5_EV0:
|
||||
case WFE_Source_TIM5_EV1:
|
||||
case WFE_Source_AES_EV:
|
||||
case WFE_Source_SPI2_EV:
|
||||
case WFE_Source_USART2_EV:
|
||||
case WFE_Source_USART3_EV:
|
||||
case WFE_Source_RTC_CSS_EV:
|
||||
|
||||
if ((WFE->CR4 & (uint8_t)WFE_Source) != (uint8_t)0x00)
|
||||
{
|
||||
/* The wake-up event source is enabled*/
|
||||
status = ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The wake-up event source is disabled*/
|
||||
status = DISABLE;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
247
firmware/inc/stm8l151x/src/stm8l15x_wwdg.c
Normal file
247
firmware/inc/stm8l151x/src/stm8l15x_wwdg.c
Normal file
@@ -0,0 +1,247 @@
|
||||
/**
|
||||
********************************************************************************
|
||||
* @file stm8l15x_wwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.6.1
|
||||
* @date 30-September-2014
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Window watchdog (WWDG) peripheral:
|
||||
* - Refresh window and Counter configuration
|
||||
* - WWDG activation
|
||||
* - Couter and software reset management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* WWDG features
|
||||
* ===================================================================
|
||||
*
|
||||
* Once enabled the WWDG generates a system reset on expiry of a programmed
|
||||
* time period, unless the program refreshes the counter (downcounter)
|
||||
* before to reach 0x3F value (i.e. a reset is generated when the counter
|
||||
* value rolls over from 0x40 to 0x3F).
|
||||
* An MCU reset is also generated if the counter value is refreshed
|
||||
* before the counter has reached the refresh window value. This
|
||||
* implies that the counter must be refreshed in a limited window.
|
||||
*
|
||||
* Once enabled the WWDG cannot be disabled except by a system reset.
|
||||
*
|
||||
* If the WWDG is activated and the watchdog reset on halt option is
|
||||
* selected (Option byte), then the HALT instruction will generate a reset.
|
||||
*
|
||||
* WWDGF flag in RST_SR register can be used to inform when a WWDG
|
||||
* reset occurs.
|
||||
*
|
||||
* WWDG timeout = (WWDG counter clock) * 12288 * (T[5:0] + 1)
|
||||
*
|
||||
* Min-max timeout value @16 MHz(PCLK1): ~0.768 ms / ~49.152 ms
|
||||
*
|
||||
* ===================================================================
|
||||
* How to use this driver
|
||||
* ===================================================================
|
||||
* 1. Configure the WWDG refresh window using WWDG_SetWindowValue() function
|
||||
*
|
||||
* 2. Set the WWDG counter value and start it using WWDG_Enable() function.
|
||||
* When the WWDG is enabled the counter value should be configured to
|
||||
* a value greater than 0x40 to prevent generating an immediate reset.
|
||||
*
|
||||
* 3. Then the application program must refresh the WWDG counter at regular
|
||||
* intervals during normal operation to prevent an MCU reset, using
|
||||
* WWDG_SetCounter() function. This operation must occur only when
|
||||
* the counter value is lower than the refresh window value,
|
||||
* programmed using WWDG_SetWindowValue().
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8l15x_wwdg.h"
|
||||
|
||||
/** @addtogroup STM8L15x_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup WWDG
|
||||
* @brief WWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define BIT_MASK ((uint8_t)0x7F)
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group1 Refresh window and Counter configuration functions
|
||||
* @brief Refresh window and Counter configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
Refresh window and Counter configuration functions
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the WWDG peripheral.
|
||||
* This function set Window Register = WindowValue, Counter Register
|
||||
* according to Counter and \b ENABLE \b WWDG
|
||||
* @param Counter : WWDG counter value
|
||||
* @param WindowValue : specifies the WWDG Window Register, range is 0x00 to 0x7F.
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_Init(uint8_t Counter, uint8_t WindowValue)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_WINDOW_LIMIT_VALUE(WindowValue));
|
||||
|
||||
WWDG->WR = WWDG_WR_RESET_VALUE;
|
||||
WWDG->CR = (uint8_t)(WWDG_CR_WDGA | Counter);
|
||||
WWDG->WR = (uint8_t)((uint8_t)BIT_MASK & (uint8_t) WindowValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG window value.
|
||||
* @param WindowValue: specifies the window value to be compared to the downcounter.
|
||||
* This parameter value must be lower than 0x80.
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue)
|
||||
{
|
||||
__IO uint8_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_WINDOW_LIMIT_VALUE(WindowValue));
|
||||
|
||||
/* Set W[6:0] bits according to WindowValue value */
|
||||
tmpreg |= (uint8_t) (WindowValue & (uint8_t) BIT_MASK);
|
||||
|
||||
/* Store the new value */
|
||||
WWDG->WR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG counter value.
|
||||
* @param Counter: specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
|
||||
* an immediate reset)
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetCounter(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER_VALUE(Counter));
|
||||
|
||||
/* Write to T[6:0] bits to configure the counter value, no need to do
|
||||
a read-modify-write; writing a 0 to WDGA bit does nothing */
|
||||
WWDG->CR = (uint8_t)(Counter & (uint8_t)BIT_MASK);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group2 WWDG activation function
|
||||
* @brief WWDG activation function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
WWDG activation function
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables WWDG and load the counter value.
|
||||
* @param Counter: specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F.
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_Enable(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER_VALUE(Counter));
|
||||
WWDG->CR = (uint8_t)(WWDG_CR_WDGA | Counter);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group3 WWDG counter and software reset management
|
||||
* @brief WWDG counter and software reset management
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
WWDG counter and software reset management
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Gets the WWDG Counter Value.
|
||||
* This value could be used to check if WWDG is in the window, where
|
||||
* refresh is allowed.
|
||||
* @param None
|
||||
* @retval WWDG Counter Value
|
||||
*/
|
||||
uint8_t WWDG_GetCounter(void)
|
||||
{
|
||||
return(WWDG->CR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates immediate WWDG RESET.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SWReset(void)
|
||||
{
|
||||
WWDG->CR = WWDG_CR_WDGA; /* Activate WWDG, with clearing T6 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Reference in New Issue
Block a user