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Seppl
2025-05-28 00:49:11 +02:00
parent 1c7aefbb07
commit 0a2bce78c7
20 changed files with 12837 additions and 5209 deletions
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17
.gitignore vendored
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@@ -11,13 +11,13 @@
*.kicad_prl
*.sch-bak
*~
*.kicad_pcb.lck
_autosave-*
*.tmp
*-save.pro
*-save.kicad_pcb
fp-info-cache
*-backups/
~*.lck
\#auto_saved_files#
# Netlist files (exported from Eeschema)
*.net
@@ -29,16 +29,3 @@ fp-info-cache
# Exported BOM files
*.xml
*.csv
# gitignore template for LTspice
# website: https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html
# Logfile
*.log
# Simulation Outputs
*.raw
*.fft
# Netlist
*.net

1
electronics/fabrication-toolkit-options.json Normal file
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{"ARCHIVE_NAME": "", "EXTRA_LAYERS": "", "ALL_ACTIVE_LAYERS": false, "EXTEND_EDGE_CUT": false, "ALTERNATIVE_EDGE_CUT": false, "AUTO TRANSLATE": true, "AUTO FILL": true, "EXCLUDE DNP": true}

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@@ -0,0 +1,149 @@
P CODE 00
P UNITS CUST 0
P arrayDim N
317GND VIA MD0059PA00X+047195Y-051998X0098Y0000R000S-1117345245
317GND VIA MD0059PA00X+047205Y-052244X0098Y0000R000S-1117345245
317GND VIA MD0059PA00X+047205Y-052480X0098Y0000R000S-1117345245
317GND VIA MD0059PA00X+047205Y-052756X0098Y0000R000S-1117345245
317GND VIA MD0059PA00X+047190Y-053016X0098Y0000R000S-1117345245
317GND VIA MD0059PA00X+047205Y-053268X0098Y0000R000S-1117345245
317GND VIA MD0059PA00X+048004Y-053536X0098Y0000R000S-1117345245
317GND VIA MD0059PA00X+047115Y-053650X0098Y0000R000S-1117345245
317GND VIA MD0059PA00X+044934Y-053279X0098Y0000R000S-1117345245
317GND VIA MD0059PA00X+044940Y-053536X0098Y0000R000S-1117345245
317GND VIA MD0059PA00X+044943Y-054046X0098Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+045866Y-053937X0315Y0000R000S-1117345245
317/DRV_LED VIA MD0157PA00X+047003Y-054027X0315Y0000R000S-1117345245
317/DRV_LED VIA MD0157PA00X+050787Y-053740X0315Y0000R000S-1117345245
317/PWR_MONO VIA MD0157PA00X+045194Y-054812X0315Y0000R000S-1117345245
317/SWIM VIA MD0157PA00X+044473Y-052470X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+042446Y-047711X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+041864Y-049309X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+043528Y-051023X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+043545Y-052105X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+042196Y-051556X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+040732Y-051656X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+042180Y-055101X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+040482Y-055068X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+050718Y-049409X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+050602Y-050907X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+050635Y-055367X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+048005Y-055301X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+047273Y-056382X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+044377Y-050124X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+043478Y-049508X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+044976Y-049209X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+047672Y-048909X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+047805Y-047245X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+043307Y-046965X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+050197Y-045276X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+041339Y-045276X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+040354Y-045276X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+040354Y-044291X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+040354Y-042323X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+040354Y-040354X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+050355Y-054124X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+050372Y-053180X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+041832Y-050791X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+040847Y-050782X0315Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+045168Y-056307X0315Y0000R000S-1117345245
317/PWR_MONO VIA MD0157PA00X+049225Y-056668X0315Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+050492Y-046850X0315Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+050787Y-047638X0315Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+050492Y-048425X0315Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+050056Y-048943X0315Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+049622Y-048970X0315Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+050047Y-050285X0315Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+049604Y-050258X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+049978Y-052338X0315Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+049982Y-056683X0315Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+045165Y-055448X0315Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+041548Y-053354X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+040796Y-042478X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+040800Y-041742X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+050552Y-042499X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+050543Y-041754X0315Y0000R000S-1117345245
317+3V0 VIA MD0157PA00X+043230Y-047635X0315Y0000R000S-1117345245
317NET-(BT101-+) VIA MD0157PA00X+044568Y-047638X0315Y0000R000S-1117345245
317NET-(BT101-+) VIA MD0157PA00X+045669Y-043110X0315Y0000R000S-1117345245
317NET-(BT101-+) VIA MD0157PA00X+045669Y-041142X0315Y0000R000S-1117345245
317NET-(BT101-+) VIA MD0157PA00X+044685Y-042126X0315Y0000R000S-1117345245
317NET-(BT101-+) VIA MD0157PA00X+046654Y-042126X0315Y0000R000S-1117345245
317NET-(BT101-+) VIA MD0157PA00X+045669Y-042126X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+040851Y-055922X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+041831Y-055906X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+045969Y-048956X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+046510Y-055448X0315Y0000R000S-1117345245
317GND VIA MD0157PA00X+046504Y-056315X0315Y0000R000S-1117345245
327/OSC32_P U101 -1 A01X+045330Y-051998X0581Y0157R000S2
327/OSC32_N U101 -2 A01X+045330Y-052254X0581Y0157R000S2
327/SWIM U101 -3 A01X+045330Y-052510X0581Y0157R000S2
327/~{RESET} U101 -4 A01X+045330Y-052766X0581Y0157R000S2
327/BTN U101 -5 A01X+045330Y-053022X0581Y0157R000S2
327GND U101 -6 A01X+045330Y-053278X0581Y0157R000S2
327GND U101 -7 A01X+045330Y-053533X0581Y0157R000S2
327+3V0 U101 -8 A01X+045330Y-053789X0581Y0157R000S2
327GND U101 -9 A01X+045330Y-054045X0581Y0157R000S2
327/PWR_MONO U101 -10 A01X+045330Y-054301X0581Y0157R000S2
327GND U101 -11 A01X+047584Y-054301X0581Y0157R000S2
327/DRV_LED U101 -12 A01X+047584Y-054045X0581Y0157R000S2
327GND U101 -13 A01X+047584Y-053789X0581Y0157R000S2
327GND U101 -14 A01X+047584Y-053533X0581Y0157R000S2
327GND U101 -15 A01X+047584Y-053278X0581Y0157R000S2
327GND U101 -16 A01X+047584Y-053022X0581Y0157R000S2
327GND U101 -17 A01X+047584Y-052766X0581Y0157R000S2
327GND U101 -18 A01X+047584Y-052510X0581Y0157R000S2
327GND U101 -19 A01X+047584Y-052254X0581Y0157R000S2
327GND U101 -20 A01X+047584Y-051998X0581Y0157R000S2
327+3V0 L101 -1 A01X+050448Y-047638X0443Y1339R180S2
327NET-(D101-A) L101 -2 A01X+048765Y-047638X0443Y1339R180S2
327GND U102 -1 A01X+050354Y-053937X0492Y0138R180S2
327/DRV_LED U102 -2 A01X+050354Y-053740X0492Y0138R180S2
327VS U102 -3 A01X+050354Y-053543X0492Y0138R180S2
327GND U102 -4 A01X+050354Y-053346X0492Y0138R180S2
327NET-(Q102-G) U102 -5 A01X+049252Y-053346X0492Y0138R180S2
327(U102-C_{EXT}) U102 -6 A01X+049252Y-053543X0492Y0138R180S2
327U102-RC_{EXT}) U102 -7 A01X+049252Y-053740X0492Y0138R180S2
327VS U102 -8 A01X+049252Y-053937X0492Y0138R180S2
327/PWR_MONO Q101 -1 A01X+049232Y-056275X0581Y0236R270S2
327+3V0 Q101 -2 A01X+049980Y-056275X0581Y0236R270S2
327VS Q101 -3 A01X+049606Y-055536X0581Y0236R270S2
317GND J101 -1 D0394PA00X+044094Y-055512X0669Y0669R180S0
317/SWIM J101 -2 D0394PA00X+044094Y-054512X0669Y0000R180S0
327GND SW102 -1 A01X+040197Y-050787X1102Y0394R000S2
327GND SW102 -1 A01X+042480Y-050787X1102Y0394R000S2
327/~{RESET} SW102 -2 A01X+040197Y-052362X1102Y0394R000S2
327/~{RESET} SW102 -2 A01X+042480Y-052362X1102Y0394R000S2
327VS R104 -1 A01X+049966Y-054724X0404Y0551R180S2
327U102-RC_{EXT}) R104 -2 A01X+049247Y-054724X0404Y0551R180S2
327+3V0 R103 -1 A01X+041865Y-053346X0404Y0551R000S2
327/BTN R103 -2 A01X+042584Y-053346X0404Y0551R000S2
327+3V0 R101 -1 A01X+043538Y-047638X0404Y0551R000S2
327NET-(BT101-+) R101 -2 A01X+044257Y-047638X0404Y0551R000S2
327GND C105 -1 A01X+044882Y-050413X0394Y0571R090S2
327/OSC32_P C105 -2 A01X+044882Y-051161X0394Y0571R090S2
327/OSC32_N C104 -1 A01X+047047Y-051161X0394Y0571R270S2
327GND C104 -2 A01X+047047Y-050413X0394Y0571R270S2
327U102-RC_{EXT}) C103 -1 A01X+048425Y-053917X0394Y0571R270S2
327(U102-C_{EXT}) C103 -2 A01X+048425Y-053169X0394Y0571R270S2
327+3V0 C102 -1 A01X+045472Y-055453X0394Y0571R000S2
327GND C102 -2 A01X+046220Y-055453X0394Y0571R000S2
327+3V0 C101 -1 A01X+045472Y-056299X0394Y0571R000S2
327GND C101 -2 A01X+046220Y-056299X0394Y0571R000S2
327+3V0 D101 -1 A01X+050049Y-049606X1102Y0217R270S2
327NET-(D101-A) D101 -2 A01X+049163Y-049606X1102Y0217R270S2
327+3V0 D101 -3 A01X+049606Y-049606X1102Y0394R270S2
327GND SW101 -1 A01X+042480Y-055906X1102Y0394R180S2
327GND SW101 -1 A01X+040197Y-055906X1102Y0394R180S2
327/BTN SW101 -2 A01X+042480Y-054331X1102Y0394R180S2
327/BTN SW101 -2 A01X+040197Y-054331X1102Y0394R180S2
327NET-(Q102-G) Q102 -1 A01X+049232Y-051944X0581Y0236R270S2
327GND Q102 -2 A01X+049980Y-051944X0581Y0236R270S2
327NET-(D101-A) Q102 -3 A01X+049606Y-051206X0581Y0236R270S2
327/OSC32_N Y101 -1 A01X+046161Y-051102X0236Y0433R180S2
327/OSC32_P Y101 -2 A01X+045768Y-051102X0236Y0433R180S2
327GND Y101 -3 A01X+045965Y-048898X0591Y0945R180S2
327NET-(BT101-+) BT101 -1 A01X+045669Y-042126X3150Y0000R180S2
327GND BT101 -2 A01X+050177Y-042126X0512Y1260R180S2
327GND BT101 -2 A01X+041161Y-042126X0512Y1260R180S2
999

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electronics/rosaled.kicad_pcb
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96
electronics/rosaled.kicad_pro
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@@ -48,10 +48,16 @@
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
"min_clearance": 0.2
}
},
"diff_pair_dimensions": [],
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
@@ -63,16 +69,20 @@
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"creepage": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_filters_mismatch": "ignore",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"hole_to_hole": "error",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
@@ -82,9 +92,11 @@
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"mirrored_text_on_front_layer": "warning",
"missing_courtyard": "warning",
"missing_footprint": "warning",
"net_conflict": "warning",
"nonmirrored_text_on_back_layer": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
@@ -96,10 +108,13 @@
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_on_edge_cuts": "error",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_angle": "error",
"track_dangling": "warning",
"track_segment_length": "error",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
@@ -109,32 +124,34 @@
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_clearance": 0.1,
"min_connection": 0.15,
"min_copper_edge_clearance": 0.2,
"min_groove_width": 0.0,
"min_hole_clearance": 0.1,
"min_hole_to_hole": 0.2,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"min_silk_clearance": 0.15,
"min_text_height": 1.0,
"min_text_thickness": 0.15,
"min_through_hole_diameter": 0.15,
"min_track_width": 0.1,
"min_via_annular_width": 0.05,
"min_via_diameter": 0.15,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"solder_mask_to_copper_clearance": 0.005,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpadsmd": true,
"td_onpthpad": true,
"td_onroundshapesonly": false,
"td_onsmdpad": true,
"td_ontrackend": false,
"td_onviapad": true
"td_onvia": true
}
],
"teardrop_parameters": [
@@ -172,7 +189,12 @@
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"track_widths": [
0.0,
0.15,
0.3,
0.5
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
@@ -199,7 +221,16 @@
"spacing": 0.6
}
},
"via_dimensions": [],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.25,
"drill": 0.15
}
],
"zones_allow_external_fillets": false
},
"ipc2581": {
@@ -209,6 +240,7 @@
"mfg": "",
"mpn": ""
},
"layer_pairs": [],
"layer_presets": [],
"viewports": []
},
@@ -403,10 +435,15 @@
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"footprint_filter": "ignore",
"footprint_link_issues": "warning",
"four_way_junction": "ignore",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"label_multiple_wires": "warning",
"lib_symbol_issues": "warning",
"lib_symbol_mismatch": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
@@ -419,9 +456,14 @@
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"same_local_global_label": "warning",
"similar_label_and_power": "warning",
"similar_labels": "warning",
"similar_power": "warning",
"simulation_model_issue": "error",
"single_global_label": "ignore",
"unannotated": "error",
"unconnected_wire_endpoint": "warning",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
@@ -433,7 +475,7 @@
},
"meta": {
"filename": "rosaled.kicad_pro",
"version": 1
"version": 3
},
"net_settings": {
"classes": [
@@ -448,6 +490,7 @@
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2147483647,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
@@ -456,7 +499,7 @@
}
],
"meta": {
"version": 3
"version": 4
},
"net_colors": null,
"netclass_assignments": null,
@@ -478,6 +521,7 @@
},
"schematic": {
"annotate_start_num": 0,
"bom_export_filename": "${PROJECTNAME}.csv",
"bom_fmt_presets": [],
"bom_fmt_settings": {
"field_delimiter": ",",
@@ -539,10 +583,17 @@
"label": "Description",
"name": "Description",
"show": false
},
{
"group_by": false,
"label": "LCSC Part #",
"name": "LCSC Part #",
"show": true
}
],
"filter_string": "",
"group_symbols": true,
"include_excluded_from_bom": false,
"name": "",
"sort_asc": true,
"sort_field": "Reference"
@@ -586,6 +637,7 @@
},
"page_layout_descr_file": "",
"plot_directory": "",
"space_save_all_events": true,
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",

7683
electronics/rosaled.kicad_sch
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36
sim/csvplotter.py Normal file
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@@ -0,0 +1,36 @@
import os
import glob
import pandas as pd
import matplotlib.pyplot as plt
def plot_csv_files_in_directory(directory):
"""
Loads all CSV files in the given directory and creates a plot for each file.
Assumes all CSV files have two columns. The plot title is the base filename.
Parameters
----------
directory : str
Path to the directory containing CSV files.
Returns
-------
None
"""
csv_files = glob.glob(os.path.join(directory, "*.csv"))
for csv_file in csv_files:
df = pd.read_csv(csv_file)
if df.shape[1] != 3:
continue # Skip files that do not have exactly two columns
plt.figure()
plt.plot(df.iloc[:, 0], df.iloc[:, 1])
plt.title(os.path.splitext(os.path.basename(csv_file))[0])
plt.xlabel('Column 1')
plt.ylabel('Column 2')
plt.tight_layout()
plt.show()
if __name__ == "__main__":
plot_csv_files_in_directory("./csvs")

0
electronics/sim/led puls.asc → sim/led puls.asc
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23
sim/led puls.log Normal file
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@@ -0,0 +1,23 @@
Circuit: * C:\Users\Joseph\Documents\Basteln\KiCAD\rosaled\led puls.asc
WARNING: Less than two connections to node ETA. This node is used by B1.
Direct Newton iteration for .op point succeeded.
Heightened Def Con from 7.337e-006 to 7.34055e-006
Date: Sat Jan 21 00:44:22 2023
Total elapsed time: 0.074 seconds.
tnom = 27
temp = 27
method = modified trap
totiter = 3860
traniter = 3854
tranpoints = 1300
accept = 1223
rejected = 78
matrix size = 12
fillins = 1
solver = Normal
Matrix Compiler1: 36 opcodes 0.1/[0.0]/0.1
Matrix Compiler2: off [0.1]/0.1/0.1

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sim/led puls.op.raw Normal file
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0
electronics/sim/led puls.plt → sim/led puls.plt
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sim/led puls.raw Normal file
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