LTSpiceXVII/examples/jigs/ADP5050_chan1_2.asc

Version 4
SHEET 1 1272 1460
WIRE -336 -96 -432 -96
WIRE -192 -96 -336 -96
WIRE 80 -96 -192 -96
WIRE 448 -96 368 -96
WIRE -432 -80 -432 -96
WIRE -336 -80 -336 -96
WIRE 448 -80 448 -96
WIRE -336 16 -336 0
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WIRE 80 16 -224 16
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WIRE 640 16 592 16
WIRE 720 16 640 16
WIRE 848 16 720 16
WIRE 928 16 848 16
WIRE 976 16 928 16
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WIRE 848 32 848 16
WIRE 448 48 448 16
WIRE 720 48 720 16
WIRE 640 112 640 16
WIRE 848 112 848 96
WIRE 976 112 976 96
WIRE -336 128 -336 112
WIRE -96 128 -112 128
WIRE 0 128 -16 128
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WIRE 400 128 368 128
WIRE 448 160 448 144
WIRE 64 192 64 128
WIRE 64 192 -128 192
WIRE -32 240 -64 240
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WIRE 640 240 640 176
WIRE 640 240 368 240
WIRE 720 240 720 128
WIRE 720 240 640 240
WIRE 720 256 720 240
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WIRE 384 352 368 352
WIRE 480 352 464 352
WIRE 720 352 720 336
WIRE -64 416 -64 240
WIRE 80 416 -64 416
WIRE -16 464 -32 464
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WIRE 400 464 368 464
WIRE 448 464 400 464
WIRE 448 480 448 464
WIRE 224 512 224 496
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WIRE 400 544 -64 544
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WIRE -496 592 -656 592
WIRE -896 608 -1040 608
WIRE -720 608 -816 608
WIRE -496 624 -656 624
WIRE -720 672 -720 640
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WIRE 448 736 448 720
WIRE -224 832 -224 16
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WIRE 448 832 368 832
WIRE 512 832 448 832
WIRE 848 832 592 832
WIRE 928 832 928 16
WIRE 928 832 848 832
WIRE 848 848 848 832
WIRE 448 864 448 832
WIRE 848 928 848 912
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WIRE 400 944 368 944
WIRE 448 976 448 960
WIRE -32 1056 -64 1056
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WIRE 640 1056 368 1056
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WIRE 448 1280 400 1280
WIRE 448 1296 448 1280
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WIRE -144 1328 -320 1328
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WIRE -320 1344 -320 1328
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WIRE -320 1440 -320 1424
FLAG 224 512 0
FLAG -336 128 0
FLAG 448 160 0
FLAG 848 112 0
FLAG 720 352 0
FLAG 480 352 0
FLAG 448 560 0
FLAG -32 464 0
FLAG -112 128 0
FLAG 848 16 OUT
FLAG 976 112 0
FLAG -432 32 0
FLAG -432 -96 IN
FLAG 224 1328 0
FLAG 448 976 0
FLAG 848 928 0
FLAG 480 1168 0
FLAG 448 1376 0
FLAG -32 1280 0
FLAG -720 672 0
FLAG -1040 608 0
FLAG -320 1440 0
SYMBOL res -352 -96 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res -352 16 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL cap 432 -80 R0
SYMATTR InstName C1
SYMATTR Value 0.1<EFBFBD>
SYMBOL cap 832 32 R0
WINDOW 123 24 74 Left 2
SYMATTR InstName C2
SYMATTR Value 8.12<EFBFBD>
SYMBOL ind 496 32 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2<EFBFBD>
SYMBOL res 704 32 R0
SYMATTR InstName R4
SYMATTR Value 34.8K
SYMBOL res 704 240 R0
SYMATTR InstName R5
SYMATTR Value 23.2K
SYMBOL res 368 368 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 22K
SYMBOL cap 432 480 R0
SYMATTR InstName C3
SYMATTR Value 1<>
SYMBOL res 80 448 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 31.6K
SYMBOL cap 64 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 2.2n
SYMBOL res 0 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1.82K
SYMBOL res -48 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R8
SYMATTR Value 10K
SYMBOL cap 624 112 R0
SYMATTR InstName C5
SYMATTR Value 47p
SYMBOL nmos 400 48 R0
SYMATTR InstName M1
SYMATTR Value BSC080N03MS
SYMBOL ADP5050_chan1_2 224 192 R0
SYMATTR InstName U1
SYMBOL res 960 0 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL VOLTAGE -432 -96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 432 736 R0
SYMATTR InstName C6
SYMATTR Value 0.1<EFBFBD>
SYMBOL cap 832 848 R0
WINDOW 123 24 74 Left 2
SYMATTR InstName C7
SYMATTR Value 8.12<EFBFBD>
SYMBOL ind 496 848 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 2.2<EFBFBD>
SYMBOL res 368 1184 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R13
SYMATTR Value 22K
SYMBOL cap 432 1296 R0
SYMATTR InstName C8
SYMATTR Value 1<>
SYMBOL res 80 1264 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R14
SYMATTR Value 31.6K
SYMBOL res -48 1072 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R16
SYMATTR Value 10K
SYMBOL nmos 400 864 R0
SYMATTR InstName M2
SYMATTR Value BSC080N03MS
SYMBOL ADP5050_chan1_2 224 1008 R0
SYMATTR InstName U2
SYMBOL Digital\\schmitt -720 544 R0
WINDOW 0 -34 73 VRight 2
WINDOW 123 26 118 Left 2
WINDOW 39 26 146 Left 2
SYMATTR InstName A1
SYMATTR Value2 Vt=0.5 vh=8m
SYMATTR SpiceLine Vhigh=5 Vlow=0
SYMATTR Description Behavioral Schmitt-Triggered inverter
SYMATTR Type schmtinv
SYMBOL externals\\xv -800 608 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 -96 70 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 10n 10n 833n 1.666u)
SYMBOL res -336 1216 R0
SYMATTR InstName R9
SYMATTR Value 600k
SYMBOL res -336 1328 R0
SYMATTR InstName R10
SYMATTR Value 100K
TEXT 536 1304 Left 2 !.tran 3m startup
TEXT -1336 312 Left 2 ;The schematic simulates channels 1 and 2 in parallel.\nNotice how the SS12, COMP, and FB pins are configured\nThis is DIFFERENT then the real world.  Channels are synced\nto out of phase clocks in order to simulate their phase relationship.
TEXT 376 424 Left 2 ;Rlim is the resistor generally placed on DL pin to set current limit