Files
LTSpiceXVII/examples/jigs/3240-2.5.asc
Joseph Hopfmüller 1d8dca1c6c initial commit
2023-01-23 08:17:09 +01:00

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769 B
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Version 4
SHEET 1 880 680
WIRE 0 176 -96 176
WIRE 32 176 0 176
WIRE 336 176 288 176
WIRE -96 192 -96 176
WIRE 0 256 0 176
WIRE 32 256 0 256
WIRE 336 256 336 240
WIRE 336 256 288 256
WIRE -96 288 -96 272
WIRE 32 336 0 336
WIRE 336 336 288 336
WIRE 432 336 336 336
WIRE 336 352 336 336
WIRE 432 352 432 336
WIRE 336 448 336 416
WIRE 432 448 432 432
FLAG 432 448 0
FLAG 336 448 0
FLAG 0 336 0
FLAG -96 288 0
FLAG -96 176 IN
FLAG 432 336 OUT
SYMBOL cap 320 176 R0
SYMATTR InstName C1
SYMATTR Value 1ľ
SYMBOL cap 320 352 R0
SYMATTR InstName C2
SYMATTR Value 4.7ľ
SYMBOL voltage -96 176 R0
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL res 416 336 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL LTC3240-2.5 160 256 R0
SYMATTR InstName U1
TEXT 64 440 Left 2 !.tran 2m startup