126 lines
3.1 KiB
Plaintext
126 lines
3.1 KiB
Plaintext
* AD8541 SPICE Macro-model Typical Values
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* Function: CMOS Rail-to-Rail General-Purpose Amplifier
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* Developed by: TAM / ADSC
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* Revision History:
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* 1.0 (06/1998)
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* 1.1 (07/2021) -HAG
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* Copyright 2021 by Analog Devices
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*
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* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
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* indicates your acceptance of the terms and provisions in the License Statement.
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*
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* BEGIN Notes:
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*
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* Parameters modeled include: Vos, Ibias, Ios, Input CM limits, CMRR, Supply Current, Output Current, Voltage & Current Noise,
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* Open-loop Gain and Phase, GBWP, Closed-loop Output Impedance, Large and Small Signal Transient Response, Slew Rate,
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*
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* Not modeled: Full-power BW, Settling time, Over-temperature characteristics (modeled on 25degC only), VS=2.7V/3.0V
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*
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* Tested on LTSpice
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*
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* END Notes
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*
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* Node Assignments
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* noninverting input
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* | inverting input
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* | | positive supply
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* | | | negative supply
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* | | | | output
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* | | | | |
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* | | | | |
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.SUBCKT AD8541 1 2 99 50 45
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*
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* INPUT STAGE
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*
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*Note: min length for MOS level 2 = 2E-6
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*
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M1 4 1 8 8 PIX L=2.0E-6 W=98E-6
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M2 6 7 8 8 PIX L=2.0E-6 W=98E-6
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M3 11 1 10 10 NIX L=2.0E-6 W=98E-6
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M4 12 7 10 10 NIX L=2.0E-6 W=98E-6
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RC1 4 50 20E3
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RC2 6 50 20E3
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RC3 99 11 20E3
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RC4 99 12 20E3
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C1 4 6 1.5E-12
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C2 11 12 1.5E-12
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I1 99 8 1.77E-5
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I2 10 50 1.77E-5
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V1 99 9 0.2
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V2 13 50 0.2
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D1 8 9 DX
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D2 13 10 DX
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EOS 7 2 POLY(3) (22,98) (73,98) (81,0) 1.0E-3 1 1 1
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IOS 1 2 0.05E-12
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GB1 1 50 POLY(3) (8,1) (4,1) (50,1) 0.5E-12 1E-12 1E-12 1E-12
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GB2 7 50 POLY(3) (8,7) (6,7) (50,7) 0.5E-12 1E-12 1E-12 1E-12
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GB3 1 50 POLY(3) (10,1) (11,1) (50,1) 0.5E-12 1E-12 1E-12 1E-12
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GB4 7 50 POLY(3) (10,7) (12,7) (50,7) 0.5E-12 1E-12 1E-12 1E-12
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*
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* CMRR 64dB, ZERO AT 20kHz
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*
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ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
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RCM1 21 22 63E3
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CCM1 21 22 30E-12
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RCM2 22 98 50
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*
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* PSRR=68dB, ZERO AT 200Hz
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*
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RPS1 70 0 1E6
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RPS2 71 0 1E6
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CPS1 99 70 1E-5
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CPS2 50 71 1E-5
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EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
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RPS3 72 73 1.59E6
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CPS3 72 73 500E-12
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RPS4 73 98 25
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*
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* VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz)
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*
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VN1 80 0 0
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RN1 80 0 16.45E-3
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HN 81 0 VN1 37
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RN2 81 0 1
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*
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* INTERNAL VOLTAGE REFERENCE
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*
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VFIX 90 98 DC 1
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S1 90 91 (50,99) VSY_SWITCH
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VSN1 91 92 DC 0
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RSY 92 98 1E3
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EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
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GSY 99 50 POLY(1) (99,50) 0 -32E-6
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*
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* ADAPTIVE GAIN STAGE
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* AT Vsy>+4.2, AVol=45 V/mv
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* AT Vsy<+3.8, AVol=450 V/mv
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*
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G1 98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5
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VR1 30 31 DC 0
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H1 31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9
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CF 45 30 19E-12
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D3 30 99 DX
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D4 50 30 DX
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*
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* OUTPUT STAGE
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*
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M5 45 46 99 99 POX L=2E-6 W=0.98E-3
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M6 45 47 50 50 NOX L=2E-6 W=0.98E-3
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EG1 99 46 POLY(1) (98,30) 1.170 1
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EG2 47 50 POLY(1) (30,98) 1.170 1
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*
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* MODELS
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*
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.MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-1,LAMBDA=0.067)
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.MODEL NOX NMOS (LEVEL=2,KP=20E-6, VTO=1,LAMBDA=0.067)
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.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.1,LAMBDA=0.01,KF=1E-31)
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.MODEL NIX NMOS (LEVEL=2,KP=20E-6, VTO=0.1,LAMBDA=0.01,KF=1E-31)
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.MODEL DX D(IS=1E-14)
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.MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-4.2,VON=-3.5)
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.ENDS AD8541
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