164 lines
3.8 KiB
Plaintext
164 lines
3.8 KiB
Plaintext
* AD8137 SPICE Macro-model
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* Description: Amplifier
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* Generic Desc: Low Power/Cost Diff 10-12 bit ADC Driver
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* Developed by: TRW/ADI
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* Revision History: 08/10/2012 - Updated to new header style
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* 07/06/2021 - Corrected current draw from the supplies
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* 4.0 (07/2006)
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* Copyright 2006, 2012 by Analog Devices, Inc.
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*
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* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
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* indicates your acceptance with the terms and provisions in the License Statement.
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*
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* BEGIN Notes:
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*
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* Not Modeled:
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* vnoise, not included in this version
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* inoise, not included in this version
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* distortion is not characterized
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* cmrr is not characterized in this version.
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*
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* Parameters modeled include:
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* closed loop gain and phase vs bandwidth
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* output current and voltage limiting
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* offset voltage (is non-static, will vary with gain)
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* ibias (again, is static, will not vary with vcm)
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* slew rate and step response performance
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* (slew rate is based on 10-90% of step response)
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* current on output will be reflected to the supplies
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* Vocm is variable and include input typical offset
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*
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* END Notes:
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*
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* Node assignments
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* non-inverting input
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* | inverting input
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* | | positive supply
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* | | | negative supply
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* | | | | output positive
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* | | | | | output negative
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* | | | | | | vocm input
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* | | | | | | |
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.SUBCKT AD8137 3a 9 99 50 71b 71 110
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*** INPUT STAGE ***
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*** POSITIVE INPUT, LEFT SIDE ***
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I1 99BUF 5 .4E-3
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Q1 50BUF 2 5 QX
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VOS 3a 2 -1.95E-3
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*** RAIL CLIPPING ***
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Dlim+ 75 14b dx
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Vlim+ 99BUF 14b 1.55
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Dlim 14c 75 dx
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Vlim 14c 50BUF 1.55
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Dlim- 13b 76 DX
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Vlim- 13b 50BUF 1.5
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Dlim-B 76 13C dx
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Vlim-B 99BUF 13C 1.5
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*** VOCM INPUT RAIL CLIPPING ***
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DOCMa 100 100A dx
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VOCMa 99BUF 100A 2.04
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DOCMb 100b 100 DX
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VOCMb 100b 50BUF 2.04
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*** NEGATIVE INPUT, RIGHT SIDE ***
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I2 99BUF 6 .4E-3
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Q2 50BUF 9 6 QX
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*** INPUT IMPEDANCE ***
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Cin 3a 9 1p
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*** POLE, ZERO POLE STAGE ***
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G1 13 14 5 6 5e-3
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C1 14 13 1.7p
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C2 13 98 11.5p
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C3 14 98 11.5p
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R11 13 98 250k
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R12 14 98 250k
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*** POLE ZERO STAGE (POSITIVE SIDE) ***
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GP1 0 75 14 98 1
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RP1 75 0 1
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CP1 75 0 2e-9
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*** POLE ZERO STAGE (NEGATIVE SIDE) ***
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GP2 0 76 13 98 1
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RP2 76 0 1
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CP2 76 0 2e-9
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*** OUTPUT STAGE (NEGATIVE SIDE) ***
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D17 76 84 DX
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VO1 84 70 .177V
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VO2 70 85 .177V
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D16 85 76 DX
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G30 70 99c 99BUF 76 91E-3
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G31 98c 70 76 50BUF 91E-3
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RO30 70 99c 11
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RO31 98c 70 11
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VIOUT1 99BUF 99c 0V ;current mon from V+
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VIOUT2 50BUF 98c 0V ;current mon from V-
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VIOUT3 70 71 0V ;current mon from OUT-
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*** OUTPUT STAGE (POSITIVE SIDE) ***
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D17b 75 84b DX
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VO1b 84b 70b .177V
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VO2b 70b 85b .177V
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D16b 85b 75 DX
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G30b 70b 99d 99BUF 75 91E-3
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G31b 98d 70b 75 50BUF 91E-3
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RO30b 70b 99d 11
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RO31b 98d 70b 11
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VIOUTB1 99BUF 99d 0V
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VIOUTB2 98d 50BUF 0V
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VIOUTB3 70b 71b 0V
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*** VOCM STAGE ***
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Gocm_a 0 75 100 0 1
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Gocm_b 0 76 100 0 1
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Rocm1 99BUF 100 70k
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Rocm2 100 50BUF 70k
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Vocmo 110 100 1e-3
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*** REFERENCE STAGE ***
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Eref 98 0 poly(2) 99BUF 0 50BUF 0 0 0.5 0.5
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*** POWER SUPPLY BUFFER ***
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E99 99BUF 0 99 0 1
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E50 50BUF 0 50 0 1
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*** CURRENT MIRROR TO SUPPLIES
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GIQ 99 50 VALUE={2.3m + I(VIOUT3)+ I(VIOUTB3)}
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;*** CURRENT MIRROR TO SUPPLIES, POSITIVE SIDE ***
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;FO1 0 99 poly(2) VIOUT1 VI1 -1.803E-3 1 -1
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;FO2 0 50 poly(2) VIOUT2 VI2 -1.803E-3 1 -1
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;FO3 0 400 VIOUT1 1
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;VI1 401 0 0
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;VI2 0 402 0
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;DM1 400 401 DX
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;DM2 402 400 DX
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;*** CURRENT MIRROR TO SUPPLIES, NEGATIVE SIDE ***
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;FO2B 0 50 poly(2) VIOUTB2 VIB2 +200E-6 1 -1
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;FO1B 0 99 poly(2) VIOUTB1 VIB1 0 1 -1
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;FO3B 0 400B VIOUTB1 1
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;VIB1 401B 0 0
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;VIB2 0 402B 0
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;DMB1 400B 401B DX
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;DMB2 402B 400B DX
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.MODEL QX PNP (BF=228.57 Is=1E-15)
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.MODEL DX D(IS=1E-15)
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.ENDS |