Files
LTSpiceXVII/examples/jigs/ADP7182.asc
Joseph Hopfmüller 1d8dca1c6c initial commit
2023-01-23 08:17:09 +01:00

60 lines
1.1 KiB
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Version 4
SHEET 1 984 680
WIRE 32 -48 -80 -48
WIRE 112 -48 32 -48
WIRE 416 -48 368 -48
WIRE 496 -48 416 -48
WIRE 608 -48 496 -48
WIRE -80 -32 -80 -48
WIRE 32 -32 32 -48
WIRE 496 -32 496 -48
WIRE 608 -32 608 -48
WIRE 416 48 416 -48
WIRE -80 64 -80 48
WIRE 32 64 32 32
WIRE 496 64 496 32
WIRE 608 64 608 48
WIRE 112 144 32 144
WIRE 416 144 416 128
WIRE 416 144 368 144
WIRE 32 160 32 144
WIRE 416 160 416 144
WIRE 32 256 32 240
WIRE 240 256 240 208
WIRE 416 256 416 240
FLAG -80 64 0
FLAG 32 64 0
FLAG 496 64 0
FLAG 32 256 0
FLAG 240 256 0
FLAG 608 64 0
FLAG 32 -48 IN
FLAG 496 -48 OUT
FLAG 416 256 0
SYMBOL cap 16 -32 R0
SYMATTR InstName C1
SYMATTR Value 2.2ľ
SYMBOL cap 480 -32 R0
SYMATTR InstName C2
SYMATTR Value 2.2ľ
SYMBOL voltage -80 -48 R0
SYMATTR InstName V1
SYMATTR Value -8
SYMBOL voltage 32 144 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 2 200u 1n 1n 10m)
SYMBOL res 592 -48 R0
SYMATTR InstName R3
SYMATTR Value 50
SYMBOL res 400 32 R0
SYMATTR InstName R1
SYMATTR Value 120k
SYMBOL res 400 144 R0
SYMATTR InstName R2
SYMATTR Value 120k
SYMBOL ADP7182 240 48 R0
SYMATTR InstName U1
TEXT 528 248 Left 2 !.tran 1m