50 lines
1.0 KiB
Plaintext
50 lines
1.0 KiB
Plaintext
Version 4
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SHEET 1 880 680
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WIRE 32 64 -64 64
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WIRE 48 64 32 64
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WIRE 336 64 304 64
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WIRE -64 80 -64 64
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WIRE 32 144 32 64
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WIRE 48 144 32 144
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WIRE 336 144 304 144
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WIRE -64 176 -64 160
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WIRE 336 224 304 224
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WIRE 480 224 336 224
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WIRE 560 224 480 224
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WIRE 480 240 480 224
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WIRE 560 240 560 224
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WIRE 48 304 32 304
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WIRE 336 304 304 304
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WIRE 480 336 480 304
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WIRE 560 336 560 320
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FLAG 480 336 0
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FLAG 32 304 0
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FLAG -64 176 0
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FLAG 560 336 0
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FLAG 336 384 0
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FLAG -64 64 IN
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FLAG 560 224 OUT
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SYMBOL ind 320 48 R0
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SYMATTR InstName L1
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SYMATTR Value 1.5µ
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SYMATTR SpiceLine Rser=80m
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SYMBOL cap 464 240 R0
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SYMATTR InstName C1
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SYMATTR Value 10µ
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SYMBOL voltage -64 64 R0
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SYMATTR InstName V1
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SYMATTR Value 3.3
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SYMBOL res 544 224 R0
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SYMATTR InstName Rload
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SYMATTR Value 50
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SYMBOL res 320 208 R0
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SYMATTR InstName R1
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SYMATTR Value 900K
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SYMBOL res 320 288 R0
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SYMATTR InstName R2
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SYMATTR Value 100K
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SYMBOL ADP2504-ADJ 176 176 R0
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SYMATTR InstName U1
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TEXT 432 408 Left 2 !.tran 400u startup
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TEXT 168 -16 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
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