88 lines
4.1 KiB
Plaintext
88 lines
4.1 KiB
Plaintext
Version 4
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SHEET 1 2580 1112
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WIRE 128 -224 128 -240
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WIRE 96 -208 80 -208
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WIRE 224 -192 160 -192
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WIRE 1072 -192 1072 -208
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WIRE 96 -176 32 -176
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WIRE 1040 -176 1024 -176
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WIRE 1168 -160 1104 -160
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WIRE 128 -144 128 -160
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WIRE 1040 -144 960 -144
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WIRE 1072 -112 1072 -128
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WIRE 128 176 128 160
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WIRE 96 192 80 192
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WIRE 224 208 160 208
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WIRE 32 224 32 -176
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WIRE 96 224 32 224
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WIRE 1056 240 1056 224
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WIRE 128 256 128 240
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WIRE 1024 256 1008 256
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WIRE 1152 272 1088 272
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WIRE 960 288 960 -144
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WIRE 1024 288 960 288
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WIRE 1056 320 1056 304
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WIRE 32 400 32 224
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WIRE 960 400 960 288
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WIRE 960 400 32 400
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WIRE 1008 400 1008 384
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WIRE 1104 400 1104 384
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WIRE 32 416 32 400
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WIRE 1008 496 1008 480
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WIRE 1104 496 1104 480
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WIRE 32 512 32 496
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FLAG 128 -240 +V
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FLAG 128 -144 -V
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FLAG 80 -208 0
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FLAG 1104 496 0
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FLAG 1008 496 0
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FLAG 1008 384 +V
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FLAG 1104 384 -V
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FLAG 32 512 0
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FLAG 128 160 +V
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FLAG 128 256 -V
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FLAG 80 192 0
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FLAG 1056 224 +V
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FLAG 1056 320 -V
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FLAG 1008 256 0
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FLAG 1072 -208 +V
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FLAG 1072 -112 -V
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FLAG 1024 -176 0
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FLAG 224 -192 1
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FLAG 224 208 2
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FLAG 1152 272 3b
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FLAG 1168 -160 3a
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SYMBOL voltage 1008 384 R0
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SYMATTR InstName V1
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SYMATTR Value 15
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SYMBOL voltage 1104 384 R0
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SYMATTR InstName V2
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SYMATTR Value -15
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SYMBOL voltage 32 400 R0
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WINDOW 0 25 22 Left 2
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WINDOW 3 27 90 Left 2
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SYMATTR InstName V3
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SYMATTR Value ac 1
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SYMBOL opamps\\UniversalOpamp2 128 -192 R0
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WINDOW 38 12 24 Left 2
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SYMATTR SpiceModel level.1
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SYMATTR InstName U1
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SYMBOL opamps\\UniversalOpamp2 128 208 R0
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WINDOW 38 12 24 Left 2
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SYMATTR InstName U2
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SYMBOL opamps\\UniversalOpamp2 1072 -160 R0
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WINDOW 38 12 24 Left 2
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SYMATTR SpiceModel level.3a
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SYMATTR InstName U3
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SYMBOL opamps\\UniversalOpamp2 1056 272 R0
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WINDOW 38 12 24 Left 2
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SYMATTR SpiceModel level.3b
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SYMATTR InstName U4
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TEXT 152 464 Left 2 !.ac oct 10 .1 100Meg
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TEXT 264 -272 Left 2 ;A linear single pole opamp with no internal nodes\nor output voltage range limit.\nAvol=DC gain GBW=GBW product Vos=offset voltage\nen=equiv. input noise voltage density\nenk=equiv. input noise voltage density corner freq.\nin=equiv. input noise current density\nink=equiv. input noise current density corner freq.\nRin=Input resistance
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TEXT 272 104 Left 2 ;A single pole opamp with one internal node,\nslew rate limit and output voltage and current limit.\nAvol=DC gain GBW=GBW product\nSlew=Slewrate limit ilimit=current limit\nrail=output stage saturation voltage\nVos=offset voltage\nen=equiv. input noise voltage density\nenk=equiv. input noise voltage density corner freq.\nin=equiv. input noise current density\nink=equiv. input noise current density corner freq.\nRin=Input resistance
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TEXT 1224 104 Left 2 ;A dominate pole opamp with a delay, slew rate limit,\noutput voltage and current limit, and a programable\nphase margin. Implemented in 7 internal nodes.\nAvol=DC gain GBW=GBW product\nSlew=Slewrate limit ilimit=current limit\nrail=output stage saturation voltage\nVos=offset voltage\nphimargin=phase margin\nen=equiv. input noise voltage density\nenk=equiv. input noise voltage density corner freq.\nin=equiv. input noise current density\nink=equiv. input noise current density corner freq.\nRin=Input resistance
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TEXT 1224 -296 Left 2 ;A two pole opamp with two internal nodes,\nslew rate limit and output voltage and current limit\nand a programable phase margin.\nAvol=DC gain GBW=GBW product\nSlew=Slewrate limit ilimit=current limit\nrail=output stage saturation voltage\nVos=offset voltage\nphimargin=phase margin\nen=equiv. input noise voltage density\nenk=equiv. input noise voltage density corner freq.\nin=equiv. input noise current density\nink=equiv. input noise current density corner freq.\nRin=Input resistance
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TEXT 904 528 Top 1 ;This example schematic is supplied for informational/educational purposes only.
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TEXT 152 -440 Left 2 ;This demonstrates the use of the symbol UniversalOpamp2(improved version to the UniversalOpamp). You set the SpiceModel to be\nhigher to simulate more aspects of opamp behavior. Level1 is merely a transconductance working into an R||C and doesn't use power\nfrom the supplies. Level2 adds slewrate, current and voltage limits. Level3a adds a second pole. Level3b adds a delay to the dominate\npole response. Noise is modeled at all levels.
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