seppl/LTSpiceXVII
0
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

initial commit

Browse Source
This commit is contained in:
Joseph Hopfmüller
2023-01-23 08:17:09 +01:00
commit 1d8dca1c6c
11733 changed files with 1219458 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
lib/sub/User/BSS138.cir Normal file
View File

@@ -0,0 +1,42 @@
* DIODES INCORPORATED AND ITS AFFILIATED COMPANIES AND SUBSIDIARIES (COLLECTIVELY, "DIODES")
* PROVIDE THESE SPICE MODELS AND DATA (COLLECTIVELY, THE "SM DATA") "AS IS" AND WITHOUT ANY
* REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, INCLUDING ANY WARRANTY OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE, ANY WARRANTY ARISING FROM COURSE OF DEALING OR COURSE OF
* PERFORMANCE, OR ANY WARRANTY THAT ACCESS TO OR OPERATION OF THE SM DATA WILL BE UNINTERRUPTED,
* OR THAT THE SM DATA OR ANY SIMULATION USING THE SM DATA WILL BE ERROR FREE. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL DIODES BE LIABLE FOR ANY DIRECT OR INDIRECT,
* SPECIAL, INCIDENTAL, PUNITIVE OR CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION WITH
* THE PRODUCTION OR USE OF SM DATA, HOWEVER CAUSED AND UNDER WHATEVER CAUSE OF ACTION OR THEORY
* OF LIABILITY BROUGHT (INCLUDING, WITHOUT LIMITATION, UNDER ANY CONTRACT, NEGLIGENCE OR OTHER
* TORT THEORY OF LIABILITY), EVEN IF DIODES HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES,
* AND DIODES' TOTAL LIABILITY (WHETHER IN CONTRACT, TORT OR OTHERWISE) WITH REGARD TO THE SM
* DATA WILL NOT, IN THE AGGREGATE, EXCEED ANY SUMS PAID BY YOU TO DIODES FOR THE SM DATA.
*ZETEX BSS138 Spice Model v2.0 Last Revised 5/4/07
*
.SUBCKT BSS138/ZTX 3 4 5
* Nodes D G S
M1 3 2 5 5 MOD1
RG 4 2 20
RL 3 5 6E6
C1 2 5 30E-12
C2 3 2 1E-12
C3 7 5 58E-12
D1 5 3 Dmod1
D2 6 3 Dmod2
Egs1 2 6 2 5 1
Egs2 8 5 2 5 1
S1 2 7 3 2 SMOD1a
S2 7 8 3 2 SMOD1b
.MODEL MOD1 NMOS VTO=1 RS=1.58 RD=0.0 IS=1E-15 KP=0.395
+CBD=53.5E-12 PB=1 LAMBDA=267E-6
.MODEL Dmod1 D IS=1.254E-13 N=1.0207 RS=0.222
.MODEL Dmod2 D CJO=40E-12
.MODEL SMOD1a VSWITCH RON=1e-2 ROFF=1e4 VON=-1 VOFF=1
.MODEL SMOD1b VSWITCH RON=1e-2 ROFF=1e4 VON=1 VOFF=-1
.ENDS
*
*$
*

63
lib/sub/User/LV_CRBP.01.cir Normal file
View File

@@ -0,0 +1,63 @@
* LED: OSLON Signal LV CRBP.01
* (c) 2023, OSRAM Opto Semiconductors GmbH. All rights reserved.
* Valid for Vf(binning) = 2.85 V and If(binning) = 350 mA
* Model is valid for junction temperature Tj=25 C only.
* VERSION: 6
.MODEL LV_CRBP.01_typ D
+ IS=3.223817631768205e-14
+ N=3.454960721622383
+ RS=0.5106691287355363
+ Tnom=25
+ mfg=OSRAM_OS
* Valid for bin '25' with Vf(binning) = 2.80 V and If(binning) = 350 mA
* Model is valid for junction temperature Tj=25 C only.
* VERSION: 6
.MODEL LV_CRBP.01_25-min D
+ IS=3.223817631764513e-14
+ N=3.454960721622244
+ RS=0.3874073653535948
+ Tnom=25
+ mfg=OSRAM_OS
* Valid for bin '25' with Vf(binning) = 2.92 V and If(binning) = 350 mA
* Model is valid for junction temperature Tj=25 C only.
* VERSION: 6
.MODEL LV_CRBP.01_25-mid D
+ IS=3.22381763176839e-14
+ N=3.454960721622387
+ RS=0.7445502224964462
+ Tnom=25
+ mfg=OSRAM_OS
* Valid for bin '25' with Vf(binning) = 3.05 V and If(binning) = 350 mA
* Model is valid for junction temperature Tj=25 C only.
* VERSION: 6
.MODEL LV_CRBP.01_25-max D
+ IS=3.223817631771053e-14
+ N=3.454960721622492
+ RS=1.101693079639287
+ Tnom=25
+ mfg=OSRAM_OS
* Valid for bin 'V5' with Vf(binning) = 2.67 V and If(binning) = 350 mA
* Model is valid for junction temperature Tj=25 C only.
* VERSION: 6
.MODEL LV_CRBP.01_V5-mid D
+ IS=3.223817631769233e-14
+ N=3.454960721622422
+ RS=0.03026450821072926
+ Tnom=25
+ mfg=OSRAM_OS
* Valid for bin 'V5' with Vf(binning) = 2.80 V and If(binning) = 350 mA
* Model is valid for junction temperature Tj=25 C only.
* VERSION: 6
.MODEL LV_CRBP.01_V5-max D
+ IS=3.223817631764513e-14
+ N=3.454960721622244
+ RS=0.3874073653535948
+ Tnom=25
+ mfg=OSRAM_OS

274
lib/sub/User/OPA377.cir Normal file
View File

@@ -0,0 +1,274 @@
*$
* OPAx377-Q1
*****************************************************************************
* (C) Copyright 2022 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer
*****************************************************************************
*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
*****************************************************************************
*
** Released by: Online Design Tools, Texas Instruments Inc.
* Part: OPAx377-Q1
* Date: 13OCT2022
* Model Type: ALL-IN-ONE
* EVM Order Number: N/A
* EVM Users Guide: N/A
* Datasheet: SBOS797A -MAY 2016-REVISED MAY 2016
*
* Model Version: Final 1.0
*
*****************************************************************************
*
* Updates:
*
* Final 1.0
* Released to web
*
*****************************************************************************
* Model Usage Notes:
* 1. MODEL FEATURES INCLUDE OUTPUT SWING, OUTPUT CURRENT
* THROUGH THE SUPPLY RAILS, RAIL-TO-RAIL OUTPUT STAGE,
* OUTPUT CURRENT LIMIT, OPEN LOOP GAIN AND PHASE WITH
* RL AND CL EFFECTS, SETTLING TIME, OVERLOAD RECOVERY
* TIME, SEPERATE COMMON MODE REJECTION WITH FREQUENCY
* EFFECTS FOR EACH INPUT REGION, OUTPUT IMPEDANCE VS
* FREQUENCY, POWER SUPPLY REJECTION WITH FREQUENCY
* EFFECTS, INPUT VOLTAGE NOISE WITH 1/F, INPUT CURRENT
* NOISE, INPUT BIAS CURRENT WITH TEMPERATURE EFFECTS,
* INPUT IMPEDANCE, INPUT COMMON MODE RANGE, SEPERATE
* INPUT OFFSET FOR EACH INPUT REGION, OFFSET TEMPERA-
* TURE EFFECTS, AND QUIESCENT CURRENT VS VOLTAGE AND
* TEMPERATURE.
* 2. SETTLING TIME IS FAIRLY ACCURATE FOR GAINS
* FROM 1 TO ABOUT 20 BUT RUNS LONG AT A GAIN OF 100.
* 3. FOR ACCURATE BIAS CURRENTS AT ROOM AND COLD
* SET THE SPICE ANALYSIS OPTIONS AS FOLLOWS :
* RELTOL 0.0001 TO 0.00001 AND GMIN 1E-13 TO 1E-14.
* SET BOTH OF THESE OPTIONS AS SMALL AS WILL ALLOW
* CONVERGANCE ON YOUR SIMULATOR.
* 4. MODEL TEMP RANGE IS -40 TO +125 DEG C.
* 5. OPAx377-Q1 model is available in single core(OPA377-Q1),
* dual core(OPA2377-Q1) and quad core(OPA4377-Q1).
*****************************************************************************
* PINOUT ORDER +IN -IN +V -V OUT
* PINOUT ORDER 3 4 5 2 1
.SUBCKT OPA377 3 4 5 2 1
*****************************************************************************
Q20 6 7 8 QNL
R3 9 10 2
R4 11 10 2
R10 7 12 100
R11 13 14 100
R12 14 5 21
R13 2 12 12.5
R17 15 16 21
R18 8 17 12.5
D5 1 5 DD
D6 2 1 DD
D7 18 0 DIN
D8 19 0 DIN
I8 0 18 0.1E-3
I9 0 19 0.1E-3
E2 8 0 2 0 1
E3 16 0 5 0 1
D9 20 0 DVN
D10 21 0 DVN
I10 0 20 0.2E-6
I11 0 21 0.2E-6
E4 22 4 20 21 0.065
G2 23 4 18 19 1E-6
E5 24 0 16 0 1
E6 25 0 8 0 1
E7 26 0 27 0 1
R30 24 28 1E6
R31 25 29 1E6
R32 26 30 1E6
R33 0 28 100
R34 0 29 100
R35 0 30 100
E10 23 31 30 0 0.15
R36 32 27 1E3
R37 27 33 1E3
C6 24 28 0.2P
C7 25 29 0.2E-12
C8 26 30 2E-12
E11 34 35 29 0 -0.055
E12 23 34 28 0 0.055
E14 36 8 16 8 0.5
D11 37 16 DD
D12 8 38 DD
M1 39 40 12 12 NOUT L=3U W=700U
M2 41 42 14 14 POUT L=3U W=400U
M3 43 43 15 15 POUT L=3U W=400U
M4 44 45 9 9 HVP L=3U W=600U
M5 46 47 11 11 HVP L=3U W=600U
M8 48 48 17 17 NOUT L=3U W=700U
R43 49 50 300
R44 51 52 300
G3 53 36 54 36 3.333E-4
R45 36 53 6E5
R46 8 44 2100
R47 8 46 2100
C13 44 46 1E-15
C14 23 0 6.5E-12
C15 22 0 6.5E-12
C16 1 0 30E-12
D13 52 6 DC
D14 55 50 DC
Q15 55 13 16 QPL
V18 31 56 280E-6
M19 57 58 59 59 PIN L=6U W=500U
I14 43 48 160E-6
E17 33 0 23 0 1
E18 32 0 4 0 1
M23 58 58 59 59 PIN L=6U W=500U
V21 57 10 0
R59 1 41 5
R60 39 1 5
J1 60 23 60 JC
J2 60 22 60 JC
J3 22 61 22 JC
J4 23 61 23 JC
C21 23 22 0.1E-12
E20 62 36 46 44 1
R62 62 54 1E4
C23 54 36 0.5E-12
G7 63 36 64 36 -1E-3
G8 36 65 64 36 1E-3
G9 36 66 48 8 1E-3
G10 67 36 16 43 1E-3
D17 67 63 DD
D18 65 66 DD
R66 63 67 1E11
R67 66 65 1E11
R68 67 16 1E3
R69 8 66 1E3
E23 16 49 16 67 1
E24 51 8 66 8 1
R70 65 36 1E11
R71 66 36 1E11
R72 36 67 1E11
R73 36 63 1E11
C27 42 41 7E-14
C28 39 40 7E-14
R74 2 5 1E6
G12 5 2 68 0 -3.3E-4
I20 0 69 1E-3
D20 69 0 DD
V24 69 68 0.71
R75 0 68 1E6
I21 5 2 660E-6
E25 70 0 1 0 1
G13 64 36 53 36 -3.2E-5
R77 36 64 4E7
C29 53 71 48E-12
C30 64 72 6E-12
R78 72 70 1
R79 71 70 5
R80 53 70 1E10
R81 64 70 2E11
D21 73 16 DD
D22 8 74 DD
V52 75 0 1
I63 0 76 1E-3
D23 76 0 DD
R307 0 76 10E6
V81 76 77 1.798
R308 0 77 20E6
E52 78 0 77 0 -0.875
R309 0 78 10E6
R310 79 78 10E6
M52 79 80 0 0 NEN L=2U W=1000U
V141 81 0 1
R311 81 80 1E6
M53 80 75 0 0 NEN L=2U W=100U
R312 0 77 20E6
G14 58 8 79 0 0.136E-3
D24 82 83 DL
V142 83 0 3
R313 0 82 1E8
G51 4 0 82 0 3.3E-11
I64 4 0 1.58E-13
G52 23 0 82 0 3.3E-11
I65 23 0 1.58E-13
R314 50 42 1
R315 52 40 1
C32 53 70 1E-15
G53 64 36 54 36 4.167E-5
R316 84 85 2
R317 84 86 2
R318 87 16 2100
R319 88 16 2100
E53 89 0 27 0 1
R320 89 90 1E6
R321 0 90 100
E54 91 92 90 0 1.5
C33 89 90 2E-12
V143 92 23 2E-3
G54 53 36 93 36 3.333E-4
R322 36 53 1E12
E55 94 36 88 87 1
R323 94 93 1E4
C34 93 36 0.5E-12
M54 87 95 85 85 HVN L=3U W=600U
M55 88 96 86 86 HVN L=3U W=600U
M56 97 97 8 8 NIN L=6U W=500U
M57 84 97 8 8 NIN L=6U W=500U
M58 97 98 99 99 PIN L=6U W=500U
R324 99 57 250
V144 16 98 0.97
G55 64 36 93 36 4.167E-5
V145 16 59 -1
V146 61 8 0.3
V147 16 60 0.3
R329 56 45 440
R330 96 22 440
R331 91 95 440
R332 47 22 440
E56 73 64 16 36 0.3
E57 64 74 36 8 0.3
E58 53 38 36 8 0.95
E59 37 53 16 36 0.95
C35 87 88 1E-15
C36 16 37 1E-15
C37 8 38 1E-15
C38 8 74 1E-15
C39 16 73 1E-15
R335 35 34 1E9
R336 34 23 1E9
R337 92 91 1E9
R338 31 23 1E9
E61 35 3 68 0 1.8E-4
R339 3 35 1E9
.MODEL DD D
.MODEL DC D IS=1E-13
.MODEL DVN D KF=1.05E-16 IS=1E-16
.MODEL DIN D
.MODEL DL D IS=0.95E-11 N=1.47 XTI=1.5
.MODEL JC NJF IS=1E-18
.MODEL QNL NPN IS=1E-13 XTI=18
.MODEL QPL PNP IS=1E-13 XTI=18
.MODEL PIN PMOS KP=200U VTO=-0.7
.MODEL NIN NMOS KP=200U VTO=0.7
.MODEL HVP PMOS KP=200U VTO=-0.7
.MODEL HVN NMOS KP=200U VTO=0.7
.MODEL NEN NMOS KP=200U VTO=0.5 IS=1E-18
.MODEL NOUT NMOS (LEVEL=3 PHI=0.7 TOX=2E-8 XJ=5E-7
+ TPG=1 VTO=0.7 DELTA=0.5 LD=1E-7 KP=2E-4 UO=650
+ THETA=0.1 GAMMA=0.5 NSUB=1E17 NFS=6E11 FC=0.5
+ VMAX=1E5 ETA=3E-6 KAPPA=10 PB=1 IS=1E-18)
.MODEL POUT PMOS (LEVEL=3 PHI=0.7 TOX=2E-8 XJ=5E-7
+ TPG=-1 VTO=-0.7 DELTA=0.5 LD=1E-7 KP=2E-4 UO=650
+ THETA=0.1 GAMMA=0.5 NSUB=1E17 NFS=6E11 FC=0.5
+ VMAX=1E5 ETA=3E-6 KAPPA=10 PB=1 IS=1E-18)
.ENDS OPAx377-Q1
* END MODEL OPAx377-Q1

43
lib/sub/User/TL081.cir Normal file
View File

@@ -0,0 +1,43 @@
* TL081 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS RELEASE 4.01 ON 06/16/89 AT 13:08
* (REV N/A) SUPPLY VOLTAGE: +/-15V
* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OUTPUT
* | | | | |
.SUBCKT TL081 1 2 3 4 5
*
C1 11 12 3.498E-12
C2 6 7 15.00E-12
DC 5 53 DX
DE 54 5 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY(5) VB VC VE VLP VLN 0 4.715E6 -5E6 5E6 5E6 -5E6
GA 6 0 11 12 282.8E-6
GCM 0 6 10 99 8.942E-9
ISS 3 10 DC 195.0E-6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX
J2 12 1 10 JX
R2 6 9 100.0E3
RD1 4 11 3.536E3
RD2 4 12 3.536E3
RO1 8 5 150
RO2 7 99 150
RP 3 4 2.143E3
RSS 10 99 1.026E6
VB 9 0 DC 0
VC 3 53 DC 2.200
VE 54 4 DC 2.200
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800.0E-18)
.MODEL JX PJF(IS=15.00E-12 BETA=270.1E-6 VTO=-1)
.ENDS


169
lib/sub/User/ad8276.cir Normal file
View File

@@ -0,0 +1,169 @@
* AD8276 SPICE Macro-model
* Description: Amplifier
* Generic Desc: iPolar, DiffAmp, Low Cost,low power, G=1
* Developed by:
* Revision History:
* 08/10/2012 - Updated to new header style
* 11/18/2013 - Added supply offsets to correct for output voltage swing
* 12/18/2014 - Nulled offsets as they broke model for single-supply operation, turned them into fine-trim values
*
* 1.3 (12/2014)
* Copyright 2012 by Analog Devices, Inc.
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
* END Notes
*
* Node assignments
+IN -IN Vcc Vee Out Ref Sense
*$
.subckt AD8276 Pin Nin Vpp Vnn out Ref Sense
*** Hack for correcting output swing
Vhh vcc vpp 0
Vhn Vee vnn 0.080
*** Internal Resistors
R63 Pin 1 Rideal 4.00E+04
R62 Nin 2 Rideal 4.00E+04
R61 Ref 1 Rideal 4.00E+04
R65 Sense 2 Rideal 4.00E+04
***Differential Stage
Q1 13 12 14 npn
Q2 17 2 16 npn
Rc1 98 13 Rideal 4.200E+00
Rc2 98 17 Rideal 4.200E+00
Re1 14 15 Rideal 4.148E+00
Re2 15 16 Rideal 4.148E+00
Ibias 15 51 1.00E+00
Dcmlim1 18 15 DQUIET
Vcmlim1 18 51 -0.074
***Voltage Noise Generation
HVnoise 9 7 Vvnoise 1
VVnoise 501 0 0
DVnoise 501 0 Dvnoise
RVnoise 501 0 3.37959E-06
***Current Noise Generation on +IN
FInoise1 12 0 VInoise1 1
VInoise1 502 0 0
DInoise1 502 0 DInoise1
RInoise1 502 0 287500
***Current Noise Generation on -IN
FInoise2 2 0 VInoise2 1
VInoise2 503 0 0
DInoise2 503 0 DInoise2
RInoise2 503 0 287500
***Common Mode Injection
Rcm1 1 601 Rideal 100Meg
Rcm2 2 601 Rideal 100Meg
Gcmr 0 602 601 75 1.00E-06
Rcmr1 602 603 Rideal 1Meg
Rcmr2 603 604 Rideal 3.162E+01
Lcmr 604 0 1.007E-03
Ecmr 10 9 603 0 1.000E+00
***Positive Power Supply Rejection
Epsr1 700 0 98 0 1
Rpsr1 700 701 Rideal 1.00E+02
Rpsr2 701 702 Rideal 1.000E-03
Lpsr1 702 0 3.979E-06
Epsr2 11 10 701 0 1
***Negative Power Supply Rejection
Epsr3 703 0 51 0 1
Rpsr3 703 704 Rideal 1.00E+02
Rpsr4 704 705 Rideal 1.000E-03
Lpsr2 705 0 5.305E-07
Epsr4 12 11 704 0 1
***Input Offset and Bias
Vos 1 7 1.000E-04
Ios 1 2 0.000E+00
***Input Impedance
Cinv 2 0 6.00E-13
Cninv 1 0 6.00E-13
***1st Gain and Slew limiting
Gslew 0 101 17 13 1.0000E+00
Rslew 101 0 Rideal 2.50E+02
Dslew1 101 102 DZENER
Dslew2 0 102 DZENER
***Second Gain and Dominant Pole with Output Voltage Limiting
Gp1 51 201 101 0 4.173E-08
Rp1 201 51 Rideal 3.032E+13
Cp1 201 51 1.50E-12
Vlim1 97 206 0.35
Dlim1 201 206 dquiet
Vlim2 207 52 0.35
Dlim2 207 201 dquiet
Esupref1 97 98 51 0 1
Esupref2 52 51 51 0 1
***Second Pole
Gp2 0 202 201 51 1.00E-03
Rp2 202 0 Rideal 1.00E+03
Cp2 202 0 3.1831E-11
***Third Pole
Gp3 0 203 202 0 1.00E-03
Rp3 203 0 Rideal 1.00E+03
Cp3 203 0 3.1831E-11
***Fourth Pole
Gp4 0 204 203 0 1.00E-03
Rp4 204 0 Rideal 1.00E+03
Cp4 204 0 1.59155E-16
***Fifth Pole
Gp5 0 205 204 0 1.00E-03
Rp5 205 0 Rideal 1.00E+03
Cp5 205 0 1.592E-16
***First Zero
Gz1 0 301 205 0 1.00E-03
Rz1 301 302 Rideal 1.00E+03
Lz1 302 0 1.061E-04
***Second Zero
Gz2 0 303 301 0 1.00E-03
Rz2 303 304 Rideal 1.00E+03
Lz2 304 0 1.592E-10
***Third Zero
Gz3 0 305 303 0 1.00E-03
Rz3 305 306 Rideal 1.00E+03
Lz3 306 0 1.59E-10
***Buffer
Gbuf 0 401 305 0 1.00E-04
Rbuf 401 0 Rideal 1.00E+04
***Output with current limiting
Eout 404 0 401 0 1.000E+00
Rout 404 405 RIDEAL 1.000E+00
Lout 405 406 1.00E-19
Cout 406 0 5.70E-11
Voutmon 406 4 0
Dout1 401 407 Dquiet
Vout1 407 406 -6.150E-01
Dout2 408 401 Dquiet
Vout2 406 408 -6.150E-01
Rsmall 4 out 1000
***Voltage reference generator
Eref1 98 0 Vcc 0 1
Eref2 51 0 Vee 0 1
Rref1 98 901 Rideal 100Meg
Rref2 901 51 Rideal 100Meg
Eref3 75 0 901 0 1
***Supply current correction
Iq Vcc Vee 0.00020
Fsup1 Vcc 0 Voutmon 1
*DZsup1 0 802 DZENER2
*Dsup1 Vcc 802 DQUIET
Fsup2 0 Vee Voutmon -1
*DZsup2 804 0 DZENER2
*Dsup2 804 Vee DQUIET
***models
.model Rideal res T_ABS=27
.model Rnoise res T_ABS=27
.model npn npn BF= 8333332.33333333
.model dquiet d
.model dvnoise d KF=980000
.model dinoise1 d KF=0.000576
.model dinoise2 d KF=0.000576
.model dzener d BV=38.9444143409777
.model dzener2 d BV=50
.ends

107
lib/sub/User/ad8603.cir Normal file
View File

@@ -0,0 +1,107 @@
* AD8603 SPICE Macro-model Typical Values
* Description: Amplifier
* Generic Desc: 1.8/5V, CMOS, OP, Low Pwr, RRIO, 1X
* Developed by: Soufiane Bendaoud, ADI Silicon Valley
* Revision History: 08/10/2012 - Updated to new header style
* 0.0
* Copyright 2003, 2012 by Analog Devices
*
* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License Statement.
*
* BEGIN Notes:
*
* Not Modeled:
*
* Parameters modeled include:
*
* END Notes
*
* Node Assignments
* noninverting input
* | inverting input
* | | positive supply
* | | | negative supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT AD8603 1 2 99 50 45
*
* INPUT STAGE
*
M1 14 7 8 8 PIX L=1E-6 W=42E-6
M2 16 2 8 8 PIX L=1E-6 W=42E-6
M3 17 7 10 10 NIX L=1E-6 W=42E-6
M4 18 2 10 10 NIX L=1E-6 W=42E-6
RC5 14 50 1E+5
RC6 16 50 1E+5
RC7 99 17 1E+5
RC8 99 18 1E+5
C1 14 16 0.8E-12
C2 17 18 0.8E-12
I1 99 8 4E-6
I2 10 50 4E-6
V1 99 9 0.3
V2 13 50 0.3
D1 8 9 DX
D2 13 10 DX
EOS 7 1 POLY(3) (22,98) (73,98) (81,98) 40E-6 1 1 1
IOS 1 2 0.05E-12
*
* CMRR 90dB, ZERO AT 15kHz, POLE AT 2MHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 0.5 0.5
CCM1 21 22 3.54E-10
RCM1 21 22 30000
RCM2 22 98 1
*
* PSRR=100dB, ZERO AT 300Hz
*
EPSY 98 72 POLY(1) (99,50) 0 1
CPS3 72 73 5.30E-9
RPS3 72 73 100E+3
RPS4 73 98 1
*
*
* VOLTAGE NOISE REFERENCE OF 20nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN 81 98 VN1 20
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY 99 50 (99,50) 1.9E-6
EVP 97 98 POLY(1) (99,50) -0.6 0.5
EVN 51 98 POLY(1) (50,99) 0.6 0.5
*
* GAIN STAGE
*
G1 98 30 POLY(2) (14,16) (17,18) 0 1.25E-5 1.25E-5
R1 30 98 4.69e7
CF 45 30 50E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5 45 46 99 99 POX L=1E-6 W=1.61E-3
M6 45 47 50 50 NOX L=1E-6 W=2.15E-3
EG1 99 46 POLY(1) (98,30) 0.3778 1
EG2 47 50 POLY(1) (30,98) 0.3771 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,RD=0)
.MODEL NOX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,RD=0)
.MODEL PIX PMOS (LEVEL=2,KP=10E-6,VTO=-0.328,LAMBDA=0.01,Kf=10E-35,AF=1,TOX=100E-3)
.MODEL NIX NMOS (LEVEL=2,KP=10E-6,VTO=+0.328,LAMBDA=0.01,KF=10E-35,AF=1,TOX=100E-3)
.MODEL DX D(IS=1E-14,RS=5)
.ENDS