initial commit
This commit is contained in:
Joseph Hopfmüller
493
lib/sub/AD8253.lib
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493
lib/sub/AD8253.lib
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@@ -0,0 +1,493 @@
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* AD8253 SPICE Macromodel Rev H. 11/2021
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* Function: PGIA
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* Description:
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* This spice model covers the AD8253 Programmable Gain Instrumentation Amplifier (PGIA).
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* Gain options are 1, 10, 100, and 1000
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* Revision History:
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* Rev D. Prior releases, 5/2011
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* Rev E. 10/2013 - Relocates .ends for AD8253 subcircuit to before the digital section to
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* accommodate spice errors in some SPICE packages. (Where Sub circuit nesting is not allowed)
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* Rev F. 7/2015 - Replace flipflops and gates with equivalent MOSFET circuit to package the model without any more additional subcircuit.
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* Rev G. 9/2018 - Fixed Gain mode bug on LTSPICE platform.
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* Rev. H 11/2021 - Fixed input bias current.
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* Developed by: ADI
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*
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* Spice model Copyright 2013 Analog Devices Inc
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*
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* Temperature variations for the AD8250 are NOT included
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* in this model.
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*
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* Voltage Noise parameters for this model will closely model
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* typical AD8253 characteristics. Current Noise parameters
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* will be slightly higher than typical AD8253 characteristics
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* due to modeling limitations.
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*
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* Node Assignments
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* inverting input
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* | digital ground
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* | | negative supply
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* | | | A0 (digital gain control)
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* | | | | A1 (digital gain control)
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* | | | | | Digital Write
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* | | | | | | output
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* | | | | | | | positive supply
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* | | | | | | | | reference
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* | | | | | | | | | non-inverting input
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*$
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.SUBCKT AD8253 -IN DGND -Vs A0 A1 WR OUT +Vs REF +IN
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*
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*Power Supply
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*
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*Analog Power Supply
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R6 0 90 0.0001
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R5 0 AGND_1 0.0001
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I2 90 -Vs 0.0045
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I1 +Vs AGND_1 0.0046
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EV6 50 90 -Vs 90 1
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EV5 99 AGND_1 +Vs AGND_1 1
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*
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*Digital power supply
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VDD1 D99 0 5
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*
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*power consumption correction
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ICORR_P1 99 0 1.6m
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ICORR_N1 0 50 1.5m
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*
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*Internal Voltage Reference
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EREF1 98 0 40 0 1
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CREF1 40 0 5e-006
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RREF2 40 50 500000
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RREF1 99 40 500000
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*
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*
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*GAIN CONTROL
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*
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*gain of 1000
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Rfb9 104 116 49.95k
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Rfb8 116 115 100
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Rfb7 103 115 49.95k
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SGC16 116 72 A1int 0 SW1
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SGC15 72 Rg+ A0int 0 SW1
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SGC14 13 115 A1int 0 SW1
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SGC13 Rg- 13 A0int 0 SW1
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*
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*gain of 100
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Rfb6 104 112 19.8k
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Rfb5 112 111 400
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Rfb4 103 111 19.8k
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SGC12 114 Rg+ A0barint 0 SW1
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SGC11 112 114 A1int 0 SW1
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SGC10 6 111 A1int 0 SW1
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SGC9 Rg- 6 A0barint 0 SW1
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*
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*Gain of 10
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Rfb3 104 108 6750
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Rfb2 108 107 1.5k
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Rfb1 103 107 6750
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SGC8 110 Rg+ A0int 0 SW1
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SGC7 108 110 A1barint 0 SW1
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SGC6 5 107 A1barint 0 SW1
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SGC5 Rg- 5 A0int 0 SW1
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*
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*Gain of 1
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SGC4 104 134 A1barint 0 SW1
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SGC3 134 Rg+ A0barint 0 SW1
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SGC2 7 103 A1barint 0 SW1
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SGC1 Rg- 7 A0barint 0 SW1
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*
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*Switches for bypassing flipflops
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*If WR is less than -3V, flipflops are
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*bypassed and A0 and A1 are passed
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*directly through
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*
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SBP4 A1bar A1barint 0 WR SW2
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SBP3 A1 A1int 0 WR SW2
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MN2 A1bar A1 D99 D99 PMOS L=3e-006 W=1.5e-005
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MI2 A1bar A1 DGND DGND NMOS L=3e-006 W=6e-006
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SBP2 A0bar A0barint 0 WR SW2
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SBP1 A0 A0int 0 WR SW2
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MN1 A0bar A0 D99 D99 PMOS L=3e-006 W=1.5e-005
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MI1 A0bar A0 DGND DGND NMOS L=3e-006 W=6e-006
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*
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*
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*Switches for latched mode
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*falling clock edge data latches with
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*switches. If WR is higher than -1.5V,
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*switches pass latched data through, which
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*is latched on falling clock edge
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*
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Vcntlin1 cntlV 0 3
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*
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*DFF for A1
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*
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SLAT4 A1bLAT A1barint WR cntlV SW1
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SLAT3 A1LAT A1int WR cntlV SW1
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*
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MN70 FFWRb_1 WR D99 D99 PMOS L=3e-006 W=1.5e-005
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MI6 FFWRb_1 WR DGND DGND NMOS L=3e-006 W=6e-006
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MN69 FFDb_1 A1 D99 D99 PMOS L=3e-006 W=1.5e-005
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MI5 FFDb_1 A1 DGND DGND NMOS L=3e-006 W=6e-006
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MN68 A1bLAT A1LAT D99 D99 PMOS L=3e-006 W=1.5e-005
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MN67 A1bLAT 132 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN66 123 132 DGND DGND NMOS L=3e-006 W=6e-006
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MN65 A1bLAT A1LAT 123 DGND NMOS L=3e-006 W=6e-006
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MN64 132 FFWRb_1 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN63 132 130 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN62 122 130 DGND DGND NMOS L=3e-006 W=6e-006
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MN61 132 FFWRb_1 122 DGND NMOS L=3e-006 W=6e-006
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MN60 A1LAT A1bLAT D99 D99 PMOS L=3e-006 W=1.5e-005
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MN59 A1LAT 135 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN58 124 135 DGND DGND NMOS L=3e-006 W=6e-006
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MN57 A1LAT A1bLAT 124 DGND NMOS L=3e-006 W=6e-006
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MN56 135 FFWRb_1 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN55 135 131 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN54 121 131 DGND DGND NMOS L=3e-006 W=6e-006
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MN53 135 FFWRb_1 121 DGND NMOS L=3e-006 W=6e-006
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MN52 130 131 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN51 130 136 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN50 125 136 DGND DGND NMOS L=3e-006 W=6e-006
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MN49 130 131 125 DGND NMOS L=3e-006 W=6e-006
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MN48 136 WR D99 D99 PMOS L=3e-006 W=1.5e-005
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MN47 136 FFDb_1 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN46 120 FFDb_1 DGND DGND NMOS L=3e-006 W=6e-006
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MN45 136 WR 120 DGND NMOS L=3e-006 W=6e-006
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MN44 131 130 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN43 131 129 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN42 126 129 DGND DGND NMOS L=3e-006 W=6e-006
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MN41 131 130 126 DGND NMOS L=3e-006 W=6e-006
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MN40 129 WR D99 D99 PMOS L=3e-006 W=1.5e-005
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MN39 129 A1 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN38 119 A1 DGND DGND NMOS L=3e-006 W=6e-006
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MN37 129 WR 119 DGND NMOS L=3e-006 W=6e-006
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MN36 FFWRb WR D99 D99 PMOS L=3e-006 W=1.5e-005
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*
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*DFF for A0
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*
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SLAT2 A0bLAT A0barint WR cntlV SW1
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SLAT1 A0LAT A0int WR cntlV SW1
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*
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MI4 FFWRb WR DGND DGND NMOS L=3e-006 W=6e-006
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MN35 FFDb A0 D99 D99 PMOS L=3e-006 W=1.5e-005
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MI3 FFDb A0 DGND DGND NMOS L=3e-006 W=6e-006
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MN34 A0bLAT A0LAT D99 D99 PMOS L=3e-006 W=1.5e-005
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MN33 A0bLAT 4 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN32 91 4 DGND DGND NMOS L=3e-006 W=6e-006
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MN31 A0bLAT A0LAT 91 DGND NMOS L=3e-006 W=6e-006
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MN30 4 FFWRb D99 D99 PMOS L=3e-006 W=1.5e-005
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MN29 4 12 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN28 64 12 DGND DGND NMOS L=3e-006 W=6e-006
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MN27 4 FFWRb 64 DGND NMOS L=3e-006 W=6e-006
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MN26 A0LAT A0bLAT D99 D99 PMOS L=3e-006 W=1.5e-005
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MN25 A0LAT 127 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN24 94 127 DGND DGND NMOS L=3e-006 W=6e-006
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MN23 A0LAT A0bLAT 94 DGND NMOS L=3e-006 W=6e-006
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MN22 127 FFWRb D99 D99 PMOS L=3e-006 W=1.5e-005
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MN21 127 11 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN20 61 11 DGND DGND NMOS L=3e-006 W=6e-006
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MN19 127 FFWRb 61 DGND NMOS L=3e-006 W=6e-006
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MN18 12 11 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN17 12 128 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN16 118 128 DGND DGND NMOS L=3e-006 W=6e-006
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MN15 12 11 118 DGND NMOS L=3e-006 W=6e-006
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MN14 128 WR D99 D99 PMOS L=3e-006 W=1.5e-005
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MN13 128 FFDb D99 D99 PMOS L=3e-006 W=1.5e-005
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MN12 27 FFDb DGND DGND NMOS L=3e-006 W=6e-006
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MN11 128 WR 27 DGND NMOS L=3e-006 W=6e-006
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MN10 11 12 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN9 11 3 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN8 10 3 DGND DGND NMOS L=3e-006 W=6e-006
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MN7 11 12 10 DGND NMOS L=3e-006 W=6e-006
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MN6 3 WR D99 D99 PMOS L=3e-006 W=1.5e-005
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MN5 3 A0 D99 D99 PMOS L=3e-006 W=1.5e-005
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MN4 20 A0 DGND DGND NMOS L=3e-006 W=6e-006
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MN3 3 WR 20 DGND NMOS L=3e-006 W=6e-006
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*
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*Resistor fb Network, output op amp
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R4 201 OUT 10000
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R3 103 201 10000
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R2 202 REF 10000
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R1 104 202 10000
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*
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* OUTPUT AMPLIFIER
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*+PS perturbation stage output amp
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EPSC2 34 98 99 0 1
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RPSC4 98 37 0.29
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CPSC2 37 34 5.2e-010
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RPSC3 37 34 100000
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*
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*CM voltage stage output amp
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ECMC3 109 98 +IN 98 1
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RCMC2 98 81 0.29
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CCMC1 81 113 2.5e-010
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RCMC1 81 113 100000
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ECMC2 113 109 -IN 98 1
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*
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*output stage output amp
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VMO9 100 OUT 0
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VMO8 102 50 0
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VMO7 99 101 0
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ROUT6 102 100 10
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ROUT5 100 101 10
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GOUT6 102 100 95 50 0.1
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GOUT5 100 101 99 95 0.1
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*
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*Current limiting output amp
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VILIM6 97 100 0.415
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VILIM5 100 96 0.415
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DILIM6 97 95 DIODE4
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DILIM5 95 96 DIODE3
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*
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*Supply current adjustment output amp
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FADJ4 0 99 VLIM6 1
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FADJ3 50 0 VLIM5 1
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*
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*voltage limiting circuitry output amp
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VLIM6 99 92 1.96
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VLIM5 93 50 2.1
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DOUT6 93 89 DIODE6
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DOUT5 89 92 DIODE5
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*
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*Intermediate gain stage output amp
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RP6 98 95 1000
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GP5 95 98 89 98 0.001
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CP4 95 98 1e-011
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*
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*Gain stage with dominant pole = 13 Hz output amp
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GP6 89 98 52 83 1
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CP3 89 98 2.1e-007
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RP5 98 89 10000000
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*
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*-PS perturbation output amp
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EPSC1 88 98 50 0 1
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RPSC2 87 88 100000
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CPSC1 87 88 2e-008
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RPSC1 98 87 0.39
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*
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*Voltage Noise stage output amp
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VN3 86 98 0.618
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DN3 86 85 DIODE1
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RNOI6 98 85 0.0004
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VMEASC1 85 98 0
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F3 84 98 VMEASC1 1
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RNOI5 98 84 1
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*
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*Offset V, CM, PS, voltage noise introduction
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D6 202 99 DIODE2
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D5 50 202 DIODE2
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EPSRC_P1 202 82 37 98 1
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VOSC1 80 79 0.0006425
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ENOISC1 106 80 84 98 1
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ECMC1 82 106 81 98 1
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EPSRC_N1 201 117 87 98 1
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VPSRC1 117 78 5.85e-005
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*
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*Input stage output amplifier
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Q5 52 78 133 PNP
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Q6 83 79 55 PNP
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RC6 50 52 5750
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RC5 50 83 5750
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RE6 59 133 175
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RE5 59 55 175
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IBIASC1 99 59 0.001
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CC1 52 83 7e-013
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*
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*COMP AMPLIFIER 2
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*
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||||
*Output stage comp amp 2
|
||||
VMO6 68 104 0
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VMO5 70 50 0
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||||
VMO4 99 69 0
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||||
ROUT4 70 68 10
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||||
ROUT3 68 69 10
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||||
GOUT4 70 68 65 50 0.1
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||||
GOUT3 68 69 99 65 0.1
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||||
*
|
||||
*Current limiting comp amp 2
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||||
VILIM4 67 68 0.415
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||||
VILIM3 68 66 0.415
|
||||
DILIM4 67 65 DIODE4
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||||
DILIM3 65 66 DIODE3
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||||
*
|
||||
*Voltage limiting circuitry comp amp 2
|
||||
VLIM4 99 62 1.5
|
||||
VLIM3 63 50 1.75
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||||
DOUT4 63 60 DIODE6
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||||
DOUT3 60 62 DIODE5
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||||
*
|
||||
*Supply Current adjustment amp2
|
||||
FADJ6 50 0 VLIM3 1
|
||||
FADJ5 0 99 VLIM4 1
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||||
*
|
||||
*Gain stage with dominant pole=0.8Hz comp amp 2
|
||||
GP4 60 98 44 56 1
|
||||
RP3 98 60 10000000
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||||
CP2 60 98 5e-008
|
||||
*
|
||||
*Intermediate gain stage comp amp 2
|
||||
GP3 65 98 60 98 0.001
|
||||
RP4 98 65 1000
|
||||
*
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||||
*+PS Perturbation stage comp amp 2
|
||||
EPSB1 77 98 99 0 1
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||||
RPSB2 74 77 100000
|
||||
CPSB1 74 77 1e-017
|
||||
RPSB1 98 74 0.1
|
||||
*
|
||||
*Voltage noise stage comp amp 2
|
||||
VN2 58 98 0.623
|
||||
DN2 58 57 DIODE1
|
||||
RNOI4 98 57 0.000135
|
||||
VMEASB1 57 98 0
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||||
F2 51 98 VMEASB1 1
|
||||
RNOI3 98 51 1
|
||||
*
|
||||
*Common mode voltage stage comp amp 2
|
||||
ECMB3 73 98 -IN 98 1
|
||||
RCMB2 98 76 0.19
|
||||
*RCMB2 98 76 0.05
|
||||
CCMB1 76 54 5e-011
|
||||
RCMB1 76 54 100000
|
||||
ECMB2 54 73 +IN 98 1
|
||||
*
|
||||
*CM, +PS, Noise introduction
|
||||
D4 +IN 99 DIODE2
|
||||
D3 50 +IN DIODE2
|
||||
ECMB1 +IN 1 76 98 1
|
||||
EPSRB1 75 49 74 98 1
|
||||
ENOISB1 1 75 51 98 1
|
||||
*
|
||||
*Bias Current Compensation
|
||||
FBIASCMPB1 +IN 0 VBIASMONB1 0.9988
|
||||
VBIASMONB1 49 48 0
|
||||
IBIASP +IN 0 8.68375u
|
||||
*
|
||||
*Input stage compare amplifier 2
|
||||
Q3 44 Rg+ 43 PNP
|
||||
Q4 56 48 45 PNP
|
||||
RC4 47 44 5000
|
||||
RC3 47 56 5000
|
||||
RE4 46 43 415
|
||||
RE3 46 45 415
|
||||
IBIASB1 99 46 0.001
|
||||
VADJB1 50 47 1.5
|
||||
*
|
||||
*COMP AMPLIFIER 1
|
||||
*Output stage comp amp 1
|
||||
VMO3 39 103 0
|
||||
VMO2 41 50 0
|
||||
VMO1 99 42 0
|
||||
ROUT2 41 39 10
|
||||
ROUT1 39 42 10
|
||||
GOUT2 41 39 36 50 0.1
|
||||
GOUT1 39 42 99 36 0.1
|
||||
*
|
||||
*Current limiting comp amp 1
|
||||
VILIM2 38 39 0.415
|
||||
VILIM1 39 35 0.415
|
||||
DILIM2 38 36 DIODE4
|
||||
DILIM1 36 35 DIODE3
|
||||
*
|
||||
*Supply current adjustment comp amp 1
|
||||
FADJ2 0 99 VLIM2 1
|
||||
FADJ1 50 0 VLIM1 1
|
||||
*
|
||||
*Voltage limiting circuitry comp amp 1
|
||||
VLIM2 99 29 1.5
|
||||
VLIM1 33 50 1.75
|
||||
DOUT2 33 32 DIODE6
|
||||
DOUT1 32 29 DIODE5
|
||||
*
|
||||
*Intermediate gain stage comp amp 1
|
||||
GP1 36 98 32 98 0.001
|
||||
RP2 98 36 1000
|
||||
*
|
||||
*Gain stage with dominant pole=0.8Hz comp amp 1
|
||||
GP2 32 98 18 16 1
|
||||
CP1 32 98 5e-008
|
||||
RP1 98 32 10000000
|
||||
*
|
||||
*-PS Perturbation stage comp amp 1
|
||||
EPSA1 31 98 50 0 1
|
||||
RPSA2 30 98 0.15
|
||||
CPSA1 31 30 4.5e-010
|
||||
RPSA1 31 30 100000
|
||||
*
|
||||
*Voltage noise stage comp amp 1
|
||||
VN1 26 98 0.623
|
||||
DN1 26 24 DIODE1
|
||||
RNOI2 98 24 0.000135
|
||||
VMEASA1 24 98 0
|
||||
F1 28 98 VMEASA1 1
|
||||
RNOI1 98 28 1
|
||||
*
|
||||
* noise, -PS offset V introduction
|
||||
D2 -IN 99 DIODE2
|
||||
D1 50 -IN DIODE2
|
||||
VPSRA_N1 23 A9 0.0001408
|
||||
EPSRA_N1 Rg- 23 98 30 1
|
||||
VOSA1 25 19 0.000158
|
||||
ENOISA1 -IN 25 28 98 1
|
||||
*
|
||||
*Bias Current Compensation
|
||||
FBIASCMPA1 -IN 0 VBIASMONA1 0.9988
|
||||
VBIASMONA1 19 2 0
|
||||
IBIASN -IN 0 8.688756u
|
||||
*
|
||||
*Input stage compare amplifier 1
|
||||
Q1 18 A9 15 PNP
|
||||
Q2 16 2 8 PNP
|
||||
RC2 21 18 5000
|
||||
RC1 21 16 5000
|
||||
RE2 22 15 415
|
||||
RE1 22 8 415
|
||||
IBIASA1 99 22 0.001
|
||||
VADJA1 50 21 1.5
|
||||
*
|
||||
.model PMOS pmos
|
||||
+ (
|
||||
+ Level=2 VTO=-0.738861 KP=2.7e-005 GAMMA=0.58 PHI=0.6 LAMBDA=0.0612279
|
||||
+ PB=0.64 CGSO=4.3e-010 CGDO=4.3e-010 RSH=120.6 CJ=0.0005 MJ=0.5052
|
||||
+ CJSW=1.349e-010 MJSW=0.2417 TOX=2e-007 LD=1.5e-007 U0=261.977
|
||||
+ NSUB=4.3318e+015 TPG=-1 NSS=100000000000 DELTA=1.79192 UEXP=0.323932
|
||||
+ UCRIT=65719.8 VMAX=25694 XJ=2.5e-007 NEFF=1.001 NFS=1000000000000
|
||||
+ )
|
||||
.model NMOS nmos
|
||||
+ (
|
||||
+ Level=2 VTO=0.743469 KP=8.00059e-005 GAMMA=0.543 PHI=0.6 LAMBDA=0.0367072
|
||||
+ PB=0.58 CGSO=4.3e-010 CGDO=4.3e-010 RSH=70 CJ=0.0003 MJ=0.6585
|
||||
+ CJSW=8e-010 MJSW=0.2402 TOX=2e-007 LD=1.5e-007 U0=655.881 NSUB=5.36726e+015
|
||||
+ TPG=1 NSS=100000000000 DELTA=2.39824 UEXP=0.157282 UCRIT=31443.8
|
||||
+ VMAX=55260.9 XJ=2.5e-007 NEFF=1.001 NFS=1000000000000
|
||||
+ )
|
||||
.model DIODE4 D
|
||||
+ (
|
||||
+ IS=5e-012
|
||||
+ )
|
||||
.model DIODE3 D
|
||||
+ (
|
||||
+ IS=5e-012
|
||||
+ )
|
||||
.model DIODE6 D
|
||||
+ (
|
||||
+ IS=5e-012
|
||||
+ )
|
||||
.model DIODE5 D
|
||||
+ (
|
||||
+ IS=5e-012
|
||||
+ )
|
||||
.model DIODE1 D
|
||||
+ (
|
||||
+ KF=2e-010 AF=1.5
|
||||
+ )
|
||||
.model DIODE2 D
|
||||
+ (
|
||||
+ IS=1e-016
|
||||
+ )
|
||||
.model PNP PNP
|
||||
+ (
|
||||
+ Level=1 VAF=100
|
||||
+ )
|
||||
.model sw1 vswitch(Von=1.5 Voff=1.2 Ron=0.01 Roff=100000000)
|
||||
.model sw2 vswitch(Von=3 Voff=2.7 Ron=0.01 Roff=100000000)
|
||||
.ENDS AD8253
|
||||
|
||||
Reference in New Issue
Block a user