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This commit is contained in:
Joseph Hopfmüller
2023-01-23 08:17:09 +01:00
commit 1d8dca1c6c
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examples/jigs/MAX4128.asc Normal file
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Version 4
SHEET 1 1720 800
WIRE 560 256 304 256
WIRE 64 288 64 272
WIRE 432 352 432 320
WIRE 304 368 304 256
WIRE 400 368 304 368
WIRE 560 384 560 256
WIRE 560 384 464 384
WIRE 656 384 560 384
WIRE 64 400 64 368
WIRE 64 400 32 400
WIRE 400 400 304 400
WIRE 32 416 32 400
WIRE 560 416 560 384
WIRE 656 432 656 384
WIRE 64 448 64 400
WIRE 432 448 432 416
WIRE 304 496 304 400
WIRE 560 528 560 496
WIRE 656 528 656 496
WIRE 64 544 64 528
WIRE 304 592 304 576
FLAG 656 384 OUT
FLAG 64 272 Vcc
FLAG 64 544 Vee
FLAG 432 320 Vcc
FLAG 432 448 Vee
FLAG 32 416 0
FLAG 304 592 0
FLAG 560 528 0
FLAG 304 400 IN
FLAG 656 528 0
SYMBOL voltage 64 432 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 2.5
SYMBOL voltage 64 272 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 2.5
SYMBOL res 544 400 R0
SYMATTR InstName RL
SYMATTR Value 100k
SYMBOL voltage 304 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50m 100k)
SYMBOL cap 640 432 R0
SYMATTR InstName CL
SYMATTR Value 10p
SYMBOL MAX4128 432 320 R0
SYMATTR InstName U1
TEXT 14 628 Left 2 !.tran 10u