seppl/LTSpiceXVII
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This commit is contained in:
Joseph Hopfmüller
2023-01-23 08:17:09 +01:00
commit 1d8dca1c6c
11733 changed files with 1219458 additions and 0 deletions
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examples/jigs/LTC7000.asc Normal file
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Version 4
SHEET 1 2608 1256
WIRE 832 -448 736 -448
WIRE 912 -448 832 -448
WIRE 928 -448 912 -448
WIRE 1040 -448 1008 -448
WIRE 1152 -448 1040 -448
WIRE 1344 -448 1248 -448
WIRE 1440 -448 1344 -448
WIRE 1536 -448 1440 -448
WIRE 1664 -448 1536 -448
WIRE 1808 -448 1664 -448
WIRE 736 -432 736 -448
WIRE 1536 -432 1536 -448
WIRE 1664 -432 1664 -448
WIRE 1808 -432 1808 -448
WIRE 2064 -416 1856 -416
WIRE 2176 -416 2144 -416
WIRE 912 -384 912 -448
WIRE 1040 -384 1040 -448
WIRE 1440 -384 1440 -448
WIRE 1872 -368 1856 -368
WIRE 928 -352 912 -384
WIRE 1024 -352 1040 -384
WIRE 1232 -352 1232 -400
WIRE 1232 -352 1136 -352
WIRE 736 -336 736 -352
WIRE 928 -336 928 -352
WIRE 1024 -336 1024 -352
WIRE 1136 -336 1136 -352
WIRE 1232 -336 1232 -352
WIRE 1344 -336 1344 -448
WIRE 1536 -336 1536 -368
WIRE 1664 -336 1664 -352
WIRE 1808 -336 1808 -352
WIRE 832 -256 832 -448
WIRE 864 -256 832 -256
WIRE 1440 -240 1440 -320
WIRE 1440 -240 1376 -240
WIRE 832 -192 832 -256
WIRE 864 -192 832 -192
WIRE 1440 -144 1376 -144
WIRE 1488 -144 1440 -144
WIRE 1568 -144 1552 -144
WIRE 1440 -128 1440 -144
WIRE 864 -112 832 -112
WIRE 1440 -32 1440 -48
WIRE 1440 -32 1376 -32
WIRE 784 48 768 48
WIRE 864 48 848 48
WIRE 1248 128 1248 112
WIRE 1120 144 1120 112
WIRE 976 176 976 112
WIRE 1248 224 1248 208
WIRE 976 288 976 256
FLAG 736 -336 0
FLAG 976 288 0
FLAG 1536 -336 0
FLAG 1664 -336 0
FLAG 736 -448 IN
FLAG 1808 -448 OUT
FLAG 1120 144 0
FLAG 1248 224 0
FLAG 768 48 0
FLAG 1568 -144 0
FLAG 1808 -336 0
FLAG 1872 -368 0
FLAG 2176 -416 0
FLAG 832 -112 0
SYMBOL voltage 736 -448 R0
SYMATTR InstName V1
SYMATTR Value 135
SYMBOL voltage 976 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 13 100 Left 2
SYMATTR Value PULSE(0 3.3 50m 10n 10n 50m 100m 1)
SYMATTR InstName V2
SYMBOL nmos 1152 -400 R270
WINDOW 0 53 42 VTop 2
WINDOW 3 -7 79 VLeft 2
SYMATTR InstName M1
SYMATTR Value BSC320N20NS3
SYMBOL cap 1520 -432 R0
WINDOW 3 39 36 Left 2
WINDOW 39 20 65 Left 2
SYMATTR Value 1<>
SYMATTR SpiceLine Rser=7m
SYMATTR InstName C1
SYMBOL res 1648 -448 R0
SYMATTR InstName R1
SYMATTR Value 13.5
SYMBOL cap 1424 -384 R0
SYMATTR InstName C2
SYMATTR Value 0.1<EFBFBD>
SYMBOL res 1232 112 R0
SYMATTR InstName R2
SYMATTR Value 150K
SYMBOL res 1424 -144 R0
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL cap 848 32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1n
SYMBOL res 912 -432 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 5m
SYMBOL cap 1488 -128 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C4
SYMATTR Value 1<>
SYMBOL voltage 2048 -416 R270
WINDOW 3 -32 56 VBottom 2
WINDOW 0 32 56 VTop 2
SYMATTR Value PWL(0 0 60m 0 +1u 1 +10m 1 +1u 0)
SYMATTR InstName V3
SYMBOL sw 1808 -336 R180
WINDOW 0 -17 96 Right 2
WINDOW 3 -32 -3 Right 2
SYMATTR InstName S1
SYMBOL LTC7000 1120 -112 R0
SYMATTR InstName U1
TEXT 1832 -264 Center 2 ;Short load with 10mohm\nto test current limit.
TEXT 1448 136 Left 2 !.tran 100m startup\n.model SW SW(Ron=10m Roff=1G Vt=0.5 Vh=-0.3)