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This commit is contained in:
Joseph Hopfmüller
117
examples/jigs/LT8722.asc
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117
examples/jigs/LT8722.asc
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Version 4
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SHEET 1 1684 936
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WIRE -1264 -32 -1328 -32
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WIRE -1200 -32 -1264 -32
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WIRE -944 -32 -1200 -32
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WIRE -1328 0 -1328 -32
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WIRE -944 0 -944 -32
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WIRE -1200 64 -1200 -32
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WIRE -1152 64 -1200 64
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WIRE -736 64 -752 64
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WIRE -656 64 -672 64
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WIRE -1328 96 -1328 80
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WIRE -1152 160 -1456 160
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WIRE -640 160 -752 160
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WIRE -528 160 -640 160
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WIRE -496 160 -528 160
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WIRE -640 176 -640 160
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WIRE -1456 192 -1456 160
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WIRE -496 208 -496 160
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WIRE -1280 256 -1360 256
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WIRE -1152 256 -1200 256
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WIRE -720 256 -752 256
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WIRE -720 272 -720 256
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WIRE -1456 288 -1456 272
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WIRE -1360 288 -1360 256
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WIRE -1152 352 -1264 352
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WIRE -720 352 -720 336
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WIRE -720 352 -752 352
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WIRE -656 352 -720 352
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WIRE -528 352 -576 352
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WIRE -496 352 -496 288
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WIRE -496 352 -528 352
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WIRE -496 368 -496 352
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WIRE -1360 384 -1360 368
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WIRE -1264 384 -1264 352
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WIRE -1152 448 -1168 448
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WIRE -624 448 -496 352
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WIRE -624 448 -752 448
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WIRE -496 448 -496 432
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WIRE -1264 480 -1264 464
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WIRE -1152 544 -1168 544
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WIRE -1152 640 -1168 640
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WIRE -736 640 -752 640
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WIRE -944 720 -944 704
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FLAG -496 448 0
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FLAG -944 720 0
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FLAG -1264 480 0
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FLAG -528 160 TEC+
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FLAG -528 352 TEC-
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FLAG -1168 448 0
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FLAG -1168 544 0
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FLAG -1168 640 0
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FLAG -1360 384 0
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FLAG -1456 288 0
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FLAG -1328 96 0
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FLAG -1264 -32 IN
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FLAG -656 64 0
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FLAG -640 240 0
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FLAG -736 640 0
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SYMBOL cap -512 368 R0
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SYMATTR Value 1<>
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SYMATTR InstName C2
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SYMATTR SpiceLine Rser=2m
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SYMBOL voltage -1264 368 M0
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WINDOW 123 24 138 Left 2
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WINDOW 39 24 117 Left 2
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SYMATTR InstName V2
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SYMATTR Value PWL(0 2.5 +80u 2.5 +4m 0 +4m 2.5 +4m 0)
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SYMBOL res -512 192 R0
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SYMATTR InstName RTEC
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SYMATTR Value 3
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SYMBOL ind -672 368 R270
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WINDOW 0 32 56 VTop 2
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WINDOW 3 5 56 VBottom 2
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SYMATTR InstName L1
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SYMATTR Value 1<>
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SYMBOL cap -736 272 R0
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WINDOW 0 35 17 Left 2
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WINDOW 3 34 49 Left 2
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SYMATTR InstName C1
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SYMATTR Value 0.1<EFBFBD>
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SYMBOL voltage -1360 272 R0
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WINDOW 123 24 138 Left 2
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WINDOW 39 24 117 Left 2
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WINDOW 3 -322 100 Left 2
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SYMATTR Value PULSE(0 3.3 2.5m 10n 1n 1 2 1)
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SYMATTR InstName V3
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SYMBOL res -1184 240 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName R1
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SYMATTR Value 20k
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SYMBOL voltage -1456 176 R0
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WINDOW 123 24 138 Left 2
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WINDOW 39 24 117 Left 2
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SYMATTR InstName V4
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SYMATTR Value 2.7
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SYMBOL voltage -1328 -16 R0
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WINDOW 123 24 138 Left 2
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WINDOW 39 24 117 Left 2
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SYMATTR InstName V5
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SYMATTR Value 15
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SYMBOL cap -736 48 M90
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WINDOW 0 0 32 VBottom 2
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WINDOW 3 32 32 VTop 2
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SYMATTR InstName C3
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SYMATTR Value 1<>
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SYMBOL cap -656 176 R0
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WINDOW 3 34 45 Left 2
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WINDOW 0 36 10 Left 2
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SYMATTR Value 150n
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SYMATTR InstName C4
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SYMATTR SpiceLine Rser=2m
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SYMBOL LT8722 -944 352 R0
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SYMATTR InstName U2
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TEXT -1032 768 Left 2 !.tran 12.5m startup
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TEXT -288 24 Left 2 ;Please read the following notes carefully, since the model presents different user interface\nthan the real part does.\n \n(1) All communication and memory address related functions and pins are not modeled. \n \n(2) Changes to all parameter values during the simulation running will not be in effect, unless the\nsimulation is stopped and restarted. This is different from the operation of the part, which will\n respond to the commanded changes while running. \n \n(3) MOSI is used as input for SPIS_DAC. Since LTspice cannot convert digital data into analog,\nthe SPIS_DAC signal must be converted first into equivalent analog voltage before starting the\nsimulation.\nExample, 0xFF000000 = 2.5V while 0x00000000 = 1.25V and 0x00FFFFFF = 30nV.\n \n(4) The following parameters can be defined, by right-clicking the symbol of LT8722. Different \nnomenclature from the datasheet is adopted here. If any value of these parameters are set beyond \nthe scope described in the datasheet, the resulting simulation outcomes are not meaningful.\n \n ENABLE_REQ -- 1 or 0, sets the ENABLE_REQ command to either 1 or 0.\n SWEN_REQ -- 1 or 0, sets the SWEN_REQ command to either 1 or 0.\n VCC_VREG -- 1 or 0, set the regulation voltage of Vcc pin 1 for 3.4V, 0 for 3.1V\n FREQ_SET -- 0 to 7, set the switching frequency of the Buck converter, 0 --> 500Khz, 1 --> 1Mhz\n 2 --> 1.5Mhz, 3 --> 2Mhz, 4 --> 2.5Mhz and 5,6,7 --> 3Mhz.\n FREQ_ADJ -- 0 to 3, adjusts the switching frequency of the Buck converter +/- 15% above the \n set frequency,\n 0 --> 0%, 1 --> +15%, 2 --> -15%, and 3 --> 0%.\n SYS_DC -- selects the duty cycle control range,\n 0 --> 20% to 80%, 1 --> 15% to 85%, and 2, 3 --> 10% to 90%.\n DAC_ILIMP -- 0 to 462 where 0 corresponds to 6.8A while 462 to 637.44mA with 13.28mA per \n step.\n DAC_ILIMN -- 48 to 511 where 48 corresponds to -637.44mA while 511 to 6.8A with -13.28mA \n per step.\n OV_CLAMP -- 0 to 15, sets the positive output voltage limit, See details on the datasheet.\n UV_CLAMP -- 0 to 15, sets the negative output voltage limit. See details on the datasheet.\n VC_INT -- 0 to 7, sets the initial peak inductor current limit. See details on the datasheet.\n AMUX -- 0 to 15, selects which signal Aout pit will output. See details on the datasheet.\n AMUX_TEST -- 0 or 1, provides additonal setting for signal selection on Aout Pin,\n See details on the datasheet.
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