seppl/LTSpiceXVII
0
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

initial commit

Browse Source
This commit is contained in:
Joseph Hopfmüller
2023-01-23 08:17:09 +01:00
commit 1d8dca1c6c
11733 changed files with 1219458 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

164
examples/jigs/LT8277.asc Normal file
View File

@@ -0,0 +1,164 @@
Version 4
SHEET 1 1740 784
WIRE -96 -352 -112 -352
WIRE -16 -352 -96 -352
WIRE 64 -352 -16 -352
WIRE 256 -352 144 -352
WIRE 496 -352 336 -352
WIRE 736 -352 496 -352
WIRE 864 -352 800 -352
WIRE 928 -352 864 -352
WIRE 1024 -352 928 -352
WIRE 1040 -352 1024 -352
WIRE 928 -320 928 -352
WIRE 1040 -320 1040 -352
WIRE -112 -288 -112 -352
WIRE -16 -256 -16 -352
WIRE 240 -256 -16 -256
WIRE 368 -256 320 -256
WIRE 688 -256 448 -256
WIRE 736 -256 688 -256
WIRE 864 -256 864 -352
WIRE 864 -256 800 -256
WIRE 928 -208 928 -256
WIRE 1040 -208 1040 -240
WIRE 496 -192 496 -352
WIRE 64 -176 64 -352
WIRE 144 -176 144 -352
WIRE 240 -176 240 -256
WIRE 320 -176 320 -256
WIRE -112 -160 -112 -208
WIRE -16 -112 -16 -256
WIRE 0 -112 -16 -112
WIRE 416 -112 384 -112
WIRE 448 -112 416 -112
WIRE 688 -112 688 -256
WIRE 496 -64 496 -96
WIRE -16 -32 -16 -112
WIRE 0 -32 -16 -32
WIRE 416 -32 384 -32
WIRE 640 -32 416 -32
WIRE 688 16 688 -16
WIRE -96 48 -112 48
WIRE -16 48 -32 48
WIRE 0 48 -16 48
WIRE 864 48 864 -256
WIRE 864 48 384 48
WIRE -16 128 -16 48
WIRE 0 128 -16 128
WIRE 416 128 384 128
WIRE 448 128 416 128
WIRE 560 128 528 128
WIRE 672 128 624 128
WIRE 416 208 384 208
WIRE 592 208 496 208
WIRE 400 368 384 368
WIRE 416 368 400 368
WIRE 528 368 496 368
WIRE 96 448 96 432
WIRE 304 448 304 432
WIRE -16 480 -16 128
WIRE 592 480 592 208
WIRE 592 480 -16 480
FLAG -112 -160 0
FLAG 496 -64 0
FLAG 688 16 0
FLAG 928 -208 0
FLAG 1040 -208 0
FLAG 672 128 0
FLAG -112 48 0
FLAG 304 448 0
FLAG 96 448 0
FLAG 528 368 0
FLAG -96 -352 IN
FLAG 1024 -352 OUT
FLAG 400 368 RT
FLAG 416 128 VC
FLAG 416 -112 DRV1
FLAG 416 -32 DRV2
SYMBOL voltage -112 -304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 25
SYMBOL res 160 -368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10m
SYMBOL ind 240 -336 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10<31>
SYMBOL schottky 736 -336 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value RB085BM-90
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL nmos 448 -192 R0
SYMATTR InstName M1
SYMATTR Value BSC028N06LS3
SYMBOL res 336 -272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10m
SYMBOL ind 352 -240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 10<31>
SYMBOL schottky 736 -240 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value RB085BM-90
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL nmos 640 -112 R0
SYMATTR InstName M2
SYMATTR Value BSC028N06LS3
SYMBOL cap 912 -320 R0
WINDOW 0 36 7 Left 2
WINDOW 3 35 55 Left 2
WINDOW 123 37 32 Left 2
SYMATTR InstName C1
SYMATTR Value 10<31>
SYMATTR Value2 X5
SYMBOL res 544 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL cap 624 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 22n
SYMBOL res 512 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 100K
SYMBOL cap -32 32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 4.7<EFBFBD>
SYMBOL res 400 352 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 200K
SYMBOL LT8277 192 128 R0
WINDOW 39 -5 383 Center 2
WINDOW 40 -17 421 Bottom 2
SYMATTR InstName U2
SYMBOL res 1024 -336 R0
SYMATTR InstName RLOAD
SYMATTR Value 30.1
TEXT 80 576 Left 2 !.tran 200m startup
TEXT 736 80 Left 2 ;Variable definition\n \nCLKOUT --> Clock out Pin Phase, 0 for 45deg, 1 for 90deg\nCLKOUT_EN --> Enable Clock Out, 0 for Disable, 1 for Enable\nPH2_LL --> Phase 2 Light Load Enable, 0 for Disable, 1 for Enable\nSS --> Enables the 4x faster soft start, 0 for Disable, 1 for Enable\n \nt0, v0 to t9, v9 --> 10 pairs of PWL settings\n \nNote: All 10 pairs must be defined whether the programming features \n are used or not.\n Just make the remaining voltage setting at same level.\n \n t0 must not be lower than 200us, this is to ensure that the first \n command will not be ignored. During this time, the part is still \n initializing the Enable and INTVcc\n \n The time interval between 2 set points must not be lower than 3us\n to allow time for capturing the set value and not greater than 32ms\n else, the Watchdog Timer will expire (for FLOATED and HIGH modes)\n \n A pulse, used to represent a valid CRC is generated to reset \n the WDT in sync with the time set on t0 to t9. After t9, no more \n command can be sent and thus WDT expires after 32ms.\n \n Communication pins are not modeled.