initial commit

2023-01-23 08:17:09 +01:00
commit 1d8dca1c6c
11733 changed files with 1219458 additions and 0 deletions
--- a/examples/jigs/LT3041.asc
+++ b/examples/jigs/LT3041.asc
@@ -0,0 +1,153 @@
+Version 4
+SHEET 1 1976 696
+WIRE -816 -544 -912 -544
+WIRE -656 -544 -816 -544
+WIRE -912 -528 -912 -544
+WIRE -656 -528 -656 -544
+WIRE -816 -480 -816 -544
+WIRE -800 -480 -816 -480
+WIRE -496 -480 -512 -480
+WIRE -416 -480 -432 -480
+WIRE -912 -432 -912 -448
+WIRE -480 -384 -512 -384
+WIRE -480 -368 -480 -384
+WIRE 752 -352 48 -352
+WIRE -480 -288 -480 -304
+WIRE -480 -288 -512 -288
+WIRE -416 -288 -480 -288
+WIRE -288 -288 -336 -288
+WIRE -208 -288 -288 -288
+WIRE -144 -288 -208 -288
+WIRE -48 -288 -144 -288
+WIRE 48 -288 48 -352
+WIRE 48 -288 -48 -288
+WIRE 176 -288 48 -288
+WIRE -288 -272 -288 -288
+WIRE -144 -256 -144 -288
+WIRE -48 -256 -48 -288
+WIRE 48 -208 48 -288
+WIRE 176 -208 48 -208
+WIRE -880 -192 -912 -192
+WIRE -800 -192 -816 -192
+WIRE -432 -192 -512 -192
+WIRE -288 -192 -288 -208
+WIRE 736 -144 720 -144
+WIRE 784 -144 736 -144
+WIRE 880 -144 784 -144
+WIRE 944 -144 880 -144
+WIRE -432 -128 -432 -192
+WIRE -384 -128 -432 -128
+WIRE -144 -128 -144 -192
+WIRE -144 -128 -304 -128
+WIRE -48 -128 -48 -176
+WIRE -48 -128 -144 -128
+WIRE 176 -128 -48 -128
+WIRE 784 -112 784 -144
+WIRE 944 -112 944 -144
+WIRE -896 -96 -912 -96
+WIRE -800 -96 -816 -96
+WIRE -496 -96 -512 -96
+WIRE -432 -80 -432 -128
+WIRE 736 -64 736 -144
+WIRE 736 -64 720 -64
+WIRE 48 -48 48 -208
+WIRE 80 -48 48 -48
+WIRE 176 -48 160 -48
+WIRE 784 -16 784 -48
+WIRE 944 -16 944 -32
+WIRE -432 16 -432 0
+WIRE 416 32 416 16
+WIRE 512 32 512 16
+WIRE 640 32 640 16
+WIRE 752 32 752 -352
+WIRE 752 32 640 32
+WIRE 288 64 288 16
+WIRE 288 96 288 64
+WIRE 288 192 288 176
+FLAG 416 32 0
+FLAG 512 32 0
+FLAG 784 -16 0
+FLAG 880 -144 OutLDO
+FLAG -912 -96 0
+FLAG -912 -192 0
+FLAG -912 -432 0
+FLAG -416 -480 0
+FLAG -288 -192 0
+FLAG -432 16 0
+FLAG -912 -544 IN
+FLAG -496 -96 0
+FLAG 944 -16 0
+FLAG 288 192 0
+FLAG -208 -288 OutSw
+FLAG 288 64 vSET
+SYMBOL res 64 -64 M90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R1
+SYMATTR Value 200K
+SYMBOL cap 768 -112 R0
+WINDOW 40 24 36 Left 2
+SYMATTR InstName C2
+SYMATTR Value 10<31>x2
+SYMATTR SpiceLine Rser=5m
+SYMBOL res -800 -112 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R5
+SYMATTR Value 40.2K
+SYMBOL cap -816 -208 R90
+WINDOW 0 0 32 VBottom 2
+WINDOW 3 32 32 VTop 2
+SYMATTR InstName C3
+SYMATTR Value 1n
+SYMBOL voltage -912 -544 R0
+SYMATTR InstName V2
+SYMATTR Value 20
+SYMBOL cap -496 -464 R270
+WINDOW 0 32 32 VTop 2
+WINDOW 3 0 32 VBottom 2
+SYMATTR InstName C4
+SYMATTR Value 1<>
+SYMBOL ind -432 -272 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 5 56 VBottom 2
+SYMATTR InstName L1
+SYMATTR Value 15<31>
+SYMATTR SpiceLine Rser=3m
+SYMBOL cap -496 -368 R0
+SYMATTR InstName C5
+SYMATTR Value .22<EFBFBD>
+SYMBOL cap -304 -272 R0
+SYMATTR InstName C6
+SYMATTR Value 47<34>
+SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
+SYMBOL res -448 -96 R0
+SYMATTR InstName R7
+SYMATTR Value 7.68K
+SYMBOL LT8608 -656 -288 R0
+SYMATTR InstName U1
+SYMBOL res -288 -144 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName R6
+SYMATTR Value 2.21K
+SYMBOL res -64 -272 R0
+SYMATTR InstName R2
+SYMATTR Value 140K
+SYMBOL res 928 -128 R0
+SYMATTR InstName RLOAD
+SYMATTR Value 10
+SYMBOL voltage 288 80 R0
+WINDOW 123 0 0 Left 2
+WINDOW 39 24 124 Left 2
+SYMATTR SpiceLine Rser=100
+SYMATTR InstName V4
+SYMATTR Value PWL(0 0 500u 0 600u 3 700u 3 900u 4 900u 4 1m 4 1.2m 3)
+SYMBOL cap -160 -256 R0
+SYMATTR InstName C1
+SYMATTR Value 220p
+SYMBOL LT3041 416 -144 R0
+SYMATTR InstName U2
+TEXT 264 280 Left 2 !.tran 1.3m startup
+TEXT -1056 -280 Left 2 ;C3 reduced for fast\nstartup simulation
+TEXT -104 -496 Left 2 ;Switcher output (OutSw) programmed to be 1 volt\ngreater than LT3041 output (OutLDO)