initial commit

examples/jigs/ADP7182-2.5.asc

@@ -0,0 +1,46 @@
+Version 4
+SHEET 1 984 680
+WIRE 32 -48 -80 -48
+WIRE 112 -48 32 -48
+WIRE 432 -48 368 -48
+WIRE 544 -48 432 -48
+WIRE -80 -32 -80 -48
+WIRE 32 -32 32 -48
+WIRE 432 -32 432 -48
+WIRE 544 -32 544 -48
+WIRE -80 64 -80 48
+WIRE 32 64 32 32
+WIRE 432 64 432 32
+WIRE 544 64 544 48
+WIRE 112 144 32 144
+WIRE 32 160 32 144
+WIRE 32 256 32 240
+WIRE 240 256 240 208
+FLAG -80 64 0
+FLAG 32 64 0
+FLAG 432 64 0
+FLAG 32 256 0
+FLAG 240 256 0
+FLAG 544 64 0
+FLAG 32 -48 IN
+FLAG 432 -48 OUT
+SYMBOL cap 16 -32 R0
+SYMATTR InstName C1
+SYMATTR Value 2.2<EFBFBD>
+SYMBOL cap 416 -32 R0
+SYMATTR InstName C2
+SYMATTR Value 2.2<EFBFBD>
+SYMBOL voltage -80 -48 R0
+SYMATTR InstName V1
+SYMATTR Value -8
+SYMBOL voltage 32 144 M0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V2
+SYMATTR Value PULSE(0 2 200u 1n 1n 10m)
+SYMBOL res 528 -48 R0
+SYMATTR InstName R1
+SYMATTR Value 50
+SYMBOL ADP7182-2.5 240 48 R0
+SYMATTR InstName U1
+TEXT 528 248 Left 2 !.tran 1m