initial commit

examples/jigs/ADP7118-4.5.asc

@@ -0,0 +1,47 @@
+Version 4
+SHEET 1 1048 680
+WIRE 64 32 -32 32
+WIRE 96 32 64 32
+WIRE 384 32 352 32
+WIRE 448 32 384 32
+WIRE 544 32 448 32
+WIRE -32 48 -32 32
+WIRE 448 48 448 32
+WIRE 544 48 544 32
+WIRE 64 128 64 32
+WIRE 96 128 64 128
+WIRE -32 144 -32 128
+WIRE 448 144 448 112
+WIRE 544 144 544 128
+WIRE 16 224 0 224
+WIRE 96 224 80 224
+WIRE 384 224 384 32
+WIRE 384 224 352 224
+WIRE 224 304 224 288
+FLAG 224 304 0
+FLAG -32 144 0
+FLAG 0 224 0
+FLAG 544 144 0
+FLAG 448 144 0
+FLAG -32 32 IN
+FLAG 544 32 OUT
+SYMBOL cap 80 208 R90
+WINDOW 0 0 32 VBottom 2
+WINDOW 3 32 32 VTop 2
+SYMATTR InstName C2
+SYMATTR Value 4.7n
+SYMBOL voltage -32 32 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 5.5
+SYMBOL res 528 32 R0
+SYMATTR InstName Rload
+SYMATTR Value 30
+SYMBOL cap 432 48 R0
+SYMATTR InstName C1
+SYMATTR Value 2.2<EFBFBD>
+SYMATTR SpiceLine Rser=1.5m
+SYMBOL ADP7118-4.5 224 128 R0
+SYMATTR InstName U1
+TEXT 408 264 Left 2 !.tran 6m startup