initial commit

2023-01-23 08:17:09 +01:00
commit 1d8dca1c6c
11733 changed files with 1219458 additions and 0 deletions
--- a/examples/jigs/ADP5051_chan1_2.asc
+++ b/examples/jigs/ADP5051_chan1_2.asc
@@ -0,0 +1,259 @@
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+SYMATTR Value BSC080N03MS
+SYMBOL Digital\\schmitt -720 544 R0
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+WINDOW 123 26 118 Left 2
+WINDOW 39 26 146 Left 2
+SYMATTR InstName A1
+SYMATTR Value2 Vt=0.5 vh=8m
+SYMATTR SpiceLine Vhigh=5 Vlow=0
+SYMATTR Description Behavioral Schmitt-Triggered inverter
+SYMATTR Type schmtinv
+SYMBOL externals\\xv -800 608 R90
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+WINDOW 3 -96 70 VTop 2
+WINDOW 123 0 0 Left 2
+WINDOW 39 0 0 Left 2
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+SYMATTR InstName R9
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+SYMBOL res -336 1328 R0
+SYMATTR InstName R10
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+SYMBOL ADP5051_chan1_2 224 192 R0
+SYMATTR InstName U1
+SYMBOL ADP5051_chan1_2 224 1008 R0
+SYMATTR InstName U2
+TEXT 632 1344 Left 2 !.tran 3m startup
+TEXT -1336 312 Left 2 ;The schematic simulates channels 1 and 2 in parallel.\nNotice how the SS12, COMP, and FB pins are configured\nThis is DIFFERENT than the real world.  Channels are synced\nto out of phase clocks in order to simulate their phase relationship.
+TEXT 384 424 Left 2 ;Rlim is the resistor generally placed on DL pin to set current limit