seppl/LTSpiceXVII
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This commit is contained in:
Joseph Hopfmüller
2023-01-23 08:17:09 +01:00
commit 1d8dca1c6c
11733 changed files with 1219458 additions and 0 deletions
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examples/jigs/ADP2503-ADJ.asc Normal file
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Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 336 224 304 224
WIRE 448 224 336 224
WIRE 528 224 448 224
WIRE 448 240 448 224
WIRE 528 240 528 224
WIRE 48 304 32 304
WIRE 336 304 304 304
WIRE 448 336 448 304
WIRE 528 336 528 320
FLAG 448 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 528 336 0
FLAG 336 384 0
FLAG -64 64 IN
FLAG 528 224 OUT
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5<EFBFBD>
SYMATTR SpiceLine Rser=80m
SYMBOL cap 432 240 R0
SYMATTR InstName C1
SYMATTR Value 10<31>
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL res 512 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL res 320 208 R0
SYMATTR InstName R1
SYMATTR Value 900K
SYMBOL res 320 288 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL ADP2503-ADJ 176 176 R0
SYMATTR InstName U1
TEXT 528 384 Left 2 !.tran 400u startup
TEXT 208 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled