initial commit

examples/jigs/ADM7172.asc

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+Version 4
+SHEET 1 1048 680
+WIRE 64 32 -32 32
+WIRE 96 32 64 32
+WIRE 400 32 352 32
+WIRE 528 32 400 32
+WIRE 624 32 528 32
+WIRE -32 48 -32 32
+WIRE 528 48 528 32
+WIRE 624 48 624 32
+WIRE 400 80 400 32
+WIRE 64 128 64 32
+WIRE 96 128 64 128
+WIRE -32 144 -32 128
+WIRE 528 144 528 112
+WIRE 624 144 624 128
+WIRE 16 224 0 224
+WIRE 96 224 80 224
+WIRE 400 224 400 160
+WIRE 400 224 352 224
+WIRE 400 240 400 224
+WIRE 224 304 224 288
+WIRE 400 336 400 320
+FLAG 224 304 0
+FLAG -32 144 0
+FLAG 0 224 0
+FLAG 624 144 0
+FLAG 528 144 0
+FLAG -32 32 IN
+FLAG 624 32 OUT
+FLAG 400 336 0
+SYMBOL cap 16 208 M90
+WINDOW 0 0 32 VBottom 2
+WINDOW 3 32 32 VTop 2
+SYMATTR InstName C2
+SYMATTR Value 1n
+SYMBOL voltage -32 32 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 3.5
+SYMBOL res 608 32 R0
+SYMATTR InstName Rload
+SYMATTR Value 2.5
+SYMBOL cap 512 48 R0
+SYMATTR InstName C1
+SYMATTR Value 4.7<EFBFBD>
+SYMATTR SpiceLine Rser=1.5m
+SYMBOL res 384 64 R0
+SYMATTR InstName R1
+SYMATTR Value 15K
+SYMBOL res 384 224 R0
+SYMATTR InstName R2
+SYMATTR Value 10K
+SYMBOL ADM7172 224 128 R0
+SYMATTR InstName U1
+TEXT 568 288 Left 2 !.tran 5m startup