seppl/LTSpiceXVII
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This commit is contained in:
Joseph Hopfmüller
2023-01-23 08:17:09 +01:00
commit 1d8dca1c6c
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examples/jigs/ADG918.asc Normal file
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Version 4
SHEET 1 2844 1336
WIRE 816 -208 816 -224
WIRE 944 -160 912 -160
WIRE 528 -96 432 -96
WIRE 672 -96 608 -96
WIRE 720 -96 672 -96
WIRE 944 -48 912 -48
WIRE 720 0 464 0
WIRE 320 32 320 16
WIRE 464 96 464 0
WIRE 320 128 320 112
WIRE 816 144 816 112
WIRE 464 192 464 176
FLAG 320 128 0
FLAG 320 16 +V
FLAG 816 -224 +V
FLAG 816 144 0
FLAG 464 192 0
FLAG 432 -96 0
FLAG 672 -96 IN
FLAG 944 -160 OUT1
FLAG 944 -48 OUT2
SYMBOL voltage 320 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value {Vdd}
SYMBOL voltage 464 80 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE({Vdd} 0 0 2n 2n 5u 10u)
SYMBOL voltage 624 -96 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE({Vdd/2} 1 10Meg)
SYMBOL Switches\\ADG918 816 -64 R0
SYMATTR InstName U1
TEXT 912 176 Left 2 !.tran 30u\n.param Vdd=2.75