seppl/LTSpiceXVII
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This commit is contained in:
Joseph Hopfmüller
2023-01-23 08:17:09 +01:00
commit 1d8dca1c6c
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examples/jigs/ADG842.asc Normal file
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Version 4
SHEET 1 880 680
WIRE 240 64 240 16
WIRE 112 96 32 96
WIRE 112 144 112 96
WIRE 144 144 112 144
WIRE 416 144 336 144
WIRE 512 144 416 144
WIRE 416 160 416 144
WIRE 512 160 512 144
WIRE 144 208 -32 208
WIRE -32 240 -32 208
WIRE 416 272 416 240
WIRE 512 272 512 224
WIRE 240 336 240 320
FLAG 416 272 0
FLAG 240 336 0
FLAG -32 320 0
FLAG -192 240 0
FLAG -48 96 0
FLAG -192 160 Vdd
FLAG 240 16 Vdd
FLAG 512 272 0
SYMBOL voltage -32 224 R0
WINDOW 3 -219 129 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 10n 10n 500n 1u 10)
SYMATTR InstName V1
SYMBOL voltage 48 96 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.5
SYMBOL voltage -192 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL res 400 144 R0
SYMATTR InstName R1
SYMATTR Value 47
SYMBOL ADG842 240 192 R0
SYMATTR InstName U1
SYMBOL cap 496 160 R0
SYMATTR InstName C1
SYMATTR Value 35p
TEXT -184 376 Left 2 !.tran 10u