initial commit

examples/jigs/ADG1412L.asc

@@ -0,0 +1,79 @@
+Version 4
+SHEET 1 2844 1336
+WIRE -160 -112 -160 -128
+WIRE -64 -112 -64 -128
+WIRE -336 -48 -368 -48
+WIRE -224 -48 -256 -48
+WIRE -208 -48 -224 -48
+WIRE 0 -48 -16 -48
+WIRE 48 -48 0 -48
+WIRE 144 -48 48 -48
+WIRE 48 -16 48 -48
+WIRE 144 0 144 -48
+WIRE -224 16 -288 16
+WIRE -208 16 -224 16
+WIRE 48 80 48 64
+WIRE 144 80 144 64
+WIRE -624 96 -624 80
+WIRE -528 96 -528 80
+WIRE -416 96 -416 80
+WIRE -288 96 -288 16
+WIRE -160 144 -160 128
+WIRE -64 144 -64 128
+WIRE -624 192 -624 176
+WIRE -528 192 -528 176
+WIRE -416 192 -416 176
+WIRE -288 192 -288 176
+FLAG -528 192 0
+FLAG -624 192 0
+FLAG -624 80 +V
+FLAG -528 80 -V
+FLAG -368 -48 0
+FLAG -160 144 -V
+FLAG -64 -128 +V
+FLAG -64 144 0
+FLAG -288 192 0
+FLAG 48 80 0
+FLAG -416 192 0
+FLAG -416 80 VL
+FLAG -160 -128 VL
+FLAG 144 80 0
+FLAG -224 -48 S
+FLAG -224 16 IN
+FLAG 0 -48 D
+SYMBOL voltage -624 80 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V1
+SYMATTR Value 15
+SYMBOL voltage -528 80 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V2
+SYMATTR Value -15
+SYMBOL voltage -240 -48 M270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 -32 56 VBottom 2
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V3
+SYMATTR Value 10
+SYMBOL voltage -288 80 R0
+WINDOW 3 50 115 Left 2
+SYMATTR Value pulse(0 1.8 0 1u 1u 5m 10m)
+SYMATTR InstName V4
+SYMBOL res 32 -32 R0
+SYMATTR InstName R1
+SYMATTR Value 301
+SYMBOL ADG1412L -112 0 R0
+SYMATTR InstName U1
+SYMBOL voltage -416 80 R0
+WINDOW 123 0 0 Left 0
+WINDOW 39 0 0 Left 0
+SYMATTR InstName V5
+SYMATTR Value 1.8
+SYMBOL cap 128 0 R0
+SYMATTR InstName C1
+SYMATTR Value 36p
+TEXT -632 240 Left 2 !.tran 30m
+TEXT -664 -216 Left 2 ;Note:\nSwitch shown for a logic 0 input