initial commit
This commit is contained in:
Joseph Hopfmüller
337
examples/jigs/4284.asc
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337
examples/jigs/4284.asc
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Version 4
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SHEET 1 2876 6124
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WIRE 1152 -512 1152 -736
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WIRE 1152 -512 1120 -512
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WIRE -816 -480 -816 -672
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WIRE -416 -480 -816 -480
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WIRE 928 -448 864 -448
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WIRE 976 -448 928 -448
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WIRE 1152 -448 1152 -512
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WIRE 1152 -448 1056 -448
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WIRE 1264 -448 1264 -576
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WIRE 1328 -448 1328 -480
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WIRE -416 -416 -512 -416
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WIRE 1328 -400 1328 -448
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WIRE -816 -352 -816 -400
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WIRE -416 -352 -560 -352
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WIRE -672 -336 -672 -416
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WIRE -560 -320 -560 -352
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WIRE 928 -320 864 -320
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WIRE -416 -288 -448 -288
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WIRE 1328 -272 1328 -320
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WIRE 928 -256 864 -256
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WIRE 1040 -256 928 -256
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WIRE 704 -192 704 -224
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WIRE 320 -176 256 -176
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WIRE -816 -144 -912 -144
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WIRE -672 -144 -672 -272
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WIRE -672 -144 -752 -144
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WIRE -560 -144 -560 -256
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WIRE -560 -144 -672 -144
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WIRE -448 -144 -448 -288
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WIRE -448 -144 -560 -144
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WIRE -304 -144 -304 -224
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WIRE -304 -144 -448 -144
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WIRE 256 -144 256 -176
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WIRE -1472 -64 -1472 -960
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WIRE 1328 -48 1328 -80
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WIRE 1392 -32 1376 -32
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WIRE 1040 -16 1040 -96
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WIRE 1216 -16 1216 -384
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WIRE 1216 -16 1040 -16
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WIRE 400 0 400 -16
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WIRE 256 16 256 -64
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WIRE 1408 16 1376 16
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WIRE 1408 32 1408 16
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WIRE -1472 64 -1472 16
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WIRE -752 64 -752 -144
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WIRE -752 64 -1472 64
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WIRE -64 64 -64 -224
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WIRE -64 64 -304 64
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WIRE -48 64 -64 64
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WIRE 48 64 48 -224
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WIRE 48 64 32 64
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WIRE 240 64 48 64
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WIRE 704 64 704 -112
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WIRE 704 64 336 64
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WIRE 1408 144 1408 112
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WIRE 288 160 240 160
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WIRE 416 160 368 160
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WIRE 480 160 416 160
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WIRE 528 160 528 -224
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WIRE 528 160 480 160
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WIRE 576 160 528 160
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WIRE 240 176 240 160
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WIRE 416 192 416 160
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WIRE 576 208 576 160
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WIRE 1104 240 1104 176
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WIRE 240 272 240 240
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WIRE 1424 272 1424 240
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WIRE 416 288 416 272
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WIRE -304 336 -304 64
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WIRE -176 336 -176 -224
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WIRE -176 336 -304 336
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WIRE -48 336 -176 336
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WIRE 160 336 160 -224
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WIRE 160 336 32 336
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WIRE 336 336 160 336
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WIRE 400 336 336 336
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WIRE 704 336 704 64
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WIRE 704 336 496 336
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WIRE 704 400 704 336
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WIRE 832 400 704 400
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WIRE 928 400 928 -96
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WIRE 928 400 832 400
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WIRE 1104 400 1104 304
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WIRE 1104 400 928 400
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WIRE 1328 400 1328 32
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WIRE 1328 400 1104 400
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WIRE 1424 400 1424 352
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WIRE 1424 400 1328 400
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WIRE 1552 400 1424 400
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WIRE 576 432 576 288
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WIRE 336 480 336 336
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WIRE 560 480 336 480
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WIRE 832 480 832 400
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WIRE 832 480 656 480
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FLAG -1472 -960 0
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FLAG 544 -816 0
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FLAG -16 -1104 0
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FLAG -1040 -800 0
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FLAG 1104 176 0
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FLAG -816 -800 0
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FLAG 1328 -80 0
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FLAG 1408 144 0
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FLAG 1392 -32 0
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FLAG -1296 -144 VEE
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FLAG 1328 -272 VEE
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FLAG 1040 -16 VEE
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FLAG 1424 240 0
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FLAG 1552 400 OUT
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FLAG 928 -320 INTVCC
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FLAG 928 -512 PGIO1
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FLAG 928 -448 PGIO2
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FLAG 240 272 VEE
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FLAG 400 0 VEE
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FLAG -208 -768 INTVCC
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FLAG 320 -176 GATE1
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FLAG 480 160 GATE2
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FLAG -512 -416 TMR
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SYMBOL voltage -1472 -80 R0
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WINDOW 123 0 0 Left 2
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WINDOW 39 0 0 Left 2
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SYMATTR InstName V1
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SYMATTR Value PWL(0 0 10u 48)
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SYMBOL nmos 336 16 R90
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WINDOW 0 -18 -6 VRight 2
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WINDOW 3 73 50 VCenter 2
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SYMATTR InstName M1
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SYMATTR Value PSMN7R6100BSE
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SYMBOL res 48 48 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName RS1
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SYMATTR Value 5m
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SYMBOL res 688 -208 R0
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SYMATTR InstName RD
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SYMATTR Value 100K
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SYMBOL res 912 -192 R0
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SYMATTR InstName RDT
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SYMATTR Value 392K
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SYMBOL res 1024 -192 R0
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SYMATTR InstName RDB
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SYMATTR Value 10K
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SYMBOL res 1072 -464 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName R6
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SYMATTR Value 100K
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SYMBOL res 1136 -528 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName R7
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SYMATTR Value 100K
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SYMBOL res 688 -832 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName RRT
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SYMATTR Value 392K
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SYMBOL res 1040 -832 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName RRB
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SYMATTR Value 10K
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SYMBOL res -32 -1072 R0
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SYMATTR InstName RIN
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SYMATTR Value 4K
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SYMBOL res -1056 -768 R0
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SYMATTR InstName RUV3
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SYMATTR Value 200K
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SYMBOL res -1056 -368 R0
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SYMATTR InstName RUV1
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SYMATTR Value 10K
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SYMBOL cap -688 -336 R0
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SYMATTR InstName CTMR
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SYMATTR Value 2.2n
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SYMBOL cap 1088 240 R0
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WINDOW 123 24 36 Left 2
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SYMATTR InstName CL
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SYMATTR Value 2000u
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SYMBOL nmos 496 288 R90
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WINDOW 0 -12 -20 VRight 2
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WINDOW 3 78 51 VCenter 2
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SYMATTR InstName M2A
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SYMATTR Value IPT020N10N3
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SYMBOL res 240 -160 R0
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SYMATTR InstName RM1
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SYMATTR Value 10
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SYMBOL res 384 -176 R0
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SYMATTR InstName RG1
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SYMATTR Value 1k
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SYMBOL cap 384 -80 R0
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SYMATTR InstName CG1
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SYMATTR Value 10n
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SYMBOL res 560 192 R0
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SYMATTR InstName RM2B
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SYMATTR Value 10
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SYMBOL res 400 176 R0
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SYMATTR InstName RM2A
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SYMATTR Value 10
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SYMBOL cap -1104 -624 R90
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WINDOW 0 0 32 VBottom 2
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WINDOW 3 32 32 VTop 2
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SYMATTR InstName CUV
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SYMATTR Value 10n
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SYMBOL cap -576 -320 R0
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SYMATTR InstName CR
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SYMATTR Value 470n
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SYMBOL res -832 -768 R0
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SYMATTR InstName ROV2
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SYMATTR Value 523K
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SYMBOL res -832 -368 R0
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SYMATTR InstName ROV1
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SYMATTR Value 10K
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SYMBOL cap -928 -352 R0
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SYMATTR InstName COV
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SYMATTR Value 10n
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SYMBOL nmos 656 432 R90
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WINDOW 0 -15 -19 VRight 2
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WINDOW 3 78 51 VCenter 2
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SYMATTR InstName M2B
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SYMATTR Value IPT020N10N3
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SYMBOL res 48 320 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName RS2
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SYMATTR Value 0.33m
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SYMBOL cap 224 176 R0
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SYMATTR InstName CG2
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SYMATTR Value 220n
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SYMBOL res 384 144 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName RG2
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SYMATTR Value 150
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SYMBOL res 1312 -576 R0
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SYMATTR InstName ROT
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SYMATTR Value 1.4k
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SYMBOL res 1312 -416 R0
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SYMATTR InstName ROB
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SYMATTR Value 10k
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SYMBOL sw 1328 -64 M0
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SYMATTR InstName S1
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SYMATTR Value SSHORT
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SYMBOL voltage 1408 16 R0
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WINDOW 123 0 0 Left 2
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WINDOW 39 0 0 Left 2
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SYMATTR InstName V2
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SYMATTR Value PWL(0 0 1.2 0 +10n 0 +20m 0 +10n 0)
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SYMBOL LTC4284 224 -448 R0
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SYMATTR InstName U1
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SYMATTR SpiceLine D7=0 D6=0 D5=1 D4=1 D3=0 D2=1 D1=0 D0=0
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SYMATTR SpiceLine2 E7=1 E6=1 E5=0 E4=1 E3=0 E2=0 E1=0 F7=0
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SYMBOL cap -320 -896 R0
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SYMATTR InstName CVCC
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SYMATTR Value 1u
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SYMBOL cap -128 -944 R90
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WINDOW 0 0 32 VBottom 2
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WINDOW 3 32 32 VTop 2
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SYMATTR InstName CIN
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SYMATTR Value .1u
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SYMBOL bi 1424 272 R0
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SYMATTR InstName B1
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SYMATTR Value I=if(V(PGIO1,Vee)<.5 & time > .1,MIN(Power/MAX(V(0,OUT),12),Imax),0)
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TEXT 1688 552 Left 2 !.tran 1.6
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TEXT 1320 -152 Left 2 !.model SSHORT SW(Ron=10m Roff=1k vt=.5 vh=-200m)
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TEXT -688 -776 Left 2 ;UV ON = -43V\nUV OFF = -38.5V\nOV OFF = -75V
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TEXT 976 -280 Left 2 ;Ratio 1/40.2
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TEXT 752 -848 Left 2 ;1/40.2
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TEXT 1392 -560 Left 2 ;VOUT LOW = -36.1V
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TEXT 1496 176 Left 4 ;2500W Constant Power Switched Load
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TEXT 1504 216 Left 2 !.param Power=2500\n.param VminLoad=12\n.param Imax=120
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TEXT -1392 176 Left 3 ;LOW STRESS STAGED START MODE
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TEXT -1296 392 Left 3 ;Non Default Bits:\n(set as params on symbol)\n \nILIM = 0011b (D7-D4)\nFB = 10b (D3,D2)\nFTBD_DL = 01b (E5,4)
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TEXT -1280 -64 Left 3 ;LINE REGULATED\nINPUT STEPS LIMITED TO <4V
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TEXT -1392 232 Left 3 ;(USE PARALLEL MODE OR HIGH STRESS STAGED START MODE\nTO RIDE THROUGH LARGE INPUT STEPS)
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TEXT -1400 704 Left 2 ;Note: All bits must be set to 0 or 1\nUndefined behaivor for other values\n \nSee datasheet for further description.\n \nBit Name Default\n Description\n \nCONTROL_1 (0x0A)\n \nA6 DVDT 1\n 1->Enable DVDT startup\nA5 THERM_TMR 0\n 1->Turns off 2 uA TMR pulldown\nA4 FET_BAD_TURN_OFF 1\n 1-> Turn MOSFET Off after FET_BAD\nA3 PWRG_RESET_CNTRL 1\n 1-> Vout Low resets Power Good\n 0-> MOSFET Off resets Power Good\nA2 PGIO2_ACLB 0\n 1-> PGIO2 configured as inverted ACL\n 0-> PGIO2 configured as inverted second Power Good\n \nCONTROL_2 (0x0B)\n \nB7 EXT_FAULT_RETRY 0\n 1->Enables Auto Retry after EXT_FAULT\nB6 PGI_RETRY 0\n 1->Enables Auto Retry after PGI_FAULT\nB5-4 FET_BAD_RETRY 00 \n Configures FET_BAD Retry\n B5,B4 Number of Retries\n 00 0 (Latch-Off)\n 01 1\n 10 7\n 11 infinite\n \nB3-2 OC_RETRY 00\n Configures OC (Over Current) Retry\n B3,B2 Number of Retries\n 00 0 (Latch-Off)\n 01 1\n 10 7\n 11 infinite\n \nB1 UV_RETRY 1\n 1-> Enables Auto Retry after UV_FAULT\nB0 OV_RETRY 1\n 1-> Enables Auto Retry after OV_FAULT
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TEXT -392 744 Left 2 ;CONFIG_1 (0x0D) \n \nD7-4 ILIM 0000\n Configures Current Limit Voltage (VILIM)\n (VILIM(FAST) = 2*VILIM)\n D7,D6,D5,D4 VILIM\n 0000 15m 1000 23m\n 0001 16m 1001 24m\n 0010 17m 1010 25m\n 0011 18m 1011 26m\n 0100 19m 1100 27m\n 0101 20m 1101 28m\n 0110 21m 1110 29m\n 0111 22m 1111 30m\n \nD3-2 FB 00\n Configures Current Limit Foldback\n D3,D2 Foldback Factor\n 00 100% (no foldback)\n 01 50%\n 10 20%\n 11 10%\n \nD1 FB_DIS 0\n 1->Foldback after Startup Disabled\nD0 LPFB 0\n 1->Load Power Foldback after Startup Enabled
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TEXT 448 736 Left 2 ;CONFIG_2 (0x0E) \n \nE7-6 VDTH 11\n Configures Drain Voltage threshold\n for starting FET bad timer\n \n E7,E6 VD,FET(TH)\n 00 72 mV\n 01 102 mV\n 10 143 mV\n 11 203 mV\n \nE5-4 FTBD_DL 00\n Configures FET_BAD filtering timer delay\n \n E5,E4 TDL(FETBAD)\n 00 0.256 sec\n 01 0.512 sec\n 10 1.02 sec\n 11 2.05 sec\n \nE3-1 COOLING_DL 000\n Configures Cooling delay before retry\n for OC_FAULT, FET_BAD_FAULT or EXT_FAULT\n \n E3,E2,E1 TDL(RTRY)\n 000 0.512 sec 100 8.19 sec\n 001 1.02 sec 101 16.4 sec\n 010 2.05 sec 110 32.8 sec\n 011 4.1 sec 111 65.5 sec\n \nCONFIG_3 (0x0F) \n \nF7 EXTFLT_TURN_OFF 0\n 1->Turn MOSFET off after External Fault
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TEXT 760 -880 Left 2 ;Ratio
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TEXT -344 624 Left 5 ;LTC4284 Programing Parameters
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TEXT 1448 72 Left 2 ;Use PWL(0 0 1.2 0 +10n 1 +20m 1 +10n 0) to short the output at 1.2sec
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Reference in New Issue
Block a user