initial commit

examples/jigs/3086.asc

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+Version 4
+SHEET 1 11676 1244
+WIRE 0 -64 -96 -64
+WIRE 176 -64 0 -64
+WIRE -96 -48 -96 -64
+WIRE 176 -48 176 -64
+WIRE 0 16 0 -64
+WIRE 16 16 0 16
+WIRE 368 16 336 16
+WIRE 496 16 368 16
+WIRE 608 16 496 16
+WIRE 672 16 608 16
+WIRE 1008 16 672 16
+WIRE 1152 16 1088 16
+WIRE 1424 16 1232 16
+WIRE 1552 16 1424 16
+WIRE 368 32 368 16
+WIRE 496 32 496 16
+WIRE 672 32 672 16
+WIRE -96 48 -96 32
+WIRE 1424 48 1424 16
+WIRE 1552 48 1552 16
+WIRE 16 128 0 128
+WIRE 368 128 368 112
+WIRE 368 128 336 128
+WIRE 496 128 496 96
+WIRE 496 128 368 128
+WIRE 672 128 672 96
+WIRE 368 144 368 128
+WIRE 1008 160 848 160
+WIRE 1152 160 1088 160
+WIRE 1424 160 1424 112
+WIRE 1424 160 1232 160
+WIRE 1552 160 1552 128
+WIRE 1552 160 1424 160
+WIRE 848 192 848 160
+WIRE 0 240 -96 240
+WIRE 16 240 0 240
+WIRE 368 240 368 224
+WIRE 368 240 336 240
+WIRE -96 256 -96 240
+WIRE 368 256 368 240
+WIRE -96 352 -96 336
+WIRE 0 352 0 240
+WIRE 16 352 0 352
+WIRE 368 352 368 336
+WIRE 368 352 336 352
+WIRE 480 352 368 352
+WIRE 608 352 608 16
+WIRE 608 352 560 352
+WIRE 608 368 608 352
+WIRE 16 464 0 464
+WIRE 608 464 608 448
+WIRE 608 464 336 464
+WIRE 176 544 176 528
+FLAG 176 544 0
+FLAG -96 48 0
+FLAG -96 352 0
+FLAG 672 128 0
+FLAG -96 -64 IN
+FLAG 1552 16 Out
+FLAG 1552 160 Return
+FLAG 848 192 0
+SYMBOL voltage -96 -64 R0
+WINDOW 123 -31 181 Left 2
+WINDOW 39 24 117 Left 2
+WINDOW 3 30 107 Left 2
+SYMATTR Value 6.5
+SYMATTR InstName V1
+SYMBOL res -112 240 R0
+SYMATTR InstName Rmon
+SYMATTR Value 357
+SYMBOL res 352 16 R0
+SYMATTR InstName Rset
+SYMATTR Value 92K
+SYMBOL res 576 336 R90
+WINDOW 0 0 56 VBottom 2
+WINDOW 3 32 56 VTop 2
+SYMATTR InstName Rpwrgdr
+SYMATTR Value 82.5K
+SYMBOL res 592 352 R0
+WINDOW 0 51 38 Left 2
+WINDOW 3 39 65 Left 2
+SYMATTR InstName R4
+SYMATTR Value 100K
+SYMBOL cap 656 32 R0
+WINDOW 39 24 84 Left 2
+SYMATTR SpiceLine Rser=5m Lser=1n
+SYMATTR InstName Cout
+SYMATTR Value 10<31>
+SYMBOL res 1536 32 R0
+SYMATTR InstName Rload
+SYMATTR Value 2.38
+SYMBOL cap 480 32 R0
+SYMATTR InstName C2
+SYMATTR Value 300p
+SYMBOL ind 992 32 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 5 56 VBottom 2
+SYMATTR InstName Lwire1
+SYMATTR Value 1<>
+SYMBOL res 1136 32 R270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName Rwire
+SYMATTR Value 0.1
+SYMBOL ind 1104 176 M270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 5 56 VBottom 2
+SYMATTR InstName Lwire2
+SYMATTR Value 1<>
+SYMBOL res 1248 176 M270
+WINDOW 0 32 56 VTop 2
+WINDOW 3 0 56 VBottom 2
+SYMATTR InstName Rwire2
+SYMATTR Value 0.1
+SYMBOL res 352 128 R0
+SYMATTR InstName Rcdc
+SYMATTR Value 54.9K
+SYMBOL res 352 240 R0
+SYMATTR InstName Rcdc2
+SYMATTR Value 54.9K
+SYMBOL cap 1408 48 R0
+WINDOW 39 24 84 Left 2
+SYMATTR SpiceLine Rser=0.1
+SYMATTR InstName C3_Tant
+SYMATTR Value 47<34>
+SYMBOL LT3086 176 240 R0
+SYMATTR InstName U1
+TEXT 584 -48 Left 2 ;Rmon*Rset
+TEXT 552 -8 Left 2 ;3000*(Rwire+Rwire2)
+TEXT 440 -32 Left 2 ;Rcdc =
+TEXT -8 -120 Left 3 ;5V 2.1A Regulator Driving Two-Wire Cable to Remote Load, With Cable Drop Compensation
+TEXT 776 280 Left 2 ;*Equivalent to 6ft #22 wire.  Voltage drop across \nRwire & Rwire2 adds to minimum input voltage requirement.  \nLTC recommends that voltage loss in the wires be < 20% of Vout.\n \n** Actual inductance will vary with cable construction\nbut other circuit values will normally remain the same.
+TEXT 1216 48 Left 3 ;*
+TEXT 1224 184 Left 3 ;*
+TEXT 1080 48 Left 3 ;**
+TEXT 1072 184 Left 3 ;**
+TEXT 1152 488 Left 2 !.tran .1 startup
+TEXT -80 944 Left 2 ;Package                        Rpkg    Tpkg       Rsink      Tsink\nFE on small board           14        10          12         250\nFE on larger board          14        10           7          350\nDHD on small board        14        10          12         250\nDHD on larger board       14        10           7          350\nR on small board              3          6           13         250\nR on larger board             3          6           10         350\nT7    No heat sink            3          6           37         250\nT7    Small heat sink         3          6           20         150\nT7  Large Heat sink          3          6            6          250
+TEXT -120 592 Left 2 ;The LT3086 model breaks new ground by simulating thermal conditions on the die.  \nIt uses a two-stage thermal model to simulate both package & heat sink thermal conditions.  \nThe default values are for an FE package on a moderate size board with thermal vias to internal planes, \ngiving an overall thermal resistance of 21<32>C/W.  Package resistance is modeled with Rpkg = 14<31>C/W, \nand a time constant, Tpkg = 10s.  Heat sink (PC board) is modeled with Rsink = 7<>C/W and Tsink = 250s.   \nThese numbers can be edited by the user by right clicking on the 3086 symbol.  \n \nThe included chart shows typical values for each package.  Die temperature is accessed by clicking \non the 3086 Temp pin, which is scaled at 10mV/<2F>C, giving 500mV at 50<35>C.  Keep in mind that when \nyou do DC sweeps, die temperature is at t -> infinite, and that the model does not attempt to change \nparameters as a function of temperature.  It is still the users responsibility to use datasheet \nspecifications as the final determiner of correct part usage.
+TEXT 1120 96 Center 2 ;cable
+LINE Normal 524 -28 784 -28
+LINE Normal 928 -44 1316 -44
+LINE Normal 928 -44 932 -44 2
+LINE Normal 928 212 1316 212
+CIRCLE Normal 1280 -44 1352 212
+ARC Normal 968 -44 900 212 936 212 932 -44 2
+ARC Normal 896 -44 964 212 932 -44 928 212