seppl/LTSpiceXVII
0
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

initial commit

Browse Source
This commit is contained in:
Joseph Hopfmüller
2023-01-23 08:17:09 +01:00
commit 1d8dca1c6c
11733 changed files with 1219458 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

55
examples/jigs/3063.asc Normal file
View File

@@ -0,0 +1,55 @@
Version 4
SHEET 1 880 680
WIRE 96 96 0 96
WIRE 112 96 96 96
WIRE 512 96 368 96
WIRE 624 96 512 96
WIRE 720 96 624 96
WIRE 0 112 0 96
WIRE 512 112 512 96
WIRE 624 112 624 96
WIRE 720 112 720 96
WIRE 0 208 0 192
WIRE 96 208 96 96
WIRE 112 208 96 208
WIRE 512 208 512 192
WIRE 512 208 368 208
WIRE 624 208 624 176
WIRE 720 208 720 192
WIRE 512 224 512 208
WIRE 112 320 80 320
WIRE 384 320 368 320
WIRE 464 320 448 320
WIRE 512 320 512 304
FLAG 80 320 0
FLAG 0 208 0
FLAG 464 320 0
FLAG 512 320 0
FLAG 624 208 0
FLAG 720 208 0
FLAG 0 96 IN
FLAG 720 96 OUT
SYMBOL PowerProducts\\LT3063 240 208 R0
SYMATTR InstName U1
SYMBOL voltage 0 96 R0
SYMATTR InstName V1
SYMATTR Value 2.3
SYMBOL cap 384 336 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value .01<EFBFBD>
SYMBOL res 496 96 R0
SYMATTR InstName R1
SYMATTR Value 118K
SYMBOL res 496 208 R0
SYMATTR InstName R2
SYMATTR Value 59K
SYMBOL cap 608 112 R0
SYMATTR InstName C2
SYMATTR Value 10<31>
SYMATTR SpiceLine Rser=10m
SYMBOL res 704 96 R0
SYMATTR InstName Rload
SYMATTR Value 9
TEXT 592 320 Left 2 !.tran .1 startup