seppl/LTSpiceXVII
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This commit is contained in:
Joseph Hopfmüller
2023-01-23 08:17:09 +01:00
commit 1d8dca1c6c
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Version 4
SHEET 1 2164 1268
WIRE -1104 -336 -1552 -336
WIRE -880 -336 -1104 -336
WIRE -800 -336 -880 -336
WIRE -752 -336 -800 -336
WIRE -608 -336 -672 -336
WIRE -544 -336 -608 -336
WIRE -288 -336 -544 -336
WIRE -144 -336 -208 -336
WIRE -1552 -320 -1552 -336
WIRE -800 -272 -800 -336
WIRE -608 -272 -608 -336
WIRE -176 -240 -240 -240
WIRE -1552 -224 -1552 -240
WIRE -432 -208 -480 -208
WIRE -240 -208 -240 -240
WIRE -432 -160 -480 -160
WIRE -1104 -128 -1104 -336
WIRE -928 -128 -1104 -128
WIRE -432 -112 -480 -112
WIRE -240 -96 -240 -128
WIRE -1104 -80 -1104 -128
WIRE -928 -48 -944 -48
WIRE -432 -48 -480 -48
WIRE -432 0 -480 0
WIRE -1104 16 -1104 -16
WIRE -928 32 -960 32
WIRE -432 48 -480 48
WIRE -432 112 -480 112
WIRE -432 160 -480 160
WIRE -432 208 -480 208
WIRE -432 272 -480 272
WIRE -432 320 -480 320
WIRE -432 368 -480 368
WIRE -1120 432 -1184 432
WIRE -928 432 -1040 432
WIRE -432 432 -480 432
WIRE -432 480 -480 480
WIRE -432 528 -480 528
WIRE -432 592 -480 592
WIRE -704 672 -704 656
FLAG -144 -336 0
FLAG -1552 -224 0
FLAG -1184 432 0
FLAG -880 -336 SP
FLAG -544 -336 SN
FLAG -240 -96 0
FLAG -176 -240 InstPower
FLAG -1104 16 0
FLAG -704 672 0
FLAG -960 32 0
SYMBOL res -768 -320 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 20m
SYMBOL res -304 -320 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL voltage -1552 -336 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1u 6 1.5 12 3 7 5 14 6 6)
SYMBOL voltage -1024 432 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PWL(0 1 .5 1 +1u 0)
SYMBOL bv -240 -224 R0
SYMATTR InstName B1
SYMATTR Value V=V(SP,SN)*V(SP)
SYMBOL cap -1120 -80 R0
SYMATTR InstName C1
SYMATTR Value .1<EFBFBD>
SYMBOL LTC2946 -704 192 R0
SYMATTR InstName U1
SYMATTR SpiceLine CA4=0 CA3=1
SYMATTR Value2 CA2=0 CA1=0 CA0=0
TEXT -320 800 Left 2 !.tran 7
TEXT -312 -24 Left 2 ;Control Bits\n \nCA7 ADIN Config\n \nCA7 = 1 ADin measured with respect to IntVcc\nCA7 = 0 Adin measured with respect to Gnd\n \nCA[6:5] Offset Calibration Config\n \nCA6 CA5\n1 1 No calibration\n1 0 Every 128 conversions\n0 1 Every 16 conversions\n0 0 Every conversion\n \nCA[2:0] Channel Configuration\n \nCA2 CA1 CA0\n1 1 1 Snapshot Mode\n1 1 0 Voltage Once, Followed by Current Indefinately\n1 0 1 ADIN, Voltage, Current at 1/256, 1/256, and 254/256 Duty Cycle, Respectively\n1 0 0 ADIN, Voltage, Current at 1/32, 1/32, and 30/32 Duty Cycle, Respectively \n0 1 1 ADIN, Voltage, Current\n0 1 0 Voltage, Current 1/128 and 127/128 Duty Cycle, Respectively\n0 0 1 Voltage, Current 1/16 and 15/16 Duty Cycle, Respectively \n0 0 0 Voltage, Current\n \n>Power, >MaxPower, etc. Analog Real Number outputs referenced to Spice global ground